SB3N551 3.3 V / 5.0 V Ultra-Low Skew 1:4 Clock Fanout Buffer Description The SB3N551 is a low skew 1−to−4 clock fanout buffer, designed for clock distribution in mind. The SB3N551 specifically guarantees low output−to−output skew. Optimal design, layout and processing minimize skew within a device and from device to device. The output enable (OE) pin three−states the outputs when low. MARKING DIAGRAMS* 8 SOIC−8 D SUFFIX CASE 751 8 1 Features • • • • • • • • • http://onsemi.com 3N551 ALYW G 1 Input/Output Clock Frequency up to 160 MHz Low Skew Outputs (50 ps typical) RMS Phase Jitter (12 kHz – 20 MHz): 43 fs (Typical) Output goes to Three−State Mode via OE Operating Range: VDD = 3.0 V to 5.5 V Ideal for Networking Clocks Packaged in 8−pin SOIC Industrial Temperature Range These are Pb−Free Devices 3N551 A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS ICLK Q1 Q2 Q1 Q3 1 8 2 7 3 6 4 5 OE VDD GND Q4 Q2 CLK Q3 ORDERING INFORMATION Q4 OE Figure 1. Block Diagram Device Package Shipping† SB3N551DG SOIC−8 (Pb−Free) 98 Units/Rail SB3N551DR2G SOIC−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 0 1 Publication Order Number: SB3N551/D SB3N551 Table 1. OE, OUTPUT ENABLE FUNCTION OE Function 0 Disable 1 Enable Table 2. PIN DESCRIPTION Pin # Name Type Description 1 ICLK (LV)CMOS/(LV)TTL Input 2 Q1 (LV)CMOS/(LV)TTL Output Clock Output 1 3 Q2 (LV)CMOS/(LV)TTL Output Clock Output 2 4 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3 5 Q4 (LV)CMOS/(LV)TTL Output Clock Output 4 6 GND Power Negative supply voltage; Connect to ground, 0 V 7 VDD Power Positive supply voltage (3.0 V to 5.5 V) 8 OE (LV)CMOS/(LV)TTL Input − EP Thermal Exposed Pad Clock Input. Internal pull-up resistor. Output Enable for the clock outputs. Outputs are enabled when HIGH or when left open; OE pin has internal pull−up resistor. Three−states outputs when LOW. (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. http://onsemi.com 2 SB3N551 Table 3. MAXIMUM RATINGS Symbol VDD VI/VO Parameter Positive Power Supply Input/Output Voltage Condition 1 Condition 2 Rating Units GND = 0 V − 7.0 V t ≤ 1.5 ns − GND–1.5 ≤ VI/VO ≤ VDD+1.5 V TA Operating Temperature Range, Industrial − − ≥ −40 to ≤ +85 °C Tstg Storage Temperature Range − − −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 1) SOIC−8 41 to 44 °C/W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) Table 4. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 4 kV > 200 V Level 1 UL−94 code V−0 @ 0.125 in 531 Devices Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 3 SB3N551 Table 5. DC CHARACTERISTICS (VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic IDD Power Supply Current @ 135 MHz, No Load, VDD = 3.3 V VOH Output HIGH Voltage – IOH = −25 mA, VDD = 3.3 V VOL Output LOW Voltage – IOL = 25 mA VOH Output HIGH Voltage – IOH = −12 mA (CMOS level) Min Typ Max Unit − 20 40 mA 2.4 − − V − − 0.4 V VDD − 0.4 − − V (VDD/2)+0.7 − 3.8 V VIH, ICLK Input HIGH Voltage, ICLK VIL, ICLK Input LOW Voltage, ICLK − − (VDD/2)−0.7 V VIH, OE Input HIGH Voltage, OE 2.0 − VDD V VIL, OE Input LOW Voltage, OE 0 − 0.8 V ZO Nominal Output Impedance − 20 − W RPU Input Pull−up Resistor, OE − 220 − kW CIN Input Capacitance, OE − 5.0 − pF IOS Short Circuit Current − ± 50 − mA Min Typ Max Unit − 50 95 mA 2.4 − − V − − 0.4 V VDD – 0.4 − − V DC CHARACTERISTICS (VDD = 4.5 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic IDD Power Supply Current @ 135 MHz, No Load, VDD = 5.0 V VOH Output HIGH Voltage – IOH = −35 mA VOL Output LOW Voltage – IOL = 35 mA VOH Output HIGH Voltage – IOH = −12 mA (CMOS level) VIH, ICLK Input HIGH Voltage, ICLK (VDD/2) + 1 − 5.5 V VIL, ICLK Input LOW Voltage, ICLK − − (VDD/2) − 1 V VIH, OE Input HIGH Voltage, OE 2.0 − VDD V VIL, OE Input LOW Voltage, OE 0 − 0.8 V ZO Nominal Output Impedance − 20 − W RPU Input Pull−up Resistor, OE − 220 − kW CIN Input Capacitance, OE − 5.0 − pF IOS Short Circuit Current − ±80 − mA Min Typ Max Unit − − 160 MHz − − 43 16 − − fs Table 6. AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol fin Characteristic Conditions Input Frequency tjitter (f) RMS Phase Jitter (Integrated 12 kHz − 20 MHz) (See Figures 2 and 3) tjitter (pd) Period Jitter (RMS, 1s) − 2.0 − ps tr/tf Output rise and fall times; 0.8 V to 2.0 V − 0.5 1.0 ns tpd Propagation Delay, CLK to Qn, 0 − 180 MHz, (Note 4) 1.5 3.0 6.0 ns − 50 250 ps tskew fcarrier = 25 MHz fcarrier = 50 MHz Output−to−Output Skew; (Note 5) 3. Outputs loaded with external RL = 33−W series resistor and CL = 15 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between VDD and GND. A 33 W series terminating resistor may be used on each clock output if the trace is longer than 1 inch. 4. Measured with rail−to−rail input clock. 5. Measured on rising edges at VDD ÷ 2. http://onsemi.com 4 SB3N551 Figure 2. Phase Noise Plot at 25 MHz at an Operating Voltage of 3.3 V, Room Temperature The above plot captured using Agilent E5052A shows Additive Phase Noise of the SB3N551 device measured with an input source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz; as shown in the shaded region of the plot) is 43 fs (RMS Jitter of the input source is 203.31 fs and Output (DUT+Source) is 247.06 fs). Figure 3. Phase Noise Plot at 50 MHz at an Operating Voltage of 5 V, Room Temperature The above plot captured using Agilent E5052A shows Additive Phase Noise of the SB3N551 device measured with an input source generated by Agilent E8663B. The RMS phase jitter contributed by the device (integrated between 12 kHz to 20 MHz; as shown in the shaded region of the plot) is 16 fs (RMS Jitter of the input source is 104.08 fs and Output (DUT + Source) is 119.77 fs). http://onsemi.com 5 SB3N551 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J SOLDERING FOOTPRINT* S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative SB3N551/D