DS8123A 00

®
RT8123A
Single Phase PWM Controller with Light Load
Efficiency Optimization
General Description
Features
The RT8123A is a high efficiency single phase
synchronous buck DC/DC controller with 5V/12V supply
voltage. At light load condition, the IC automatically
operates in the pulse skip mode to reduce switching
frequency so as to improve conversion efficiency. As the
load current increases, the RT8123A leaves the pulse skip
mode and operates in the continuous conduction mode
with fixed-frequency PWM.

The RT8123A has embedded MOSFET gate driver with
high driving capability, supporting driving voltage up to 12V
for high output current application. Other features include
power good indication, external error-amp compensation,
over voltage protection, over current protection,, enable/
disable control and internal Soft-Start. With the above
functions, the IC provides customers a cost-effective
solution for high efficiency power conversion. The RT8123A
is available in a WQFN-16L 3x3 package.
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Ordering Information
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RT8123A
Package Type
QW : WQFN-16L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free))

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Note :
High Performance Operational Error Amplifier
Internal Soft-Start/Stop
± 0.5% Internal Voltage Accuracy, 0.8V Voltage
Reference
OCP accuracy, Four Re-entry Times Before Latch
“Lossless” Differential Inductor Current Sensing
Internal High Precision Current Sensing Amplifier
Oscillator Frequency Range of 100kHz − 1000kHz
20ns Adaptive FET Non-Overlap Time of Internal
Gate Driver
5V to 12V Operation
Support VIN from 1.5V to 19V
VOUT from 0.8V to 3.3V (5V with 12 VCC)
Chip Enable Through RT/EN pin
Latched Over Voltage Protection (OVP)
Internally Fixed OCP Threshold
Guaranteed Startup Into Pre-Charged Loads
Thermally Compensated Current Monitoring
Thermal Shutdown Protection
Integrated MOSFET Drivers
Integrated BOOST Diode with Internal RBST = 2.2Ω
Ω
Automatic Power Saving Mode to Maximize
Efficiency During Light Load Operation
Sync Function
Remote Ground Sensing
Richtek products are :

RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
87= : Product Code
87=YM
DNN
Memory and Termination Supply
 Subsystem Power Supply (MCH, IOCH, PCI)
 CPU and DSP Power Supply
 Distributed Power Supply
 General DC/DC Converter

YMDNN : Date Code
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8123A-00
Applications
September 2015
is a registered trademark of Richtek Technology Corporation.
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1
RT8123A
Pin Configurations
GND
VCC
RT/EN
ISENP
(TOP VIEW)
16 15 14 13
VCCLG
LGATE
PHASE
BOOT
1
12
2
11
GND
3
10
17
4
9
6
7
8
UGATE
PGOOD
SYN
COMP
5
ISENN
RGND
VSEN
FB
WQFN-16L 3x3
Typical Application Circuit
VCC
5V
VCCLG
5V
R3
2.2
R2
2.2
C1
1µF
C2
1µF
VCC
5V
1
PGOOD
VCC
15
VCCLG
R1
10k
EN
BOOT
4
Q1
UGATE 5
6 PGOOD
RT8123A
SYN
VIN
PHASE
VOUT
L1
3
Q2
7 SYN
LGATE 2
14 RT/EN
16 GND
17
EXPOSED PAD
ISENP
VSEN
FB
9
R5
NC
10
12
R4
Optional
RGND
ISENN
8 COMP
13
11
R6
100
R7
100
VCC_SNS
VSS_SNS
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is a registered trademark of Richtek Technology Corporation.
DS8123A-00
September 2015
RT8123A
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VCCLG
Low-Side Driver Section Power Supply. Operative voltage is 5V to 12V bus.
Filter with 1F MLCC to GND.
2
LGATE
Low-Side Driver Output. Connect directly to the low-side MOSFET gate. A
small series resistor can be useful to reduce dissipated power especially in
high frequency applications.
3
PHASE
High-Side Driver Return Path. Connect to the high-side MOSFET source.
This pin is also monitored for the adaptive dead-time management.
4
BOOT
High-Side Driver Supply. This pin supplies the high-side floating driver.
Connect through the CBOOT capacitor to the PHASE pin. The pin is
internally connected through a boot diode to the VCCLG pin. A 2.2 series
resistor is also provided.
5
UGATE
High-Side Driver Output. Connect to high-side MOSFET gate. A small series
resistor may help in reducing the PHASE pin negative spike as well as
cooling the device.
6
PGOOD
Power Good. It is an open-drain output set free after SS as long as the
output voltage monitored through VSEN is within specifications. If not used
it can be left floating.
7
SYN
Synchronization Pin. The controller synchronizes on the falling edge of a
square wave provided to this pin. Short to GND if not used.
8
COMP
Error Amplifier Output. Connect with an RF-CF to FB. The device cannot be
disabled by grounding this pin.
9
FB
Error Amplifier Inverting Input. Connect with a resistor RFB to VSEN and
with an RF-CF to COMP.
10
VSEN
Output Voltage Monitor. It manages OVP and UVP protections and PGOOD.
Connect to the positive side of the load for remote sensing.
11
RGND
Remote Ground Sense.
Connect to the negative side of the load for remote sensing.
12
ISENN
Current Sense Negative Input. Connect to the output-side of the main
inductor.
13
ISENP
Current Sense Positive Input. Connect through an R-C filter to the
phase-side of the main inductor.
14
RT/EN
15
VCC
16
GND
17 (Exposed Pad)
GND
Internally Set to 1.24V, It Allows Programming the Switching Frequency fSW
of The Device. Switching frequency can be increased according to the
resistor connected to GND with a gain of 10kHz/A. If floating, the switching
frequency is 200kHz.
Device Power Supply. The embedded bootstrap diode is internally
connected to this pin. Operative voltage is 5V to 12V bus. Filter with 1F
MLCC to GND.
All Internal References, Logic and Driver Return Path are Referenced to this
Pin. Connect to the PCB GND ground plane and filter to VCC and VCCLG.
The exposed pad must be soldered to a large PCB and connected to GND
for maximum power dissipation.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8123A-00
September 2015
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3
RT8123A
VCC
PGOOD
Function Block Diagram
BOOT
ISENN
-
ISENP
+
UG Rds ON
PWM Logic, Monitor, Protections
DRV
VSEN
+
125% VREF
-
75% VREF
+
UGATE
OV
10k
PHASE
Dead Time
Controller
UV
VCCLG
+
-
LG Rds ON
PWM
LGATE
DRV
CLK
10k
RT/EN
SYN
Programmable
Oscillator
GND
+
RAMP
COMP
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4
+
-
VREF
FB
RGND
is a registered trademark of Richtek Technology Corporation.
DS8123A-00
September 2015
RT8123A
Absolute Maximum Ratings
(Note 1)
VCC, VCCLG to GND ---------------------------------------------------------------------------------------------------- BOOT to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 100ns --------------------------------------------------------------------------------------------------------------------- BOOT to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------< 100ns --------------------------------------------------------------------------------------------------------------------- PHASE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< −100ns ------------------------------------------------------------------------------------------------------------------- RGND to GND ------------------------------------------------------------------------------------------------------------- UGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< 100ns --------------------------------------------------------------------------------------------------------------------- UGATE to PHASE
DC ----------------------------------------------------------------------------------------------------------------------------< −100ns ------------------------------------------------------------------------------------------------------------------- LGATE to GND
DC ----------------------------------------------------------------------------------------------------------------------------< −100ns ------------------------------------------------------------------------------------------------------------------- ISENP, ISENN to GND --------------------------------------------------------------------------------------------------- Other Input, Output or I/O Voltage ------------------------------------------------------------------------------------ Power Dissipation, PD @ TA = 25°C
WQFN-16L 3x3 ----------------------------------------------------------------------------------------------------------- Package Thermal Resistance (Note 2)
WQFN-16L 3x3, θJA ------------------------------------------------------------------------------------------------------WQFN-16L 3x3, θJC ----------------------------------------------------------------------------------------------------- Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------ Junction Temperature ---------------------------------------------------------------------------------------------------- Storage Temperature Range ------------------------------------------------------------------------------------------- ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------
Recommended Operating Conditions
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−0.3V to 15V
−0.3V to 40V
−0.3V to 45V
−0.3V to 15V
−0.3V to 20V
−5V to 25V
−10V to 30V
−0.7V to 0.7V
−0.3V to 40V
−10V to 45V
−0.3V to 15V
−5V to 20V
−0.3V to 15V
−5V to 20V
−0.3V to 6.5V
−0.3V to 6.5V
3.33W
30°C/W
7.5°C/W
260°C
150°C
−65°C to 150°C
1kV
200V
(Note 4)
Supply Voltage, VCC ------------------------------------------------------------------------------------------------------ 4.5V to 13.2V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C
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RT8123A
Electrical Characteristics
(VCC = VCCLG = 5V to 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
--
13.2
V
Supply Operating
VCC, VCCLG Bias
Voltage
Supply Current
Shutdown Current
POR Threshold
VCC, VCCLG
ICC
UGATE, LGATE open
--
--
5
ICCLG
UGATE, LGATE open
3.5
5
ICC_SHDN
RT = GND
---
--
400
ICCLG_SHDN
RT = GND
--
--
200
VCC_th
VCC Rising
--
--
4.5
V
--
0.3
--
V
--
--
4.2
V
--
0.15
--
V
POR Hysteresis
VCC_hys
POR Threshold
VCCLG_th
POR Hysteresis
VCCLG_hys
VCCLG Rising
mA
A
Error Amplifier COMP
Open Loop DC Gain
ADC
(Note 5)
--
80
--
dB
Gain Bandwidth
GBW
(Note 5)
--
15
--
MHz
Slew Rate
IEA_SLEW
COMP with 100pF to ground,
(Note 5)
--
8
--
V/s
0.796
0.8
0.804
V
180
200
220
kHz
VREF
Internal Reference
Voltage
Oscillator
Frequency
fOSC
RT/EN = Open
OSC Gain
Note 5
--
10
--
kHz/A
Disable OSC
RT/EN Falling
--
--
0.75
V
Minimum On-time
--
90
--
ns
Minimum Off-time
250
350
450
ns
Modulators
Magnitude of the PWM
Ramp
RT/EN = Open
--
1.5
--
V
Maximum Duty cycle
RT/EN = Open
--
95
--
%
25
--
--
kHz
--
5.12
--
ms
RT/EN ties to ground
--
20
--

ISENP-ISENN; 4x Masking
17
20
23
ISENP-ISENN; Immediate Action
--
30
--
ASM frequency
Soft-Start
Soft-Start Time
Soft-Off
VOUT Discharge
Resistor
Over Current Protection
OC Threshold
VOC_th
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mV
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DS8123A-00
September 2015
RT8123A
Parameter
Symbol
Test Conditions
Min Typ
Max
Unit
Synchronization Pin
Synchronization Input
VIL
--
--
1
VIH
2.5
--
--
--
--
0.4
V
Protection and PGOOD
Output Voltage
Sink 1mA
V
VSEN Rising
117 125
130
Un-latch, VSEN Falling
40
50
60
VSEN Falling
70
75
80
%
PGOOD High Delay
Note 5
--
--
50
s
PGOOD Low Delay
Note 5
--
--
1
s
OVP Threshold
VOV
UVP Threshold
VUV
%
Driver
UGATE Driver Source
RUGATEsr IUGATE = 150mA, VCC = 12V
--
2.5
5

UGATE Driver Sink
RUGATEsk VUGATE VPHASE = 0.1V, VCC = 12V
--
2
2.5

LGATE Driver Source
RLGATEsr
--
2
3

LGATE Driver Sink
RLGATEsk VLGATE = 0.1V, VCCLG = 12V
--
1
1.5

From LGATE falling to UGATE rising
--
30
--
ns
From UGATE falling to LGATE rising
--
30
VCC to BOOT, IBOOT = 10mA, VCC = 12V
--
40
80

150 180
--
C
--
C
Dead time
Boost Switch Ron
RBOOT
ILGATE = 150mA, VCCLG = 12V
ns
Thermal Shutdown
Thermal Shutdown
TSD
Thermal Shutdown Hysteresis
TSD
--
50
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8123A-00
September 2015
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7
RT8123A
Typical Operating Characteristics
Efficiency vs. Load Current
Output Voltage vs. Load Current
1.0530
90
1.0525
Output Voltage (V)
100
Efficiecncy (%)
80
70
60
50
40
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V, L = 1μH, DCR = 3.3mΩ
30
1.0520
1.0515
1.0510
1.0505
1.0500
1.0495
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V
1.0490
20
1.0485
0
2
4
6
8
10
12
14
16
18
0
2
4
6
Load Current (A)
8
10
12
14
16
18
20
Load Current (A)
Output Voltage vs. Input Voltage
Output Voltage vs. Temperature
1.0535
1.2
1.0530
1.0525
Output Voltage (V)
Output Voltage (V)
1.1
1.0
0.9
0.8
0.7
1.0520
1.0515
1.0510
1.0505
1.0500
1.0495
1.0490
1.0485
0.6
VOUT = 1.05V, VCC = VCCLG = 5V, IOUT = 0.5A
0.5
1.0480
VIN = 12V, VCC = VCCLG = 5V
1.0475
-50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
25
50
75
Power On from RT/EN
Power Off from RT/EN
RT/EN
(1V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
VIN = 12V,
VOUT = 1.05V,
VCC = VCCLG = 5V,
IOUT = 10A
PGOOD
(5V/Div)
100
125
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V, IOUT = 10A
VOUT
(500mV/Div)
PGOOD
(5V/Div)
Time (2ms/Div)
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0
Temperature (°C)
RT/EN
(1V/Div)
VOUT
(500mV/Div)
-25
Input Voltage (V)
Time (50μs/Div)
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RT8123A
Over Current Protection
Load Transient Response
VOUT
(50mV/Div)
UGATE
(20V/Div)
LGATE
(10V/Div)
PHASE
(10V/Div)
VOUT
(500mV/Div)
IOUT
(5A/Div)
IL
(10A/Div)
VIN = 12V, VOUT = 1.05V, VCC = VCCLG = 5V
Time (100μs/Div)
Time (20μs/Div)
Over Voltage Protection
Under Voltage Protection
VSEN
(500mV/Div)
VSEN
(500mV/Div)
UGATE
(10V/Div)
UGATE
(10V/Div)
LGATE
(5V/Div)
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V, IOUT = 5A
LGATE
(5V/Div)
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V, IOUT = 5A
Time (20μs/Div)
Pre-Bias Startup
Synchronization
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V, IOUT = 30mA
Time (20μs/Div)
RT/EN
(1V/Div)
PHASE
(10V/Div)
VOUT
(500mV/Div)
PGOOD
(5V/Div)
VOUT
(50mV/Div)
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V, IOUT = 500mA
SYN
(5V/Div)
UGATE
(10V/Div)
Time (10ms/Div)
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS8123A-00
VIN = 12V, VOUT = 1.05V,
VCC = VCCLG = 5V
September 2015
Time (2μs/Div)
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9
RT8123A
Application Information
The RT8123A requires an external bias supply for VCC
and VCCLG. VCC powers the high-side integrated
MOSFET driver and the control circuit. VCCLG biases the
low-side integrated MOSFET driver. It’s preferred and
recommended to add a resistor (2.2 to 10Ω) between
VCC and VCCLG pins and decoupling capacitors on both
pins to ground.
The Power On Reset (POR) circuit monitors the supply
voltage at VCC and VCCLG pins. If VCC and VCCLG are
both exceed the POR rising threshold voltage, the
controller is reset and preparing the PWM for operation. If
VCC and VCCLG fall below the POR falling threshold during
normal operation, all MOSFETs stop switching. The POR
rising and falling threshold has a hysteresis to prevent
noise caused reset.
Soft-Start
The RT8123A provides internal soft-start function to prevent
the large inrush current and output voltage overshoot when
the converter starts up. The Soft-Start (SS) automatically
begins once the VCC, VCCLG both exceeds their POR
thresholds and RT/EN pin is set free. During Soft-Start,
the internal Soft-Start capacitor is charged and generates
a linear ramping up voltage across the capacitor. This
voltage clamps the feedback voltage at the FB pin, causing
PWM pulse width increasing slowly to reduce the output
surge current. The internal 0.8V reference takes over the
loop control once the internal ramping up voltage is higher
than 0.8V. The Soft-Start ramp will wait a fixed delay time
at Soft-Start beginning, and the PGOOD will indicate high
after 30us delay time once the output voltage is within
PGOOD window (±10 % of reference voltage 0.8V).
A power on sequence should be concerned. When RT/
EN is set free with VCC/VCCLG but VIN is not present,
the VOUT voltage cannot be generated and the COMP
will be pulled high during UV blanking time then into hiccup
mode. Once VCC/VCCLG both exceeds POR threshold
and VIN comes in the Soft-Start period where COMP is
pulled high, Soft-Start begins but OCP or OVP may be
triggered fault latch to cause power on failed. For
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10
successful power up, to make sure the correct sequence
of VIN, VCC/VCCLG and RT/EN is needed.
Power Good Output
The PGOOD is an open-drain type output and requires a
pull-up resistor. PGOOD is actively held low in soft-start,
shutdown and if the OVP or UVP is triggered. It is released
when the voltage on the VSEN pin within ±10% of reference
voltage (0.8V).
Switching Frequency
Higher PWM switching frequency enhances better
transient response and smaller component size, trading
off efficiency due to higher switching losses.
The switching frequency can be programmed by a resistor
(RRT) which connecting between RT/EN pin and ground.
Figure 1 shows the typical operation frequency vs. RRT
for quick reference.
Frequency vs. RRT
310
290
Frequency (kHz)1
Supply Voltage and Power On Reset
270
250
230
210
190
0
100
200
300
400
500
600
700
800
RRT (k Ω)
Figure 1. Operation Frequency vs. RRT
Synchronization Function
The RT8123A provides the synchronization function that
allows the different converters can share the same input
filter for reducing the input RMS current and reducing the
total input capacitors.
Synchronization can be programmed through the SYN pin
by external PWM signal with a fixed delay time such as
PHASE, UGATE etc. The UGATE of RT8123A will track
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DS8123A-00
September 2015
RT8123A
the falling edge of external PWM signal on SYN pin, and
the synchronize frequency range is 100% to 130% of
RT8123A's setting frequency.
Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage. If the voltage on VSEN pin exceeds than OVP
threshold (125% of VREF), the over voltage protection is
triggered and the LGATE low-side gate driver is forced
high. This activates the low-side MOSFET switch, which
rapidly discharges the output capacitor and pulls the input
voltage downward. When the VSEN pin voltage falls below
0.4V, LGATE will go low to stop the discharge.
The RT8123A is latched once OVP is triggered and can
only be released by toggling VCC, VCCLG or RT/EN. There
is a fixed delay time built into the over voltage protection
circuit to prevent false transition.
Pre-OVP Function
When RT/EN signal is low, the pre-OVP circuit senses
the voltage on VSEN pin. Once the VSEN voltage exceeds
Pre-OVP threshold, LGATE will be forced high to
discharge the output voltage for protecting the load. PreOVP protection is not latch mode. Once the VSEN voltage
is less than Pre-OVP threshold, LGATE will go low to
stop discharge immediately.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage. If the voltage on VSEN pin is less than 75% of
VREF, under voltage protection is triggered, then both
UGATE and LGATE gate drivers are forced low. The UVP
will be ignored during Soft-Start period. Toggle VCC,
VCCLG or RT/EN to reset the UVP fault latch and restart
the controller.
Over Current Protection (OCP)
The RT8123A uses continuous inductor current sensing
to make the controller less noise sensitive. Low offset
amplifier is used for over current detection. The ISENP
and ISENN denote the positive and negative input of the
current sense amplifier.
The RT8123A observes the differential voltage VX, across
the ISENP and ISENN pins for inductor current information.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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September 2015
There are two over current thresholds (VOC_th1 = 20mV
and VOC_th2 = 30mV) designed for different over current
condition. If the differential voltage across ISENP and
ISENN (VX) exceeds than 20mV (but below than 30mV)
for four switching cycles, VOC_th1 will be triggered. Both
UGATE and LGATE gate drivers are forced low to turn off
MOSFETs and latched. Once the differential voltage VX
exceeds than 30mV, VOC_th2 will be triggered. Both UGATE
and LGATE gate drivers are forced low and latched
immediately.
The value of current sensing network is calculated as below
formula for meet inductor time constant.
L = R
 CS1 // RCS2   C
DCR
Therefore, the OCP thresholds can be calculated as,
R
+ RCS2
VOC_th1 = 20mV  CS1
DCR
RCS2
R
+ RCS2
VOC_th2 = 30mV  CS1
DCR
RCS2
VOUT
L
DCR
PHASE
RCS1
RCS2
C
ISENP
+ VX -
ISENN
Figure 2. Current Sensing Network
Output Voltage Setting
The RT8123A allows the output voltage of the DC/DC
converter to be adjusted from 0.8V to 80% of VIN via an
external resistor divider as shown in Figure 3. It will try to
maintain the feedback pin at internal reference voltage.
VOUT
RFB1
FB
RFB2
Figure 3. Output Voltage Setting
The output voltage can be set according to :
R
VOUT = VREF   1 + FB1 
RFB2 

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RT8123A
Compensation Network Design
The frequency of the double-pole is determined as follows.
fP(LC) =
1
2 LOUT  COUT
The frequency of the ESR zero is determined as follows.
fZ(ESR) =
1
2  COUT  ESR
A typical type-II compensation network is shown in
Figure 4.
C2
R2 C1
R1
EA
+
+
-
VREF
FP1
Gain (dB)
The RT8123A is a voltage mode synchronous Buck
controller. To compensate a typical voltage mode buck
converter, there are two ordinary compensation schemes,
well known as type-II compensator and type-III
compensator. The choice of using type-II or type-III
compensator will be up to platform designers, and the
main concern will be the position of the capacitor ESR
zero and mid-frequency to high frequency gain boost.
Typically, the ESR zero of output capacitor will tend to
stabilize the effect of output LC double poles, hence the
position of the output capacitor ESR zero in frequency
domain may influence the design of voltage loop
compensation. If fZ(ESR) is < 1/2fC , where fC denotes 0dB
crossing frequency, type-II compensation will be sufficient
for voltage stability. If fZ(ESR) is > 1/2fC (or higher gain and
phase margin is required at mid frequency to highfrequency), then type-III compensation may be a better
solution for voltage loop compensation.
FZ1
FP2
Frequency (Hz)
Figure 5. Bode Plot of the Type-II Compensation
The frequencies of poles and zero are :
1
fZ1 =
2  R2  C1
fP1 = 0
fP2 =
1
2  R2  C1 C2
C1 + C2
Determining the 0dB crossing frequency (fC, control loop
bandwidth) is the first step of compensator design. Usually,
the fC is set to 0.1 to 0.3 times of the switching frequency.
The second step is to calculate the open loop modulator
gain and find out the gain loss at fC. The third step is to
design a compensator gain that can compensate the
modulator gain loss at fC. The final step is to design fZ1
and fP2 to allow the loop sufficient phase margin. fZ1 is
designed to cancel one of the double-pole of modulator.
Usually, place fZ1 before fP(LC) . fP2 is usually placed below
the switching frequency (typically, 0.5 to 1 times of the
switching frequency) to cancel high frequency noise.
A typical type-III compensation contains two zeros and
two poles, where the extra one zero and one pole compared
with type-II compensation are added for stabilizing the
system when ESR zero is relatively far from LC doublepole in frequency domain. Figure 6 and Figure 7 show the
typical circuit and bode plot of the type-III compensation.
C2
Figure 4. Type-II Compensation Network
After determining the phase margin at crossover
frequency, the position of zero and pole produced by typeII compensation network, F Z1 and F P2, can then be
determined. The bode plot of type-II compensation is
shown in Figure 5.
R3 C3
R2 C1
R1
EA
+
+
-
VREF
Figure 6. Type-III Compensation Network
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is a registered trademark of Richtek Technology Corporation.
DS8123A-00
September 2015
RT8123A
Gain (dB)
FP1
FZ1
FZ2
FP2
Frequency (Hz)
FP3
Figure 7. Bode Plot of the Type-III Compensation
A well-designed compensator regulates the output voltage
according to the reference voltage VREF with fast transient
response and good stability. In order to achieve fast
transient response and accurate output regulation, an
adequate compensator design is necessary. The goal of
the compensation network is to provide adequate phase
margin (usually greater than 45°) and the highest bandwidth
(0dB crossing frequency, f C ) possible. It is also
recommended to manipulate the loop frequency response
such that its gain crosses 0dB with a slope of −20dB/
dec. According to Figure 7, the frequencies of poles and
zeros are :
1
2  R2  C1
1
fZ2 =
2  R1 + R3   C3
fZ1 =
fP1 = 0
1
2  R3  C3
1
fP3 =
2  R2  C1 C2
C1 + C2
fP2 =
conduction loss. In addition, the inductor covers a
significant proportion of the board space, so its size is
also important. Low profile inductors can save board space
especially when the height has a limitation. However, low
DCR and low profile inductors are usually cost ineffective.
Additionally, larger inductance results in lower ripple
current, which translates into the lower power loss.
However, the inductor current rising time increases with
inductance value. This means the transient response will
be slower. Therefore, the inductor design is a trade-off
between performance, size and cost.
In general, inductance is chosen such that the ripple
current ranges between 20% to 40% of the full load current.
The inductance can be calculated using the following
equation :
VIN  VOUT
V
L(MIN) =
 OUT
fSW  k  IOUT_Full Load
VIN
where k is the ratio between inductor ripple current and
rated output current.
Input Capacitor Selection
Voltage rating and current rating are the key parameters
when selecting an input capacitor. Conservatively speaking,
an input capacitor should have a voltage rating 1.5 times
greater than the maximum input voltage to be considered
a safe design. The input capacitor is used to supply the
input RMS current, which can be approximately calculated
using the following equation :
IRMS = IOUT 
VOUT 
V
 1  OUT 
VIN 
VIN 
Generally, fZ1 and fZ2 are designed to cancel the doublepole of the modulator. Usually, place fZ1 at a fraction of
fP(LC) , and place fZ2 at fP(LC) . fP2 is usually placed at fZ(ESR)
to cancel the ESR zero, and fP3 is placed below the
switching frequency to cancel high frequency noise.
The next step is to select a proper capacitor for the RMS
current rating. Using more than one capacitor with low
Equivalent Series Resistance (ESR) in parallel to form a
capacitor bank is a good design. Placing the ceramic
capacitor close to the drain of the high-side MOSFET can
also be helpful in reducing the input voltage ripple at heavy
load.
Inductor Selection
Output Capacitor Selection
The inductor plays an importance role in step-down
converters because it stores the energy from the input
power rail and then releases the energy to the load. From
the viewpoint of efficiency, the dc resistance (DCR) of the
inductor should be as small as possible to minimize the
The output capacitor and the inductor form a low-pass filter
in the buck topology. In steady state condition, the ripple
current flowing into/out of the capacitor results in voltage
ripple. The output voltage ripples contains two
components, ΔVOUT_ESR and ΔVOUT_C.
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September 2015
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RT8123A
VOUT_ESR = IL  ESR
VOUT_C = IL 
1
8  COUT  fSW
When load transient occurs, the output capacitor supplies
the load current before controller can respond. Therefore,
the ESR will dominate the output voltage sag during load
transient. The output voltage sag can be calculated using
the following equation :
VOUT_SAG = ESR  VOUT
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore ESL contributes to part of the voltage sag. Using
a capacitor with low ESL will obtain better transient
performance. Generally, using several capacitors
connected in parallel will also have better transient
performance than just one single capacitor with the same
total ESR.
Unlike electrolytic capacitors, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, it is
suggested to use a mixed combination of electrolytic
capacitor and ceramic capacitor for achieving better
transient performance.
MOSFET Selection
the on-state resistance. However, this depends on the
low-side MOSFET driver capability and the budget.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-16L 3x3 packages, the thermal resistance, θJA, is
30°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for
WQFN-16L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 8 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
The majority of power loss in the step-down power
conversion is due to the loss in the power MOSFETs. For
low voltage high current applications, the duty cycle of
the high-side MOSFET is small. Therefore, the switching
loss of the high-side MOSFET is of concern. Power
MOSFETs with lower total gate charge are preferred in
such kind of application. However, the small duty cycle
means the low-side MOSFET is on for most of the
switching cycle. Therefore, the conduction loss tends to
dominate the total power loss of the converter. To improve
the overall efficiency, MOSFETs with low RDS(ON) are
preferred in the circuit design. In some cases, more than
one MOSFET are connected in parallel to further decrease
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is a registered trademark of Richtek Technology Corporation.
DS8123A-00
September 2015
RT8123A
Maximum Power Dissipation (W)1
3.5
Four-Layer PCB
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 8. Derating Curve of Maximum Power Dissipation
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DS8123A-00
September 2015
is a registered trademark of Richtek Technology Corporation.
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15
RT8123A
Outline Dimension
D
SEE DETAIL A
D2
L
1
E
E2
e
b
A
A1
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
1.300
1.750
0.051
0.069
E
2.950
3.050
0.116
0.120
E2
1.300
1.750
0.051
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 16L QFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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DS8123A-00
September 2015