HPCN Schematics

1
2
4
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freescale
A
6
8
7
TM
A
semiconductor
B
B
C
C
HPCN: High-Performance Computing platform for Networking
by
Cass Arnett
Steve Foster
Gary Milliorn
Tiffany Tran-Chandler
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
D
Gary Milliorn
4
Title: Cover Story
Time Changed: 2:05:21 pm
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Page:
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Schematic Notes
1.
A
2.
Unless otherwise specified:
All resistors are SMD0402, in ohms, 0.08W, +/-5%
All capacitors are SMD0402, in microfarads (uF), +/-20%.
All inductances are in microhenries (uH).
All ferrites are Z=50 ohms at 100 MHz.
All fuses are self-resetting polyswitch (PTC) devices.
Board impedance is 55 +/- 5 ohms.
Integrated circuits have default connections to power
and ground unless explicitly shown otherwise. Global power
connections are:
VCC_3.3
VCC_5
VCC_2.5
VCC_1.2
GND
VCORE
3.
Part numbers used are for reference only; compatible
parts may be used; refer to the bill of materials.
4.
Freescale and the Freescale logo are registered
trademarks of Freescale Semiconductor. PowerPC is a trademark
of IBM. Other trademarks are the respective property of their
respective copyright holders. Anyone perfect must be lying,
anything easy has it’s cost, anyone plain can be lovely, anyone
loved can be lost. All rights reserved. No warranty is made,
express or implied.
5.
6.
Page
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The sheet-to-sheet cross reference format is:
Sheet VertZoneLetter HorizZoneNumber
Components with the label "No_Stuff" are not to be installed by
default; they are for test or manufacturing purposes only.
No_Stuff
null
7.
C123
33pF
All buses follow big-endian bit numbering order (bit 0 is
the most-significant bit), except where industry standards
apply (i.e. PCI). Little-endian numbering is noted at the
source component.
null1
B
This schematic is provided for reference purposes only.
All information is subject to change without notice.
No warranty, expressed or applied, is made as to the
accuracy of the information contained herein. Contact
Freescale Sale/FAEs to obtain the latest information on
this product.
C
REV
D
V1.0
V1.0a
V1.02
DATE
CHANGES
2005Aug03
2006Feb27
2006Nov07
freescale
semiconductor
1
Page
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Contents
LocalBus Debug
MC8641D SERDES #2
PCIExpress Slot #1
MC8641D SERDES #1
PEX Alternate Slot #1 and MidBus Probe
M1573 ULI PEX Connection
M1573 PCI, RTC, LPC and Misc
M1573 USB + APIC
M1573 SATA + IDE
AC97 Codec
PCI Slots #1 and #2
USB Ports
AC97 Audio Connectors
SIO
LPC Flash
Debug, LEDs
Global Bypass, Mounting, etc.
A
B
C
D
Initial version
Initial production
PCB Tweaks
Freescale Semiconductor
TM
Contents
Cover Page
General Information
Block Diagram
Placement and PCB Stackup
Power Entry, Switches
Hot Power Supplies
VCORE Power Supply
VCORE Power Supply, cont’d
Platform Power
1.2V power
SERDES and 1.8V Power
System and PHY Clocks
SERDES (REFCLK) and BCLK Clocks
PIXIS System Logic, Part 1
PIXIS System Logic, Part 2
PCI Isolation Buffer
Configuration Switches
MC8641D Control Block
COP and Debug Interfaces
MC8641D Power part 1
MC8641D Power part 2
MC8641D DDR Interface #1
DDR1 DIMM #1
DDR1 DIMM #2
DDR1 Termination
MC8641D DDR Interface #2
DDR2 DIMM #1
DDR2 DIMM #2
DDR2 Termination and Power
MC8641D Quad Ethernet MAC
QuadPHY MAC
QuadPHY Power
QuadPHY Ports
Ethernet Port Connectors #1/#2
Ethernet Port Connectors #3/#4
Serial Ports 1 and 2
MC8641D LocalBus Interface
Flash and PromJet Headers
CompactFlash Header
I2CBus Devices
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Information, please
Time Changed: 2:05:47 pm
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Page:
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1
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A
A
VCORE
RJ45MAG
RJ45MAG
RJ45MAG
DDR #1
VSC8244
QuadPHY
RJ45MAG
DDR #2
MC8641D
Serial
B
B
Flash
Local
Bus
PromJET
CF+
PEx
PIXIS
PEX Slot
PEx
PEX Slot
LPC
PCI 2
PCI 1
C
M1575
C
SIO
Flash
AUDIO
USB
PATA
SATA
Clock
Group
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Block Diagram
Time Changed: 2:05:55 pm
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Page:
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244mm (9.6")
158.75mm (6.25")
A
RJ45
RJ45
AUDIO
RJ45
RJ45
SER #1
USB
A
PS/2
Mounting holes, positioned per microATX spec.
Mounting holes for socket.
MIC2077
FAN
A12V
LT1331
AC97
VDD_PLAT
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
LED
USB
M1575
APA PROG
SATA2
SATA1
ON
29LV641
PromJet
RST
PWR
SVC
RST
PWR
SATA4
SATA3
USBHDR
IDE
LPCFlash
APA150
SuperIO
CONFIG SWITCHES
PCIExpress 4X
MPC9855
B
COP
VTT PLANE + POWER #2
DDR #2 DIMM #1
DDR #2 DIMM #2
VTT PLANE + POWER
DDR #1 DIMM #1
STATUS LEDS
244mm (9.6")
DDR #1 DIMM #2
MC8641D
INFO LEDS
B
ATX POWER
VCORE
PCIExpress 8X (in 16X slot)
PCI 2
PCI 3
Note: Not Definitive -- see
Design Workbook.
QPHY
Batt.
C
C
.093
LAYER 1
LAYER 2
LAYER 3
LAYER 4
LAYER 5
LAYER 6
LAYER 7
LAYER 8
LAYER 9
LAYER 10
LAYER 11
LAYER 12
1.5oz
1.0oz
0.5oz
0.5oz
1.0oz
0.5oz
1.0oz
1.0oz
0.5oz
0.5oz
1.0oz
1.5oz
SIGNAL
PLANE
SIGNAL
SIGNAL
PLANE
SIGNAL
PLANE
PLANE
SIGNAL
SIGNAL
PLANE
SIGNAL
SIGNAL: 1
PLANE: GND 1
SIGNAL: 3
SIGNAL: 4
PLANE: VCC_3.3, VCORE
SIGNAL: 5
PLANE: GND
PLANE: VCC_5, VCC_HOT_xxx
SIGNAL: 6
SIGNAL: 7
PLANE: GND
SIGNAL: 2
BURIED CAP LAYER OPTION
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Placement Guide and PCB Stackup
Time Changed: 2:06:05 pm
5
6
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Page:
04
8
1
2
4
3
VCC_12_BULK
VCC_12N
VCC_5
VCC_3.3
VCC_3.3
J2
atxpwr_12v_2x2vert
1
2
GND1
P12V4
GND2
P12V3
VCC_5
5
VCC_12
VCC_HOT_5
6
7
8
VCC_5
VCC_3.3
J6
4
J7
header.1x2
1
R54
atxpwr_2x10vert_nopeg
3
11
1
+3.3V_P11
2
-12V_P12
+3.3V_P2
GND_P13
GND_P3
14
PS_ON
15
GND_P15
16
GND_P16
17
GND_P17
18
-5V_P18
NC
R46
3
ATX POWER
13
A
4.7K
A
4
VCC_P4
VCC_5
5
VCC_12
GND_P5
6
P2
VCC_P6
conn.fan.3pos
7
GND_P7
8
1
PWRGOOD
19
9
VCC_P19
BK
2
VSTDBY
20
R53
4.7K
10
VCC_P20
CHASSIS POWER LED
2
220
+3.3V_P1
12
+12V_P10
PC FANSINK HEADER
RD
3
BL
FAN_TACH
+
C33
330uF
C32
330uF
+ 25V
25V
+ C34
+ C35
+ C36
330uF
25V
330uF
25V
330uF
25V
+ C38
330uF
25V
ATX CHASSIS POWER
R58
10
10
FAN_PWM
54D1
VCC_12
J8
VCC and VCC_3.3 on separate power planes.
PS_ON*
14C8
R56
54D1
R55
FANPWR
header.1x3
1
SHORT_POWER
CUBE FANSINK HEADER
2
10
3
NC
B
B
FORCE PSU ALWAYS ON
1
J3
header.1x2
2
R47
3.3K
CHASSIS RESET SWITCH
1
J4
header.1x2
2
R50
R45
PWRGD
100
R48
SW7
+
C39
0.1uF
6.8K
sw.1spdt
14C2
14B2
(3V)
100
C41
10uF
1
LOCAL RESET SWITCH
2
3
NC
VCC_3.3
SW9
sw.1spdt
R49
1
C
3.3K
R51
LOCAL EVENT SWITCH
C
EVENT*
2
14D2
14C2
3
NC
VCC_HOT_3.3
100
VCC_HOT_3.3
+
C40
0.1uF
C42
10uF
22ms
R43
4.7K
OPTION
22ms R-C delay, or FPGA
control (not both).
R44
220K
VCC_HOT_3.3
VCC_HOT_3.3
R1
RSMRST*
14E2
14D2
220
1
No_Stuff
CHASSIS POWER
1
J5
header.1x2
C37
0.1uF
2
2
U1
4
SB_RSMRST
R57
47K
1
74lvc1g125.sc70
VCC_3.3=VCC_HOT_3.3
PWRSWS*
2
SW10
10K
PWRSW*
4
VCC_3.3=VCC_HOT_3.3
1
C43
0.1uF
2
LOCAL POWER
D
14C8
74lvc1g125.sc70
R52
sw.1spdt
U2
D
3
NC
SB_RSMRST*
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
48C7
Gary Milliorn
4
Title: Power Entry, System Reset
Time Changed: 2:06:19 pm
5
6
Page:
7
05
8
2
1
3
5
4
VCC_HOT_3.3
6
7
VCC_HOT_5
VCC_HOT_3.3
A
14
15
16
C138
1.0uF
R63
R64
220K
10K
No_Stuff
8
C139
1.0uF
PH1
VIN1
PH2
VIN2
PH3
VIN3
PH4
C140
100uF
PH5
A
L3
10
3.3UH
9
1
AREA_FILL
2
8
7
+
6
C152
470uF
U18
tps54310pwp.htssop20
C148
0.047uF
HOT_RST*
15B1
4
PWRGD
19
SYNC
18
SS_ENA
TP2
BOOT
5
R69
10.0K
C151
2200pF
R68
PS_H33_PG
56B1
4
U56
C137
0.027uF
C470
0.1uF
13
12
2
11
1
74lvc1g125.sc70
21
VCC_3.3=VCC_HOT_3.3
VSENSE
2
750
PGND1
1%
PGND2
PGND3
R66
AGND
POWERPAD
20
TOP LAYER POUR FOR AGND
SEE LAYOUT RULES FOR VIAS TO GROUND PLANE
RES
C149
2200pF
3
18K
B
R67
3.74K
C150
47pF
17
RT
B
COMP
VBIAS
1
1%
1%
C145
0.1uF
R65
71.5K
1%
VCC_HOT_3.3
ACTEL POWER SEQUENCING
VCC_HOT_2.5
CR1
CR2
MBRS360T3
MBRS360T3
1
2
smc_403
No_Stuff
2
1
2
smc_403
No_Stuff
1
R4
10
3
4
SHORT_POWER
C
SHORT_POWER
VCC_HOT_3.3
5
rc1210
No_Stuff
NC
6
C143
100uF
C141
100uF
U7
OUT
nRESET_FB
C
TPS72525KTT
ddpak5
GND_TAB
Add 0.5 square inch fill to ground tab.
1
2
3
4
5
NC
6
C144
100uF
IN
GND
C146
1.0uF
VCC_HOT_1.8
C142
100uF
ENABLE
ENABLE
IN
GND
OUT
nRESET_FB
U8
TPS72518KTT
ddpak5
GND_TAB
Add 0.5 square inch fill to ground tab.
C147
1.0uF
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Cass Arnett
4
Title: Hot Power Supplies
Time Changed: 2:07:28 pm
5
6
Page:
7
06
8
1
2
3
VCC_3.3
4
6
5
VCC_5
7
8
VCC_12
Place caps close to pins.
A
R27
R28
R31
R33
680
1%
10K
10K
10
C21
1uF
cc0805
C19
1uF
cc0805
C25
0.1uF
C23
0.1uF
25V
cc0805
25V
cc0805
A
VCC_5
VCCA
C17
1uF
cc0805
CR4
MBR0530
sod_123
VTRC1
0
1
R24
0
12
nPG
42
19
14
VIN2
R23
VIN1
No_Stuff
PS_VCORE_PG
14B2,56D1
V5_2
V5_1
37
BSTRCD1
R35
100
rc0603
PG_DEL
VPN1
VCCA
BST1
43
VPN1
41
BST1
C27
1000pF
R38
16.2K
28
TG1
PS_CORE_EN
14C8
36
DRN1
EN
BG1
R32
0
44
DRIFT
B
20
0
11
1
10
2
9
3
8
4
7
5
6
6
5
20D1
sc458.mlp44
21
22
35
TP1
VID2
DRPp
VID3
VID4
DRPn
VID6_MSB
FBp
CS2n
FBn
TG2
NC
VREF
VPN2
HYS
3
4
38
33
C29
10nF
CS1P
cc0805
NPO
25V
32
B
23.7K
1%
No_Stuff
DRPP
DRPN
23
130K
1%
cc0805
NPO
25V
TG2
DRN2
BG2
16
17
18
13
15
R37
VPN2
82.5K
1%
1%
8C1
8D1
8D1
CS2P
1%
BST2
rc0603
C20
1000pF
34
R42
0
rc0603
C26
1000pF
VTRC2
C28
10nF
cc0805
NPO
R40
25V
1%
No_Stuff
ISH
C30
1uF
cc0805
C
VCC_5
CR5
MBR0530
BSTRCD2
23.7K
sod_123
CS2N
8C8
R34
2.40K
1%
C804
12pF
ERC
R30
30.1K
8C8
31
ISH
ERROUT
29
SS
DAC
26
AGND
DAC
C18
10nF
R26
8C8
30
R36
100
ERROUT
130K
1%
25
GND
SS
R29
8B8
CLSET
27
R25
8B1
8B1
R39
C
45
8A1
24
16.2K
HYS
BST2
CLSET
TG1
DRN1
BG1
39
VID5
BG2
2
1%
40
CS1N
VID1
DRN2
VREF
C31
1uF
cc0805
VID0_LSB
CS2p
VCORE_SENSEp
VCORE_SENSEn
20D1
DUAL
CS1n
CFG_VID(6:0)
14C8,17C1
CS1p
U38
R41
0
rc0603
C24
0.1uF
cc0805
25V
C22
560pF
VREF
R22
SC458_AGND
0
rc0603
D
D
All grounds tied together at output caps.
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Cass Arnett
4
Title: Processor VDD (Vcore) Supplies
Time Changed: 2:07:37 pm
5
6
7
Page:
07
8
1
2
3
4
5
6
7
8
VCC_12_BULK
C6
10uF
C4
10uF
C7
10uF
A
A
5
TG1
7B7
6
7
8
5
Q4
IRF7821
so8
4
1
2
6
7
0.5..1.5V
55A maximum
8
Q3
IRF7821
so8
4
3
1
2
3
VCORE
L2
DRN1
7B7
1
2
DRNx is the "+" end of the inductor.
CSxN is the "-" end of the inductor.
0.50UH
5
BG1
7B7
6
7
8
5
Q5
IRF7832
so8
4
6
7
8
5
Q2
IRF7832
so8
4
6
7
+
8
Q1
IRF7832
so8
4
1
D2
mbrs140lt3.smb403a
R12
R13
16.2K
1%
0
C10
390uF
2.5V
+
+
C12
390uF
2.5V
C14
390uF
2.5V
C471
0.1uF
C472
0.1uF
C473
0.1uF
Distribute caps along plane to processor.
No_Stuff
B
1
2
3
1
2
3
1
2
3
B
2
CS1N
7B7
33K
R14
18.2K
1%
C9
56nF
TH1
R17
NPO
cc0805
25V
47K
VCC_12_BULK
R18
DCR_DR1
DRPP
7B7
47K
Route CS1x, CS2x, DRPx and FBx
as differential pairs.
C2
10uF
C3
10uF
C16
100pF
R19
DCR_DR2
R21
26.1K
1%
47K
C5
10uF
C8
56nF
R20
NPO
cc0805
25V
DRPN
7B7
47K
TH2
C
C
R15
18.2K
5
TG2
7C7
6
7
8
5
Q7
IRF7821
4
6
7
2
1%
33K
Q8
IRF7821
4
so8
1
8
CS2N
7C7
so8
3
1
2
3
R11
R16
16.2K
1%
0
VCORE
L1
DRN2
7C7
1
2
0.50UH
5
6
7
8
5
6
7
Q10
BG2
7C7
4
8
5
6
7
Q9
IRF7832
so8
4
IRF7832
so8
+
8
C11
390uF
2.5V
+
C13
390uF
2.5V
+
C15
390uF
2.5V
C474
0.1uF
C806
0.1uF
C807
0.1uF
Q6
4
IRF7832
so8
1
D1
mbrs140lt3.smb403a
Distribute caps along plane to processor.
No_Stuff
1
2
1
3
2
3
1
2
3
2
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Cass Arnett
4
Title: Processor VDD (Vcore) Supply, Part 2
Time Changed: 2:07:45 pm
5
6
7
Page:
08
8
1
2
A
4
3
VCC_3.3
5
6
7
8
A
VCC_3.3
VCC_PLAT
1.0-1.2V @ 9A
VCC_PLAT
20
21
22
C790
1.0uF
R677
C791
1.0uF
C792
1.0uF
C793
1.0uF
10K
C794
100uF
6.3V
C796
100uF
6.3V
23
24
PH1
VIN1
PH2
VIN2
PH3
VIN3
PH4
VIN4
PH5
U50
VIN5
PH6
tps54910pwp.htssop28
PH7
PH8
PH9
TP170
PS_PLATFORM_EN
14C8
4
PWRGD
27
SYNC
26
SS_ENA
15
16
C795
0.033uF
17
18
19
B
TOP LAYER POUR FOR AGND
SEE LAYOUT RULES FOR VIAS TO GROUND PLANE
1
29
BOOT
1UH
7
1
AREA_FILL
2
8
9
+
10
11
C802
470uF
+
C803
470uF
4V
4V
12
13
C798
0.047uF
14
5
R682
10.0K
1%
C801
PGND1
PGND2
VSENSE
R681
2
750
PGND3
1%
2200pF
PGND4
PGND5
B
C799
AGND
COMP
VBIAS
PS_PLATFORM_PG
14B2,56D1
L13
6
3
Rset
18K
2200pF
C800
25
28
RT
POWERPAD
R679
47pF
R678
Rset
56.2K
42.2K
42.2K
1%
71.5K
1%
VCC_PLAT
1.05 V
1.10 V
CFG_PLATVDD
1 / ON
0 / OFF
Rset = sum of R680 + R156 (switch open)
Rset = R680 (switch closed)
VCC_3.3
R156
14.0K
1%
C797
0.1uF
VCC_PLAT SETTING
R680
U25
74cbtlv1g125dbv.so5
VCC
2
1
A
OE
B
GND
5
4
3
sop5
CFG_PLATVDD
14D8,17C1
C
C
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Wednesday, February 14, 2007
Engineer:
1.03
3
Cass Arnett
4
Title: Platform Power (nominally 1.1V)
Time Changed: 10:56:47 am
5
6
7
Page:
09
8
1
2
3
VCC_3.3
4
5
6
7
8
VCC_5
VCC_1.2
14
A
15
16
C737
1.0uF
R514
C738
1.0uF
PH1
VIN1
PH2
VIN2
PH3
VIN3
PH4
C740
100uF
PH5
VCC_1.2
1.2v @ 3.3A
L12
10
4.7UH
9
1
AREA_FILL
2
A
8
7
+
6
C746
470uF
U33
10K
tps54310pwp.htssop20
C743
0.047uF
PS_1.2V_PG
14B2,56D1
TP151
PS_1.2V_EN
14C8
4
PWRGD
19
SYNC
18
SS_ENA
BOOT
5
R519
10.0K
1%
C745
R518
13
12
11
1
TOP LAYER POUR FOR AGND
SEE LAYOUT RULES FOR VIAS TO GROUND PLANE
21
VSENSE
2
750
PGND1
1%
2200pF
PGND2
PGND3
C742
AGND
R516
3
18K
2200pF
C744
17
20
RT
POWERPAD
B
COMP
VBIAS
C739
0.027uF
R517
28.7K
1%
B
47pF
R515
C741
0.1uF
71.5K
1%
C
C
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Wednesday, February 14, 2007
Engineer:
1.03
3
Cass Arnett
4
Title: General 1.2V Power
Time Changed: 10:47:45 am
5
6
Page:
7
10
8
1
2
3
VCC_3.3
4
5
7
6
8
VCC_5
VCC_SERDES
14
15
A
16
R502
C717
1.0uF
C719
1.0uF
PH1
VIN1
PH2
VIN2
PH3
VIN3
PH4
C723
100uF
PH5
VCC_SERDES
Typically 1.1V @ 3.3A
L10
10
3.3UH
1
9
2
8
A
7
+
6
C735
470uF
U11
10K
tps54310pwp.htssop20
C729
0.047uF
PS_SERDES_PG
14C2,56C1
4
PWRGD
19
SYNC
18
SS_ENA
TP149
PS_SERDES_EN
14C8
BOOT
5
R512
10.0K
1%
C733
13
12
11
1
TOP LAYER POUR FOR AGND
SEE LAYOUT RULES FOR VIAS TO GROUND PLANE
21
VSENSE
R510
2
PGND1
750
1%
2200pF
PGND2
PGND3
C727
AGND
COMP
VBIAS
C720
0.027uF
R506
R508
18K
42.2K
1%
2200pF
C731
17
20
RT
POWERPAD
3
B
B
47pF
C725
0.1uF
R504
71.5K
1%
VCC_3.3
VCC_5
VCC_1.8
14
15
16
R503
C718
1.0uF
C721
1.0uF
PH1
VIN1
PH2
VIN2
PH3
VIN3
PH4
C724
100uF
PH5
L11
10
VCC_1.8
1.8V @ 3.3A
4.7UH
1
9
2
8
7
+
6
C736
470uF
U12
10K
tps54310pwp.htssop20
C730
C
C
0.047uF
PS_ULI_1.8V_PG
14C2,56C1
TP150
PS_ULI_1.8V_EN
14C8
4
PWRGD
19
SYNC
18
SS_ENA
BOOT
5
R513
10.0K
1%
C734
13
12
11
1
21
R511
2
PGND1
750
1%
2200pF
PGND2
PGND3
C728
AGND
POWERPAD
COMP
R507
3
18K
2200pF
C732
17
20
RT
TOP LAYER POUR FOR AGND
SEE LAYOUT RULES FOR VIAS TO GROUND PLANE
VSENSE
VBIAS
C722
0.027uF
R509
9.76K
1%
47pF
R505
C726
0.1uF
71.5K
1%
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
D
Cass Arnett
4
Title: SERDES 1.2V and PHY 1.8V Power
Time Changed: 2:08:11 pm
5
6
7
Page:
11
8
1
2
3
4
5
6
7
8
VCC_3.3
R70
MBUF1_PWR
SHORT_POWER
5
C155
0.1uF
C153
0.1uF
A
A
PHY Clocks
Fixed 125.0 MHz reference.
No special match requirements.
VCC_3.3
7
VDD
U9
125.000MHz
R71
PHYCLKPWR
SHORT_POWER 4
C154
0.1uF
5
V3.3V
2
OUT
GND
OE
3
1
UTPCLK
1CM_MAX
R73
33
1
PCLK
NC
EH2645TS-125.000M
NC
8
ICLK
Q1
U10
MPC94551EF
Q2
so8
Q3
OE
Q4
GND
2
UTPHYCLK0
1CM_MAX
R77
33
0
3
UTPHYCLK1
1CM_MAX
R78
33
1
4
UTPHYCLK2
1CM_MAX
R79
33
2
5
PHYCLK(0:2)
30D1,32B1
NC
6
VCC_3.3
R75
ICSCLKPWR
POWER_TRACE
10
B
+
B
C156
22uF
6.3V
OSCON
C157
0.1uF
R72
0
SRCCLK
7
1
SYSCLK_R(4:0)
20
GND2
CLK
4
28
3
27
2
26
1
25
0
24
X2
SYSCLK_EN
2
5
1
4
0
3
19
2CM_MAX
21
R81
22
33
UTLSYSCLK
Any Length
NC
R82
SYSCLK
0
19D1
Very Short
U14
ics525_02.ssop28
R6
V8
R5
V7
R4
V6
R3
V5
R2
V4
R1
V3
R0
V2
V1
SYSCLK_S(2:0)
15B1
GND1
REF
8
NC
2
15B8
VDD2
X1_ICLK
Very Short
R5
51
No_Stuff
C
9
23
conn.sma
No_Stuff
6
P1
conn.sma
No_Stuff
Very Short
15B8
C159
0.1uF
P7
VDD1
SYS_REFCLK
15B1
C158
0.1uF
S2
V0
18
17
7
16
6
15
5
14
4
13
3
12
2
11
1
10
0
SYSCLK Clock
Variable 1-200 MHz reference.
No special match requirements.
C
S1
S0
PDTS
R74
R76
R80
100
100
100
SYSCLK_V(7:0)
15A1
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: System Clock Generator
Time Changed: 2:08:21 pm
5
6
Page:
7
12
8
2
1
3
5
4
7
6
8
VCC_3.3
A
C783
C784
0.1uF
0.1uF
BCLK Clock
14.318 MHz reference.
No special match requirements.
VCC_3.3
7
VDD
1
R530
REFCLKPWR1
POWER_TRACE
5
+
C775
22uF
6.3V
OSCON
C779
0.1uF
C777
0.1uF
NC
VCC_3.3
8
Q1
ICLK
U54
MPC94551EF
Q2
so8
Q3
OE
REFCLKPWR2
POWER_TRACE
POWER_TRACE
Q4
GND
VCC_3.3
R531
2
1CM_MAX
R561
33
M1575_BCLK
3
1CM_MAX
R562
33
SIO_BCLK
4
1CM_MAX
R563
33
RTC_CLK
5
1CM_MAX
R564
33
AUD_CLK
47C8
54A1
19D1
50A1
6
R534
REFCLKPWR3
5
5
+
C776
22uF
6.3V
OSCON
C780
0.1uF
C778
0.1uF
+
C781
0.1uF
C782
22uF
6.3V
OSCON
VCC_3.3
REFCLKPWR0
4
V3.3V
OUT
3
UTRCLK
R529
33
RCLK
1
XIN_CLKIN
VCC_3.3
REFOUT
5
UTBCLK
1CM_MAX
R536
33
BCLK
1CM_MAX
C774
0.1uF
5
B
REFCLK (SerDes) Clock
100.0, 125.0 or 156.25 MHz (common)
Clocks routed as differential pairs.
No special match requirements.
48
VDDA
U52
14.318MHz
R528
10 14 19 31 36 40
VDD6
VDD7
3
P9
conn.sma
No_Stuff
VDD1
VDD2
VDD3
VDD4
VDD5
B
A
2
GND
OE
1
NC
2
R533
Very Short
NC
DIF0_P
DIF0_N
OE_0
X2
51
No_Stuff
DIF1_P
DIF1_N
OE_1
DIF2_P
DIF2_N
CFG_REFCLKSEL(2:0)
14B2,17C8
2
6
1
44
0
45
FS2
FS1
FS0
OE_2
DIF3_P
DIF3_N
OE_3
U53
ICS9FG108BG-LFT
tssop48
C
VCC_3.3
27
DIF4_P
DIF4_N
OE_4
SEL14M_25M
25
23
24
SDATA
SCLK
DIF6_P
DIF6_N
OE_6
IREF
DIF7_P
DIF7_N
OE_7
46
GND1
1CM_MAX
UTREFSD1P
1CM_MAX
R537
33
DIFF_CLK
RCLK1
41
UTREFSD1N
1CM_MAX
R538
33
DIFF_CLK
RCLK1
39
UTREFSD2P
1CM_MAX
R539
33
DIFF_CLK
RCLK2
38
UTREFSD2N
1CM_MAX
R540
33
DIFF_CLK
RCLK2
33
UTREFSL1P
1CM_MAX
R541
33
DIFF_CLK
RCLK3
32
UTREFSL1N
1CM_MAX
R542
33
DIFF_CLK
RCLK3
30
UTREFSL2P
1CM_MAX
R543
33
DIFF_CLK
RCLK4
29
UTREFSL2N
1CM_MAX
R544
33
DIFF_CLK
RCLK4
20
UTREFTAPP
1CM_MAX
R545
33
DIFF_CLK
RCLK5
21
UTREFTAPN
1CM_MAX
R546
33
DIFF_CLK
RCLK5
17
UTREFULIP
1CM_MAX
R547
33
DIFF_CLK
RCLK6
18
UTREFULIN
1CM_MAX
R548
33
DIFF_CLK
RCLK6
4
15
35
44C8
44C8
REFCLK_SD2p
REFCLK_SD2n
42C7
42C7
37
REFCLK_SLOT1p
REFCLK_SLOT1n
43A1
REFCLK_SLOT2p
REFCLK_SLOT2n
45A1
REFCLK_TAPp
REFCLK_TAPn
45C1
REFCLK_M1575p
REFCLK_M1575n
46A1
43B1
34
45A1
28
C
45C1
22
46A1
16
11
NC
R549
R550
R551
R552
R553
R554
R555
R556
R557
R558
R559
R560
NC
51
51
51
51
51
51
51
51
51
51
51
51
12
13
REFCLK TERMINATION
Both series and parallel are near the clock source.
8
NC
9
NC
7
NC
R535
0
R532
475
1%
REFCLK_SD1p
REFCLK_SD1n
43
GNDA
19C8,23D1,24D1,27D1,28D1,#6
I2C2_SDA
I2C2_SCL
SPREAD
GND3
19C8,23D1,24D1,27D1,28D1,#6
26
DIF5_P
DIF5_N
OE_5
GND2
17D8
CFG_REFSPREAD
DIF_STOP
42
47
TEST: Connect pin 1 to U53 pin 16
to disable ULI REFCLK. Required to
test Serial RapidIO modes.
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: RefClk (SERDES) and base clock.
Time Changed: 2:08:30 pm
5
6
7
Page:
13
8
1
2
3
4
5
VCC_HOT_3.3
6
7
8
VCC_HOT_2.5
U49
apa150.1of2.fbga256
E6
E7
C752
0.1uF
C751
0.1uF
C754
0.1uF
C753
0.1uF
C758
0.1uF
C755
0.1uF
C761
0.1uF
E10
C762
0.1uF
A
R524
R525
10K
10K
E11
F5
F12
G5
G12
C756
VCC_HOT_2.5
NC
NC
NC
NC
NC
NC
NC
NC
C759
16V
C757
J34
conn.2x13
0.1uF
K5
0.1uF
K12
16V
0.1uF
C760
L5
0.1uF
L12
16V
16V
1
2
M6
3
4
M7
5
6
M10
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10CM_MAX
M11
10CM_MAX
P14
10CM_MAX
R15
10CM_MAX
P13
10CM_MAX
R14
10CM_MAX
R16
10CM_MAX
T15
10CM_MAX
N14
P15
26
VDDP_1
VDDP_2
VDDP_3
VDD_1
GND
See MapFile
VDD_2
VDD_3
VDDP_4
VDD_4
VDDP_5
VDD_5
VDDP_6
VDD_6
VDDP_7
VDD_7
VDDP_8
VDD_8
VDDP_9
VDD_9
VDDP_10
VDD_10
VDDP_11
VDD_11
VDDP_12
VDD_12
VDDP_13
VDD_13
VDDP_14
VDD_14
VDDP_15
VDD_15
VDDP_16
VDD_16
VPP
AVDD_1
VPN
AVDD_2
F7
F8
F9
C765
0.1uF
C763
0.1uF
F10
C768
0.1uF
C767
0.1uF
C769
0.1uF
G11
H6
H11
J6
K6
K11
L7
L8
L9
L10
VCC_1.8
J11
VCC_HOT_2.5
J3
R526
J15
APA150_VDDPWR
2CM_MAX
5
C764
0.22uF
R527
C766
0.22uF
10K
1
TDO
2
TMS
AGND_1
AGND_2
C773
0.1uF
A
TDI
TRST
C772
0.1uF
G6
TCK
RCK
C771
0.1uF
C770
0.1uF
U51
MEM_RST*
4
23D1,24D1,27D1,28D1
H4
H15
74lvc1g125.sc70
B
B
A2
17B8,18B1
13C1,17C8
17B8
17B8,38B1
5B8
7B1,56D1
9B1,56D1
10A1,56D1
11A1,56C1
11C1,56C1
25B8,56C1
29B8,56C1
19D8,56B1
15C1,16B8
18D1
18D1
C
18D1
19C1
5C8
19C1
19C1
19C1
19C1
19B1
18C1
46C8
CFG_PORTDIV
CFG_REFCLKSEL(2:0)
CFG_FLASHMAP
CFG_FLASHBANK
PWRGD
PS_VCORE_PG
PS_PLATFORM_PG
PS_1.2V_PG
PS_SERDES_PG
PS_ULI_1.8V_PG
M1_DDR_IOPWRGD
M2_DDR_IOPWRGD
0
A3
1
A4
2
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
IO_A2
IO_A3
IO_C13
IO_A4
IO_C14
IO_A5
IO_C15
IO_A6
IO_C16
B1
0
B2
1
B3
2
B4
COP_HRST*
COP_SRST*
COP_TRST*
HRESET_REQ*
EVENT*
CPU_HRST*
CPU_TRST*
SRESET_0*
SRESET_1*
SPARE01*
CFGDRV*
SB_CPURST*
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
IO_A8
IO_D1
IO_A9
IO_D2
IO_A10
IO_D3
IO_A11
IO_D4
IO_A12
IO_D5
IO_A13
IO_D6
IO_A14
IO_A15
IO_D7
IO_D8
IO_B1
IO_D10
IO_B2
IO_D11
IO_B3
IO_D12
IO_B4
IO_B5
IO_B6
IO_B7
IO_D13
IO_D14
IO_D15
IO_D16
46C8
48C7
48D7
5D1
54B1
19B1,46C8,54B1
43B1,45A1
D
freescale
semiconductor
1
4
C2
5
C3
6
C4
SB_INIT*
SB_OFFPWR_S3*
C5
C6
TP164
SB_PWG
RSMRST*
PME*
SMI*
PEX_RST*
C7
C8
C9
C10
C11
C12
Freescale Semiconductor
TM
C1
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
IO_B9
IO_E1
IO_B10
IO_E2
IO_B11
IO_E3
IO_B12
IO_E4
IO_B13
IO_E5
IO_B14
IO_E8
IO_B15
IO_E9
IO_B16
IO_E12
IO_C1
IO_E14
IO_C2
IO_E15
IO_C3
32B1
D1
48C7
7
D2
V3_CBE*(3:0)
0
D3
8
D4
9
D5
D6
D7
TP166
D8
D9
D10
TP167
D12
D13
D14
0
D16
1
PWRSW*
PS_ON*
5D8
PS_CORE_EN
PS_PLATFORM_EN
7B1
5B1
9B1
PS_1.2V_EN
PS_SERDES_EN
PS_ULI_1.8V_EN
SB_OFFPWR_S4_S5*
CFG_BOOTSEQ(0:1)
D11
D15
15C1,16B8
10B1
11A1
11C1
48C7
17A8,18B1
C
IO_E16
10
E1
E2
11
E3
12
E4
13
E5
0
E8
1
E9
2
E12
3
E13
4
E14
5
E15
6
CFG_VID(6:0)
7B1,17C1
CFG_PLATVDD
E16
IO_C5
IO_F1
IO_C6
IO_F2
IO_C7
IO_F3
IO_C8
IO_F4
IO_C9
IO_F13
IO_C10
IO_F14
IO_C11
IO_F15
IO_C12
IO_F16
F1
14
9C1,17C1
F2
15
F3
1
V3_PAR
CFG_BOOTLOC(0:3)
F4
F13
0
F14
1
F15
2
F16
3
16B8
17B1,18A1
D
Date Changed: Thursday, February 1, 2007
Engineer:
3
C16
IO_C4
HPCN: Argo Navis
1.03
C15
32B1
38C1,39C1,41C1
IO_B8
IO_E13
3
C14
IO_A7
IO_D9
ASLEEP
V3_AD(31:0)
PHYRST*
LB_RST*
GEN_RST*
PWRSWX*
C13
Stephen Foster
4
Title: PIXIS System Controller, Page 1
Time Changed: 2:08:40 pm
5
6
7
Page:
14
8
1
2
3
4
A
5
6
7
8
A
U49
apa150.2of2.fbga256
V3_SERR*
V3_PERR*
V3_STOP*
V3_DEVSEL*
SYSCLK_V(7:0)
16A8
16A8
16A8
16A8
12D1
G1
G2
G3
G4
0
G13
1
G14
PIXIS_DEBUG(0:1)
41C1
0
G15
1
G16
12C1
H1
H2
H3
TP155
VCC_HOT_3.3
2
H5
3
H12
U48
33.000MHz
R520
H13
TP158
H14
5
4
C749
22uF
6.3V
OSCON
C750
0.1uF
V3.3V
OUT
UTHOTCLK
3
33
R521
HOTCLK
H16
2
GND
OE
1
J1
TP159
NC
J2
NC
J4
J5
5
PCICLK_SB
R691
J12
33
J13
NC
SYS_REFCLK
PCI_CLK(0:4)
47A8,51B1,54A1,55B1
R522
33
16A8
16A8
14B8,16B8
17A8,18B1
2
J16
K3
K4
2
0
K13
1
K14
0
K15
1
K16
IO_N4
IO_G13
IO_N5
IO_G14
IO_N6
IO_N7
IO_G15
IO_N8
IO_G16
IO_N10
GL1
IO_N11
NPECL1
IO_N12
IO_H5
IO_N13
IO_H12
IO_N15
IO_H13_GLMX2
IO_N16
L1
17
L2
18
L3
19
L4
C
0
L13
1
L14
2
L15
3
L16
IO_P1
GL4
GL2
IO_P3
PPECL1
IO_P4
IO_J4
IO_P5
IO_J5
IO_P6
IO_J12
IO_P7
PPECL2
IO_P8
IO_J14
IO_P9
IO_P10
GL3
IO_K1
IO_P12
IO_K2
M1
21
M2
22
M3
23
M4
CFG_COREPLL(0:4)
17A1,18A1
CFG_SYSCLK(0:2)
17A1
0
M5
1
M8
2
M9
3
M12
4
M13
0
M14
1
M15
2
M16
R523
33
19
N2
3
N3
24
N4
25
N5
0
N6
2
LB_WE*(0:3)
LB_GPL(0:5)
FCS*
PJCS*
PASS_LED*
FAIL_LED*
LB_CS*(0:3)
N7
N8
N9
N10
N11
0
N12
1
N13
2
N15
3
N16
18B8,37D8,38B1,41B1
18B8,37D8,38B1,39A1,41C1
38B1
38B1
56A1
56A1
37D8,39A1,41C1
4
IO_P16
P1
26
P2
27
P3
28
P4
29
P5
P6
0
P7
1
P8
2
P9
3
P10
4
P11
0
P12
1
P16
2
B
LB_CLK(0:1)
1
37D8,41A1
SYSCLK_R(4:0)
12C1
SYSCLK_S(2:0)
12C1
IO_K3
IO_K4
IO_R1
IO_K13
IO_R2
IO_K14
IO_R3
IO_K15
IO_R4
IO_R5
IO_K16
IO_L1
IO_R7
IO_L2
IO_R8
IO_L3
IO_R9
IO_L4
IO_R10
IO_L13
IO_R11
IO_L14
IO_R12
IO_L15
IO_R13
R1
30
R2
31
V3_REQ*
V3_GNT*
IRQ*(0:11)
CF_RDYBSY*
CF_CD*
LB_A(0:31)
R3
R4
R5
8
R6
R7
R8
31
R9
30
R10
29
R11
28
R12
27
R13
26
IO_M1
IO_T3
IO_M2
IO_T4
IO_M3
IO_T5
IO_M4
IO_T6
IO_M5
IO_T7
IO_M8
IO_T8
IO_M9
IO_T9
IO_M12
IO_T10
IO_M13
IO_T11
IO_M14
IO_T12
IO_M15
IO_T13
IO_M16
IO_T14
T2
0
T3
1
16B8
16B8
19B1,32A1,46C8
39B1
39B1
37D8,38A1,39A1,41B1
C
IO_L16
IO_T2
20
N1
NPECL2
IO_R6
16
CFG_CCBPLL(0:3)
17B1,18A1
J14
K2
V3_AD(31:0)
14C2,16B8
1CM_MAX
K1
CFG_PIXISOPT(0:1)
17B8
IO_G4
IO_P11
V3_TRDY*
V3_IRDY*
V3_FRAME*
V3_CBE*(3:0)
CFG_HOSTMODE(0:1)
16A8
IO_N3
IO_P2
4
12B1
IO_G3
1CM_MAX
B
47A8
IO_N2
IO_H3_GLMX1
NC
+
IO_G2
IO_N9
HOT_RST*
SYSCLK_EN
6B1
IO_N1
IO_G1
V3_INT*(0:1)
16B8
DATABLIZZARD_INTD*
T4
T5
6
T6
7
T7
0
T8
1
T9
2
T10
3
T11
4
T12
5
T13
6
T14
7
51A8
LB_D(0:31)
37D8,38A1,39A1,41A1
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
Date Changed: Thursday, February 1, 2007
HPCN: Argo Navis
Engineer:
1.03
3
Stephen Foster
4
Title: PIXIS System Controller, Page 2
Time Changed: 2:09:03 pm
5
6
7
Page:
15
8
1
2
3
4
5
6
7
8
VCC_5
C747
0.1uF
U46
A
A
SN74CBTD16211DGGR
56
55
PCI_FRAME*
PCI_DEVSEL*
PCI_IRDY*
PCI_TRDY*
PCI_STOP*
PCI_PERR*
PCI_SERR*
PCI_REQ*(0:2)
PCI_GNT*(0:2)
PCI_CBE*(3:0)
47C1,51B1
47C1,51B1
47C1,51B1
47C1,51B1
47C1,51B1
51B1
47C1,51B1
47D1,51B1
47C1,51B1
47B1,51C1
2
3
4
5
6
7
9
2
2
PCI_INT*(0:3)
47C1,51C1
PCI_PAR
PCI_AD(31:0)
47A1,51D1
11
0
12
1
13
2
14
3
15
0
16
1
47C1,51C1
10
18
20
31
B
21
30
22
29
23
28
24
27
25
26
26
25
27
24
28
1OE
VCC
2OE
NC
1A1
1B1
1A2
1B2
1A3
1B3
1A4
VCC
1A5
17
1A6
1B7
1A8
1A10
1A11
1A12
2A1
1B5
1B6
1A7
1A9
1B4
1B8
GROUND
1B9
8
1B10
19
1B11
38
49
1B12
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
NC
2B5
2A6
1
2B6
2A7
2B7
2A8
2B8
2A9
2B9
2A10
2B10
2A11
2B11
2A12
2B12
17
1
NC
V3_FRAME*
V3_DEVSEL*
V3_IRDY*
V3_TRDY*
V3_STOP*
V3_PERR*
V3_SERR*
V3_REQ*
V3_GNT*
V3_CBE*(3:0)
54
53
52
51
50
48
47
46
45
44
0
43
1
42
2
41
3
40
0
39
1
31
35
30
34
29
33
28
32
27
31
26
30
25
29
24
15A1
15B1
15B1
15A1
15A1
15A1
15C8
15C8
14B8,15C1
V3_INT*(0:1)
15C8
V3_PAR
V3_AD(31:0)
37
36
15B1
14D8
14C2,15C1
B
tssop56
C748
0.1uF
U47
SN74CBTD16211DGGR
56
55
23
22
21
20
19
C
2
3
4
5
6
18
7
17
9
16
15
10
11
14
12
13
13
12
14
11
15
10
16
9
8
7
6
18
20
21
22
5
23
4
24
3
25
2
26
1
27
0
28
1OE
VCC
2OE
NC
1A1
1B1
1A2
1B2
1A3
1B3
1A4
VCC
1B4
1A5
17
1B5
1A6
1B6
1A7
1B7
1A8
1A9
1B8
GROUND
1B9
8
1B10
1A11
19
1B11
1A12
38
1A10
2A1
49
1B12
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
NC
2B5
2A6
1
2B6
2A7
2B7
2A8
2B8
2A9
2B9
2A10
2B10
2A11
2B11
2A12
2B12
17
1
NC
54
23
53
22
52
21
51
20
50
19
48
18
47
17
46
16
45
15
44
14
43
13
42
12
41
11
40
10
39
9
37
8
36
7
35
6
34
5
33
4
32
3
31
2
30
1
29
0
C
tssop56
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: PCI 5V-to-3V Level Translators
Time Changed: 2:09:15 pm
5
6
7
Page:
16
8
2
3
4
5
1K
1K
1K
1K
R633
R637
R641
1K
R625
R629
1K
1K
R621
1K
R613
R617
1K
1K
R607
R610
1K
1K
R601
R604
1K
1K
R598
1K
R595
1K
1
16
1
16
0
1
2
15
2
15
1
2
3
14
3
14
0
3
4
13
4
13
1
4
5
12
5
12
0
0
6
11
6
11
1
1
7
10
7
10
2
2
8
9
8
9
3
4.7K
4.7K
1K
R642
R673
1K
R638
R669
1K
R634
4.7K
1K
R630
4.7K
1K
R626
2
3
14
3
14
3
4
13
4
13
0
5
12
5
12
0
1
6
11
6
11
1
2
7
10
7
10
0
3
8
9
8
9
1
4.7K
4.7K
4.7K
4.7K
4.7K
R658
R662
R666
R670
R674
R643
4.7K
1K
1K
R639
R654
1K
R635
4.7K
1K
R631
4.7K
1K
R627
R650
1K
R623
R646
1K
1K
R615
R619
1K
1K
R609
R612
1K
1K
R603
R606
1K
R600
4.7K
R587
1K
4.7K
R584
R597
4.7K
R581
1K
4.7K
R578
1K
4.7K
R575
R591
4.7K
R572
VCC_3.3
R594
4.7K
4.7K
R566
R569
VCC_3.3
16
1
16
5
2
15
2
15
4
3
14
3
14
2
1
0
4
13
4
13
2
5
12
5
12
1
6
11
6
11
7
10
7
10
9
8
14B2
14B2,38B1
38C1,55B1
14B2,18B1
15C1
CFG_LADOPT(0:1)
B
18B1
30A8
CFG_CPUBOOT
CFG_BOOTADDR
CFG_REFCLKSEL(2:0)
18B1
18B1
13C1,14B2
CFG_SERROM_ADDR
CFG_MEMDEBUG
CFG_DDRDEBUG
40A1
18C1
18C1
4.7K
4.7K
4.7K
4.7K
4.7K
R667
R671
R675
4.7K
R655
R663
4.7K
R659
4.7K
1K
10
8
9
R648
4.7K
7
47B8
47B8,50B1
47B8
48C7,56B1
13C1
48D7
40C8
4.7K
11
R672
6
47B8,50B1
D
R676
12
4.7K
5
R668
13
4.7K
4
4.7K
14
R664
3
ACZ_SYNC
ACB_SYNC
ACZ_SDOUT
ACB_SDOUT
SUSLED
CFG_REFSPREAD
ACPWR
CFG_IDWP
R660
15
4.7K
16
2
4.7K
1
R656
1K
R651
C
SW8
sw.8spst.cts
R644
R640
1K
R636
1K
R632
R588
1K
R624
4.7K
R585
1K
4.7K
R582
1K
4.7K
R579
CFG_FLASHMAP
CFG_FLASHBANK
CFG_FLASHWP*
CFG_PORTDIV
CFG_PIXISOPT(0:1)
9
VCC_3.3
R620
R616
4.7K
R576
1K
4.7K
4.7K
R573
4.7K
4.7K
R567
R570
VCC_HOT_3.3
Date Changed: Thursday, February 1, 2007
Engineer:
3
18B1
sw.8spst.cts
HPCN: Argo Navis
1.03
CFG_IOPORTS(0:3)
SW6
1
Project:
14C8,18B1
CFG_ASMP
6
Revision:
CFG_BOOTSEQ(0:1)
A
sw.8spst.cts
R628
2
R665
1K
R622
15
D
1
4.7K
1K
R618
2
C
semiconductor
R661
1K
R614
15
sw.8spst.cts
7700 W. Parmer Ln
Austin, Texas 78729
R657
1K
R611
2
8
Freescale Semiconductor
4.7K
1K
R608
16
1
CFG_PLATVDD
TM
4.7K
1K
R605
1
0
freescale
R653
1K
R602
4.7K
1K
R599
16
3
9C1,14D8
R649
1K
R596
1
SW3
CFG_VID(6:0)
15C1,18B1
SW5
0
sw.8spst.cts
7B1,14C8
R645
1K
R586
1K
4.7K
4.7K
R583
R593
4.7K
R580
VCC_3.3
R590
4.7K
4.7K
R577
4.7K
R571
R574
4.7K
4.7K
R565
R568
VCC_3.3
R647
CFG_BOOTLOC(0:3)
14D8,18A1
B
CFG_HOSTMODE(0:1)
sw.8spst.cts
SW2
CFG_CCBPLL(0:3)
8
SW4
0
sw.8spst.cts
15C1,18A1
7
VCC_3.3
4.7K
CFG_SYSCLK(0:2)
15D1
R592
SW1
CFG_COREPLL(0:4)
15C1,18A1
A
R589
VCC_3.3
6
R652
1
Gary Milliorn
4
Title: General Configuration
Time Changed: 2:09:24 pm
5
6
Page:
7
17
8
1
2
3
4
5
6
7
8
U22
74lvc16244adgg.tssop48
CFG_CCBPLL(0:3)
15C1,17B1
0
47
2
28
1
46
3
29
2
44
5
30
3
43
6
31
1
A1
OE1
Y1
LB_LA(27:31)
37A8,41B1
VCC_3.3
7
CFG_COREPLL(0:4)
15C1,17A1
A
0
1
41
18
8
0
40
31
9
1
11
2
12
3
2
38
3
37
48
CFG_BOOTLOC(0:3)
14D8,17B1
A2
42
Y2
LB_DP(0:3)
A
OE2
4
36
13
0
35
14
R323
330
0
1
33
16
R324
330
1
2
32
17
R325
330
2
R326
330
3
25
37A8,41C1
A3
Y3
GND
OE3
27
TSEC2_TXD(3:0)
30B1,31B1
4
10
CFG_HOSTMODE(0:1)
15C1,17A8
3
30
0
29
1
27
CFG_CPUBOOT
17C8
15
A4
26
24
19
21
28
34
Y4
39
20
2
22
3
23
0
LB_WE*(0:3)
45
15A8,37D8,38B1,41B1
Route TSECxxx lines through pin 2 of these
330-ohm resistors (no stubs in path).
OE4
tssop48
U23
74lvc16244adgg.tssop48
CFG_BOOTADDR
CFG_PORTDIV
CFG_IOPORTS(0:3)
17C8
14B2,17B8
17A8
B
47
2
R692
330
0
46
3
R157
330
1
5
R327
330
0
6
R328
330
1
0
44
1
43
1
Y1
A1
OE1
TSEC1_TXD(3:0)
TSEC4_TXD(3:0)
30A1,31A1
30B8,31B8
B
VCC_3.3
7
2
3
CFG_BOOTSEQ(0:1)
14C8,17A8
41
18
8
R329
330
2
40
31
9
R330
330
3
0
38
1
37
48
CFG_LADOPT(0:1)
17B8
A2
42
Y2
11
3
12
5
36
13
29
1
35
14
30
NC
NC
Y3
A3
32
25
15A8,37D8,38B1,39A1,41C1
OE2
0
33
LB_GPL(0:5)
17
GND
OE3
16
LB_LAD(0:31)
37A8
NC
NC
4
10
CFG_MEMDEBUG
CFG_DDRDEBUG
17C8
17C8
21
29
NC
NC
CFGDRV*
14C2
15
30
27
A4
26
24
34
39
45
Y4
19
R331
330
0
20
R332
330
1
22
23
NC
NC
OE4
VCC_3.3
C
28
P8
conn.banjo_alt
tssop48
C
CLK_QUALn
10.0K
10.0K
1K
10.0K
10.0K
10.0K
10.0K
10.0K
10.0K
10.0K
10.0K
Place near CPU.
CLK_QUALp
TRIG_OUT
TRIG_IN
19B8
MDVAL2
D2_MSRCID(4:0)
19B8
A15
A13
19B8
GROUND
A2, A5, A8, A11, A14
CPU_TDO
CPU_TDI
19C1
19C1
CPU_TCK
CPU_TMS
COP_SRST*
COP_HRST*
CKSTP_OUT*
19C1
19C1
14C2
14C2
19C1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R322
header_riscwatch
R321
(MSB)
R320
R319
R318
R317
R316
R315
R314
R313
R312
B2, B5, B8, B11
J26
D7p
D7n
D6n
D6p
D5p
D5n
D4n
NC
D4p
CPU JTAG Header
D3p
D3n
NC KEY
D2n
D2p
D1p
D
semiconductor
1
D0n
(LSB)
COP_TRST*
14C2
freescale
D1n
CKSTP_IN*
19C1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
3
B10
A12
A10
TP109
TP110
TP111
TP112
B9
B7
4
A9
3
A7
2
B6
1
B4
0
MDVAL1
D1_MSRCID(4:0)
A6
A4
4
B3
3
B1
2
A3
1
A1
0
19B8
19B8
19B8
D
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
D0p
B12
Gary Milliorn
4
Title: Configuration Buffer; COP and Debug
Time Changed: 2:09:33 pm
5
6
7
Page:
18
8
2
3
VCC_3.3
4
VCC_3.3
5
6
1K
4.7K
4.7K
4.7K
4.7K
R112
R113
R114
R115
R116
1K
1K
R111
1K
R109
R110
4.7K
4.7K
R107
R108
4.7K
4.7K
R105
R106
4.7K
R101
4.7K
4.7K
R100
E31
E32
D32
F30
TP6
F31
TP7
F32
TP8
DMA_DREQ0
DMA_DREQ1
SYSTEM
TEMP_ANODE
TEMP_CATHODE
DMA_DACK0
DMA_DACK1
DMA_DDONE0
TP9
TP11
SMI*
L16
D1_MSRCID1
MCP_1
D1_MSRCID2
D1_MSRCID3
SMI_0
SMI_1
SPARE01*
J17
SPARE1
1
G29
2
H27
J23
3
M23
4
5
J27
6
F28
7
J24
L23
8
B30
9
C30
10
D30
11
D1_MSRCID4
D1_MDVAL
D2_MSRCID0
D2_MSRCID1
G28
0
IRQ0
D2_MSRCID2
IRQ1
D2_MSRCID3
IRQ2
D2_MSRCID4
D2_MDVAL
IRQ3
0
R118
0
TP14
J13
F15
MCP_0
L15
R117
Y11
TRIG_IN
TRIG_OUT_READY_QUIESCE
D1_MSRCID0
F17
H17
AA11
J14
DMA_DDONE1
TP10
IRQ*(0:11)
4.7K
4.7K
4.7K
4.7K
R97
R99
4.7K
R96
R98
4.7K
4.7K
R95
R93
R94
4.7K
4.7K
R92
4.7K
4.7K
R89
4.7K
4.7K
R88
R91
4.7K
R87
R90
4.7K
4.7K
R85
R86
4.7K
4.7K
R83
R84
U32
TP5
15C8,32A1,46C8
A
mc8641d.1of9.system.cbga1023
TP4
14C2
R104
MPC8641 V1.0("PD4") - Pulldowns
MPC8641 V2.0("PD6") - Pullups
0
4.7K
R698
0
No_Stuff
R103
R699
TP3
B
8
VCC_3.3
IRQ[0:7] Pullup/Pulldowns
A
14D2,46C8,54B1
7
VCC_3.3
R102
1
IRQ4
1
K14
2
H15
3
G15
4
54C1
TRIG_IN
TRIG_OUT
18C8
54C1
18C8
D1_MSRCID(4:0)
0
K15
TEMP_ANODE
TEMP_CATHODE
18D8
MDVAL1
J16
E16
0
C17
1
F16
2
H16
3
K16
4
18D8
D2_MSRCID(4:0)
18D8
B
MDVAL2
D19
18D8
C18
IRQ5
LSSD_MODE
IRQ6
TEST_MODE0
IRQ7
TEST_MODE1
IRQ8_AUX_CLKOUT
TEST_MODE2
IRQ9_DMA_DREQ3
TEST_MODE3
C16
E17
D18
D16
IRQ10_DMA_DACK3
IRQ11_DMA_DDONE3
0
R6
0
J26
IRQ_OUT
CKSTP_IN*
CKSTP_OUT*
18D1
18D1
L17
14C2
14C2
14C2
C21
IIC2_SDA
IIC2_SCL
B18
C20
I2C1_SDA
I2C1_SCL
A16
B17
CKSTP_IN
CKSTP_OUT
K18
IIC1_SDA
IIC1_SCL
L18
CPU_HRST*
HRESET_REQ*
SRESET_0*
SRESET_1*
14C2
C
No_Stuff
40A8
40A8
I2C2_SDA
I2C2_SCL
A21
B21
13C1,23D1,24D1,27D1,28D1,#6
13D1,23D1,24D1,27D1,28D1,#6
HRESET
HRESET_REQ
UART1_TXD
UART1_RXD
UART1_CTS*
UART1_RTS*
D31
SRESET_0
UART_SOUT1
SRESET_1
UART_SIN1
UART_CTS1
B32
A31
C31
36A1
36B1
36B1
UART_RTS1
UART2_TXD
UART2_RXD
A32
18C1
18D1
18D1
14C2
UART_SOUT2
J18
CPU_TDI
CPU_TDO
CPU_TCK
CPU_TMS
CPU_TRST*
18D1
G18
H18
F18
A17
TDI
TDO
TCK
UART_SIN2
UART_CTS2
B31
36A1
36B1
TP15
E30
TP16
UART_RTS2
TMS
TRST
C32
C
36B1
AG26
RSVD10
AD24
RSVD9
K17
RTC_CLK
SYSCLK
13A8
12B8
C19
RTC
G16
C1
SYSCLK
ASLEEP
ASLEEP
R7
R8
1K
No_Stuff
TP12
100pF
14C2,56B1
B16
CLK_OUT
49.9
No_Stuff
TP13
No_Stuff
CLKOUT: Place outside
the socket outline on the
top layer.
Option: EMI Suppression
and external clock term.
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: MC8641D System Interfaces
Time Changed: 2:09:43 pm
5
6
Page:
7
19
8
2
1
3
4
5
7
6
8
VCORE
R59
SHORT_POWER
10
C74
2.2uF
C66
2.2uF
U32
C82
0.1uF
VCC_PLAT
mc8641d.8of9.power.cbga1023
B20
AVDD_CORE0
AVDD_PLAT
B19
R61
SHORT_POWER
10
A
L12
L13
C44
0.1uF
C48
0.1uF
C54
0.1uF
C68
0.1uF
C60
0.1uF
C76
0.1uF
C90
0.1uF
C83
0.1uF
L14
M13
M15
N12
N14
P11
C45
0.1uF
C49
0.1uF
C55
0.1uF
C61
0.1uF
C77
0.1uF
C69
0.1uF
C91
0.1uF
C84
0.1uF
P13
P15
R12
R14
T11
T13
C50
0.1uF
C56
0.1uF
C62
0.1uF
C70
0.1uF
C78
0.1uF
C85
0.1uF
C92
0.1uF
T15
U12
U14
V11
V13
V15
W12
W14
B
Bypass Capacitor Placement
Refer to design workbook for detailed
placement.
Y12
Y13
Y15
AA12
AA14
AB13
VCORE
R60
SHORT_POWER
M14
P14
10
C67
2.2uF
R16
R18
C51
0.1uF
C57
0.1uF
C63
0.1uF
C79
0.1uF
C71
0.1uF
C93
0.1uF
C87
0.1uF
R20
T17
T19
T21
T23
C
U16
C47
0.1uF
C52
0.1uF
C58
0.1uF
C64
0.1uF
C80
0.1uF
C72
0.1uF
C88
0.1uF
C94
0.1uF
U18
U22
V17
V19
V21
V23
C53
0.1uF
C59
0.1uF
C65
0.1uF
C73
0.1uF
C81
0.1uF
C89
0.1uF
C95
0.1uF
W16
W18
W20
W22
Y17
Y19
Y21
Y23
AA16
AA18
FOR MC8641D: V1.0
VCORE_0 and VCORE_1 are connected
internally.
AA20
AA22
AB23
R2
0
AC24
AVDD_LBIU
VCORE_SENSEp
VCORE_SENSEn
7C1
7C1
U20
V20
R3
0
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
LVDD_1
LVDD_2
LVDD_3
TVDD_1
TVDD_2
TVDD_3
C116
0.1uF
C109
2.2uF
AC20
VDD_ENET_IO
VCC_3.3
AD23
AH22
F1
SHORT_POWER
AC17
AG18
C98
0.1uF
AK20
2A
Z=115ohms
C110
0.1uF
C103
0.1uF
VCC_SERDES
VDD_CORE1_1
VDD_CORE1_2
VDD_CORE1_3
VDD_CORE1_4
VDD_CORE1_5
VDD_CORE1_6
VDD_CORE1_7
VDD_CORE1_8
VDD_CORE1_9
VDD_CORE1_10
VDD_CORE1_11
VDD_CORE1_12
VDD_CORE1_13
VDD_CORE1_14
VDD_CORE1_15
VDD_CORE1_16
VDD_CORE1_17
VDD_CORE1_18
VDD_CORE1_19
VDD_CORE1_20
VDD_CORE1_21
VDD_CORE1_22
VDD_CORE1_23
VDD_CORE1_24
VDD_CORE1_25
VDD_CORE1_26
VDD_CORE1_27
VDD_CORE1_28
H31
SHORT_POWER
B
J29
K28
K32
C99
0.1uF
C104
0.1uF
C111
0.1uF
C117
0.1uF
C121
0.1uF
C125
0.1uF
C129
0.1uF
C133
0.1uF
C100
0.1uF
C105
0.1uF
C112
0.1uF
C118
0.1uF
C122
0.1uF
C126
0.1uF
C130
0.1uF
C134
0.1uF
2A
Z=115ohms
L30
M28
M31
N29
R30
T31
U29
V32
W30
Y31
AA29
AB32
AC30
AD31
AE29
AG30
AH31
AJ29
AK32
C
AL30
VCC_SERDES
AM31
F3
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
SENSEVDD_CORE1
SENSEVSS_CORE1
K26
SHORT_POWER
L24
M27
N25
C101
0.1uF
C106
0.1uF
C113
0.1uF
C119
0.1uF
C123
0.1uF
C127
0.1uF
C131
0.1uF
C135
0.1uF
C102
0.1uF
C107
0.1uF
C114
0.1uF
C120
0.1uF
C124
0.1uF
C128
0.1uF
C132
0.1uF
C136
0.1uF
2A
Z=115ohms
P26
R24
R28
T27
U25
V26
W24
Y27
AA25
AB28
AC26
AD27
AF28
AH27
D
AK28
AM27
AE25
cbga_31x31_1mm_skt
Date Changed: Thursday, February 1, 2007
Engineer:
3
SHORT_POWER
F2
SVDD_1
SVDD_2
SVDD_3
SVDD_4
SVDD_5
SVDD_6
SVDD_7
SVDD_8
SVDD_9
SVDD_10
SVDD_11
SVDD_12
SVDD_13
SVDD_14
SVDD_15
SVDD_16
SVDD_17
SVDD_18
SVDD_19
SVDD_20
SVDD_21
SVDD_22
SVDD_23
SVDD_24
SVDD_25
AVDD_CORE1
HPCN: Argo Navis
1.03
A20
10
SENSEVDD_CORE0
SENSEVSS_CORE0
No_Stuff
freescale
A
C115
0.1uF
R62
C97
2.2uF
No_Stuff
D
C108
2.2uF
VCC_PLAT
C86
0.1uF
C75
2.2uF
A19
C46
0.1uF
C96
2.2uF
VDD_CORE0_1
VDD_CORE0_2
VDD_CORE0_3
VDD_CORE0_4
VDD_CORE0_5
VDD_CORE0_6
VDD_CORE0_7
VDD_CORE0_8
VDD_CORE0_9
VDD_CORE0_10
VDD_CORE0_11
VDD_CORE0_12
VDD_CORE0_13
VDD_CORE0_14
VDD_CORE0_15
VDD_CORE0_16
VDD_CORE0_17
VDD_CORE0_18
VDD_CORE0_19
VDD_CORE0_20
VDD_CORE0_21
VDD_CORE0_22
VDD_CORE0_23
VDD_CORE0_24
VDD_CORE0_25
VDD_CORE0_26
VDD_CORE0_27
VDD_CORE0_28
Gary Milliorn
4
5
Page:
Title: MC8641D Power
Time Changed: 2:09:52 pm
6
7
20
8
1
2
3
4
5
6
7
U32
VCC_DDRA_IO
8
VCC_DDRB_IO
mc8641d.9of9.power.cbga1023
C507
0.1uF
C511
0.1uF
C515
0.1uF
C519
0.1uF
C523
0.1uF
C531
0.1uF
C527
0.1uF
C535
0.1uF
D10
D13
F9
F12
H8
H11
C508
0.1uF
C512
0.1uF
C516
0.1uF
C520
0.1uF
C524
0.1uF
C536
0.1uF
C532
0.1uF
C528
0.1uF
H14
K10
K13
L8
P8
R6
U8
V6
W10
Y8
AA6
AB10
AC8
AD12
AE10
AF8
B
AG12
AH10
AJ8
AJ14
AK12
AL10
AL16
VCC_3.3
B22
B25
C505
0.1uF
C509
0.1uF
C513
0.1uF
C517
0.1uF
C521
0.1uF
C529
0.1uF
C525
0.1uF
C533
0.1uF
B28
D17
D24
D27
F19
F22
C506
0.1uF
C510
0.1uF
C514
0.1uF
C518
0.1uF
C522
0.1uF
C526
0.1uF
C530
0.1uF
C534
0.1uF
F26
F29
G17
H21
H24
C
K19
K23
M21
GVDD1_1
GVDD1_2
GVDD1_3
GVDD1_4
GVDD1_5
GVDD1_6
GVDD1_7
GVDD1_8
GVDD1_9
GVDD1_10
GVDD1_11
GVDD1_12
GVDD1_13
GVDD1_14
GVDD1_15
GVDD1_16
GVDD1_17
GVDD1_18
GVDD1_19
GVDD1_20
GVDD1_21
GVDD1_22
GVDD1_23
GVDD1_24
GVDD1_25
GVDD1_26
GVDD1_27
GVDD1_28
GVDD1_29
GVDD1_30
GVDD1_31
GND
See Spec or
mapfile.
GVDD2_1
GVDD2_2
GVDD2_3
GVDD2_4
GVDD2_5
GVDD2_6
GVDD2_7
GVDD2_8
GVDD2_9
GVDD2_10
GVDD2_11
GVDD2_12
GVDD2_13
GVDD2_14
GVDD2_15
GVDD2_16
GVDD2_17
GVDD2_18
GVDD2_19
GVDD2_20
GVDD2_21
GVDD2_22
GVDD2_23
GVDD2_24
GVDD2_25
GVDD2_26
GVDD2_27
GVDD2_28
GVDD2_29
GVDD2_30
VDD_PLAT_1
VDD_PLAT_2
VDD_PLAT_3
VDD_PLAT_4
VDD_PLAT_5
VDD_PLAT_6
VDD_PLAT_7
VDD_PLAT_8
VDD_PLAT_9
VDD_PLAT_10
VDD_PLAT_11
OVDD_1
OVDD_2
OVDD_3
OVDD_4
OVDD_5
OVDD_6
OVDD_7
OVDD_8
OVDD_9
OVDD_10
OVDD_11
OVDD_12
OVDD_13
OVDD_14
OVDD_15
OVDD_16
SENSEVDD_PLAT
SENSEVSS_PLAT
B2
B5
A
B8
D4
C538
0.1uF
C541
0.1uF
C544
0.1uF
C547
0.1uF
C550
0.1uF
C553
0.1uF
C556
0.1uF
C559
0.1uF
C539
0.1uF
C542
0.1uF
C545
0.1uF
C548
0.1uF
C551
0.1uF
C554
0.1uF
C557
0.1uF
C560
0.1uF
D7
E2
F6
G4
H2
J6
K4
L2
M6
N4
P2
T4
U2
W4
Y2
AB4
AC2
AD6
AE4
AF2
B
AG6
AH4
AJ2
AK6
AL4
VCC_PLAT
AM2
M16
M17
M18
C540
0.1uF
C537
0.1uF
N20
C543
0.1uF
C546
0.1uF
C549
0.1uF
C552
0.1uF
C558
0.1uF
C555
0.1uF
N22
P17
P19
P21
P23
N16
VCC_3.3
R22
CBGA1023 Escape Pattern
and Capacitor Placement
N18
P18
R683
C
51
OVDD_17
AM30
c
B14
cbga_31x31_1mm_skt
c
B11
A
R684
c
160
No_Stuff
etc.
c
c
etc.
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
c
etc.
c
c
etc.
D
c
D
Or, use via-in-pad (see Design
workbook for details).
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: MC8641D Power, Part 2
Time Changed: 2:10:02 pm
5
6
Page:
7
21
8
1
2
3
4
5
6
7
8
mc8641d.2of9.ddr_1.cbga1023
M1_MCLK0p
M1_MCLK0n
M1_MCLK1p
M1_MCLK1n
M1_MCLK2p
M1_MCLK2n
M1_MCLK3p
M1_MCLK3n
M1_MCLK4p
M1_MCLK4n
M1_MCLK5p
M1_MCLK5n
23C1
23C1
23C1
23C1
23C1
23C1
24C1
24C1
A
24C1
24C1
24C1
24C1
M1_MCK0T
DIFF_CLK
R382
0
M1_MCK0
M1_DIFFSERIES
M1_MCK0p
W6
M1_MCK0T
DIFF_CLK
R383
0
M1_MCK0
M1_DIFFSERIES
M1_MCK0n
Y6
M1_MCK1T
DIFF_CLK
R384
0
M1_MCK1
M1_DIFFSERIES
M1_MCK1p
E13
M1_MCK1T
DIFF_CLK
R385
0
M1_MCK1
M1_DIFFSERIES
M1_MCK1n
E12
M1_MCK2T
DIFF_CLK
R386
0
M1_MCK2
M1_DIFFSERIES
M1_MCK2p
AH11
M1_MCK2T
DIFF_CLK
R387
0
M1_MCK2
M1_DIFFSERIES
M1_MCK2n
AH12
M1_MCK3T
DIFF_CLK
R388
0
M1_MCK3
M1_DIFFSERIES
M1_MCK3p
Y7
M1_MCK3T
DIFF_CLK
R389
0
M1_MCK3
M1_DIFFSERIES
M1_MCK3n
AA7
M1_MCK4T
DIFF_CLK
R390
0
M1_MCK4
M1_DIFFSERIES
M1_MCK4p
F14
M1_MCK4T
DIFF_CLK
R391
0
M1_MCK4
M1_DIFFSERIES
M1_MCK4n
F13
M1_MCK5T
DIFF_CLK
R392
0
M1_MCK5
M1_DIFFSERIES
M1_MCK5p
AG10
M1_MCK5T
DIFF_CLK
R393
0
M1_MCK5
M1_DIFFSERIES
M1_MCK5n
AG11
M1_MDQ(63:0)
23A8,24A8
B
C
VCC_DDRA_IO
D
0
M1_TDL0
D15
1
M1_TDL0
A14
2
M1_TDL0
B12
3
M1_TDL0
D12
4
M1_TDL0
A15
5
M1_TDL0
B15
6
M1_TDL0
B13
7
M1_TDL0
C13
8
M1_TDL1
C11
9
M1_TDL1
D11
10
M1_TDL1
D9
11
M1_TDL1
A8
12
M1_TDL1
A12
13
M1_TDL1
A11
14
M1_TDL1
A9
15
M1_TDL1
B9
16
M1_TDL2
F11
17
M1_TDL2
G12
18
M1_TDL2
K11
19
M1_TDL2
K12
20
M1_TDL2
E10
21
M1_TDL2
E9
22
M1_TDL2
J11
23
M1_TDL2
J10
24
M1_TDL3
G8
25
M1_TDL3
H10
26
M1_TDL3
L9
27
M1_TDL3
L7
28
M1_TDL3
F10
29
M1_TDL3
G9
30
M1_TDL3
K9
31
M1_TDL3
32
M1_TDL4
33
M1_TDL4
34
M1_TDL4
35
M1_TDL4
36
M1_TDL4
37
M1_TDL4
38
M1_TDL4
39
M1_TDL4
40
M1_TDL5
41
M1_TDL5
42
M1_TDL5
43
M1_TDL5
44
M1_TDL5
45
M1_TDL5
46
M1_TDL5
47
M1_TDL5
48
M1_TDL6
49
M1_TDL6
50
M1_TDL6
51
M1_TDL6
52
M1_TDL6
53
M1_TDL6
54
M1_TDL6
55
M1_TDL6
56
M1_TDL7
57
M1_TDL7
58
M1_TDL7
59
M1_TDL7
60
M1_TDL7
61
M1_TDL7
62
M1_TDL7
63
R394
18.2
R395
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
18.2
1%
1%
M1_TDL7
2CM_MAX
2CM_MAX
D1_MCK0
D1_MCK0_B
D1_MCK1
D1_MCK1_B
D1_MCK2
D1_MCK2_B
D1_MCK3
D1_MCK3_B
D1_MCK4
D1_MCK4_B
D1_MCK5
D1_MCK5_B
D1_MDQ0
D1_MDQ1
D1_MDQ2
D1_MDQ3
D1_MDQ4
D1_MDQ5
D1_MDQ6
D1_MDQ7
Freescale
D1_MDQ9
D1_MDQ10
D1_MDQ11
D1_MDQ12
D1_MDQ13
D1_MDQ14
D1_MDQ15
D1_MDQ16
M1_MVREF
POWER_TRACE
M1_TDL0
C10
M1_TDL1
1
H12
M1_TDL2
2
J7
M1_TDL3
3
AE8
M1_TDL4
4
AM9
M1_TDL5
5
AK13
M1_TDL6
6
AK17
M1_TDL7
7
N9
M1_TDL8
8
M1_MDQS(8:0)
D14
M1_TDL0
0
M1_MDQS_B(8:0)
B10
M1_TDL1
1
H13
M1_TDL2
2
J8
M1_TDL3
3
AD8
M1_TDL4
4
AL9
M1_TDL5
5
AJ13
M1_TDL6
6
AM16
M1_TDL7
7
P10
M1_TDL8
8
M8
M1_TDL8
0
M7
M1_TDL8
1
R8
M1_TDL8
2
T10
M1_TDL8
3
L11
M1_TDL8
4
L10
M1_TDL8
5
P9
M1_TDL8
6
R10
M1_TDL8
7
D1_MDM0
D1_MDM1
D1_MDM2
D1_MDM3
D1_MDM4
D1_MDM5
D1_MDM6
D1_MDM7
D1_MDM8
C14
M1_TDL0
0
A10
M1_TDL1
1
G11
M1_TDL2
2
H9
M1_TDL3
3
AD7
M1_TDL4
4
AJ9
M1_TDL5
5
AM12
M1_TDL6
6
AK16
M1_TDL7
7
N10
M1_TDL8
8
D1_MBA0
D1_MBA1
D1_MBA2
AA8
M1_TSERIES
0
AA10
M1_TSERIES
1
T9
M1_TSERIES
2
Y10
M1_TSERIES
0
W8
M1_TSERIES
1
W9
M1_TSERIES
2
V7
M1_TSERIES
3
V8
M1_TSERIES
4
U6
M1_TSERIES
5
V10
M1_TSERIES
6
U9
M1_TSERIES
7
U7
M1_TSERIES
8
U10
M1_TSERIES
9
Y9
M1_TSERIES
10
T6
M1_TSERIES
11
T8
M1_TSERIES
12
AE12
M1_TSERIES
13
R7
M1_TSERIES
14
P6
M1_TSERIES
15
D1_MDQS0
D1_MDQS1
D1_MDQS2
D1_MDQS3
D1_MDQS4
D1_MDQS5
D1_MDQS6
D1_MDQS7
D1_MDQS8
D1_MDQS0_B
D1_MDQS1_B
D1_MDQS2_B
D1_MDQS3_B
D1_MDQS4_B
D1_MDQS5_B
D1_MDQS6_B
D1_MDQS7_B
D1_MDQS8_B
D1_MECC0
D1_MECC1
D1_MECC2
D1_MECC3
D1_MECC4
D1_MECC5
D1_MECC6
D1_MECC7
C503
0.1uF
C504
0.01uF
A
D1_MDQ19
D1_MDQ20
D1_MDQ21
D1_MDQ22
D1_MDQ23
D1_MDQ24
D1_MDQ25
D1_MDQ26
D1_MDQ29
D1_MDQ30
K8
D1_MDQ31
AC6
D1_MDQ32
AC7
D1_MDQ33
AG8
D1_MDQ34
AH9
D1_MDQ35
AB6
D1_MDQ36
AB8
D1_MDQ37
AE9
D1_MDQ38
AF9
D1_MDQ39
AL8
D1_MDQ40
AM8
D1_MDQ41
AM10
D1_MDQ42
AK11
D1_MDQ43
AH8
D1_MDQ44
AK8
D1_MDQ45
AJ10
D1_MDQ46
AK10
D1_MDQ47
AL12
D1_MDQ48
AJ12
D1_MDQ49
AL14
D1_MDQ50
AM14
D1_MDQ51
AL11
D1_MDQ52
AM11
D1_MDQ53
AM13
D1_MDQ54
AK14
D1_MDQ55
AM15
D1_MDQ56
AJ16
D1_MDQ57
AK18
D1_MDQ58
AL18
D1_MDQ59
AJ15
D1_MDQ60
AL15
D1_MDQ61
AL17
D1_MDQ62
AM17
D1_MDQ63
E15
D1_MDIC0
G14
D1_MDIC1
D1_MA0
D1_MA1
D1_MA2
D1_MA3
D1_MA4
D1_MA5
D1_MA6
D1_MA7
D1_MA8
D1_MA9
D1_MA10
D1_MA11
D1_MA12
D1_MA13
D1_MA14
D1_MA15
D1_MWE_B
D1_MRAS_B
D1_MCAS_B
D1_MCS0_B
D1_MCS1_B
D1_MCS2_B
D1_MCS3_B
D1_MCKE0
D1_MCKE1
D1_MCKE2
D1_MCKE3
D1_MODT0
D1_MODT1
D1_MODT2
D1_MODT3
AB11
23A1,24A1
23D8,24D8
B
M1_MDM(8:0)
D1_MDQ27
D1_MDQ28
23A1,24A1
M1_MECC(7:0)
D1_MDQ17
D1_MDQ18
23B8,24B8,25A1
0
23B1,24B1
M1_MBA(2:0)
23B1,24B1,25D1
M1_MA(15:0)
23B1,24B1,25C1
C
M1_MWE*
M1_MRAS*
M1_MCAS*
M1_TSERIES
AB12
AC10
M1_TSERIES
AB9
M1_TSERIES
AD10
M1_TSERIES
1
AC12
M1_TSERIES
2
AD11
M1_TSERIES
3
P7
M1_TSERIES
0
M10
M1_TSERIES
1
N8
M1_TSERIES
2
M11
AC9
M1_TSERIES
3
M1_TSERIES
0
AF12
M1_TSERIES
1
AE11
M1_TSERIES
2
AF10
M1_TSERIES
3
M1_TSERIES
23C1,24C1,25C1
23C1,24C1,25C1
23C1,24C1,25C1
M1_MCS*(3:0)
0
23C1,24C1,25C1
M1_MCKE(3:0)
23D1,24D1,25C1
D
M1_MODT(3:0)
23D1,24D1,25D1
Date Changed: Thursday, February 1, 2007
Engineer:
3
MEMORY #1
AM18
A13
D1_MDQ8
HPCN: Argo Navis
1.03
D1_MVREF
U32
Gary Milliorn
4
Title: DDR-2 Interface #1
Time Changed: 2:10:11 pm
5
6
Page:
7
22
8
1
2
3
4
5
6
7
8
P6
conn_240_ddr2_vert_1of2
FOXCONN
M1_MDQS(8:0)
M1_MDQS_B(8:0)
22A8,24A1
22A8,24A1
7
0
6
0
16
1
15
1
28
2
27
2
A
37
3
36
3
84
4
83
4
5
93
6
105
92
5
104
6
114
7
113
7
8
46
0
125
45
8
M1_MDM(8:0)
22B8,24B1
B
M1_MBA(2:0)
22C8,24B1,25D1
M1_MA(15:0)
22C8,24B1,25C1
1
134
2
146
3
155
4
202
5
211
6
223
7
232
8
164
0
71
1
2
190
54
0
188
1
183
2
63
3
182
4
61
5
60
6
180
7
58
8
179
9
177
70
10
22D8,24C1,25C1
C
22D8,24C1,25C1
22D8,24C1,25C1
57
12
176
13
196
14
174
15
173
73
M1_MWE*
M1_MRAS*
M1_MCAS*
M1_MCS*(3:0)
22C8,24C1,25C1
11
192
74
0
193
1
76
185
M1_MCLK0p
M1_MCLK0n
M1_MCLK1p
M1_MCLK1n
M1_MCLK2p
M1_MCLK2n
22A1
22A1
22A1
22A1
22A1
22A1
186
137
138
220
221
M1_MODT(3:0)
22D8,24D1,25D1
M1_MCKE(3:0)
0
MEM_RST*
55
NC
I2C2_SDA
I2C2_SCL
13C1,19C8,24D1,27D1,28D1,#6
13D1,19C8,24D1,27D1,28D1,#6
119
120
239
VCC_3.3
C697
D
C698
240
C699
101
PLACE CAPS BY
DIMM PINS
freescale
semiconductor
1
5pF
5pF
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
(AP)
WE
RAS
CAS
S0
S1
NC
102
Not Supported
CK_H0
CK_L0
CK_H1
CK_L1
CK_H2
CK_L2
126, 135, 147, 156
165, 203, 212, 224
233
ODT0
77
ODT1
52
CKE0
171
CKE1
18
RESET
1
14B8,24D1,27D1,28D1
(DQS9)
(DQS10)
(DQS11)
(DQS12)
(DQS13)
(DQS14)
(DQS15)
(DQS16)
(DQS17)
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
195
0
1
22D8,24D1,25C1
DM0
AT24013-D3-4F
DDR2 DIMM
DQS0
DQS0n
DQS1
DQS1n
DQS2
DQS2n
DQS3
DQS3n
DQS4
DQS4n
DQS5
DQS5n
DQS6
DQS6n
DQS7
DQS7n
DQS8
DQS8n
RC
SDA
SCL
SA0
SA1
SA2
DIMM #1 SPD
ADDR=0x51
(ECC0)
(ECC1)
(ECC2)
(ECC3)
(ECC4)
(ECC5)
(ECC6)
(ECC7)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
M1_MDQ(63:0)
0
3
4
1
9
2
10
3
122
4
123
5
128
6
129
7
12
8
13
9
21
10
VTT_A
VCC_DDRA_IO
P6
conn_240_ddr2_vert_2of2
FOXCONN
AT24013-D3-4F
C700
53
59
0.1uF
64
C701
67
69
22
11
131
12
132
13
140
14
141
15
24
16
25
17
30
18
51
31
19
56
143
20
144
21
149
22
150
23
33
24
34
25
39
26
40
27
152
28
153
29
158
30
159
31
80
81
32
86
34
172
0.1uF
35
199
36
200
37
205
38
206
39
89
40
90
41
95
42
96
43
208
44
209
45
214
46
215
47
98
48
99
49
107
50
108
51
217
52
218
53
226
54
227
55
110
56
111
57
116
58
117
59
229
60
230
61
235
62
236
63
42
0
43
1
48
2
49
3
161
4
162
5
178
C702
184
187
189
0.1uF
197
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
C703
0.1uF
62
C704
72
75
78
0.1uF
170
C705
175
181
191
0.1uF
194
C706
A
19
PWR2_SEL_OPT1
68
PWR1_SEL_OPT1
66
PWR2_SEL_OPT2
50
PWR1_SEL_OPT2
NC
NC
NC
GROUND
2, 5, 8, 11, 14, 17, 20,
23, 26, 29, 32, 35, 38,
41, 44, 47, 65,
79, 82, 85, 88, 91,
94, 97, 100, 103, 106,
109, 112, 115, 118, 121,
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
124, 127, 130, 133, 136,
139, 142, 145, 148, 151,
154, 157, 160, 163, 166,
VCC_3.3
169, 198, 201, 204, 207,
210, 213, 216, 219, 222,
225, 228, 231, 234, 237
VDDSPD
VREF
238
1
B
M1_MVREF
22A8,24B8,25A1
C716
0.1uF
0.1uF
C707
33
87
22A1,24A8
0.1uF
C708
0.1uF
C709
0.1uF
C710
0.1uF
C711
C
0.1uF
C712
0.1uF
C713
0.1uF
C714
0.1uF
167
6
168
7
C715
0.1uF
D
M1_MECC(7:0)
22B8,24D8
5pF
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: DDR-II Interface #1DIMM Socket #1
Time Changed: 2:10:20 pm
5
6
7
Page:
23
8
1
2
3
4
5
6
7
8
P3
conn_240_ddr2_vert_1of2
FOXCONN
M1_MDQS(8:0)
M1_MDQS_B(8:0)
22A8,23A1
22A8,23A1
7
0
6
0
16
1
15
1
28
2
27
2
A
37
3
36
3
84
4
83
4
93
5
92
5
105
6
104
6
114
7
113
7
8
46
0
125
45
8
M1_MDM(8:0)
22B8,23B1
B
M1_MBA(2:0)
22C8,23B1,25D1
M1_MA(15:0)
22C8,23B1,25C1
1
134
2
146
3
155
4
202
5
211
6
223
7
232
8
164
0
71
1
2
190
54
0
188
1
183
2
63
3
182
4
61
5
60
6
180
7
58
8
179
9
177
70
10
22D8,23C1,25C1
C
22D8,23C1,25C1
22D8,23C1,25C1
57
12
176
13
196
14
174
15
173
73
M1_MWE*
M1_MRAS*
M1_MCAS*
M1_MCS*(3:0)
22C8,23C1,25C1
11
192
74
2
193
3
76
185
M1_MCLK3p
M1_MCLK3n
M1_MCLK4p
M1_MCLK4n
M1_MCLK5p
M1_MCLK5n
22A1
22A1
22A1
22A1
22A1
22A1
186
137
138
220
221
M1_MODT(3:0)
22D8,23D1,25D1
M1_MCKE(3:0)
2
MEM_RST*
55
NC
119
I2C2_SDA
I2C2_SCL
13C1,19C8,23D1,27D1,28D1,#6
13D1,19C8,23D1,27D1,28D1,#6
120
239
VCC_3.3
C677
D
C678
240
C679
101
PLACE CAPS BY
DIMM PINS
freescale
semiconductor
1
5pF
5pF
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
(AP)
WE
RAS
CAS
S0
S1
NC
102
Not Supported
CK_H0
CK_L0
CK_H1
CK_L1
CK_H2
CK_L2
126, 135, 147, 156
165, 203, 212, 224
233
ODT0
77
ODT1
52
CKE0
171
CKE1
18
RESET
3
14B8,23D1,27D1,28D1
(DQS9)
(DQS10)
(DQS11)
(DQS12)
(DQS13)
(DQS14)
(DQS15)
(DQS16)
(DQS17)
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
195
2
3
22D8,23D1,25C1
DM0
AT24013-D3-4F
DDR2 DIMM
DQS0
DQS0n
DQS1
DQS1n
DQS2
DQS2n
DQS3
DQS3n
DQS4
DQS4n
DQS5
DQS5n
DQS6
DQS6n
DQS7
DQS7n
DQS8
DQS8n
RC
SDA
SCL
SA0
SA1
SA2
DIMM #2 SPD
ADDR=0x52
(ECC0)
(ECC1)
(ECC2)
(ECC3)
(ECC4)
(ECC5)
(ECC6)
(ECC7)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
M1_MDQ(63:0)
0
3
4
1
9
2
10
3
122
4
123
5
128
6
VTT_A
VCC_DDRA_IO
P3
conn_240_ddr2_vert_2of2
FOXCONN
AT24013-D3-4F
C680
53
129
7
12
8
13
9
21
10
69
22
11
172
131
12
59
0.1uF
64
C681
67
0.1uF
178
132
13
140
14
141
15
24
16
25
17
30
18
51
31
19
56
143
20
144
21
149
22
150
23
33
24
34
25
39
26
181
40
27
191
152
28
153
29
158
30
159
31
80
81
32
86
34
C682
35
199
36
200
37
205
38
206
39
89
40
90
41
95
42
96
43
208
44
209
45
214
46
215
47
98
48
99
49
107
50
108
51
217
52
218
53
226
54
227
55
110
56
111
57
116
58
117
59
229
60
230
61
235
62
236
63
42
0
43
1
48
2
184
187
189
0.1uF
197
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
C683
0.1uF
62
C684
72
75
78
0.1uF
170
C685
175
0.1uF
194
C686
A
19
PWR2_SEL_OPT1
68
PWR1_SEL_OPT1
66
PWR2_SEL_OPT2
50
PWR1_SEL_OPT2
NC
NC
NC
GROUND
2, 5, 8, 11, 14, 17, 20,
23, 26, 29, 32, 35, 38,
41, 44, 47, 65,
79, 82, 85, 88, 91,
94, 97, 100, 103, 106,
109, 112, 115, 118, 121,
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
124, 127, 130, 133, 136,
139, 142, 145, 148, 151,
154, 157, 160, 163, 166,
VCC_3.3
169, 198, 201, 204, 207,
210, 213, 216, 219, 222,
225, 228, 231, 234, 237
VDDSPD
VREF
238
1
B
M1_MVREF
22A8,23B8,25A1
C696
0.1uF
0.1uF
33
87
22A1,23A8
C687
0.1uF
C688
0.1uF
C689
0.1uF
C690
0.1uF
C691
C
0.1uF
C692
0.1uF
C693
0.1uF
C694
0.1uF
49
3
161
4
162
5
167
6
168
7
C695
0.1uF
D
M1_MECC(7:0)
22B8,23D8
5pF
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: DDR-II Interface #1 DIMM Socket #2
Time Changed: 2:10:29 pm
5
6
7
Page:
24
8
2
1
3
4
5
6
7
VTT_A
8
VCC_5
VCC_3.3
VCC_5
VCC_5
4.7K
100K
4.7K
C638
10uF
4.7K
POWER_TRACE
C635
10uF
C662
C639
10uF
C644
10uF
R685
4.7K
R501
TPS51116PWP
R500
U13
R499
R498
0.1uF
A
A
5
6
7
8
Q13
IRF7821PBF
so8
4
1
20
VLDOIN
VBST
VTT
DRVH
2
3
R478
VTTGND
LL
VTTSNS
DRVL
GND
PGND
4
100K
5
No_Stuff
6
M1_MVREF
22A8,23B8,24B8
MODE
CS
7
POWER_TRACE
V5IN
VTTREF
8
PGOOD
COMP
9
C645
0.1uF
S5
VDDQSNS
R487
0
+
18
2
3
17
L9
1
16
15
IMAX=20A
2
1UH
14
20A
5
13
6
7
8
12
+
Q14
IRF7832PBF
so8
4
S3
VDDQSET
C650
4.7uF
10V
OSCON
1
11
10
VCC_DDRA_IO
19
C669
150uF
4V
OSCON
+
C671
150uF
4V
OSCON
tssop20HT
R479
1
100K
2
3
No_Stuff
M1_DDR_IOPWRGD
B
14C2,56C1
M1_DDR_IOPWR_S3
54D8
M1_DDR_IOPWR_S5
54D8
VTT_A
C633
0.1uF
C636
0.1uF
C642
0.1uF
C640
0.1uF
C651
0.1uF
C648
0.1uF
C646
0.1uF
C655
0.1uF
C653
0.1uF
R497
VTT SENSE
Place at midpoint of VTT fill plane.
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
0
10 11 12 13 14 15
R496
9
R493
8
R492
7
R491
R490
R489
R488
R486
5
R485
4
R484
3
R483
2
R482
1
R481
R477
0
R480
R476
3
R475
2
R474
1
R473
R471
R467
0
R495
22D8,23D1,24D1
2
R494
22C8,23B1,24B1
1
R472
22C8,23B1,24B1
0
R470
22D8,23C1,24C1
R469
22D8,23D1,24D1
R468
22C8,23C1,24C1
R466
22D8,23C1,24C1
R465
M1_MRAS*
M1_MCAS*
M1_MWE*
M1_MCKE(3:0)
M1_MCS*(3:0)
M1_MA(15:0)
M1_MBA(2:0)
M1_MODT(3:0)
22D8,23C1,24C1
R464
R463
R462
R461
R460
C
0
1
2
C
VTT TERMINATION PLANE
Place resistors immediately behind DIMM on a plane
Place capacitors behind or intermingled with resistors.
One capacitor per four VTT resistors.
3
6
0
1
2
3
0
C634
22pF
D
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
C637
22pF
C641
22pF
2
1
0
C647
22pF
C643
22pF
Project:
Revision:
2
1
0
freescale
B
C649
22pF
C652
22pF
C654
22pF
7
6
8
9
10
11
12
13
2
1
15
14
C656
22pF
C657
22pF
C658
22pF
C659
22pF
C660
22pF
C661
22pF
C663
22pF
C664
22pF
C666
22pF
C665
22pF
C667
22pF
C668
22pF
C672
22pF
C670
22pF
C673
22pF
C674
22pF
C675
22pF
C676
22pF
Date Changed: Thursday, February 1, 2007
Engineer:
3
5
3
HPCN: Argo Navis
1.03
4
3
Gary Milliorn
4
Title: DDR-II Interface #1 Power and Termination
Time Changed: 2:10:39 pm
5
6
7
Page:
25
8
D
1
2
3
4
5
6
7
8
mc8641d.3of9.ddr_2.cbga1023
M2_MCLK0p
M2_MCLK0n
M2_MCLK1p
M2_MCLK1n
M2_MCLK2p
M2_MCLK2n
M2_MCLK3p
M2_MCLK3n
M2_MCLK4p
M2_MCLK4n
M2_MCLK5p
M2_MCLK5n
27C1
27C1
27C1
27C1
27C1
27C1
28C1
28C1
A
28C1
28C1
28C1
28C1
M2_MCK0T
M2_DIFFCLK
R446
0
M2_MCK0
M2_DIFFSERIES
M2_MCK0p
U1
M2_MCK0T
M2_DIFFCLK
R447
0
M2_MCK0
M2_DIFFSERIES
M2_MCK0n
V1
M2_MCK1T
M2_DIFFCLK
R448
0
M2_MCK1
M2_DIFFSERIES
M2_MCK1p
F5
M2_MCK1T
M2_DIFFCLK
R449
0
M2_MCK1
M2_DIFFSERIES
M2_MCK1n
G5
M2_MCK2T
M2_DIFFCLK
R450
0
M2_MCK2
M2_DIFFSERIES
M2_MCK2p
AJ3
M2_MCK2T
M2_DIFFCLK
R451
0
M2_MCK2
M2_DIFFSERIES
M2_MCK2n
AJ4
M2_MCK3T
M2_DIFFCLK
R452
0
M2_MCK3
M2_DIFFSERIES
M2_MCK3p
V2
M2_MCK3T
M2_DIFFCLK
R453
0
M2_MCK3
M2_DIFFSERIES
M2_MCK3n
W2
M2_MCK4T
M2_DIFFCLK
R454
0
M2_MCK4
M2_DIFFSERIES
M2_MCK4p
E7
M2_MCK4T
M2_DIFFCLK
R455
0
M2_MCK4
M2_DIFFSERIES
M2_MCK4n
E6
M2_MCK5T
M2_DIFFCLK
R456
0
M2_MCK5
M2_DIFFSERIES
M2_MCK5p
AG4
M2_MCK5T
M2_DIFFCLK
R457
0
M2_MCK5
M2_DIFFSERIES
M2_MCK5n
AG5
M2_MDQ(63:0)
27A8,28A8
B
C
VCC_DDRB_IO
D
0
M2_TDL0
A7
1
M2_TDL0
B7
2
M2_TDL0
C5
3
M2_TDL0
D5
4
M2_TDL0
C8
5
M2_TDL0
D8
6
M2_TDL0
D6
7
M2_TDL0
A5
8
M2_TDL1
C4
9
M2_TDL1
A3
10
M2_TDL1
D3
11
M2_TDL1
D2
12
M2_TDL1
A4
13
M2_TDL1
B4
14
M2_TDL1
C2
15
M2_TDL1
C1
16
M2_TDL2
E3
17
M2_TDL2
E1
18
M2_TDL2
H4
19
M2_TDL2
G1
20
M2_TDL2
D1
21
M2_TDL2
E4
22
M2_TDL2
G3
23
M2_TDL2
G2
24
M2_TDL3
J4
25
M2_TDL3
J2
26
M2_TDL3
L1
27
M2_TDL3
L3
28
M2_TDL3
H3
29
M2_TDL3
H1
30
M2_TDL3
K1
31
M2_TDL3
32
M2_TDL4
33
M2_TDL4
34
M2_TDL4
35
M2_TDL4
36
M2_TDL4
37
M2_TDL4
38
M2_TDL4
39
M2_TDL4
40
M2_TDL5
41
M2_TDL5
42
M2_TDL5
43
M2_TDL5
44
M2_TDL5
45
M2_TDL5
46
M2_TDL5
47
M2_TDL5
48
M2_TDL6
49
M2_TDL6
50
M2_TDL6
51
M2_TDL6
52
M2_TDL6
53
M2_TDL6
54
M2_TDL6
55
M2_TDL6
56
M2_TDL7
57
M2_TDL7
58
M2_TDL7
59
M2_TDL7
60
M2_TDL7
61
M2_TDL7
62
M2_TDL7
63
R458
18.2
R459
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
18.2
1%
1%
M2_TDL7
2CM_MAX
2CM_MAX
D2_MCK0
D2_MCK0_B
D2_MCK1
D2_MCK1_B
D2_MCK2
D2_MCK2_B
D2_MCK3
D2_MCK3_B
D2_MCK4
D2_MCK4_B
D2_MCK5
D2_MCK5_B
D2_MDQ0
D2_MDQ1
D2_MDQ2
D2_MDQ3
D2_MDQ4
D2_MDQ5
D2_MDQ6
D2_MDQ7
D2_MDQ9
D2_MDQ10
D2_MDQ11
D2_MDQ12
D2_MDQ13
D2_MDQ14
D2_MDQ15
D2_MDQ16
A8
M2_MVREF
POWER_TRACE
B6
M2_TDL0
0
B1
M2_TDL1
1
F1
M2_TDL2
2
K2
M2_TDL3
3
AB3
M2_TDL4
4
AF1
M2_TDL5
5
AL1
M2_TDL6
6
AL6
M2_TDL7
7
L6
M2_TDL8
8
M2_MDQS(8:0)
A6
M2_TDL0
0
M2_MDQS_B(8:0)
A2
M2_TDL1
1
F2
M2_TDL2
2
K3
M2_TDL3
3
AB2
M2_TDL4
4
AE3
M2_TDL5
5
AK2
M2_TDL6
6
AJ6
M2_TDL7
7
K5
M2_TDL8
8
H6
M2_TDL8
0
J5
M2_TDL8
1
M5
M2_TDL8
2
M4
M2_TDL8
3
G6
M2_TDL8
4
H7
M2_TDL8
5
M2
M2_TDL8
6
M1
M2_TDL8
7
D2_MDM0
D2_MDM1
D2_MDM2
D2_MDM3
D2_MDM4
D2_MDM5
D2_MDM6
D2_MDM7
D2_MDM8
C7
M2_TDL0
0
B3
M2_TDL1
1
F4
M2_TDL2
2
J1
M2_TDL3
3
AB1
M2_TDL4
4
AE2
M2_TDL5
5
AK1
M2_TDL6
6
AM5
M2_TDL7
7
K6
M2_TDL8
8
D2_MBA0
D2_MBA1
D2_MBA2
W5
M2_TSERIES
0
V5
M2_TSERIES
1
P3
M2_TSERIES
2
W1
M2_TSERIES
0
U4
M2_TSERIES
1
U3
M2_TSERIES
2
T1
M2_TSERIES
3
T2
M2_TSERIES
4
T3
M2_TSERIES
5
T5
M2_TSERIES
6
R2
M2_TSERIES
7
R1
M2_TSERIES
8
R5
M2_TSERIES
9
V4
D2_MDQS0
D2_MDQS1
D2_MDQS2
D2_MDQS3
D2_MDQS4
D2_MDQS5
D2_MDQS6
D2_MDQS7
D2_MDQS8
D2_MDQS0_B
D2_MDQS1_B
D2_MDQS2_B
D2_MDQS3_B
D2_MDQS4_B
D2_MDQS5_B
D2_MDQS6_B
D2_MDQS7_B
D2_MDQS8_B
D2_MECC0
D2_MECC1
D2_MECC2
D2_MECC3
D2_MECC4
D2_MECC5
D2_MECC6
D2_MECC7
C631
0.1uF
C632
0.01uF
A
D2_MDQ19
D2_MDQ20
D2_MDQ21
D2_MDQ22
D2_MDQ23
D2_MDQ24
D2_MDQ25
D2_MDQ26
D2_MDQ29
D2_MDQ30
L4
D2_MDQ31
AA4
D2_MDQ32
AA2
D2_MDQ33
AD1
D2_MDQ34
AD2
D2_MDQ35
Y1
D2_MDQ36
AA1
D2_MDQ37
AC1
D2_MDQ38
AC3
D2_MDQ39
AD5
D2_MDQ40
AE1
D2_MDQ41
AG1
D2_MDQ42
AG2
D2_MDQ43
AC4
D2_MDQ44
AD4
D2_MDQ45
AF3
D2_MDQ46
AF4
D2_MDQ47
AH3
D2_MDQ48
AJ1
D2_MDQ49
AM1
D2_MDQ50
AM3
D2_MDQ51
AH1
D2_MDQ52
AH2
D2_MDQ53
AL2
D2_MDQ54
AL3
D2_MDQ55
AK5
D2_MDQ56
AL5
D2_MDQ57
AK7
D2_MDQ58
AM7
D2_MDQ59
AK4
D2_MDQ60
AM4
D2_MDQ61
AM6
D2_MDQ62
AJ7
D2_MDQ63
F8
D2_MDIC_0
F7
D2_MDIC_1
D2_MA0
D2_MA1
D2_MA2
D2_MA3
D2_MA4
D2_MA5
D2_MA6
D2_MA7
D2_MA8
D2_MA9
D2_MA10
D2_MA11
D2_MA12
D2_MA13
D2_MA14
D2_MA15
D2_MWE_B
D2_MRAS_B
D2_MCAS_B
D2_MCS0_B
D2_MCS1_B
D2_MCS2_B
D2_MCS3_B
D2_MCKE0
D2_MCKE1
D2_MCKE2
D2_MCKE3
D2_MODT0
D2_MODT1
D2_MODT2
D2_MODT3
M2_TSERIES
10
R4
M2_TSERIES
11
P1
M2_TSERIES
12
AH5
M2_TSERIES
13
P4
M2_TSERIES
14
N1
M2_TSERIES
15
Y4
27A1,28A1
27D8,28D8
B
M2_MDM(8:0)
D2_MDQ27
D2_MDQ28
27A1,28A1
M2_MECC(7:0)
D2_MDQ17
D2_MDQ18
27B8,28B8,29A1
27B1,28B1
M2_MBA(2:0)
27B1,28B1,29D1
M2_MA(15:0)
27B1,28B1,29C1
C
M2_MWE*
M2_MRAS*
M2_MCAS*
M2_TSERIES
W3
AB5
M2_TSERIES
Y3
M2_TSERIES
0
AF6
M2_TSERIES
1
AA5
M2_TSERIES
2
AF7
M2_TSERIES
3
N6
M2_TSERIES
0
N5
M2_TSERIES
1
N2
M2_TSERIES
2
N3
AE6
M2_TSERIES
3
M2_TSERIES
0
M2_TSERIES
AG7
M2_TSERIES
1
AE5
M2_TSERIES
2
AH6
M2_TSERIES
3
27C1,28C1,29C1
27C1,28C1,29C1
27C1,28C1,29C1
M2_MCS*(3:0)
27C1,28C1,29C1
M2_MCKE(3:0)
27D1,28D1,29C1
D
M2_MODT(3:0)
27D1,28D1,29D1
Date Changed: Thursday, February 1, 2007
Engineer:
3
MEMORY #2
D2_MDQ8
HPCN: Argo Navis
1.03
D2_MVREF
U32
Gary Milliorn
4
Title: DDR-II Interface #2
Time Changed: 2:10:48 pm
5
6
Page:
7
26
8
1
2
3
5
4
6
8
7
P5
conn_240_ddr2_vert_1of2
FOXCONN
M2_MDQS(8:0)
M2_MDQS_B(8:0)
26A8,28A1
26A8,28A1
7
0
6
0
16
1
15
1
28
2
27
2
A
37
3
36
3
84
4
83
4
5
93
6
105
92
5
104
6
114
7
113
7
8
46
0
125
45
8
M2_MDM(8:0)
26B8,28B1
B
M2_MBA(2:0)
26C8,28B1,29D1
M2_MA(15:0)
26C8,28B1,29C1
1
134
2
146
3
155
4
202
5
211
6
223
7
232
8
164
0
71
1
2
190
54
0
188
1
183
2
63
3
182
4
61
5
60
6
180
7
58
8
179
9
177
70
10
26D8,28C1,29C1
C
26D8,28C1,29C1
26D8,28C1,29C1
57
12
176
13
196
14
174
15
173
73
M2_MWE*
M2_MRAS*
M2_MCAS*
M2_MCS*(3:0)
26C8,28C1,29C1
11
192
74
0
193
1
76
185
M2_MCLK0p
M2_MCLK0n
M2_MCLK1p
M2_MCLK1n
M2_MCLK2p
M2_MCLK2n
26A1
26A1
26A1
26A1
26A1
26A1
186
137
138
220
221
M2_MODT(3:0)
26D8,28D1,29D1
M2_MCKE(3:0)
26D8,28D1,29C1
0
195
1
77
0
52
1
171
18
MEM_RST*
14B8,23D1,24D1,28D1
55
NC
119
I2C2_SDA
I2C2_SCL
13C1,19C8,23D1,24D1,28D1,#6
13D1,19C8,23D1,24D1,28D1,#6
120
239
VCC_3.3
C242
D
C243
240
C244
101
PLACE CAPS BY
DIMM PINS
freescale
semiconductor
1
5pF
5pF
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
(DQS9)
(DQS10)
(DQS11)
(DQS12)
(DQS13)
(DQS14)
(DQS15)
(DQS16)
(DQS17)
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
AT24013-D3-4F
DDR2 DIMM
DQS0
DQS0n
DQS1
DQS1n
DQS2
DQS2n
DQS3
DQS3n
DQS4
DQS4n
DQS5
DQS5n
DQS6
DQS6n
DQS7
DQS7n
DQS8
DQS8n
(AP)
WE
RAS
CAS
S0
S1
NC
102
Not Supported
CK_H0
CK_L0
CK_H1
CK_L1
CK_H2
CK_L2
126, 135, 147, 156
165, 203, 212, 224
233
ODT0
ODT1
CKE0
CKE1
RESET
RC
SDA
SCL
SA0
SA1
SA2
DIMM #3 SPD
ADDR=0x53
(ECC0)
(ECC1)
(ECC2)
(ECC3)
(ECC4)
(ECC5)
(ECC6)
(ECC7)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
3
4
0
9
2
M2_MDQ(63:0)
26A1,28A8
1
10
3
122
4
123
5
128
6
VTT_B
VCC_DDRB_IO
P5
conn_240_ddr2_vert_2of2
FOXCONN
AT24013-D3-4F
C245
53
129
7
12
8
13
9
21
10
22
11
131
12
132
13
140
14
141
15
24
16
25
17
30
18
51
31
19
56
143
20
144
21
149
22
150
23
33
24
34
25
59
0.1uF
64
C246
67
69
172
0.1uF
178
C247
184
187
189
0.1uF
197
C248
0.1uF
62
C249
72
75
78
0.1uF
170
C250
175
39
26
181
40
27
191
152
28
153
29
158
30
159
31
80
81
32
86
34
87
35
199
36
200
37
205
38
0.1uF
39
89
40
90
41
95
42
96
43
208
44
209
45
214
46
215
47
98
48
99
49
107
50
108
51
217
52
218
53
226
54
227
55
110
56
111
57
116
58
117
59
229
60
230
61
235
62
236
63
42
0
43
1
48
2
49
3
161
4
162
5
194
C251
A
19
PWR2_SEL_OPT1
68
PWR1_SEL_OPT1
66
PWR2_SEL_OPT2
50
PWR1_SEL_OPT2
NC
NC
NC
GROUND
2, 5, 8, 11, 14, 17, 20,
23, 26, 29, 32, 35, 38,
41, 44, 47, 65,
79, 82, 85, 88, 91,
94, 97, 100, 103, 106,
109, 112, 115, 118, 121,
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
124, 127, 130, 133, 136,
139, 142, 145, 148, 151,
154, 157, 160, 163, 166,
VCC_3.3
169, 198, 201, 204, 207,
210, 213, 216, 219, 222,
225, 228, 231, 234, 237
VDDSPD
VREF
238
1
B
M2_MVREF
26A8,28B8,29A1
C261
0.1uF
0.1uF
33
206
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
C252
0.1uF
C253
0.1uF
C254
0.1uF
C255
0.1uF
C256
C
0.1uF
C257
0.1uF
C258
0.1uF
C259
0.1uF
167
6
168
7
C260
0.1uF
D
M2_MECC(7:0)
26B8,28D8
5pF
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: DDR-II Interface #2 DIMM Socket #1
Time Changed: 2:10:56 pm
5
6
7
Page:
27
8
1
2
3
4
5
6
7
8
P4
conn_240_ddr2_vert_1of2
FOXCONN
M2_MDQS(8:0)
M2_MDQS_B(8:0)
26A8,27A1
26A8,27A1
7
0
6
0
16
1
15
1
2
28
3
37
27
2
A
36
3
84
4
83
4
93
5
92
5
105
6
104
6
114
7
113
7
8
46
0
125
45
8
M2_MDM(8:0)
26B8,27B1
B
M2_MBA(2:0)
26C8,27B1,29D1
M2_MA(15:0)
26C8,27B1,29C1
1
134
2
146
3
155
4
202
5
211
6
223
7
232
8
164
0
71
1
2
190
54
0
188
1
183
2
63
3
182
4
61
5
60
6
180
7
58
8
179
9
177
70
10
26D8,27C1,29C1
C
26D8,27C1,29C1
26D8,27C1,29C1
57
12
176
13
196
14
174
15
173
73
M2_MWE*
M2_MRAS*
M2_MCAS*
M2_MCS*(3:0)
26C8,27C1,29C1
11
192
74
2
193
3
76
185
M2_MCLK3p
M2_MCLK3n
M2_MCLK4p
M2_MCLK4n
M2_MCLK5p
M2_MCLK5n
26A1
26A1
26A1
26A1
26A1
26A1
186
137
138
220
221
M2_MODT(3:0)
26D8,27D1,29D1
M2_MCKE(3:0)
26D8,27D1,29C1
2
195
3
77
2
52
3
171
18
MEM_RST*
14B8,23D1,24D1,27D1
55
NC
119
I2C2_SDA
I2C2_SCL
13C1,19C8,23D1,24D1,27D1,#6
13D1,19C8,23D1,24D1,27D1,#6
120
239
VCC_3.3
C311
D
C312
240
C313
101
PLACE CAPS BY
DIMM PINS
freescale
semiconductor
1
5pF
5pF
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
(DQS9)
(DQS10)
(DQS11)
(DQS12)
(DQS13)
(DQS14)
(DQS15)
(DQS16)
(DQS17)
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
BA0
BA1
BA2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
AT24013-D3-4F
DDR2 DIMM
DQS0
DQS0n
DQS1
DQS1n
DQS2
DQS2n
DQS3
DQS3n
DQS4
DQS4n
DQS5
DQS5n
DQS6
DQS6n
DQS7
DQS7n
DQS8
DQS8n
(AP)
WE
RAS
CAS
S0
S1
NC
102
Not Supported
CK_H0
CK_L0
CK_H1
CK_L1
CK_H2
CK_L2
126, 135, 147, 156
165, 203, 212, 224
233
ODT0
ODT1
CKE0
CKE1
RESET
RC
SDA
SCL
SA0
SA1
SA2
DIMM #4 SPD
ADDR=0x54
(ECC0)
(ECC1)
(ECC2)
(ECC3)
(ECC4)
(ECC5)
(ECC6)
(ECC7)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
3
4
0
9
2
10
3
122
4
123
5
128
6
M2_MDQ(63:0)
26A1,27A8
1
VTT_B
VCC_DDRB_IO
P4
conn_240_ddr2_vert_2of2
FOXCONN
AT24013-D3-4F
C314
53
129
7
12
8
13
9
21
10
69
22
11
172
131
12
132
13
140
14
141
15
24
16
59
0.1uF
64
C315
67
0.1uF
178
C316
184
187
189
0.1uF
197
25
17
30
18
51
31
19
56
143
20
144
21
149
22
150
23
33
24
34
25
39
26
181
40
27
191
152
28
153
29
158
30
159
31
80
81
32
86
34
C317
0.1uF
35
199
36
200
37
205
38
206
39
89
40
90
41
95
42
96
43
208
44
209
45
214
46
215
47
98
48
99
49
107
50
108
51
217
52
218
53
226
54
227
55
110
56
111
57
116
58
117
59
229
60
230
61
235
62
236
63
42
0
43
1
48
2
49
3
161
4
162
5
167
6
168
7
62
C318
72
75
78
0.1uF
170
C319
175
0.1uF
194
C320
A
19
PWR2_SEL_OPT1
68
PWR1_SEL_OPT1
66
PWR2_SEL_OPT2
50
PWR1_SEL_OPT2
NC
NC
NC
GROUND
2, 5, 8, 11, 14, 17, 20,
23, 26, 29, 32, 35, 38,
41, 44, 47, 65,
79, 82, 85, 88, 91,
94, 97, 100, 103, 106,
109, 112, 115, 118, 121,
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
124, 127, 130, 133, 136,
139, 142, 145, 148, 151,
154, 157, 160, 163, 166,
VCC_3.3
169, 198, 201, 204, 207,
210, 213, 216, 219, 222,
225, 228, 231, 234, 237
VDDSPD
VREF
238
1
B
M2_MVREF
26A8,27B8,29A1
C330
0.1uF
0.1uF
C321
33
87
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
0.1uF
C322
0.1uF
C323
0.1uF
C324
0.1uF
C325
C
0.1uF
C326
0.1uF
C327
0.1uF
C328
0.1uF
C329
0.1uF
D
M2_MECC(7:0)
26B8,27D8
5pF
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: DDR-II Interface #2 DIMM Socket #2
Time Changed: 2:11:04 pm
5
6
7
Page:
28
8
1
2
3
4
5
VTT_B
VCC_5
6
7
VCC_3.3
8
VCC_5
VCC_5
4.7K
100K
4.7K
C566
10uF
4.7K
POWER_TRACE
C563
10uF
C590
C567
10uF
C572
10uF
0.1uF
R436
R435
U35
R434
A
R433
R686
4.7K
A
5
6
7
8
TPS51116PWP
Q11
IRF7821PBF
so8
4
1
20
VLDOIN
VBST
VTT
DRVH
2
3
R414
VTTGND
LL
VTTSNS
DRVL
GND
PGND
4
100K
No_Stuff
5
6
M2_MVREF
26A8,27B8,28B8
MODE
CS
7
POWER_TRACE
VTTREF
V5IN
8
COMP
PGOOD
9
C573
0.1uF
VDDQSNS
S5
10
C578
4.7uF
10V
OSCON
R423
R415
0
100K
1
18
2
3
17
L8
1
16
2
15
1UH
14
20A
5
13
6
7
+
Q12
IRF7832PBF
so8
4
S3
IMAX=20A
8
12
11
VDDQSET
+
VCC_DDRB_IO
19
C597
150uF
4V
OSCON
+
C599
150uF
4V
OSCON
tssop20HT
1
2
3
No_Stuff
M2_DDR_IOPWRGD
B
14C2,56C1
M2_DDR_IOPWR_S3
54D8
M2_DDR_IOPWR_S5
54D8
VTT_B
C561
0.1uF
C568
0.1uF
C564
0.1uF
C570
0.1uF
C574
0.1uF
C576
0.1uF
C579
0.1uF
C583
0.1uF
C581
0.1uF
R697
VTT SENSE
Place at midpoint of VTT fill plane.
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
0
R432
10 11 12 13 14 15
R429
9
R428
8
R427
R426
R425
R422
7
R424
5
R421
4
R420
3
R419
2
R418
1
R417
R413
0
R416
R412
3
R411
2
R410
1
R409
R407
R403
0
R431
26D8,27D1,28D1
2
R430
26C8,27B1,28B1
1
R408
26C8,27B1,28B1
0
R406
26D8,27C1,28C1
R405
26D8,27D1,28D1
R404
26C8,27C1,28C1
R402
26D8,27C1,28C1
R400
M2_MRAS*
M2_MCAS*
M2_MWE*
M2_MCKE(3:0)
M2_MCS*(3:0)
M2_MA(15:0)
M2_MBA(2:0)
M2_MODT(3:0)
26D8,27C1,28C1
R401
R399
R398
R396
R397
C
0
1
2
C
VTT TERMINATION PLANE
Place resistors immediately behind DIMM on a plane
Place capacitors behind or intermingled with resistors.
One capacitor per four VTT resistors.
3
6
0
1
2
3
0
0
0
C562
22pF
D
freescale
semiconductor
1
B
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
C565
22pF
C569
22pF
1
Project:
Revision:
C575
22pF
2
C577
22pF
C580
22pF
C582
22pF
C584
22pF
HPCN: Argo Navis
3
5
4
6
7
9
8
10
12
11
14
13
2
1
15
C585
22pF
C586
22pF
C587
22pF
C588
22pF
C589
22pF
C591
22pF
C592
22pF
C593
22pF
C594
22pF
C595
22pF
C596
22pF
C598
22pF
C600
22pF
C601
22pF
C602
22pF
C603
22pF
C604
22pF
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
3
2
C571
22pF
1
Gary Milliorn
4
Title: DDR-II Interface #2 Power and Termination
Time Changed: 2:11:16 pm
5
6
7
Page:
29
8
D
1
2
3
4
18B8,31A1
A
R139
No_Stuff
0
TSEC1
R145
10
1CM_MAX
AF25
1
TSEC1
R146
10
1CM_MAX
AC23
2
TSEC1
R147
10
1CM_MAX
AG24
3
TSEC1
R148
10
1CM_MAX
AG23
1K
R140
1K
R141
1K
TSEC1_TXCTL
31B1
NC
AE22
AD22
cfg_tsec1_prtcl
10
R149
TSEC1
AC22
TP19
TSEC1_TXCLK
AH26
AH25
TSEC1
AM24
AM25
TSEC1_RXD(3:0)
31B1
0
TSEC1
AL25
1
TSEC1
AL24
2
TSEC1
AK26
3
TSEC1
AK25
AM26
AF26
AH24
AG25
B
TSEC1_RXCTL
31B1
AJ25
TSEC1_RXCLK
31B1
AK24
TSEC1
ETHERNET
ETSEC1_TXD0
ETSEC3_TXD0
ETSEC1_TXD1
ETSEC3_TXD1
ETSEC1_TXD2
ETSEC3_TXD2
ETSEC1_TXD3
ETSEC3_TXD3
ETSEC1_TXD4
ETSEC3_TXD4
ETSEC1_TXD5
ETSEC3_TXD5
ETSEC1_TXD6
ETSEC3_TXD6
ETSEC1_TXD7
ETSEC3_TXD7
TSEC2_TXD(3:0)
18A8,31B1
0
TSEC2
1
TSEC2
R151
2
3
No_Stuff
R10
R142
No_Stuff
1K
1K
R143
1K
R144
1K
TSEC2_TXCTL
31C1
R9
1K
1CM_MAX
AB20
10
1CM_MAX
AJ23
TSEC2
R152
10
1CM_MAX
AJ22
TSEC2
R153
10
1CM_MAX
AD19
AH23
cfg_dram_type0
AH21
cfg_tsec2_reduce
AG22
AG21
cfg_tsec2_prtcl
10
R154
TSEC2
No_Stuff
10
1CM_MAX
ETSEC3_TX_EN
ETSEC1_TX_ER
ETSEC3_TX_ER
ETSEC1_TX_CLK
ETSEC3_TX_CLK
ETSEC1_GTX_CLK
ETSEC3_GTX_CLK
ETSEC1_CRS
ETSEC3_CRS
ETSEC1_COL
ETSEC3_COL
ETSEC1_RXD0
13
AC21
TP20
TSEC2_TXCLK
31C1
AD20
TSEC2
AE20
AE21
ETSEC1_RXD1
ETSEC3_RXD1
ETSEC1_RXD2
ETSEC3_RXD2
ETSEC1_RXD3
ETSEC3_RXD3
ETSEC1_RXD4
ETSEC3_RXD4
ETSEC1_RXD5
ETSEC3_RXD5
ETSEC1_RXD6
ETSEC3_RXD6
ETSEC1_RXD7
ETSEC3_RXD7
C
0
TSEC2
AL22
1
TSEC2
AK22
2
3
AM21
TSEC2
AH20
TSEC2
AG20
AF20
AF23
AF22
TSEC2_RXCTL
31D1
ETSEC3_RX_DV
ETSEC1_RX_ER
AD21
TSEC2_RXCLK
31D1
AM22
TSEC2
ETSEC3_RX_ER
ETSEC2_TXD0
ETSEC4_TXD0
ETSEC2_TXD1
ETSEC4_TXD1
ETSEC2_TXD2
ETSEC4_TXD2
ETSEC2_TXD3
ETSEC4_TXD3
ETSEC2_TXD4
ETSEC4_TXD4
ETSEC2_TXD5
ETSEC4_TXD5
ETSEC2_TXD6
ETSEC4_TXD6
ETSEC2_TXD7
ETSEC4_TXD7
AL23
1
AM23
R155
No_Stuff
No_Stuff
12A8,32B1
0
15
10
TSEC3
0
R167
10
TSEC3
1
AM20
1CM_MAX
R168
10
TSEC3
2
AJ20
1CM_MAX
R169
10
TSEC3
3
AM19
NC
AK21
AH17
1CM_MAX
R170
R174
330
R171
1K
R172
1K
R173
1K
10
ETSEC4_TX_ER
ETSEC2_TX_ER
ETSEC2_TX_CLK
ETSEC4_TX_CLK
ETSEC2_GTX_CLK
ETSEC4_GTX_CLK
ETSEC2_CRS
ETSEC4_CRS
2 4
ETSEC4_RXD0
ETSEC2_RXD1
ETSEC4_RXD1
ETSEC2_RXD2
ETSEC4_RXD2
ETSEC2_RXD3
ETSEC4_RXD3
ETSEC2_RXD4
ETSEC4_RXD4
ETSEC2_RXD5
ETSEC4_RXD5
ETSEC2_RXD6
ETSEC4_RXD6
ETSEC2_RXD7
ETSEC4_RXD7
17B8
No_Stuff
TSEC3
TSEC3_TXCTL
TSEC3
TSEC3_TXCLK
31B8
NC
AH18
TP21
AG19
31B8
AE15
AF15
AJ17
TSEC3
0
AE16
TSEC3
1
AH16
TSEC3
2
AH14
TSEC3
3
TSEC3_RXD(3:0)
31B8
AJ19
AH15
AG16
AE19
TSEC3
TSEC3_RXCTL
TSEC3
TSEC3_RXCLK
B
31B8
AF16
AJ18
AC18
1CM_MAX
R161
10
TSEC4
0
AC16
1CM_MAX
R162
10
TSEC4
1
AD18
1CM_MAX
R163
10
TSEC4
2
AD17
31B8
1CM_MAX
R164
10
TSEC4
TSEC4_TXD(3:0)
cfg_lynx_vdd_sel
R159
1K
AB18
cfg_tsec4_reduce
R175
1K
R176
1K
R177
1K
AB17
cfg_tsec4_prtcl
AB16
AF19
1CM_MAX
R165
10
18B8,31B8
3
AD16
No_Stuff
No_Stuff
TSEC4
TSEC4_TXCTL
TSEC4
TSEC4_TXCLK
31C8
NC
AF18
TP22
AG17
31C8
AB14
AC13
AG14
TSEC4
0
AD13
TSEC4
1
AF13
TSEC4
2
AD14
TSEC4
3
ETSEC4_RX_DV
ETSEC2_RX_ER
ETSEC4_RX_ER
TSEC4_RXD(3:0)
31C8
C
AE14
AB15
AC14
AE17
AC15
ETSEC2_RX_DV
EC2_GTX_CLK125
CFG_ASMP
ETSEC4_COL
ETSEC2_RXD0
EC1_GTX_CLK125
31A8
A
cfg_tsec3_reduce
cfg_tsec3_prtcl
AL19
TSEC3_TXD(3:0)
cfg_core2_trans
AL20
AF17
ETSEC4_TX_EN
ETSEC2_TX_EN
ETSEC2_RX_CLK
PHYCLK(0:2)
R166
1CM_MAX
ETSEC3_RX_CLK
AC19
TSEC2
1CM_MAX
AJ21
AG15
ETSEC1_RX_DV
ETSEC2_COL
TSEC2_RXD(3:0)
31C1
ETSEC3_RXD0
AB21
AB19
cfg_dram_type1
AL21
AH19
ETSEC1_TX_EN
ETSEC1_RX_CLK
R150
8
mc8641d.4of9.ethernet.cbga1023
AJ24
TSEC1
7
MC8641D
AB22
1CM_MAX
NC
31B1
AE24
AE23
cfg_tsec1_reduce
6
U32
NOTE: Series terminations can be omitted
if trace lengths are < 3 inches; this is not
anticipated for ArgoNavis.
TSEC1_TXD(3:0)
5
TSEC4
TSEC4_RXCTL
TSEC4
TSEC4_RXCLK
31D8
AF14
AG13
31D8
ETSEC4_RX_CLK
EC_MDC
EC_MDIO
MDC
MDIO
G31
G32
32A1
32A1
R158
15
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
C167
10pF
No_Stuff
No_Stuff
Optional: EMI tweaks.
C168
10pF
D
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: MC8641 Ethernet Ports
Time Changed: 2:11:27 pm
5
6
Page:
7
30
8
1
2
3
4
5
6
7
8
U6
vsc8244.2of3.macs.pbga260
A
TSEC1_TXD(3:0)
18B8,30A1
30A1
30A1
TSEC3_TXD(3:0)
VSC8244HG
3
TSEC1
T17
2
TSEC1
V18
1
TSEC1
U18
0
TSEC1
T18
TSEC1_TXCTL
TSEC1
U17
TSEC1_TXCLK
TSEC1
V17
TXD_3_0
TXD_3_2
TXD_2_0
TXD_2_2
TXD_1_0
TXD_1_2
TXD_0_0
TXD_0_2
TX_CTL_0
TX_CLK_0
TX_CTL_2
TX_CLK_2
V9
TSEC3
3
T10
TSEC3
2
U10
TSEC3
1
V10
TSEC3
0
U9
TSEC3
TSEC3_TXCTL
T9
TSEC3
TSEC3_TXCLK
TSEC1_RXD(3:0)
30B1
TSEC3_RXD(3:0)
B
3
TSEC1
T15
2
TSEC1
V16
1
TSEC1
U16
0
TSEC1
T16
TSEC1_RXCLK
TSEC1_RXCTL
30B1
30B1
TSEC1
V15
TSEC1
U15
RXD_3_0
RXD_3_2
RXD_2_0
RXD_2_2
RXD_1_0
RXD_1_2
RXD_0_0
RXD_0_2
RX_CLK_0
RX_CTL_0
RX_CLK_2
RX_CTL_2
V7
TSEC3
3
T8
TSEC3
2
U8
TSEC3
1
V8
TSEC3
0
T7
TSEC3
U7
TSEC3
TSEC3_RXCLK
TSEC3_RXCTL
TSEC4_TXD(3:0)
30C1
30C1
3
TSEC2
T13
2
TSEC2
V14
1
TSEC2
U14
0
TSEC2
T14
TSEC2_TXCTL
TSEC2
V13
TSEC2_TXCLK
TSEC2
U13
TXD_3_1
TXD_3_3
TXD_2_1
TXD_2_3
TXD_1_1
TXD_1_3
TXD_0_1
TXD_0_3
TX_CTL_1
TX_CLK_1
TX_CTL_3
TX_CLK_3
30A8
30A8
30B8
B
TSEC2_TXD(3:0)
18A8,30B1
A
30A8
V5
TSEC4
3
T6
TSEC4
2
U6
TSEC4
1
V6
TSEC4
0
U5
TSEC4
TSEC4_TXCTL
T5
TSEC4
TSEC4_TXCLK
30B8
30B8
18B8,30B8
30C8
30C8
C
C
TSEC4_RXD(3:0)
TSEC2_RXD(3:0)
30C1
TSEC2_RXCLK
TSEC2_RXCTL
30C1
30C1
3
TSEC2
V11
2
TSEC2
V12
1
TSEC2
U12
0
TSEC2
T12
TSEC2
T11
TSEC2
U11
RXD_3_1
RXD_3_3
RXD_2_1
RXD_2_3
RXD_1_1
RXD_1_3
RXD_0_1
RXD_0_3
RX_CLK_1
RX_CTL_1
RX_CLK_3
RX_CTL_3
V3
TSEC4
T4
TSEC4
2
U4
TSEC4
1
V4
TSEC4
0
V2
TSEC4
U3
TSEC4
30C8
3
TSEC4_RXCLK
TSEC4_RXCTL
30C8
30C8
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Quad Ethernet Port MACs
Time Changed: 2:11:35 pm
5
6
Page:
7
31
8
1
2
3
4
5
6
7
8
VCC_3.3
R215
R216
R217
4.7K
4.7K
4.7K
No_Stuff
vsc8244.3of3.sys_pwr.pbga260
MDC
MDIO
30D8
A
30D8
P16
P17
TDI
TDO
MDIO
TMS
IRQ*(0:11)
15C8,19B1,46C8
VSC8244HG
MDC
P18
10
N16
N17
N18
MDINT_0
TCK
MDINT_1
TRST
L18
NC
2
D17
TP26
K18
TP27
K17
TP28
R219
L16
VCC_3.3
4.7K
MDINT_3
CLK125MICRO
U6
EECLK
R17
NC
M18
NC
C216
1.0uF
EEDAT
REF_REXT
PHYCLK(0:2)
12A8,30D1
A
TP25
K16
MDINT_2
CLK125MAC
L17
J16
C9
R218
2.00K
1%
XTAL1
R220
REF_FILT
D18
NC
GEN_RST*
PHYRST*
14B8
14B8
M16
M17
RESET
VSS_1
SOFT_RESET
VSS_2
VSS_4
VSS_5
PHYPWR_CORE
D14
POWER_TRACE
D15
+
C176
22uF
6.3V
OSCON
C178
0.1uF
C179
0.1uF
C183
0.1uF
C190
0.1uF
C185
0.1uF
C195
0.1uF
C200
0.1uF
C205
0.1uF
C210
0.1uF
E4
E5
H3
J3
M3
N3
VCC_1.2
R3
VDD12_1
VSS_6
VDD12_2
VSS_7
VDD12_3
VSS_8
VDD12_4
VSS_9
VDD12_5
VSS_10
VDD12_6
VSS_11
VDD12_7
VSS_12
VDD12_8
VSS_13
VDD12_9
VSS_14
VSS_15
F12
PHYPWR_DIG
H4
POWER_TRACE
H15
+
C177
22uF
6.3V
OSCON
C180
0.1uF
C184
0.1uF
C186
0.1uF
C191
0.1uF
C196
0.1uF
C201
0.1uF
C211
0.1uF
C206
0.1uF
J4
J15
P4
R4
R14
R15
VDD_ENET_IO
VDDDIG_1
VSS_16
VDDDIG_2
VSS_17
VDDDIG_3
VSS_18
VDDDIG_4
VSS_19
VDDDIG_5
VSS_20
VDDDIG_6
VSS_21
VDDDIG_7
VSS_22
VDDDIG_8
VSS_23
VSS_24
VSS_25
R5
POWER_TRACE
R6
+
C
C181
22uF
6.3V
OSCON
C187
0.1uF
C192
0.1uF
C197
0.1uF
C202
0.1uF
C207
0.1uF
C212
0.1uF
R7
R9
R11
VCC_3.3
R12
VDDIO_MAC_1
VSS_26
VDDIO_MAC_2
VSS_27
VDDIO_MAC_3
VSS_28
VDDIO_MAC_4
VSS_29
VDDIO_MAC_5
VSS_30
VDDIO_MAC_6
VSS_31
VSS_32
C8
POWER_TRACE
D4
+
C182
22uF
6.3V
OSCON
C193
0.1uF
C188
0.1uF
C198
0.1uF
C203
0.1uF
C208
0.1uF
C213
0.1uF
D5
D6
D9
D10
D11
C194
0.1uF
C189
0.1uF
C199
0.1uF
C204
0.1uF
C214
0.1uF
C209
0.1uF
D12
D13
F15
G15
L4
R16
VDD33_1
VSS_33
VDD33_2
VSS_34
VDD33_3
VSS_35
VDD33_4
VSS_36
NC
VDD33_5
VSS_37
See spec.
VDD33_6
VSS_38
VDD33_7
VSS_39
VDD33_8
VSS_40
VDD33_9
VSS_41
VDD33_10
VSS_42
VDD33_11
VSS_43
VDD33_12
VSS_44
VDD33_13
VSS_45
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
3
VSSIO_7
VSSIO_6
VSSIO_5
VSS_48
C12
C13
C14
D7
D8
B
F2
G4
G7
G8
G9
G10
G11
G12
H7
H8
H9
H10
H11
H12
J7
J8
J9
J10
J11
J12
K2
K3
C
K4
K7
K8
K9
K10
K11
K12
L3
L7
L8
L9
L10
L11
L12
M4
N4
N15
P2
P3
P15
M15
M12
VSSIO_3
VSSIO_4
VSS_47
C11
D
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
M11
VSSIO_2
D
M10
M9
M8
VDD_MICRO
M7
L15
VDD_CTL
VSSIO_1
VSS_46
K15
1.0uF
0 ohms
VCC_1.2
F11
C215
XTAL2
VSS_3
B
C10
Gary Milliorn
4
Title: Quad Ethernet Port Power and Control
Time Changed: 2:11:43 pm
5
6
7
Page:
32
8
1
2
MDI0_P0
MDI0_N0
MDI0_P1
MDI0_N1
MDI0_P2
MDI0_N2
MDI0_P3
MDI0_N3
34B1
34B1
34B1
A
3
34B1
34B1
34B1
34B1
34B1
5
4
CLASS=[
PHY0_0]
DIFF_PHY
A18
CLASS=[
PHY0_0]
DIFF_PHY
B18
CLASS=[
PHY0_1]
DIFF_PHY
A17
CLASS=[
PHY0_1]
DIFF_PHY
B17
CLASS=[
PHY0_2]
DIFF_PHY
A16
CLASS=[
PHY0_2]
DIFF_PHY
B16
CLASS=[
PHY0_3]
DIFF_PHY
A15
CLASS=[
PHY0_3]
DIFF_PHY
B15
TP29
TP30
TP31
M0_LEDS(0:1)
34A1
MDI1_P0
MDI1_N0
MDI1_P1
MDI1_N1
MDI1_P2
MDI1_N2
MDI1_P3
MDI1_N3
35B1
35B1
35B1
35B1
35B1
35B1
35B1
35B1
J18
J17
H18
1
H17
0
H16
CLASS=[
PHY1_0]
DIFF_PHY
A14
CLASS=[
PHY1_0]
DIFF_PHY
B14
CLASS=[
PHY1_1]
DIFF_PHY
A13
CLASS=[
PHY1_1]
DIFF_PHY
B13
CLASS=[
PHY1_2]
DIFF_PHY
A12
CLASS=[
PHY1_2]
DIFF_PHY
B12
CLASS=[
PHY1_3]
DIFF_PHY
A11
CLASS=[
PHY1_3]
DIFF_PHY
B11
6
U6
vsc8244.1of3.ports.pbga260
VSC8244HG
TXVPA_0
TXVNA_0
TXVPA_2
TXVNA_2
TXVPB_0
TXVPB_2
TXVNB_0
TXVNB_2
TXVPC_0
TXVPC_2
TXVNC_0
TXVNC_2
0
TXVPD_0
TXVND_0
2
TXVPD_2
TXVND_2
LED4_0
LED4_2
LED3_0
LED3_2
LED2_2
LED2_0
LED1_2
LED1_0
LED0_0
LED0_2
TXVPA_1
TXVPA_3
TXVNA_1
TXVNA_3
TXVPB_1
TXVPB_3
TXVNB_1
TXVNB_3
TXVPC_1
TXVPC_3
TXVNC_1
TXVNC_3
1
TXVPD_1
TXVND_1
3
TXVPD_3
TXVND_3
7
A10
CLASS=[
PHY2_0]
DIFF_PHY
B10
CLASS=[
PHY2_0]
DIFF_PHY
A9
CLASS=[
PHY2_1]
DIFF_PHY
B9
CLASS=[
PHY2_1]
DIFF_PHY
A8
CLASS=[
PHY2_2]
DIFF_PHY
B8
CLASS=[
PHY2_2]
DIFF_PHY
A7
CLASS=[
PHY2_3]
DIFF_PHY
B7
CLASS=[
PHY2_3]
DIFF_PHY
C5
C4
C3
8
MDI2_P0
MDI2_N0
MDI2_P1
MDI2_N1
MDI2_P2
MDI2_N2
MDI2_P3
MDI2_N3
34C1
34C1
A
34C1
34C1
34C1
34C1
34C1
34C1
TP35
TP36
TP37
B2
1
A2
0
M2_LEDS(0:1)
A6
CLASS=[
PHY3_0]
DIFF_PHY
B6
CLASS=[
PHY3_0]
DIFF_PHY
A5
CLASS=[
PHY3_1]
DIFF_PHY
B5
CLASS=[
PHY3_1]
DIFF_PHY
A4
CLASS=[
PHY3_2]
DIFF_PHY
B4
CLASS=[
PHY3_2]
DIFF_PHY
A3
CLASS=[
PHY3_3]
DIFF_PHY
B3
CLASS=[
PHY3_3]
DIFF_PHY
34D1
MDI3_P0
MDI3_N0
MDI3_P1
MDI3_N1
MDI3_P2
MDI3_N2
MDI3_P3
MDI3_N3
35C1
35C1
35C1
35C1
35C1
35C1
35C1
35C1
B
B
TP32
TP33
TP34
M1_LEDS(0:1)
35A1
G18
G17
G16
1
F18
0
F17
LED4_1
LED4_3
LED3_1
LED3_3
LED2_1
LED2_3
LED1_1
LED1_3
LED0_1
LED0_3
A1
D3
E3
TP38
TP39
TP40
F3
1
G3
0
M3_LEDS(0:1)
35D1
VCC_3.3
CMode
0
1
C
2
3
4
5
6
7
D
freescale
semiconductor
1
bit
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Definition
=1
Advertise Symmetric Pause
LED0[1]
LED0[0]
MAC Interface[1]
Advertise Asymmetric Pause
LED1[1]
LED1[0]
MAC Interface[2]
Phy Crossover Mode
LED2[1]
LED2[0]
PHY Address[2]
Speed/Dup Modes[0]
LED3[1]
LED3[0]
PHY Address[3]
Speed/Dup Modes[1]
LED4[1]
LED4[0]
PHY Address[4]
=0
LED Combine 10/100/1G/Act
LED Combine Col/Dup
RGMII Clock Skew[0]
=0
LED Combine Link/Act
LED PulseStretch/Blink
RGMII Clock Skew[1]
=0
ActiPHY
Link Speed Downshift Ena.
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Value
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
Set
Resistor
1100
8.25K -> 3.3V
1100
8.25K -> 3.3V
1000
0 -> 3.3V
0000
0 -> GND
0000
0 -> GND
0001
2.26K -> GND
R221
8.25K
1%
2CM_MAX
F16
R222
8.25K
1%
2CM_MAX
E18
R223
0
1%
2CM_MAX
E17
R224
0
2CM_MAX
E16
R225
0
2CM_MAX
D16
R226
2.26K
1%
2CM_MAX
C18
R227
12.1K
1%
2CM_MAX
C17
R228
22.6K
1%
2CM_MAX
C16
CMODE0
TXREF_0
CMODE1
TXREF_1
CMODE2
TXREF_2
CMODE3
TXREF_3
R13
R10
R8
T3
CMODE4
MICRO_REF
CMODE5
R18
CMODE6
CMODE7
C
0101
12.1K -> GND
1111
22.6K -> 3.3V
Project:
Revision:
NOTE: RGMII-ID mode of VSC8244 used
to implement both TX/RX clock delays
in lieu of routing restrictions.
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
D
Gary Milliorn
4
Title: Quad Ethernet Port MII Interfaces
Time Changed: 2:11:52 pm
5
6
7
Page:
33
8
1
2
3
4
5
6
7
8
A
A
VCC_3.3
M0_LEDS(0:1)
33B1
0
1
M0_1GACT*
M0_100ACT*
R229
R230
R231
R232
100
100
100
100
J38
conn.rj45.2x1vert.led.ra
MDI0_P0
MDI0_N0
33A1
33A1
0845-2R1T-E4
31
UPPER
32
G
6
RJ1
MDI0_P1
MDI0_N1
33A1
33A1
7
13
RJ2
11
RJ3
12
MDI0_P2
MDI0_N2
33A1
33A1
5
RJ6
3
RJ4
4
B
B
10
RJ5
MDI0_P3
MDI0_N3
33A1
33A1
8
RJ7
9
2
RJ8
33
C219
0.1uF
C217
0.1uF
C221
0.1uF
34
C223
0.1uF
Y
G
1
S2
HVCap
LOWER
27
28
MDI2_P0
MDI2_N0
33A8
33A8
G
15
RJ1
14
21
RJ2
23
RJ3
MDI2_P1
MDI2_N1
33A8
33A8
22
16
RJ6
18
RJ4
17
MDI2_P2
MDI2_N2
33A8
33A8
24
RJ5
26
RJ7
25
C
C
19
RJ8
MDI2_P3
MDI2_N3
33A8
33A8
29
C218
0.1uF
C220
0.1uF
C222
0.1uF
30
C224
0.1uF
Y
G
20
S1
HVCap
C225
10pF
M2_LEDS(0:1)
33B8
0
1
M2_1GACT*
M2_100ACT*
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Ethernet Ports #1 and #3
Time Changed: 2:12:00 pm
5
6
Page:
7
34
8
1
2
3
4
5
6
7
8
A
A
VCC_3.3
M1_LEDS(0:1)
33B1
0
1
M1_1GACT*
M1_100ACT*
R233
R234
R235
R236
100
100
100
100
J39
conn.rj45.2x1vert.led.ra
0845-2R1T-E4
MDI1_P0
MDI1_N0
33B1
33B1
31
UPPER
32
G
6
RJ1
7
MDI1_P1
MDI1_N1
33B1
33B1
13
RJ2
11
RJ3
12
5
RJ6
MDI1_P2
MDI1_N2
33B1
33B1
B
3
RJ4
4
B
10
RJ5
8
RJ7
MDI1_P3
MDI1_N3
33B1
33B1
9
2
RJ8
33
C226
0.1uF
C228
0.1uF
C230
0.1uF
34
C232
0.1uF
Y
G
1
S2
HVCap
LOWER
27
28
MDI3_P0
MDI3_N0
33B8
33B8
G
15
RJ1
14
21
RJ2
23
RJ3
MDI3_P1
MDI3_N1
33B8
33B8
22
16
RJ6
18
RJ4
17
MDI3_P2
MDI3_N2
33B8
33B8
24
RJ5
26
RJ7
25
C
C
19
RJ8
MDI3_P3
MDI3_N3
33B8
33B8
29
C229
0.1uF
C227
0.1uF
C231
0.1uF
30
C233
0.1uF
Y
G
20
S1
HVCap
C234
10pF
M3_LEDS(0:1)
33B8
0
1
M3_1GACT*
M3_100ACT*
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Ethernet Ports #2 and #4
Time Changed: 2:12:12 pm
5
6
Page:
7
35
8
1
2
3
4
5
6
7
8
A
A
VCC_5
VCC_5
VCC_3.3
U45
lt1331cg.ssop28
SYS
LINE
UART1_TXD
UART2_TXD
UART1_RTS*
19C8
19C8
19C8
25
23
19
NC
16
24
UART1_RXD
19C8
NC
UART1_CTS*
UART2_RXD
19C8
19C8
21
20
18
13
1CM_MAX
C160
0.1uF
B
C162
0.1uF
1CM_MAX
1CM_MAX
C161
0.1uF
C163
0.1uF
1CM_MAX
D1IN
D1OUT
D2IN
D2OUT
D3IN
D3OUT
2CM_MAX
5
7
2CM_MAX
11
NC
DRVDIS
R1OUT
22
J9
conn.db9.plug.rta
R1IN
R2OUT
R2IN
R3OUT
R3IN
R4OUT
R4IN
R5OUT
R5IN
6
NC
NC
2CM_MAX
8
9
5
4
3
2
1
9
8
7
6
NC
NC
Serial Port #1
NC
2CM_MAX
10
12
ON
3
C1+
VCC
C1-
VL
C2+
V+
2
1
4
26
27
V-
C2GND
17
14
1
1CM_MAX
28
1CM_MAX
2
J1
header.1x3
3
Serial Port #2
No_Stuff
Requires custom cable.
B
NC
15
C164
0.1uF
C165
0.1uF
NC
C
C
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Serial Ports
Time Changed: 2:12:20 pm
5
6
Page:
7
36
8
1
2
3
4
5
6
7
8
LB_DP(0:3)
18A8,41C1
LB_LA(27:31)
LB_LAD(0:31)
18A8,41B1
LB_LAD(0:31)
18B8
A
A
U40
74ALVCH32973ZKER
4.7K
4.7K
4.7K
R138
R137
R136
4.7K
4.7K
R134
R135
4.7K
4.7K
R132
R133
4.7K
4.7K
4.7K
4.7K
R131
R130
R129
R696
4.7K
R160
4.7K
4.7K
R128
U32
R127
R126
4.7K
No_Stuff
VCC_3.3
0
A1
1
B1
2
C1
3
D1
4
E1
5
F1
6
G1
7
H1
1A1
1Q1
1A2
1Q2
1A3
1Q3
1A4
1Q4
1A5
1Q5
1A6
1Q6
1A7
1Q7
1A8
1Q8
U42
74ALVCH32973ZKER
A6
0
16
A1
B6
1
17
B1
2
18
C1
3
19
D1
C6
D6
E6
4
20
E1
F6
5
21
F1
G6
6
22
G1
H6
7
23
H1
A5
0
B5
1
1B1
mc8641d.5of9.localbus.cbga1023
1B2
LOCALBUS
B
0
LBUS_LATCH
1
LBUS_LATCH
E29
2
LBUS_LATCH
C29
3
LBUS_LATCH
D28
4
LBUS_LATCH
D29
5
LBUS_LATCH
H25
6
LBUS_LATCH
B29
7
LBUS_LATCH
A29
8
LBUS_LATCH
C28
9
LBUS_LATCH
L22
10
LBUS_LATCH
M22
11
LBUS_LATCH
A28
12
LBUS_LATCH
C27
G26
LBUS_LATCH
14
B27
LBUS_LATCH
15
16
LBUS_LATCH
B26
17
LBUS_LATCH
A27
18
E27
LBUS_LATCH
G25
LBUS_LATCH
19
D26
LBUS_LATCH
20
E26
LBUS_LATCH
21
C
H26
LBUS_LATCH
13
22
LBUS_LATCH
G24
23
LBUS_LATCH
F27
24
LBUS_LATCH
A26
25
LBUS_LATCH
A25
26
LBUS_LATCH
C25
27
LBUS_LATCH
H23
28
LBUS_LATCH
29
LBUS_LATCH
K22
D25
F25
LBUS_LATCH
30
LBUS_LATCH
H22
27
LBUS
LBUSLN
J21
28
LBUS
LBUSLN
K21
29
LBUS
LBUSLN
G22
30
LBUS
LBUSLN
F24
31
LBUS
LBUSLN
G21
31
A22
A30
LAD0
LCS0
LAD1
LCS1
LAD2
LCS2
LAD3
LCS3
LAD4
LCS4
LAD5
LCS5_DMA_DREQ2
LAD6
LCS6_DMA_DACK2
LAD7
LCS7_DMA_DDONE2
R244
C22
1CM_MAX
R361
27
1
H3
D23
1CM_MAX
R693
27
2
H4
E22
1CM_MAX
R694
A23
LBUS
4
A4
LBUS
5
A3
B23
27
0
27
E23
LBUS
6
F23
LBUS
7
LAD9
LAD10
LWE0_LBS0
LWE1_LBS1
LWE2_LBS2
LWE3_LBS3
LAD12
LAD13
LAD14
LAD15
J1
9
K1
10
L1
M1
N1
LBUS
1
13
P1
D22
LBUS
2
14
R1
E20
LBUS
3
15
T1
F21
1B5
1LOE
1B6
27
1DIR
2Q2
2A2
GND
2Q3
2A3
B3 B4
D3 D4
E3 E4
G3 G4
2Q4
K3 K4
M3 M4
N3 N4
R3 R4
2Q7
2A4
2A5
2A6
2A7
2A8
2Q5
2Q6
2B1
2B2
D21
1CM_MAX
R119
0
8
K6
9
24
J1
L6
10
25
K1
M6
11
26
L1
12
27
M1
13
28
N1
R6
14
29
P1
15
30
R1
31
T1
J5
8
K5
9
M5
T3
LALE
LAD21
E19
1CM_MAX
R120
0
T4
390
R121
J4
LGPL0_LSDA10
LGPL1_LSDWE
LGPL2_LOE_LSDRAS
LGPL3_LSDCAS
LGPL4_LGTA_LUPWAIT_LPBSE
LGPL5
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LCKE
LAD31
LA27
F20
LBUS
0
H20
LBUS
1
J20
LBUS
2
K20
LBUS
3
LA29
LA30
NC
L21
LBUS
4
J19
LBUS
5
NC
NC
NC
H19
TP17
LCLK0
L19
LCLK1
M20
LCLK2
LA28
R700
4.7K
NC
NC
NC
1CM_MAX
R122
27
0
1CM_MAX
R123
27
1
1CM_MAX
2LOE
2B6
P5
2DIR
J3
NC
G19
2B5
C2
13
T4
14
15
E2
G2
J2
L2
N2
R2
Y1
D2
Y2
D3
Y3
D4
Y4
D5
Y5
D6
Y6
D7
Y7
D8
Y8
D2
F2
H2
K2
M2
P2
T2
21
G6
22
H6
23
A5
16
B5
17
C5
18
D5
19
1LE
1B5
1LOE
1B6
E5
20
F5
21
1DIR
G5
22
H5
23
1B8
1TOE
see map for
pwr pins
2Q2
2A2
GND
2Q3
2A3
B3 B4
D3 D4
E3 E4
G3 G4
2Q4
K3 K4
M3 M4
N3 N4
R3 R4
2Q7
2A4
2A5
2A6
2A7
2A8
2Q5
2Q6
J6
24
K6
25
L6
26
M6
27
N6
28
P6
29
R6
30
T6
31
2Q8
2LE
2B5
2LOE
2B6
2DIR
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B
J5
24
K5
25
L5
26
M5
27
N5
28
P5
29
R5
30
T5
31
2B7
J4
REV 4
TP18
20
F6
2B4
J3
D1
1Q8
E6
2B3
T3
T5
2B8
B2
1Q7
1A8
19
2B2
2TOE
A2
1A7
18
D6
2B1
12
R5
2B7
LAD22
LAD23
N5
2LE
1Q6
11
2B4
LAD20
1Q5
1A6
10
2B3
LAD19
1A5
2Q1
P6
L5
1Q4
2A1
N6
T6
1A4
17
C6
1B7
A4
J6
2Q8
LAD17
LBCTL
H4
A3
1TOE
see map for
pwr pins
LAD16
LAD18
H3
7
1Q3
16
B6
1B4
4
6
1A3
A6
1B3
5
H5
1Q2
1B2
F5
G5
1Q1
1A2
1B1
E5
1B8
2A1
11
R695
1LE
2Q1
8
12
1CM_MAX
3
1B7
0
E21
2
D5
1B4
3
LAD8
LAD11
C5
1B3
1CM_MAX
1A1
2B8
2TOE
A2
C2
E2
G2
J2
L2
N2
R2
D1
Y1
D2
Y2
D3
Y3
D4
Y4
D5
Y5
D6
Y6
D7
Y7
D8
Y8
B2
D2
F2
H2
K2
M2
P2
T2
NC
NC
NC
C
NC
NC
NC
NC
NC
REV 4
OCT 23 2002
OCT 23 2002
lfbga96_016pad
lfbga96_016pad
LA31
0
LBUS_LATCH
A24
1
LBUS_LATCH
E24
2
LBUS_LATCH
C24
3
LBUS_LATCH
B24
LBCTL
41B1
R124
LDP0
M19
LSYNC_IN
D20
LSYNC_OUT
LDP1
LDP2
2CM_MAX
LB_D(0:31)
LB_A(0:31)
0
LBUS
2CM_MAX
15D8,38A1,39A1,41A1
15C8,38A1,39A1,41B1
R125
LDP3
LB_CS*(0:7)
27
C166
10pF
No_Stuff
15B8,39A1,41C1
LALEX
41B1
LB_WE*(0:3)
LB_GPL(0:5)
LB_CLK(0:1)
15A8,18B8,38B1,41B1
15A8,18B8,38B1,39A1,41C1
15B8,41A1
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: LocalBus Interface and Demultiplexer
Time Changed: 2:12:29 pm
5
6
7
Page:
37
8
1
2
4
3
5
6
7
8
LB_D(0:31)
LB_A(0:31)
15D8,37D8,39A1,41A1
15C8,37D8,39A1,41B1
VCC_3.3
U17
VCC_3.3
A
C235
0.1uF
VCC_3.3
5
9
1
Vcc
25
29
24
28
23
27
22
26
21
25
20
24
19
23
18
22
8
21
7
20
6
19
5
18
4
17
3
16
2
15
1
14
48
13
17
12
16
11
15
4
10
9
2CM_MAX
SN74LVC1G86DBVR
2
sot23_5p
CFG_FLASHBANK
14B2,17B8
B
C236
0.1uF
30
10
U15
26
15A8,18B8,37D8,39A1,41C1
15A8
0
FWE*
LB_GPL(0:5)
PJCS*
2
FOE*
A
WR_H*
A2
DQ0
A3
DQ1
A4
DQ2
A5
DQ3
A6
DQ4
A7
DQ5
A8
DQ6
A9
DQ7
A10
DQ8
A11
DQ9
A12
DQ10
A13
DQ11
A14
DQ12
A15
A16
A17
A18
2
1
NC
DQ13
VCC_3.3
DQ14
37
DQ15
GND
29
15
31
14
33
13
35
12
38
11
40
10
42
9
44
8
30
7
32
6
34
5
36
4
39
3
41
2
43
1
45
0
C238
0.1uF
C239
0.1uF
30
VCC_3.3
R238
5
C237
0.1uF
A0
3
4
CS*
5
6
OE*
15
D0
7
8
D8
7
14
D1
9
10
D9
6
13
D2
11
12
D10
5
12
D3
13
14
D11
4
VCC
15
16
D4
11
3
D12
17
18
D5
10
2
D13
19
20
D6
9
1
D14
21
22
D7
8
0
D15
23
24
GND
A16
14
A14
25
NC
27
26
16
28
A15
15
NC
VCC_3.3
Header for EmuTec PROMJET attach.
Leave 1.5 cm around header clearance.
27,46
WR_L*
NC
GND
SHORT_POWER
A19
18
A12
29
30
A13
17
20
A10
31
32
A11
19
22
A8
33
34
A9
21
10
A20
35
36
A21
9
7
A23
37
38
NC
NC
NC
R237
1K
A20
A21
ACC
CE
28
LB_WE*(0:3)
FCS*
J12
header_2x25_05sp
47
A1
WE
3
15A8
VIO
A0
11
GND
15A8,18B8,37D8,41B1
VCC_3.3
am29lv641d.tsop48w
WP
OE
RESET
13
TP41
14
12
12
A18
39
NC
41
40
A22
8
42
A19
11
23
A7
43
44
A17
13
25
A5
45
46
A6
24
27
A3
47
48
A4
26
29
A1
49
50
A2
28
B
PromJet Pinout
Note little-endian conversion
CFG_FLASHWP*
LB_RST*
17B8,55B1
14B8,39C1,41C1
VCC_3.3
U19
S29GL064M90BFIR5
C
30
G2
29
F2
28
E2
27
C2
26
D2
25
F3
24
E3
23
C3
22
D6
21
C6
20
E6
19
F6
18
D7
17
C7
16
E7
15
F7
14
G7
13
D3
12
E4
11
F5
10
F4
E5
bga63
A0
VCC
J5
A1
H7
A2
VIO
A3
C
A4
DQ0
A5
A6
DQ1
A7
DQ2
A8
DQ3
A9
DQ4
A10
DQ5
A11
DQ6
A12
DQ7
A13
DQ8
A14
DQ9
A15
DQ10
A16
DQ11
A17
DQ12
A18
DQ13
A19
DQ14
A20
DQ15
G3
15
K3
14
G4
13
K4
12
K5
11
G5
10
K6
9
G6
8
H3
7
J3
6
H4
5
J4
4
H5
3
J6
2
H6
1
J7
0
Alternate flash build option.
Place BGA flash under TSOP flash
A21
C4
TP42
RY_BYn
D4
WPn_ACC
D5
RESETn
D
D
NC
C5
WEn
H2
CSn
J2
Y
OEn
Ax, Bx
Lx
Mx
GND1
GND2
K2
K7
No_Stuff
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
Date Changed: Wednesday, November 8, 2006
HPCN: Argo Navis
Engineer:
1.03
3
Gary Milliorn
4
Title: Local Bus - Flash and Flash Emulator
Time Changed: 10:23:30 am
5
6
7
Page:
38
8
1
2
A
3
4
5
6
7
8
A
LB_D(0:31)
LB_A(0:31)
15D8,37D8,38A1,41A1
15C8,37D8,38A1,41B1
LB_GPL(0:5)
LB_CS*(0:7)
15A8,18B8,37D8,38B1,41C1
15B8,37D8,41C1
1
CF_OE*
2
CF_CE1*
Compact Flash Mapping
VCC_3.3
VCC_3.3
R239
R240
R241
1K
1K
10K
C240
0.1uF
Pin
2
3
4
5
6
8
10
11
12
14
15
16
17
18
19
20
21
22
23
44
C241
0.1uF
J13
conn.cflash.vert.sm
CF_CD*
15C8
NC
B
NC
NC
NC
NC
CF_CS1*
NC
NC
NC
2
CF_WE*
CF_RDYBSY*
15C8
NC
LB_RST*
14B8,38C1,41C1
4
CF_WAIT*
NC
16
NC
NC
NC
26
1
27
2
4
28
3
3
29
4
2
30
5
1
31
6
0
32
7
33
8
34
9
35
10
22
36
11
23
37
12
24
38
13
39
14
25
40
15
26
41
16
27
42
17
28
43
18
29
44
19
30
45
20
46
21
7
47
22
6
48
23
49
24
50
25
21
Function
D03
D04
D05
D06
D07
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
D00
D01
D02
REG-
Connection
LB_D[4]
LB_D[3]
LB_D[2]
LB_D[1]
LB_D[0]
LB_A[21]
LB_A[22]
LB_A[23]
LB_A[24]
LB_A[25]
LB_A[26]
LB_A[27]
LB_A[28]
LB_A[29]
LB_A[30]
LB_A[31]
LB_D[7]
LB_D[6]
LB_D[5]
LB_A[16]
B
31
5
NC
C
C
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
Date Changed: Thursday, February 1, 2007
HPCN: Argo Navis
Engineer:
1.03
3
Gary Milliorn
4
Title: Compact Flash Interface
Time Changed: 2:12:42 pm
5
6
Page:
7
39
8
1
2
3
4
5
6
7
8
U27
at24c64a.s08
8K x 8 serial EEPROM
DATA
19C8
19C8
A
7
A2
WC
NC
3
A0
A1
2
6
CLK
GND
4
1
I2C1_SDA
I2C1_SCL
5
VCC_3.3
8
PROCESSOR INIT EEPROM
Address = 0x50 or 0x51.
A
CFG_SERROM_ADDR
17C8
VCC_3.3
VCC_3.3
8
VCC
J25
header.1x4
U21
ltc4300_1.ms8
1
3
SCL_O
SCL_I
2
2
REMOTE PROGRAMMING
HEADER
3
4
6
1
B
SDA_I
SDA_O
ENABLE
READY
7
C386
0.1uF
5
B
NC
GND
4
VCC_3.3
U26
at24c02.tssop8
256 x 8
serial EEprom
1
2
SYSTEM EEPROM / MAC Address
Address = 0x57
3
I2C2_SCL
I2C2_SDA
6
A0
SCL
A1
SDA
5
13D1,19C8,23D1,24D1,27D1,#6
13C1,19C8,23D1,24D1,27D1,#6
VCC
GND
A2
7
4
8
WP
C
C
CFG_IDWP
C805
0.1uF
17D8
U55
at24c02.tssop8
256 x 8
serial EEprom
1
DINK ENV EEPROM
Address = 0x56
2
3
6
A0
SCL
A1
SDA
5
8
WP
4
VCC
7
NC
GND
A2
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Miscellaneous I2C Bus Devices
Time Changed: 2:12:50 pm
5
6
7
Page:
40
8
1
2
3
4
5
6
7
8
A
A
LB_D(0:31)
15D8,37D8,38A1,39A1
LB_CLK(0:1)
LALEX
15B8,37D8
37D8
0
LB_A(0:31)
15C8,37D8,38A1,39A1
ADDR
J22
STAT
J21
conn.mictor.38
1
NC
38
NC
37
NC
LBCTL
LB_WE*(0:3)
37C8
15A8,18B8,37D8,38B1
LB_GPL(0:5)
15A8,18B8,37D8,38B1,39A1
LB_RST*
PIXIS_DEBUG(0:1)
15A1
C
15B8,37D8,39A1
37
:
:
19
20
19
20
7
PIN
27
8
3
CKQ_0_3
CLK_EVEN
26
9
4
POD3-7
D15EVEN
25
10
5
POD3-6
D14EVEN
6
POD3-5
D13EVEN
D12EVEN
24
11
7
POD3-4
D11EVEN
23
12
8
POD3-3
22
13
CKQ_0_3
CLK_EVEN
27
9
4
POD3-7
D15EVEN
28
10
5
POD3-6
D14EVEN
6
POD3-5
D13EVEN
29
11
7
POD3-4
30
12
8
POD3-3
31
13
TEK
HP
9
POD3-2
D10EVEN
10
POD3-1
D9EVEN
11
POD3-0
D8EVEN
TEK
POD2-7
13
POD2-6
POD2-5
D5EVEN
18
17
14
15
POD2-4
D4EVEN
16
POD2-3
D3EVEN
2
17
14
17
POD2-2
D2EVEN
18
POD2-1
D1EVEN
19
POD2-0
D0EVEN
20
POD0-0
D0ODD
21
POD0-1
D1ODD
17
18
16
19
36
15
35
20
0
4
1
5
2
6
3
7
PIN
4
8
3
CKQ_0_3
CLK_EVEN
4
POD3-7
D15EVEN
5
TEK
HP
POD3-6
D14EVEN
6
POD3-5
D13EVEN
7
POD3-4
D12EVEN
D11EVEN
8
12
8
POD3-3
9
13
D8EVEN
12
19
B
11
POD3-0
16
:
7
11
15
POD2-6
37
:
D12EVEN
D10EVEN
20
POD2-7
13
38
2
9
D9EVEN
19
12
16
1
3
10
POD3-1
D6EVEN
15
3
is numbered Tek style
SDA
5
POD3-2
D7EVEN
4
Note: This connector
SCL
6
9
14
14
HP
10
21
5
LA5V
NC
6
3
36
:
28
8
19
37
:
29
0
0
38
2
5
PIN
18
1
37
NC
4
7
38
NC
is numbered Tek style
SDA
30
6
NC
Note: This connector
SCL
31
1
conn.mictor.38
1
LA5V
3
2
D11EVEN
9
POD3-2
D10EVEN
10
POD3-1
D9EVEN
11
POD3-0
D8EVEN
10
14
D7EVEN
11
15
12
POD2-7
D7EVEN
D6EVEN
12
16
13
POD2-6
D6EVEN
POD2-5
D5EVEN
13
17
14
POD2-5
D5EVEN
15
POD2-4
D4EVEN
15
POD2-4
D4EVEN
16
POD2-3
D3EVEN
16
POD2-3
D3EVEN
17
POD2-2
D2EVEN
18
POD2-1
D1EVEN
19
POD2-0
D0EVEN
20
POD0-0
D0ODD
21
POD0-1
D1ODD
17
POD2-2
D2EVEN
18
POD2-1
D1EVEN
19
POD2-0
D0EVEN
20
POD0-0
D0ODD
21
POD0-1
D1ODD
14
18
15
19
36
NC
16
35
1
34
22
POD0-2
D2ODD
14
34
22
POD0-2
D2ODD
17
34
22
POD0-2
D2ODD
0
33
23
POD0-3
D3ODD
13
33
23
POD0-3
D3ODD
18
33
23
POD0-3
D3ODD
32
24
POD0-4
D4ODD
32
24
POD0-4
D4ODD
32
24
POD0-4
D4ODD
25
POD0-5
D5ODD
25
POD0-5
D5ODD
25
POD0-5
D5ODD
3
12
19
2
31
26
POD0-6
D6ODD
11
31
26
POD0-6
D6ODD
20
31
26
POD0-6
D6ODD
1
30
27
POD0-7
D7ODD
10
30
27
POD0-7
D7ODD
21
30
27
POD0-7
D7ODD
0
29
28
POD1-0
D8ODD
9
29
28
POD1-0
D8ODD
22
29
28
POD1-0
D8ODD
28
29
POD1-1
D9ODD
28
29
POD1-1
D9ODD
28
29
POD1-1
D9ODD
30
POD1-2
D10ODD
30
POD1-2
D10ODD
30
POD1-2
D10ODD
TP64
7
LB_CS*(0:7)
38
2
5
35
LB_DP(0:3)
18A8,37A8
1
37
NC
3
TP63
14B8,38C1,39C1
3
1
38
NC
is numbered Tek style
SDA
4
LB_LA(27:31)
18A8,37A8
NC
Note: This connector
SCL
B
TP62
conn.mictor.38
1
LA5V
DATA
J23
27
8
7
27
23
24
27
31
POD1-3
D11ODD
31
POD1-3
D11ODD
31
POD1-3
D11ODD
6
26
32
POD1-4
D12ODD
6
26
32
POD1-4
D12ODD
25
26
32
POD1-4
D12ODD
5
25
33
POD1-5
D13ODD
5
25
33
POD1-5
D13ODD
26
25
33
POD1-5
D13ODD
4
24
34
POD1-6
D14ODD
4
24
34
POD1-6
D14ODD
27
24
34
POD1-6
D14ODD
35
POD1-7
D15ODD
35
POD1-7
D15ODD
35
POD1-7
D15ODD
36
CKQ_1_2
CLK_ODD
36
CKQ_1_2
CLK_ODD
36
CKQ_1_2
CLK_ODD
3
23
2
28
23
22
29
22
1
21
30
21
0
20
31
20
3
23
22
2
1
21
0
20
2
GROUND
GROUND
2
39,40,41,42,43
GROUND
GROUND
2
39,40,41,42,43
C
GROUND
GROUND
39,40,41,42,43
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Local Bus Debug
Time Changed: 2:13:00 pm
5
6
Page:
7
41
8
1
3
2
4
5
6
7
8
SerDes TX AC Coupling Caps
Must have symmetric placement and near the port pins
A
A
C333
CLASS=[
SD2_TX0 ]
DIFF_SERDES
CLASS=[
SD2_TX0 ]
DIFF_SERDES
CLASS=[
SD2_TX1 ]
DIFF_SERDES
CLASS=[
SD2_TX1 ]
DIFF_SERDES
CLASS=[
SD2_TX2 ]
DIFF_SERDES
CLASS=[
SD2_TX2 ]
DIFF_SERDES
CLASS=[
SD2_TX3 ]
DIFF_SERDES
CLASS=[
SD2_TX3 ]
DIFF_SERDES
CLASS=[
SD2_TX4 ]
DIFF_SERDES
CLASS=[
SD2_TX4 ]
DIFF_SERDES
CLASS=[
SD2_TX5 ]
DIFF_SERDES
CLASS=[
SD2_TX5 ]
DIFF_SERDES
CLASS=[
SD2_TX6 ]
DIFF_SERDES
CLASS=[
SD2_TX6 ]
DIFF_SERDES
CLASS=[
SD2_TX7 ]
DIFF_SERDES
CLASS=[
SD2_TX7 ]
DIFF_SERDES
AE32
CLASS=[
SD2_CLK ]
DIFF_SERIES
AE31
CLASS=[
SD2_CLK ]
DIFF_SERIES
SD2_TX_P(7:0)
0
43C1
C341
0.1uF
0
SD2_TX_N(7:0)
43C1
C334
0.1uF
1
C342
0.1uF
1
C335
0.1uF
U32
mc8641d.7of9.serdes_2.cbga1023
0.1uF
SD2_RX_P(7:0)
SD2_RX_N(7:0)
43C8
0
0
1
1
2
2
3
3
B
4
4
5
CLASS=[
SD2_RX0 ]
DIFF_SERDES
Y30
CLASS=[
SD2_RX0 ]
DIFF_SERDES
Y29
CLASS=[
SD2_RX1 ]
DIFF_SERDES
AA32
CLASS=[
SD2_RX1 ]
DIFF_SERDES
CLASS=[
SD2_RX2 ]
DIFF_SERDES
AA31
AB30
CLASS=[
SD2_RX2 ]
DIFF_SERDES
AB29
CLASS=[
SD2_RX3 ]
DIFF_SERDES
AC32
CLASS=[
SD2_RX3 ]
DIFF_SERDES
AC31
CLASS=[
SD2_RX4 ]
DIFF_SERDES
6
6
7
7
AH29
CLASS=[
SD2_RX4 ]
DIFF_SERDES
CLASS=[
SD2_RX5 ]
DIFF_SERDES
AJ32
DIFF_SERDES
AJ31
CLASS=[
5
AH30
SD2_RX5 ]
CLASS=[
SD2_RX6 ]
DIFF_SERDES
AK30
CLASS=[
SD2_RX6 ]
DIFF_SERDES
AK29
CLASS=[
SD2_RX7 ]
DIFF_SERDES
AL32
CLASS=[
SD2_RX7 ]
DIFF_SERDES
AL31
SD_2_TX0
SD_2_RX0
SD_2_TX0_B
SD_2_RX0_B
SD_2_TX1
SD_2_RX1
SD_2_RX1_B
SD_2_RX2
SD_2_TX1_B
SD_2_RX2_B
SD_2_TX2_B
SD_2_TX2
SD_2_RX3
SD_2_TX3
SD_2_RX3_B
SD_2_RX4
Y24
DIFF_SERDES_AC
Y25
DIFF_SERDES_AC
AA27
DIFF_SERDES_AC
AA28
DIFF_SERDES_AC
AB25
DIFF_SERDES_AC
AB26
DIFF_SERDES_AC
AC27
DIFF_SERDES_AC
AC28
DIFF_SERDES_AC
AE27
DIFF_SERDES_AC
SD_2_TX3_B
RX
TX
SD_2_RX4_B
SD_2_TX4
SD_2_TX4_B
SD_2_RX5
SD_2_TX5
SD_2_RX5_B
SD_2_TX5_B
SD_2_RX6
SD_2_TX6
SD_2_RX6_B
SD_2_TX6_B
SD_2_RX7
SD_2_TX7
SD_2_RX7_B
2
C336
SERDES 2
43C8
2
C343
AE28
AG27
DIFF_SERDES_AC
AG28
DIFF_SERDES_AC
DIFF_SERDES_AC
AJ28
DIFF_SERDES_AC
AL27
DIFF_SERDES_AC
AL28
DIFF_SERDES_AC
3
0.1uF
3
C337
0.1uF
4
C345
0.1uF
4
C338
0.1uF
B
5
C346
0.1uF
DIFF_SERDES_AC
AJ27
SD_2_TX7_B
0.1uF
C344
5
C339
0.1uF
6
C347
0.1uF
6
C340
0.1uF
VCC_SERDES
7
C348
0.1uF
SHORT_POWER
V28
R687
330
R688
330
W28
AG32
R302
AG31
SD2_RSV1
SD2_NC0
SD2_RSV0_B
SD2_NC1
SD2_RSV1
SD2_NC2
SD2_RSV1_B
SD2_NC3
W26
W27
AD25
AD26
7
TP69
0.1uF
TP70
TP71
TP72
1CM_MAX
1
SD_2_REF_CLK
C332
0.033uF
C331
1.0uF
SD_2_REF_CLK_B
AF32
AF30
C
AVDD_SRDS2
AGND_SRDS2
SD_2_DLL_TPA
AD30
R706
330
AD29
R707
330
AF31
R709
AF29
R708
SD_2_DLL_TPD
REFCLK_SD2p
REFCLK_SD2n
13C8
13C8
C
No_Stuff
R303
100
R304
200
1%
1%
1CM_MAX
AM29
1CM_MAX
AA26
SD_2_IMP_CAL_TX
SD_2_PLL_TPA
SD_2_PLL_TPD
SD_2_IMP_CAL_RX
330
330
No_Stuff
TP73
TP74
TP75
TP76
cbga_31x31_1mm_skt
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: MC8641D PCIExpress/SERDES/Lynx Port 2
Time Changed: 2:13:09 pm
5
6
7
Page:
42
8
1
2
3
4
5
VCC_HOT_3.3
A
6
VCC_12
C349
0.1uF
7
8
VCC_3.3
C350
0.1uF
C351
0.1uF
C352
0.1uF
A
C353
0.1uF
J24
pciexpress_conn_x16
REFCLK_SLOT1p
REFCLK_SLOT1n
13C8
13C8
A13
A1
REFCLKP
PRSNT1
REFCLKN
PRSNT2_1
B17
A14
B31
PRSNT2_2
PEX_RST*
14D2,45A1
A11
B48
PERST
PRSNT2_3
P3.3V_AUX
PRSNT2_4
B10
S1_PRSNT*
B81
54D8
A6
TDI
I2C2_SCL
I2C2_SDA
13D1,19C8,23D1,24D1,27D1,#6
13C1,19C8,23D1,24D1,27D1,#6
NC
A7
B5
SMCLK
TDO
SMDAT
TCK
NC
A5
B6
NC
A8
TMS
B11
TP77
TRST
B79
NC
NC
PETn15
PERn15
PETp15
PERp15
PETn14
PERn14
PETp14
PERp14
PETn13
PERn13
PETp13
PERp13
PETn12
PERn12
PETp12
PERp12
PETn11
PERn11
PETp11
PERp11
PETn10
PERn10
PETp10
PERp10
PETn9
PERn9
PETp9
PERp9
NC
SD2_TX_P(7:0)
C
SD2_TX_N(7:0)
42A8
PETn8
PERn8
PETp8
PERp8
+3.3V
PETn7
0
NC
SD2_RX_P(7:0)
A52
B46
0
NC
A53
B50
NC
NC
A56
B51
42A8
NC
A57
B54
NC
NC
A60
B55
NC
NC
A61
B58
NC
NC
A64
B59
NC
NC
A65
B62
NC
NC
A68
B63
NC
NC
A69
B66
NC
NC
A72
B67
NC
NC
A73
B70
NC
NC
A76
B71
NC
B
NC
A77
B74
NC
NC
A80
B75
NC
NC
A81
B78
B
NC
B9
WAKE_N
B45
NC
A47
C
SD2_RX_N(7:0)
0
A48
PERn7
B8 A9 A10
42B1
42B1
0
PERp7
PETp7
+12V
1
B42
1
A44
PETn6
1
PERn6
B1 B2 B3 A2 A3
1
A43
B41
PETp6
PERp6
GND
2
B38
PETn5
2
B37
PETp5
3
B34
PETn4
3
B33
PETp4
LANE REVERSAL
B28
4
PETn3
B27
4
Both RX and TX are reversed
to ease the routing for the
MPC8641D in an ATX chassis.
PETp3
5
A36
A35
3
4
A30
PERn3
A29
4
PERp3
B65 A66 A67 B68 B69
PERn2
B80 A82
PERp2
A26
5
A25
PETn1
PETp1
5
6
A22
NC
PERn1
6
A21
B3 B12 B30 A32 A33
A50 B82 A19
PERp1
B15
7
3
PERn4
A70 A71 B72 B73 A74
A75 B76 B77 A78 A79
B19
7
2
PERp4
B44 A45 A46 B47 B49
A49 A51 B52 B53 A54
A55 B56 B57 A58 A59
B60 B61 A62 A63 B64
PETp2
B20
6
2
A39
PERp5
B23
6
D
A40
PERn5
PETn2
B24
5
B4 A4 B7 A12 B13 A15
B16 B18 A18 A20 B21
B22 A23 A24 B25 B26
A27 A28 B29 A31 B32
A34 B35 B36 A37 A38
B39 B40 A41 A42 B43
7
A17
PETn0
PERn0
PETp0
PERp0
D
7
A16
B14
conn_pciexpress16
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: PCIExpress 8X Slot 1
Time Changed: 2:13:19 pm
5
6
Page:
7
43
8
1
2
3
4
5
6
7
8
SerDes TX AC Coupling Caps
Must have symmetric placement and near the port pins
A
A
C389
CLASS=[
SD1_TX0]
DIFF_SERDES
CLASS=[
SD1_TX0]
DIFF_SERDES
CLASS=[
SD1_TX1]
DIFF_SERDES
CLASS=[
SD1_TX1]
DIFF_SERDES
CLASS=[
SD1_TX2]
DIFF_SERDES
CLASS=[
SD1_TX2]
DIFF_SERDES
CLASS=[
SD1_TX3]
DIFF_SERDES
CLASS=[
SD1_TX3]
DIFF_SERDES
CLASS=[
SD1_TX4]
DIFF_SERDES
CLASS=[
SD1_TX4]
DIFF_SERDES
CLASS=[
SD1_TX5]
DIFF_SERDES
CLASS=[
SD1_TX5]
DIFF_SERDES
CLASS=[
SD1_TX6]
DIFF_SERDES
CLASS=[
SD1_TX6]
DIFF_SERDES
CLASS=[
SD1_TX7]
DIFF_SERDES
CLASS=[
SD1_TX7]
DIFF_SERDES
SD1_TX_P(7:0)
0
45B1,46A1
C397
0.1uF
0
SD1_TX_N(7:0)
45B1,46A1
C390
0.1uF
1
C398
0.1uF
1
C391
0.1uF
2
C399
mc8641d.6of9.serdes_1.cbga1023
0.1uF
SD1_RX_P(7:0)
SD1_RX_N(7:0)
45B8,46A1
45B8,46A1
0
0
1
1
2
2
3
3
B
4
4
5
CLASS=[
SD1_RX0 ]
DIFF_SERDES
J32
CLASS=[
SD1_RX0 ]
DIFF_SERDES
J31
CLASS=[
SD1_RX1 ]
DIFF_SERDES
K30
CLASS=[
SD1_RX1 ]
DIFF_SERDES
CLASS=[
SD1_RX2 ]
DIFF_SERDES
K29
L32
CLASS=[
SD1_RX2 ]
DIFF_SERDES
L31
CLASS=[
SD1_RX3 ]
DIFF_SERDES
M30
CLASS=[
SD1_RX3 ]
DIFF_SERDES
M29
CLASS=[
SD1_RX4 ]
DIFF_SERDES
T30
CLASS=[
SD1_RX4 ]
DIFF_SERDES
T29
CLASS=[
SD1_RX5 ]
DIFF_SERDES
U32
DIFF_SERDES
U31
CLASS=[
5
6
6
7
7
SD1_RX5 ]
CLASS=[
SD1_RX6 ]
DIFF_SERDES
V30
CLASS=[
SD1_RX6 ]
DIFF_SERDES
V29
CLASS=[
SD1_RX7 ]
DIFF_SERDES
W32
CLASS=[
SD1_RX7 ]
DIFF_SERDES
W31
SD_1_TX0
SD_1_RX0
U32
SD_1_RX0_B
SD_1_TX0_B
SD_1_TX1
SD_1_RX1
SD_1_RX1_B
SD_1_RX2
SD_1_TX1_B
SD_1_RX2_B
SD_1_TX2_B
SD_1_TX2
SD_1_RX3
SD_1_TX3
SD_1_RX3_B
SD_1_RX4
SD_1_TX3_B
RX
TX
SD_1_RX4_B
SD_1_TX4
SD_1_TX4_B
SD_1_RX5
SD_1_TX5
SD_1_RX5_B
SD_1_TX5_B
SD_1_RX6
SD_1_TX6
SD_1_RX6_B
SD_1_TX6_B
SD_1_RX7
SD_1_TX7
SD_1_RX7_B
SD_1_TX7_B
L26 DIFF_SERDES_AC
L27 DIFF_SERDES_AC
0.1uF
3
C400
M24 DIFF_SERDES_AC
M25 DIFF_SERDES_AC
0.1uF
3
C393
N26 DIFF_SERDES_AC
N27 DIFF_SERDES_AC
0.1uF
4
C401
P24 DIFF_SERDES_AC
P25 DIFF_SERDES_AC
0.1uF
4
C394
0.1uF
R26 DIFF_SERDES_AC
B
5
C402
R27 DIFF_SERDES_AC
T24 DIFF_SERDES_AC
0.1uF
T25 DIFF_SERDES_AC
U26 DIFF_SERDES_AC
5
C395
0.1uF
U27 DIFF_SERDES_AC
V24 DIFF_SERDES_AC
6
C403
0.1uF
V25 DIFF_SERDES_AC
6
C396
0.1uF
VCC_SERDES
7
C404
0.1uF
H30
SHORT_POWER
2
C392
SERDES 1
R689
330
R690
330
H29
R32
R309
R31
SD1_RSV1
SD1_NC0
SD1_RSV0_B
SD1_NC1
SD1_RSV1
SD1_NC2
SD1_RSV1_B
SD1_NC3
K24
K25
P28
P29
7
TP97
0.1uF
TP98
TP99
TP100
1CM_MAX
N32
1
SD_1_REF_CLK
C388
0.033uF
C387
1.0uF
P32
P30
C
REFCLK_SD1p
REFCLK_SD1n
N31
SD_1_REF_CLK_B
AVDD_SRDS1
AGND_SRDS1
SD_1_DLL_TPA
P31
R703
330
N28
R702
330
T28
R704
U28
R705
SD_1_DLL_TPD
13B8
13B8
C
No_Stuff
R310
100
R311
200
1%
1%
1CM_MAX
Y26
1CM_MAX
J28
SD_1_IMP_CAL_TX
SD_1_PLL_TPA
SD_1_PLL_TPD
SD_1_IMP_CAL_RX
330
330
No_Stuff
TP101
TP102
TP103
TP104
cbga_31x31_1mm_skt
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: MC8641D PCIExpress/SERDES/Lynx Port 1
Time Changed: 2:13:27 pm
5
6
7
Page:
44
8
2
1
3
VCC_12
4
VCC_3.3
C786
0.1uF
C785
0.1uF
6
5
7
8
VCC_HOT_3.3
C789
0.1uF
C788
0.1uF
C787
0.1uF
A
A
J36
pciexpress_conn_x4
13C8
13C8
REFCLK_SLOT2p
REFCLK_SLOT2n
A13
PEX_RST*
A11
A1
REFCLKP
PRSNT1
REFCLKN
PRSNT2_1
A14
B17
S2_PRSNT*
B31
PRSNT2_2
14D2,43B1
54D8
PERST
B10
P3.3V_AUX
A6
TDI
I2C2_SCL
I2C2_SDA
13D1,19C8,23D1,24D1,27D1,#6
13C1,19C8,23D1,24D1,27D1,#6
B5
NC
A7
SMCLK
TDO
B6
NC
A5
TCK
SMDAT
NC
A8
TMS
TP169
SD1_TX_P(7:0)
44A8,46A1
SD1_TX_N(7:0)
44A8,46A1
B11
WAKE_N
4
B27
PETp3
5
PETn2
B23
PETp2
6
PETn1
B19
PETp1
SerDes TX AC Coupling Caps
Must have symmetric placement and near the port pins
5
A25
PERp2
GND
6
A22
B
PERn1
B16 B18 A18 A20 B21
B22 A23 A24 B25 B26
A27 A28 B29 A31 B32
6
A21
PERp1
7
A17
PERn0
B3 B12 B30 A19 A32
B14
5
A26
PERn2
B1 B2 A2 A3
PETn0
7
44B1,46A1
4
A29
NC
B15
7
44B1,46A1
SD1_RX_N(7:0)
4
PERp3
B8 A9 A10
B4 A4 B7 A12 B13 A15
B20
6
SD1_RX_P(7:0)
PERn3
+3.3V
+12V
B24
5
NC
A30
PETn3
B
TRST
B28
4
NC
B9
7
A16
PETp0
PERp0
No_Stuff
J37
pciexpress_midbusprobe_gen_x16
J35
header_1x3_sm
FTR-103-02-S-S
REFCLK_TAPp
13C8
2
4
6
6
6
1
8
2
REFCLK_TAPn
13C8
10
4
3
12
4
14
16
2
18
2
MidPoint Tap Clock
Place near ’midbusprobe’
C
20
22
0
24
0
26
28
6
30
6
MidBus Tap is placed in the middle (obviously)
and all signals flow THROUGH the pads.
32
34
4
36
4
This pinout is optimized for uninterrupted
routing. Connections are made with flying
leads, so any (reasonable) pinout may be used.
38
40
2
42
2
44
46
0
48
0
GND0
CAp
CBp
CAn
CBn
GND8
GND1
CCp
CDp
CCn
CDn
GND9
GND2
CEp
CFp
CEn
CFn
GND10
GND3
CGp
CHp
CGn
CHn
GND11
GND4
CIp
CJp
CIn
CJn
GND12
GND5
CKp
CLp
CKn
CLn
GND13
GND6
CMp
CNp
CMn
CNn
GND14
GND7
CPp
CQp
CPn
CQn
GND15
1
7
7
3
5
7
5
5
9
11
13
3
3
15
17
19
C
1
1
21
23
7
25
7
27
29
5
31
5
33
35
3
37
3
39
41
1
43
1
45
47
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: PEX Alternate Slot + MidBus Probe
Time Changed: 2:13:35 pm
5
6
7
Page:
45
8
44A8,45B1
44B1,45B8
44B1,45B8
0
AA29
C372
0
0.1uF
C376
0
AA26
0.1uF
AA25
1
W28
1
W29
C373
1
0.1uF
C377
1
W26
0.1uF
W25
2
U28
2
U29
C374
2
0.1uF
C378
2
U26
0.1uF
U25
3
R28
3
R29
C375
3
0.1uF
C379
3
R26
0.1uF
R25
V29
PLACE CAPS CLOSE TO SB
R305
NC
2.2K
NC
B
NC
NC
NC
NC
NC
NC
VCC_1.8
NC
NC
NC
NC
NC
+
C357
1000uF
10V
+
C355
4.7uF
10V
OSCON
C358
1.0uF
C356
1.0uF
C360
1.0uF
C362
1.0uF
C364
0.1uF
C368
0.1uF
C366
0.1uF
C370
0.1uF
NC
NC
NC
NC
NC
NC
NC
NC
PLACE CAPS CLOSE TO SB VDD18M_CORE PINS
NC
NC
NC
C
VCC_1.8
NC
NC
NC
NC
NC
+
C354
1000uF
10V
+
C359
4.7uF
10V
OSCON
+
C361
4.7uF
10V
OSCON
+
C363
4.7uF
10V
OSCON
C365
0.1uF
C367
0.1uF
C369
0.1uF
C371
0.1uF
NC
NC
NC
NC
NC
NC
NC
PLACE CAPS CLOSE TO SB PCE_VDDA PINS
NC
G25
G26
G28
G29
H25
H26
H27
H28
H29
J25
J26
J27
J28
J29
J30
K25
K26
K27
K28
K29
L25
L26
L27
L28
L29
L30
M25
M26
M27
M28
M29
N25
N26
N27
N28
N29
N30
AJ30
AK30
AK29
AH28
V27
V28
AE30
AE29
AE28
AE27
AE26
AE25
PCE_VDD0
SB_TAP
PCE_VDD1
U37
PCE_VDD2
PCE_VDD3
SB_RBN
m1575.1of4.sb.bga628
SB_RBP
PCE_VDD4
PCE_VDD5
SB_TBN
SB_RCN
SB_RCP
SB_TCN
PCI-Express
SB_TCP
SB_RDN
SB_RDP
SB_TDN
SB_TDP
REF
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
2
Project:
Revision:
R19
C381
1.0uF
C383
1.0uF
C384
2.2uF
VCC_1.8
T19
U19
V19
VDD18M_CORE0
N12
P12
VDD18M_CORE2
R12
VDD18M_CORE3
T12
VDD18M_CORE4
U12
VDD18M_CORE5
V12
VDD18M_CORE6
M12
VDD18M_CORE7
M13
VDD18M_CORE8
M18
VDD18M_CORE9
M19
VDD18M_CORE10
M20
VDD18M_CORE11
W12
VDD18M_CORE12
W13
VDD18M_CORE13
W14
VDD18M_CORE14
W15
VDD18M_CORE15
W16
VDD18M_CORE16
W17
VDD18M_CORE17
W18
VDD18M_CORE18
W19
VDD18M_CORE19
W20
VDD18M_CORE20
Y17
VDD18M_CORE21
Y18
VDD18M_CORE22
Y19
VDD_CPU
NC13
nA20M
NC14
CPUPWG
NC15
nFERR
NC16
nCPURST
NC17
nIGNNE
NC
NC18
nSTPCLK
NC19
nSMI
NC20
NMI
NC21
INTR
NC22
nDSLEEP
VCC_3.3
+
R307
R308
62
1K
B
C382
4.7uF
10V
OSCON
C385
1.0uF
Y20
AK28
OHCI_INT*
1
AJ27
EHCI_INT*
1
AH29
SB_CPURST*
AH26
AH30
AG26
NC
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
SMI*
AJ29
AG29
NC
IRQ9*
AG28
AH27
14C2
NC
14D2,19B1,54B1
IRQ*(0:11)
9
15C8,19B1,32A1
NC
AJ28
nCPUHI
nSLEEP AG27
AK27
nINIT
AG25
nTHRM
AG24
nVRHI
AE23
DSPVRHI
AJ26
VRMPWG
NC
AH25
THRMTRIP
NC
HTTPWROK AF28 NC
AF29
nHTTRESET
NC
AG30
nHTTSTOP
NC
F25
VDD33R_IO0
F26
VDD33R_IO1
CPU
NC23
IRQ0*
IDE_IRQ15
3
SATA_INT*
0
R306
IRQ2*
IDE_IRQ14
3
AUDIO_INT*
2
C
SB_INIT*
THERM*
0
14D2
54B1
VCC_HOT_3.3
NC36
GND0
PCE_GND32
GND1
PCE_GND33
GND2
PCE_GND34
GND3
PCE_GND35
PCE_GND29
PCE_GND36
PCE_GND30
PCE_GND37
N18
P18
R18
T18
U18
V18
PCE_GND28
PCE_GND27
PCE_GND26
PCE_GND25
W30
D
V26
V25
U30
U27
PCE_GND24
G27
PCE_GND23
F27
PCE_GND22
G30
PCE_GND21
P25
PCE_GND20
P26
PCE_GND19
P27
PCE_GND18
P28
PCE_GND17
P29
PCE_GND14
PCE_GND15
PCE_GND16
R27
T26
R30
PCE_GND13
T27
PCE_GND12
T28
PCE_GND11
T29
PCE_GND10
AB29
PCE_GND9
AB28
PCE_GND8
AB27
PCE_GND7
AB26
PCE_GND5
PCE_GND3
PCE_GND4
PCE_GND6
AB25
AA30
Y29
AA27
PCE_GND1
PCE_GND2
Y28
Y27
W27
Date Changed: Thursday, February 1, 2007
Engineer:
3
C380
1.0uF
NC12
HPCN: Argo Navis
1.03
A
P19
VDD18M_CORE1
NC11
PCE_GND0
1
7700 W. Parmer Ln
Austin, Texas 78729
N19
NC10
Y26
semiconductor
Freescale Semiconductor
VCC_1.8
SB_TBP
D
TM
PLACE CAPS CLOSE TO SB PCE_VDD/VTT PINS
SB_RAP
SB_TAN
PCE_GND38
freescale
8
SB_RAN
PCE_GND31
VDD_SBCORE_1.8 = VCC_1.8V
7
VCC_1.8
PCE_VDDA17
PCE_VDDA16
PCE_VDDA15
PCE_VDDA14
PCE_VDDA13
AE24
AD29
AD27
AD26
AD25
V20
U20
T20
R20
P20
N20
AD28
PCE_VDDA9
PCE_VDDA8
PCE_VDDA7
PCE_VDDA6
PCE_VDDA5
PCE_VDDA4
PCE_VDDA3
PCE_VDDA2
PCE_VDDA1
PCE_VDDA0
T25
AC30
AC29
AC28
Y25
PCE_VTT7
PCE_VTT6
PCE_VTT5
PCE_VTT4
PCE_VDDA12
AA28
REFCLK_N
PCE_VDDA11
0
REFCLK_P
6
PCE_VDDA10
SD1_TX_N(7:0)
SD1_TX_P(7:0)
SD1_RX_N(7:0)
SD1_RX_P(7:0)
44A8,45B1
A
F29
PCE_VTT3
13C8
F28
PCE_VTT0
REFCLK_M1575p
REFCLK_M1575n
13C8
AC27
5
AC26
4
PCE_VTT2
3
AC25
2
PCE_VTT1
1
Tiffany Tran-Chandler
4
Title: South Bridge PEX Interface
Time Changed: 2:13:44 pm
5
6
Page:
7
46
8
2
3
4
N1
8
N2
9
M3
10
M2
11
M6
12
M5
13
L4
14
L5
15
K6
16
H6
17
J4
18
J1
19
J2
20
B
J3
22
H3
23
G4
24
F6
25
F5
26
G1
27
F4
28
G2
29
G3
30
F3
31
F2
0
N3
1
L1
2
H5
3
G5
PCI_FRAME*
PCI_IRDY*
PCI_TRDY*
PCI_DEVSEL*
PCI_SERR*
PCI_PAR
PCI_STOP*
16A1,51B1
16A1,51B1
16A1,51B1
16A1,51B1
16A1,51B1
16B1,51C1
16A1,51B1
AE6
AE7
VDD18R_CORE6
VDD18R_CORE5
AE5
AE4
VDD18R_CORE3
AE2
AE3
VDD18R_CORE2
AE1
VDD18R_CORE0
VDD18R_CORE1
W11
V11
U11
T11
P11
AC6
AA6
W6
T6
R11
VDD33M_IO9
VDD33M_IO8
VDD33M_IO7
VDD33M_IO6
N6
L6
J6
G6
AD3
PCICLK
PCICLKFBO
AD4
PCICLKFBI
K4
K5
J5
K3
PCICLK_SB
E7
R248
F8
U37
m1575.2of4.sb.bga628
AD6
AD7
PCICLK0
PCICLK1
AD8
PCICLK2
AD9
PCICLK3
AD10
PCICLK4
AD11
PCICLK5
PCI
AD12
PCICLK6
AD13
PCICLK7
AD14
PCICLK8
AD15
PCICLK9
15B1
A
33
E8
AD5
R1
R249
33
0
U5
R250
33
1
R6
R251
33
2
R5
R252
33
3
R2
R253
33
4
T3
TP43
NC
R3
T2
15B1,51B1,54A1,55B1
NC
U6
T4
PCI_CLK(0:4)
VCC_HOT_3.3
TP44
C265
NC
AD16
AD17
VDDSW
AD18
VDDBAT
AD19
VDD33R_RTC
V5
12pF
V3
Y1
V6
RTC
AD21
X32KI
AD22
X32KII
AD23
X32K_OSC_MODE
AD24
nRTCRST
ACZ_BITCLK
AD27
ACZ_SDOUT
AD28
ACZ_SYNC
AD29
ACB_BITCLK
AC97
AD30
ACB_SDOUT
AD31
ACB_SYNC
nCBE0
nVOLUME_MUTE
nCBE1
nVOLUME_DOWN
1M
No_Stuff
C266
U1
U2
V4
R245
0
12pF
V2
AD25
AD26
R257
32.768kHz
sm_xtal_4p
AD20
nVOLUME_UP
PCI_CBE*(3:0)
16B1,51C1
H2
21
8
1
N5
7
7
4
6
VDD33M_IO14
P4
VDD33M_IO13
N4
VDD33M_IO12
4
5
VDD33M_IO11
P5
AD2
VDD33M_IO10
3
AD1
VDD33M_IO5
P6
AD0
VDD33M_IO4
P2
2
VDD33M_IO3
P3
1
6
VCC_HOT_1.8
VDD33M_IO2
A
0
VDD33M_IO0
PCI_AD(31:0)
16B1,51D1
VDD33M_IO1
F7
VCC_3.3
5
VDD18R_CORE4
1
W1
R246
B
ACZ_BITCLK
ACZ_SDOUT
ACZ_SYNC
22
W2
W3
Y2
R247
ACB_SDOUT
ACB_SYNC
Y6
Y5
W5
17D8,50B1
17C8,50B1
10K
Y3
W4
50B1
17D8
17D8
NC
NC
NC
nCBE2
nCBE3
LAD0
nFRAME
LAD1
nIRDY
LAD2
nTRDY
LAD3
LPC
nDEVESEL
nLDRQ0
L3
nLDRQ1
nSERR
L2
PAR
SERIRQ
K2
nLFRAME
nSTOP
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LDRQ0*
AA1
AB3
AB2
AC3
AD3
AD2
54B1,55B1
54B1,55B1
54B1,55B1
54B1,55B1
54B1
NC
LPC_SERIRQ
LPC_FRAMEJ*
AC2
AA2
54A1
54B1,55B1
D3
nCLKRUN
NC
NC
PCI_REQ*(0:2)
16B1,51B1
B3
B5
0
A3
1
B2
2
R243
C5
C3
1K
C4
C6
B4
B6
AC5
AD4
AD6
AD5
AF3
AA3
nPCIGNT2
RUNGPIO0
nPCIGNT3
RUNGPIO1
nPCIGNT4
RUNGPIO2
nPCIGNT5
RUNGPIO3
NC
NC37
NC38
nPCIREQ2
NC39
50B1
53D8
NC
NC
VCC_1.8
NC
NC
R254
AA5
RTC/NVRAM ENABLE
1-2: Normal
2-3: Reset RTC/NVRAM
0
Y4
TP56
AB5
R255
3
2
2
1
1
sod_123
TP57
AB6
CR6
MBR0530
J14
header.1x3
C262
0.1uF
AF2
VCC_HOT_3.3
R258
TP58
CR7
MBR0530
0
10K
nPCIREQ1
C
SPKR
IDE_80PIN
NC
nPCIGNT6
nPCIREQ0
13A8
TP49
2
T5
NC
1
VCC_1.8
U3
R259
NC
AF5
VBAT
sod_123
NC
F13
nPCIREQ3
1K
nPCIREQ4
VDD18COREPLL
nPCIREQ5
VSSCOREPLL
nPCIREQ6
AVDD18COREPLL
D7
C263
0.1uF
B7
C264
4.7uF
C267
1.0uF
R256
A7
J15
conn.battery
+
C268
0.1uF
C269
1uF
D
0
-
AC4
D
AVSSCOREPLL
C7
2
CIC21P300NE
+
NC
D4
GND14
NC
SPKR
AC1
nPCIGNT1
GND13
C2
E4
2
nPCIGNT0
M1575_BCLK
AB4
D8
E1
MISC
GND12
1
A20GATE
nPIRQH
A1
A5
nKBCRC
GND11
16B1,51B1
0
nHTTREQ_nAGPBUSY
nPIRQG
A2
PCI_GNT*(0:2)
nPIRQF
GND10
E6
nAGPSTOP
B1
E5
nCPUSTP
nPIRQE
GND9
E2
nPIRQD
GND8
D2
nPCISTP
H4
E3
1K
nPIRQC
M4
3
R242
CLK48M_24M
GND7
C1
CLK14M
nPIRQB
R4
2
nPIRQA
GND6
D6
U4
D5
1
GND5
VCC_3.3
AA4
PCI_INT*(0:3)
16B1,51C1
C
0
GND4
TP45
1
TP46
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: M1573_PCI/LPC/RTC/MISC
Time Changed: 2:13:52 pm
5
6
Page:
7
47
8
1
2
3
5
4
6
8
7
52C1
A
52C1
52C1
USB_P1P
C22
USB_P1N
D22
52C1
A25
B25
USB_P3P
USB_P3N
52D1
52D1
EEDI
EEDO
USB_D0_N
ULI
M1575-GN
USB_D1_P
USB_D1_N
MDC
MDIO
A23
B23
COL
USB_D2_P
VCC_3.3
U24
48.000MHz
4
C405
0.1uF
2
V3.3V
OUT
GND
OE
3
1
USB_CLK
15K
C20
R338
15K
D20
R339
15K
C18
R340
15K
D18
R341
15K
A21
R342
15K
B21
TXCLK
U37
USB_D3_P
LAN
TXEN
m1575.3of4.sb.bga628
USB_D3_N
TXD0
USB_D4_P
TXD2
USB_D4_N
TXD3
USB_D5_P
RXCLK
USB_D5_N
RXER
RXDV
NC
USB_D6_P
RXD0
USB_D6_N
RXD1
RXD2
15K
A19
R344
15K
B19
52A1
52B1
52B1
USB_D7_P
RXD3
USB_D7_N
GND79
GND80
USBOV0*
USBOV1*
USBOV2*
USBOV3*
52A1
B
R343
D27
E26
B26
E27
A27
TP113
C26
TP114
D26
TP115
VCC_HOT_1.8
E25
TP116
nUSBOV1
VDD33R_IO4
nUSBOV2
VDD33R_IO5
nUSBOV3
VDD33R_IO6
USB
nUSBOV4
VDD33R_IO7
nUSBOV5
VDD33R_IO8
nUSBOV6
VDD33R_IO9
C406
C407
0.1uF
R334
VDD18R_CORE8
AVDD18RUSBPLL
VDD18R_CORE9
AVSSUSBPLL
VDD18R_CORE10
F19
4.7uF
F18
C411
B13
C13
A15
C416
+
NC
150uF
NC
R348
B15
1K
2.2uF
+
C16
A17
2.2uF
D14
C14
B14
E14
E13
0.1uF
C413
F15
C418
NC
NC
0.1uF
NC
0.1uF
C414
C419
NC
NC
0.1uF
B16
0.1uF
C415
E17
F17
D16
0.1uF
E16
E15
R349
C15
33
D15
B17
VCC_HOT_3.3
AVDD33RUSBBGR
VDD18R_CORE11
AVSSUSBBGR
VDD18R_CORE12
USB_TX_CS
SMBCLK
SMBDATA
USB_RX_TXEM
nSMBALERT
C27
R333
C25
0
R336
C408
0.1uF
D25
R346
14.3K
14.3K
B24
1%
1%
E24
C23
R335
C
D23
B22
0
E22
C21
D21
B20
E20
C19
D19
B18
E18
D17
D10
TP118
ACZ_SDIN0
ACZ_RST*
GND16
nOFFCLKS1
GND17
nOFFPWRS3
RESUME
GND18
nOFFPWRS4_S5
nPCIEX_WAKEUP
GND19
GND20
RI
GND21
nPME
GND22
nSUSPEND
GND23
nPWRBTN
GND24
nPCIRST
GND25
nRSMRST
SUSLED
GND26
CLK32KO
GND27
GND28
LID
GND29
nLOWBAT
GND30
nSLPBTN
GND31
PWG
DFTSE
GND32
F11
E9
F9
F10
F12
B
VCC_HOT_3.3
L14
L15
M14
VCC_HOT_1.8
M15
L11
NOTE: PLACE CAPS CLOSE
L12
L13
C409
0.1uF
L20
TO VDD18R_CORE PINS
C410
0.1uF
N11
M11
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
I2C2_SCL
I2C2_SDA
B12
C12
D12
ACPWR
E12
TP120
SB_OFFPWR_S3*
SB_OFFPWR_S4_S5*
C8
B9
B11
C11
B10
C30
14C8
C
TP122
TP123
TP124
PWRSWX*
SB_PCIRST*
SB_RSMRST*
SUSLED
A9
C10
A11
A28
E30
14D2
TP121
14B8
51B1,53C1,54B1,55B1
5D8
17D8,56B1
TP125
D28
C28
B8
TP126
SB_PWG
C9
14D2
B28
B29
ACPWR
B27
ACZ_SDATAIN0
AC97_ENABLE
AC97 Cont.
nACZ_RST
LAN_ENABLE
AZLA_ENABLE
ACB_SDATAIN
OHCI_ENABLE
nACB_RST
E28
E29
C29
17D8
D29
TP127
TP128
TP129
TP130
HPCN: Argo Navis
GND70
GND69
GND67
GND66
GND65
D
V16
L16
V17
A30
B30
GND60
GND64
A29
U17
GND58
GND57
GND56
GND59
U16
U15
U14
U13
GND55
T17
GND53
GND52
GND51
GND49
GND48
GND54
T16
T15
T14
T13
R17
R16
GND47
R15
GND46
R14
GND45
R13
GND44
P17
GND42
GND41
GND40
GND43
P16
P15
P14
P13
GND39
N17
N16
N15
N14
D9
GND38
10K
GND37
R353
10K
GND36
R351
10K
GND35
R350
1K
GND34
R347
10K
GND33
R345
1K
Date Changed: Thursday, February 1, 2007
Engineer:
3
13C1,19C8,23D1,24D1,27D1,#6
TP119
R352
1.03
13D1,19C8,23D1,24D1,27D1,#6
ACZ_SDATAIN1
D11
D
ACZ_SDATAIN2
N13
50B1
50B1
E11
TO VDD33R_IO PINS
TO VDD33RUSB PINS
GND15
DFTTM
E10
TP117
NOTE: PLACE CAPS CLOSE
NOTE: PLACE CAPS CLOSE
F16
0
C17
A
C417
C412
nUSBOV7
VDD18R_CORE7
F23
VCC_HOT_3.3
NC
nUSBOV0
F20
F22
VCC_HOT_3.3
NC
USB_D2_N
TXD1
R337
D13
A13
+
F14
F13
VDD33R_IO3
VDD33R_IO2
E23
F21
E21
F20
E19
L19
L18
M17
VDD33RUSB8
VDD33RUSB7
VDD33RUSB6
VDD33RUSB5
EECS
EECK
CRS
USB_P2P
USB_P2N
52C1
USB_D0_P
VDD33RUSB4
D24
VDD33RUSB3
C24
VDD33RUSB2
USB_P0P
USB_P0N
52C1
USBCLK
VDD33RUSB1
F24
VDD33RUSB0
L17
VCC_HOT_3.3
Tiffany Tran-Chandler
4
Title: M157X: USB, AC97, Power Management
Time Changed: 2:14:00 pm
5
6
7
Page:
48
8
1
2
3
4
6
5
7
VCC_1.8
8
VCC_3.3
C441
J27
GND3
12pF
7
NC
R357
AE9
AF9
J28
AH4
conn.sata.7pin.vert
GND2
SATA PORT #1
RX_N
RX_P
GND3
AE20
AE21
VDD33M_IO20
VDD33M_IO19
AE17
AE18
AE15
AE13
AF27
AF26
AF25
AF24
Y15
Y14
Y13
PIDEA2
NC37
AG4
nPIDECS1
SATA0_TX_P
SATA0
SATA0_TX_N
nPIDECS3
nPIDEIOR
SATA0_RX_N
nPIDEIOW
SATA0_RX_P
1
2
SATA1_TX_P_B
3
SATA1_TX_N_B
C427
PIDERDY
0.01uF
C435
AK7
0.01uF
AJ7
AK5
4
5
SATA1_RX_N_B
6
SATA1_RX_P_B
C428
0.01uF
C436
AJ5
0.01uF
nPIDEDAK
SATA1_TX_P
PIDEIRQ
SATA1_TX_N
SATA1_RX_N
Primary
SATA1_RX_P
PIDED0
IDE
7
NC
R358
12.1K
AF12
AF11
PIDED1
NC38
PIDED2
SATA1_REXT
PIDED3
1%
PIDED4
AH10
AG10
AH8
J29
AG8
conn.sata.7pin.vert
SATA2_TX_P
PIDED5
SATA2_TX_N
PIDED6
SATA1
SATA2_RX_N
PIDED7
PIDED8
SATA2_RX_P
B
PIDED9
GND1
TX_P
TX_N
GND2
SATA PORT #2
RX_N
RX_P
GND3
1
AK11
2
SATA2_TX_P_B
3
SATA2_TX_N_B
C429
0.01uF
C437
AJ11
0.01uF
AK9
AJ9
4
5
6
SATA2_RX_N_B
C430
0.01uF
C438
SATA2_RX_P_B
SATA3_TX_P
PIDED10
U37
SATA3_TX_N
PIDED11
m1575.4of4.sb.bga628
SATA3_RX_N
PIDED12
PIDED13
SATA3_RX_P
PIDED14
0.01uF
NC
7
NC
NC
NC
AH2
AH1
AH12
AJ12
PIDED15
SATA_GPI0
R359
J30
4.7K
AG3
AH3
conn.sata.7pin.vert
R360
4.7K
AG2
1
R701
1K
AG1
GND1
TX_P
TX_N
SATA PORT #3
GND2
RX_N
RX_P
GND3
2
SATA3_TX_P_B
3
SATA3_TX_N_B
C431
0.01uF
C439
SIDEA0
4
5
SATA3_RX_N_B
6
SATA3_RX_P_B
C432
NC
F21
0.01uF
C440
SIDEA2
SATA_GPO0
AF7
AE8
0.01uF
C443
C445
NC
AE11
AE10
7
R354
4.7uF
SATA_GPO2
SIDEDRQ
SATA_GPO3
nSIDECS1
SATA_LED
nSIDEIOR
NC39
nSIDEIOW
SIDERDY
SATA_AVDDPLL0
NC40
SATA_AVDDPLL1
SIDED0
Secondary
IDE
SATA PLL
SIDED1
SIDED2
VCC_3.3
SIDED3
SIDED4
F22
SIDED5
SIDED6
C446
SIDED7
4.7uF
SIDED8
0.1uF
SIDED9
SIDED10
0
SIDED11
SIDED12
SIDED13
SIDED14
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
3
AE19
AF19
AF20
AG20
AG21
AJ25
0
AH24
1
AJ23
2
AJ22
3
AK21
4
AH21
5
AH20
6
AJ19
7
AK19
8
AJ20
9
AJ21
10
AH22
11
AH23
12
AK23
13
AJ24
14
AK25
15
53D1
53D8
53D1
53D1
53D1
53D1
53D1
PIDE(15:0)
53C1
B
AF16
NC
AE16
NC
AG17 NC
Place close to VDD33M_IO pins.
VCC_3.3
AE14
NC
AF17
NC
AF18
NC
AF14
NC
AF13
NC
+
C447
150uF
C448
C449
C450
C451
C452
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
AG14 NC
NC
AK17
NC
AH17
NC
AH16
NC
AJ15
NC
AJ14
NC
AK13
NC
AH13
NC
AJ13
NC
C
VCC_1.8
C420
AH14
NC
AH15
NC
AK15
NC
AJ16
NC
AJ17
NC
AH18
NC
AH19
NC
1000uF
10V
Place close to SATA_18M pins.
C421
0.1uF
C422
0.1uF
C423
0.1uF
GND77
GND76
GND75
GND78
D
0.1uF
AK2
AK1
AJ1
M16
GND74
AG22
GND72
GND73
AG19
AG16
GND71
C424
AG13
SATA_GND20
SATA_GND19
SATA_GND18
SATA_GND17
SATA_GND16
SATA_GND15
SATA_GND14
SATA_GND21
V15
V14
V13
AE12
AF10
AF8
AF6
AF4
SATA_GND13
AG12
SATA_GND12
AG11
SATA_GND10
SATA_GND9
SATA_GND8
SATA_GND11
AG9
AG7
AG5
AH11
SATA_GND7
AH9
SATA_GND6
AH7
SATA_GND4
SATA_GND5
AH5
AJ10
SATA_GND2
SATA_GND3
SATA_GND1
AJ18
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
AJ8
Y16
freescale
AJ6
SATALED
D
AJ4
SATA_GND0
SIDED15
56A8
AG23
0.1uF
0
R355
AF23
53D1
AG15 NC
nSIDEDAK
AF15 NC
SIDEIRQ
C
C444
53D8
PIDEDRQ
PIDECS1*
PIDECS3*
PIDEIOR*
PIDEIOW*
PIDERDY
PIDEDAK*
PIDEIRQ
AG18
SATA_GPO1
nSIDECS3
AJ2
53D1
SATA_GPI2
SATA_GPI3
No_Stuff
VCC_3.3
0.01uF
AE22
A
53D1
SATA_GPI1
SIDEA1
NC
PIDEA0
PIDEA1
PIDEA2
AF22
AF21
SATA0_REXT
PIDEDRQ
AH6
TX_N
PIDEA0
1%
AG6
TX_P
X25M2
PIDEA1
12.1K
GND1
X25M1
VDD33M_IO18
SATA0_RX_P_B
AK3
0.01uF
VDD33M_IO17
C434
VDD33M_IO16
AJ3
0.01uF
SATA_18M8
C426
VDD33M_IO15
6
SATA0_RX_N_B
SATA_18M7
4
5
Y2
SATA_18M6
1M
C442
Y12
R356
0.01uF
SATA_18M5
C433
+
RX_P
SATA0_TX_N_B
0.01uF
SATA_18M4
RX_N
3
C425
SATA_18M3
GND2
SATA0_TX_P_B
SATA_18M2
SATA PORT #0
A
2
SATA_18M1
TX_N
12pF
1
SATA_18M0
TX_P
25.000MHz
GND1
Y11
conn.sata.7pin.vert
Gary Milliorn
4
5
Page:
Title: M157X: SATA, IDE
Time Changed: 2:14:07 pm
6
7
49
8
1
3
2
4
5
6
7
8
VCC_3.3
R437
A
A
10K
C607
.01uF
AUD_CLK
13B8
R441
0
R440
10
R438
10K
ACZ_BITCLK
47B8
U44
ACZ_SYNC
ACZ_SDOUT
ACZ_SDIN0
17C8,47B8
17D8,47B8
B
10
5
R439
10
8
48D1
SPKR
47C8
C617
1.0uF
12
13
TP141
C613
1.0uF
14
C620
C615
1.0uF
1.0uF
16
1.0uF
17
A
C618
C621
C611
MIC_L
MIC_R
LINE_L
LINE_R
53B1
53B1
53A1
53A1
C609
15
1.0uF
1.0uF
18
20
1.0uF
21
C610
1.0uF
22
C614
1.0uF
23
C619
1.0uF
24
1
9
VCC_3.3
25
38
VCC_5
VREF
VREF_OUT
AFILT2
PC_BEEP
PHONE
AUX_L
VRAD
VRDA
NC1
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_R
MIC1
FrontMIC
CENTER_OUT
LFE_OUT
GPIO0
XTLSEL
EAPD_SPDIFI
MIC2
LINE_L
LINE_R
SPDIFO
SURR_OUT_L
NC2
SURR_OUT_R
C626
+
C623
LOUT_L
LOUT_R
100uF
100uF
VDD2
AVDD1
AVDD2
AVDD_5
53A1
53B1
37
TP142
4.7uF
+
C627
27
VREF_FLT
28
C625
29
C629
30
C624
31
53B1
1.0uF
+
1.0uF
B
C630
22uF
1.0uF
C628
32
1.0uF
33
NC
34
TP143
43
TP144
44
TP145
45
A
TP146
46
47
48
39
TP147
40
NC
41
R445
TP148
0
VDD1
C
C605
0.1uF
AFILT1
AUDIO
CODEC
SDIN
4
F23
nRESET
BITCLK
SYNC
SDOUT
36
AGND1
AGND2
6
35
42
11
26
ACZ_RST*
48D1
MONO_OUT
XTAL_OUT
CD_GND
NC
LINE_OUT_L
LINE_OUT_R
19
3
XTAL_IN
GND1
GND2
2
7
C608
22pF
+
ALC650.lqfp48
A
J32
header.1x3
C
1
C606
0.1uF
2
C616
0.1uF
C612
0.1uF
3
F24
A
C622
1.0uF
A
AVDD_5 should be a copper fill
under the CODEC.
J33
header.1x4
R442
1K
1
R443
1K
2
R444
1K
3
4
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Tiffany Tran-Chandler
4
Title: M1575 AC97 Audio Codec
Time Changed: 2:14:16 pm
5
6
Page:
7
50
8
1
1
16B1,47A1
freescale
semiconductor
1
TM
Freescale Semiconductor
7700 W. Parmer Ln
Austin, Texas 78729
2
Revision:
Project:
1.03
3
Engineer:
4
PCI_AD(31:0)
HPCN: Argo Navis
Gary Milliorn
A22
B23
A23
27
26
5
A28
B29
22
21
B32
A32
A44
B45
A46
B47
A47
B48
17
16
15
14
13
12
11
10
B52
B53
A54
B55
A55
B56
A57
B58
A58
7
6
Time Changed: 2:14:24 pm
6
5
4
3
2
1
0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
VIO: 3.3V or 5V
A9 A11
B10 B14
NC
B22 B28 B34 B38 B46
B57
A12 A13 B12 B13 A18
A24 A30 A35 A37 A42
A48 A56 B3 B15 B17
GND
B1
-12V
A2
+12V
A5 A8 A61 A62 B5
B6 B61 B62
+5V
AUX_3V
A14
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
17
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
IDSEL
ACK64
REQ64
REQ
GNT
M66EN
VIO: 3.3V or 5V
A9 A11
B10 B14
NC
B22 B28 B34 B38 B46
B57
A12 A13 B12 B13 A18
A24 A30 A35 A37 A42
A48 A56 B3 B15 B17
GND
B1
-12V
A2
+12V
A5 A8 A61 A62 B5
B6 B61 B62
+5V
B43 B54
A21 A27 A33 A39 A45
A53 B25 B31 B36 B41
+3.3V
AUX_3V
PME
PAR
C_BE0
C_BE1
C_BE2
C_BE3
A14
A19
A43
A52
B44
B33
B26
B8
A7
B7
NC
NC
NC
NC
NC
NC
0
1
2
3
0
3
2
1
R279
R277
PCI_CBE*(3:0)
VCC_5
Title: PCI Bus
7
C270
C277
+
A58
B58
A57
B56
A55
B55
A54
B53
B52
A49
B48
A47
B47
A46
B45
A44
A32
B32
A31
B30
A29
B29
A28
B27
A25
B24
A23
B23
A22
B21
A20
B20
A26
B60
A60
B18
A17
B49
INTD
INTC
INTB
INTA
A6
A1
A3
NC
NC
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
6
+
NC
SMBDAT
SMBCLK
SERR
PERR
LOCK
TRST
TMS
TCK
B2
B4
A4
B11
B9
R276
R275
R274
R273
R272
R271
R270
R269
R268
R267
R266
10K
10K
5
8
A49
A31
18
AD20
AD21
AD22
AD23
AD24
AD25
B43 B54
NC
0
1
0
0
A41
A40
B42
B40
STOP
TRDY
IRDY
TDO
TDI
PRSNT2
PRSNT1
0
R264
R265
10K
10K
3
9
B30
19
A29
B27
23
20
A25
pciconn_with_3.3V_aux_32bit
24
J17
AD26
C
A21 A27 A33 A39 A45
A53 B25 B31 B36 B41
+3.3V
A19
A43
A52
B44
2
3
0
3
2
1
B39
A38
A36
DEVSEL
FRAME
5V: 145154-1
3V: 145154-1
pciconn_with_3.3V_aux_32bit
AD27
AD28
AD29
AD30
PME
PAR
C_BE0
C_BE1
C_BE2
B33
NC
NC
NC
CLK
RST
J16
B24
B21
29
28
AD31
IDSEL
ACK64
REQ64
C_BE3
B26
B8
A7
B7
A6
A1
A3
B35
B37
A34
A15
B16
2
1
R263
R262
10K
10K
4
25
A20
33
30
R278
B20
A26
B60
A60
REQ
GNT
M66EN
INTD
INTC
INTB
INTA
TRST
TMS
TCK
PCI_PERR*
PCI_SERR*
PCI_GNT*(0:2)
PCI_REQ*(0:2)
B18
A17
B49
SMBDAT
SMBCLK
SERR
PERR
LOCK
STOP
TRDY
IRDY
B2
NC
NC
0
0
1
R260
R261
3
31
NC
A41
A40
B42
B40
B39
A38
A36
B35
B4
A4
16B1,47C1
TDI
16B1,47B1
TDO
16B1,47C1
DEVSEL
16B1,47C1
FRAME
16A1
B37
16A1,47C1
NC
NC
16A1,47C1
B11
B9
16A1,47C1
PRSNT2
PRSNT1
16A1,47C1
5V: 145154-1
3V: 145154-1
16A1,47C1
A34
CLK
16A1,47C1
PCI_CLK(0:4)
SB_PCIRST*
PCI_FRAME*
PCI_DEVSEL*
PCI_IRDY*
PCI_TRDY*
PCI_STOP*
RST
B
2
A15
B16
15B1,47A8,54A1,55B1
48C7,53C1,54B1,55B1
18
1
3
A
2
1
7
8
VCC_3.3
0
DATABLIZZARD_INTD*
I2C2_SCL
I2C2_SDA
15C8
VCC_HOT_3.3
VCC_5
A
B59
B19
A59
A16
A10
VCC_3.3
VCC_5
33
C271
47uF
C278
47uF
C272
0.1uF
C273
0.1uF
C274
0.1uF
C275
0.1uF
C276
0.1uF
0.1uF
Page:
B
C279
0.1uF
16B1,47D1
C280
0.1uF
PCI_INT*(0:3)
C281
0.1uF
PCI_PAR
VCC_HOT_3.3
C282
0.1uF
C283
0.1uF
B59
B19
0.1uF
C
A59
A16
A10
13D1,19C8,23D1,24D1,27D1,#6
13C1,19C8,23D1,24D1,27D1,#6
D
D
Date Changed: Thursday, February 1, 2007
51
8
1
2
3
4
VCC_3.3
VCC_5
5
6
7
8
Place caps near IN_AB and IN_CD
with heavy power traces.
A
A
R280
10K
R281
10K
R282
10K
R283
10K
C285
0.1uF
U16
mic2077-2bm.so16
2
USBOV0*
13
ENA
IN_AB
FLGA
IN_CD
ENB
OUTA
FLGB
OUTB
5
1
15
USBOV1*
16
3
USB_POWER1
14
USB_POWER2
6
USB_POWER3
11
USB_POWER4
OUTC
7
USBOV2*
GND1
FLGD
GND2
C286
33uF
16V
+
C288
33uF
16V
+
C289
33uF
16V
12
FUSB_POWER4
9
+
C284
33uF
16V
FB5
USBOV3*
48B1
END
FUSB_POWER1
+
4
10
FUSB_POWER2
FLGC
FB4
8
FB3
48B1
OUTD
ENC
FB1
48B1
FUSB_POWER3
48B1
C287
0.1uF
B
B
J19
conn.usb.dual.stacked.ra
usb_dual_ra
1
USB_P0N
48A1
USB_P0P
48A1
CLASS=[
CLASS=[
USB0
USB0
]
]
DIFF_USB
1
DIFF_USB
L4
4
2
3
CLASS=[
CLASS=[
USBO0
USBO0
]
DIFF_USB
]
DIFF_USB
USBO1 ]
DIFF_USB
P0N
2
P0P
3
4
TV
TN
TP
TOP
TG
DLW21SN900SQ2B
5
USB_P1N
48A1
USB_P1P
48A1
CLASS=[
CLASS=[
USB1
USB1
]
]
DIFF_USB
1
DIFF_USB
L5
4
2
3
CLASS=[
CLASS=[
USBO1 ]
P1N
6
P1P
7
DIFF_USB
8
BV
BN
BP
BOTTOM
BG
SHIELD
DLW21SN900SQ2B
9
R284
R286
R288
R290
15K
15K
15K
15K
C
FB6
C
C290
J18
header.2x5
USB_P2N
48A1
USB_P2P
48A1
CLASS=[
CLASS=[
USB2
USB2
]
]
DIFF_USB
1
DIFF_USB
L6
4
2
3
CLASS=[
CLASS=[
USBO2 ]
USBO2 ]
DIFF_USB
2
P2N
3
4
P3N
P2P
5
6
P3P
7
8
9
10
DIFF_USB
DLW21SN900SQ2B
48A1
48A1
USB_P3N
CLASS=[
USB3
]
DIFF_USB
USB_P3P
CLASS=[
USB3
]
DIFF_USB
1
4
L7
10pF
1
C291
NC
2
CLASS=[
USBO3 ]
DIFF_USB
3
CLASS=[
USBO3 ]
DIFF_USB
10pF
R285
R287
R289
R291
15K
15K
15K
15K
FB2
DLW21SN900SQ2B
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Tiffany Tran-Chandler
4
Title: USB Ports
Time Changed: 2:14:34 pm
5
6
Page:
7
52
8
1
2
3
4
5
6
7
8
U20
audiojack.3port
Place caps close to connector.
Triple Audio Jack
F14
LINE_L
50C1
32
NC
33
NC
34
Top
A
50C1
LINE_R
F15
LOUT_L
F16
A
Light Blue
Line In
35
31
50B8
22
NC
23
NC
24
Middle
Lime
F17
LOUT_R
50B8
Line Out
25
21
F18
MIC_L
50C1
VREF_FLT
50B8
2
R294
NC
4
Bottom
Mic In
B
F19
MIC_R
50C1
3
Pink
4.7K
B
NC
5
R299
22K
22K
C304
C305
C306
C307
C308
C309
47pF
47pF
47pF
47pF
47pF
47pF
A
6
R297
22K
7
R296
22K
8
R295
9
1
A
A
PIDE(15:0)
49B8
J20
header.vertical.shrouded.2x20
SB_PCIRST*
48C7,51B1,54B1,55B1
7
3
6
5
5
7
4
9
49A8
49A8
49A8
49A8
49B8
49A8
49A8
49A8
56A8
4
8
6
9
8
10
10
11
3
11
12
12
2
13
14
13
1
15
16
14
0
17
18
19
20
PIDEDRQ
PIDEIOW*
PIDEIOR*
PIDERDY
PIDEDAK*
PIDEIRQ
PIDEA1
PIDEA0
PIDECS1*
PATALED
49A8
C
2
1
shrouded
C
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
15
NC
R300
470
NC
IDE_80PIN
PIDEA2
PIDECS3*
R301
D
47C8
49A8
49A8
C310
0.047uF
100K
R298
D
10K
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Tiffany Tran-Chandler
4
Title: USB and Audio AC97 Connectors
Time Changed: 2:14:41 pm
5
6
7
Page:
53
8
2
3
4
VCC_HOT_3.3
6
5
VCC_3.3
53
LED1_GP60
VCC1
65
U43
VCC2
93
VCC3
18
MCLK
44
10K
MDAT
VREF
7
POWER/GND
VSS1
31
A
KEYBOARD
KCLK
MOUSE
VSS2
60
KDAT
VSS3
GP36_nKBDRST
VSS4
GP37_A20M
R181
49
59
58
57
56
63
64
47C8
48C7,51B1,53C1,55B1
NC
J11
91
PCI_CLK
nDCD1
20
NC
90
LAD0
nRI1
NC
LAD2
RXD2_IRRX1_GP52
LPC
23
LAD3
2A
Z=115ohms
NC
96
TXD2_IRTX1_GP53
NC
98
24
nRTS2_GP55
nLFRAME
25
NC
F6
99
nLDRQ
SERIAL
nCTS2_GP56
nPCI_RESET
PORT 2
nDTR2_GP57
26
2CM_MAX
NC
100
2A
Z=115ohms
NC
97
NC
nDSR2_GP54
VCC_3.3
nRI2_GP50
nIO_PME_GP42
nIO_SMI_GP27
R200
F7
10K
2CM_MAX
nRDATA
104
11
103
SCLK
nWGATE
SDA
nWDATA
A0_nRESET_nTHERM_XNOROUT
nHDSEL
2A
Z=115ohms
F8
NC
10
105
NC
12
VCC_12_BULK
107
108
VCC_5
110
R185
470
115
VID2
470
116
470
117
R188
470
119
R189
470
120
3.3V_IN
nINDEX
2.5V_IN
DRVDEN0_GP40
1.8V_IN
GP41_DRVDEN1
R204
10K
F9
2A
C174
22pF
CGND1
C175
NC
66
POWER/GND
67
HVCC2
PD0
HVCC3
PD1
HVCC4
PD2
128
HVSS1
PD3
HVSS2
PD4
PARALLEL
HVSS3
PD5
PORT
HVSS4
PD6
HVSS5
PD7
HVSS6
SLCT
113
D0n_XNORIN
BUSY
123
124
70
NC
NC
NC
VCC_3.3
NC
72
73
74
75
77
78
79
NC
C
NC
NC
NC
NC
NC
NC
80
114
C169
2200pF
69
71
PE
TEMP_CATHODE
NC
68
10K
127
NC
nINIT
nSLCTIN
10K
Vccp_IN
R209
126
680
B
NC
NC
R210
125
C
R183
B2
10pF
10K
118
112
2
10K
10K
10K
470
101
J10
B1
NC
2
122
header.1x2
B4
1.5V_IN
121
680
B6
B3
1
HVCC1
R182
R202
R203
nTRK0
111
1
NC
14
nWRTPRT
13
102
TEMP_ANODE
B5
NC
15
R207
R190
BOTTOM
3
nMTR0
5V_IN
R186
NC
Z=115ohms
nDS0
DRIVE
12V_IN_VID4
R187
NC
CGND
C171
22pF
nDSKCHG
VID3
470
T2
5
109
R184
10K
R208
VCC_DDRA_IO
R201
10K
VCC_SERDES
4
FLOPPY
VID1
NC
10K
VCC_3.3
9
nSTEP
R205
VCC_1.8
T4
T1
2CM_MAX
2A
Z=115ohms
NC
R206
VCC_PLAT
T6
T3
NC
nDIR
VID0
T5
NC
50
106
19A8
C173
22pF
92
8
19A8
C170
22pF
NC
nDCD2_GP51
17
I2C2_SCL
I2C2_SDA
THERM*
46C8
TOP
2CM_MAX
95
16
13C1,19C8,23D1,24D1,27D1,#6
F5
LAD1
22
94
13D1,19C8,23D1,24D1,27D1,#6
conn.din6.dual.stacked.ra
21
nLPCPD
14D2,19B1,46C8
4.7K
NC
86
nDSR1
29
PME*
SMI*
B
2A
Z=115ohms
C172
0.1uF
89
SER_IRQ
27
14D2
4.7K
nDTR1
R214
PORT 1
NC
R213
NC
88
nCTS1
4.7K
nRTS1
SERIAL
2CM_MAX
47C8,55B1
47C8,55B1
30
SHORT_POWER
POLYSW
NC
87
CLOCKS
CLOCKI
3
F10
85
19
LPC_SERIRQ
PCI_CLK(0:4)
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_FRAMEJ*
LPC_LDRQ0*
SB_PCIRST*
47C8,55B1
F4
ptc_smd100
NC
TXD1
CLKI32
47C8,55B1
NC
84
6
47C8,55B1
VCC_5
AVSS
RXD1
15B1,47A8,51B1,55B1
A
NC
40
SIO_BCLK
56A1
NC
4.7K
R180
R179
R178
76
SIO_LED
48
R211
10K
10K
10K
LED2_GP61
lpc47m192.qfp128
VTR
47C8
8
???
VCC_3.3
13A8
7
R212
1
nACK
D0p
NC
81
NC
nERROR
D1p
82
nALF
D1n
NC
83
nSTROBE
NC
55
FAN_PWM
FAN_TACH
5B8
5A8
R191
FAN1_GP33
10K
61
54
IRRX2_GP34
FAN2_GP32
52
R192
FAN
FAN_TACH1_GP31
10K
IRTX2_GP35
62
SIO_TP8
SIO_TP9
TP23
TP24
51
FAN_TACH2_GP30
R193
VCC_3.3
J1B1_GP10
10K
28
GP43_DDRC
R194
10K
41
R195
10K
42
R196
10K
43
R197
10K
45
J1B2_GP11
GP20_P17
J2B1_GP12
GP21_P16_nDS1
J2B2_GP13
GAME PORT
GP22_P12_nMTR1
IXO
R198
10K
46
R199
10K
47
J1X_GP14
GP24_SYSOPT
J1Y_GP15
GP25_MIDIIN
J2X_GP16
GP26_MIDIOUT
J2Y_GP17
M1_DDR_IOPWR_S3
M1_DDR_IOPWR_S5
M2_DDR_IOPWR_S3
M2_DDR_IOPWR_S5
32
33
34
35
36
37
38
SIO_TP14
S1_PRSNT*
S2_PRSNT*
25B1
25B1
29B1
29B1
S1_PRSNT*
S2_PRSNT*
43B8
45A8
39
D
D
680 ohm resistors generate -69deg Celsius
470ohm to 1K ohm are placed for input safety
Refer to RG for therm & voltage monitor, VID[3:0]
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Tiffany Tran-Chandler
4
Title: SIO
Time Changed: 2:14:49 pm
5
6
Page:
7
54
8
2
1
3
4
5
6
8
7
A
A
Replace with socket:
21303602
Place these caps less than
1cm from VDD.
U4
VCC_3.3
VCC_3.3
sst49lf016c.plcc32
PCI_CLK(0:4)
LPC_FRAMEJ*
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
15B1,47A8,51B1,54A1
47C8,54B1
47C8,54B1
47C8,54B1
47C8,54B1
47C8,54B1
4
31
23
13
14
15
17
SB_PCIRST*
48C7,51B1,53C1,54B1
2
24
8
VDD
LAD0
ID0
LAD1
ID1
LAD2
ID2
LAD3
ID3
7
6
5
4
3
30
1
NC1
NC2
NC
18
19
nTBL
NC3
20
21
nWP_AAI
NC5
GPI0_RYnBY
NC6
22
GPI1_nLD
NC7
GPI2
NC8
GPI3
NC9
GPI4
NC10
26
27
28
29
32
NC11
3V FLASH
C298
0.1uF
Place caps close to SIO.
4.7uF
9
nINIT
C296
0.1uF
C293
0.1uF
10
2MB x 8
R292
10K
+
11
nRST
C294
33uF
C292
12
NC4
CFG_FLASHWP*
17B8,38C1
B
+
25
LCLK
nLFRAME
R293
10K
VCC_5
NC
NC
NC
NC
+
NC
B
C295
33uF
C297
0.1uF
C299
0.1uF
C300
0.1uF
C301
0.1uF
C302
0.1uF
C303
0.1uF
NC
NC
NC
NC
NC
16
VSS
C
C
D
D
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Tiffany Tran-Chandler
4
Title: LPC Boot Flash / ULI/AC97 Config
Time Changed: 2:14:57 pm
5
6
7
Page:
55
8
1
2
3
4
5
VCC_3.3
R362
SIO_LED
54A8
D3
1
330
A
R363
PASS_LED*
15B8
330
R364
FAIL_LED*
15B8
Green
Green
SIO
SATA
1
8
Green
PASS
PATA
SATALED
49D1
330
D21
Green
R379
1
R380
A
PATALED
53D1
330
CR8
MBR0530
D5
1
7
VCC_3.3
D20
D4
1
6
R381
330
Red
FAIL
RC73L2Z331JTF
sod_123
1
ASLEEP
14C2,19D8
2
R365
4
U28
74lvc1g125.sc70
330
D6
J31
header.1x2
1
17D8,48C7
R366
D7
330
Green
No_Stuff
2
Green
ASLEEP
SUSLED
CR9
MBR0530
1
Chassis disk activity LED connector.
sod_123
1
SUS
VCC_HOT_5
R367
D8
B
330
1
B
Green
HOT_5V
R368
PS_H33_PG
6B1
330
VCC_HOT_2.5
R369
4
U3
74lvc1g125.sc70
VCC_HOT_1.8
330
R370
4
U5
74lvc1g125.sc70
VCC_3.3
330
330
14C2,25B8
U29
R372
4
74lvc1g125.sc70
C
330
M2_DDR_IOPWRGD
2
U30
R373
4
74lvc1g125.sc70
330
PS_ULI_1.8V_PG
2
U31
R374
4
74lvc1g125.sc70
330
PS_SERDES_PG
2
U34
R375
4
74lvc1g125.sc70
330
10A1,14B2
2
U36
R376
4
74lvc1g125.sc70
330
9B1,14B2
2
U39
R377
4
74lvc1g125.sc70
330
PS_VCORE_PG
7B1,14B2
D
U41
D14
C
1
Green
D15
1
Green
D16
1
Green
D17
1
Green
D18
1
Green
VPLAT
1
2
1
1.2V
1
PS_PLATFORM_PG
D13
Green
VSERDES
1
PS_1.2V_PG
1
1.8V
1
11A1,14C2
D12
Green
M2_VTT
1
11C1,14C2
1
M1_VTT
1
14C2,29B8
D11
Green
3.3V
1
2
1
HOT_1.8V
VCC_3.3=VCC_HOT_3.3
R371
M1_DDR_IOPWRGD
D10
Green
HOT_2.5V
VCC_3.3=VCC_HOT_3.3
1
2
1
HOT_3.3V
1
2
D9
Green
R378
4
74lvc1g125.sc70
330
D19
1
D
Green
CORE
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: LEDs, Misc
Time Changed: 2:15:05 pm
5
6
Page:
7
56
8
1
3
2
4
5
6
7
8
VCC_5
+
A
+
C485
33uF
16V
C491
33uF
16V
+
+
C495
33uF
16V
C499
33uF
16V
VCC_3.3
+
C486
22uF
6.3V
OSCON
+
C492
22uF
6.3V
OSCON
+
+
C496
22uF
6.3V
OSCON
A
GLOBAL BULK CAPACITANCE
Place ~2cm from each corner
and one in the center.
C500
22uF
6.3V
OSCON
VCC_3.3
B
B
C453
C455
C462
C464
C466
C468
C475
C477
C479
C481
C483
C487
C489
C493
C497
C501
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
VCC_5
C454
C456
C463
C465
C467
C469
C476
C478
C480
C482
C484
C488
C490
C494
C498
C502
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
GLOBAL HF CAPACITANCE
Place in a grid ~5cm everywhere.
INTER POWER PLANE CAPACITANCE
Place ~2cm from each corner
and one in the center.
C
C
VCC_5
VCC_3.3
C457
GROUND TEST POINTS
Place in each corner and center
0.1uF
CHASSIS MOUNTING HOLES
ATX/Micro-ATX Chassis: 7 holes.
C458
G1
tp.black
G2
tp.black
G3
tp.black
G4
tp.black
G5
tp.black
MH1
MH2
MH3
MH4
MH5
MH6
MH7
0.1uF
C459
0.1uF
C460
0.1uF
C461
D
D
0.1uF
freescale
semiconductor
1
Freescale Semiconductor
TM
7700 W. Parmer Ln
Austin, Texas 78729
2
Project:
Revision:
HPCN: Argo Navis
Date Changed: Thursday, February 1, 2007
Engineer:
1.03
3
Gary Milliorn
4
Title: Global Bypass Capacitors and Mounting
Time Changed: 2:15:13 pm
5
6
7
Page:
57
8