SC4525F 18V, 3A, 350kHz Step-Down Switching Regulator POWER MANAGEMENT Features Input Voltage Range: 3V to 18V 3A Output Current 350kHz Fixed Switching Frequency Precision 1V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE Compliant Applications IN F ig.1 b: 3 50 kH z 1 0-1 6V to 5 V /3A S tep -D ow n C on verter (F ro nt P ag e E fficien S C 4525A C4 10mF BST IN SW S C 4525F S S /E N 85 1N 4148 C1 0.33mF L1 OUT 10mH 5 V /3 A 80 R4 33 .2 k FB COMP C8 47pF RSET R7 11 .5k GND R5 60 .4k D2 20 B Q 030 Efficiency 90 D1 10 V – 16 V C7 22 nF Peak current-mode PWM control employed in the SC4525F achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4525F is available in SOIC-8 EDP package. XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs Typical Application Circuit V The SC4525F is a 350kHz constant frequency peak current-mode step-down switching regulator capable of producing 3A output current from an input ranging from 3V to 18V. The SC4525F is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. R6 8.25k Efficiency (%) Description C2 47mF VIN =1 2 V 75 70 65 60 55 50 45 C5 2 .2 nF 40 0 L1: C oiltronics C D 1- 100 C 2: M urata G R M 31 C R 60J476 M C 4 : M urata G R M 31 C R 61 E 106 K 0.5 1 1.5 2 2.5 3 Load Current (A) Figure 1 — 350kHz 10V - 16V to 5V/3A Step-down Converter Revision 2.1 E fficien cy of the 1M H z 10 V -28 V to 5 V /3A S te p-D ow n C onve rte r (Fron t P ag © 2013 Semtech Corporation SC4525F Pin Configuration Ordering Information SW 1 8 BST IN 2 7 FB RSET 3 6 COMP GND 4 5 S S /E N 9 Device Package SC4525FSETRT(1)(2) SOIC-8 EDP SC4525FEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E9010) SC4525F Absolute Maximum Ratings Thermal Information VIN Supply Voltage ……………………………… -0.3 to 24V Junction to Ambient (1) ……………………………… 36°C/W BST Voltage ……………………………………………… 40V Junction to Case (1) ………………………………… BST Voltage above SW …………………………………… 24V Maximum Junction Temperature……………………… 150°C Storage Temperature ………………………… -65 to +150°C SS Voltage ……………………………………………-0.3 to 3V Lead Temperature (Soldering) 10 sec ………………… 300°C FB Voltage ……………....…………………………… -0.3 to 7V Recommended Operating Conditions SW Voltage ………………………………………… -0.6 to VIN SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V Peak IR Reflow Temperature …………………………. 5.5°C/W Input Voltage Range ……………………………… 3V to 18V 260°C ESD Protection Level(2) ………………………………… 2000V Maximum Output Current ……………………………… 3A Operating Ambient Temperature …………… -40 to +105°C Operating Junction Temperature …………… -40 to +125°C Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, RSET = 60.4kΩ. Parameter Conditions Min Typ Max Units 18 V 2.95 V Input Supply Input Voltage Range VIN Start Voltage 3 VIN Rising 2.70 VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown 2.82 225 mV VCOMP = 0 (Not Switching) 2 2.6 mA VSS/EN = 0, VIN = 12V 40 52 µA 1.000 1.020 V Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current 0.980 VIN = 3V to 18V 0.005 VFB = 1V, VCOMP = 0.8V -170 %/V -340 nA Error Amplifier Transconductance 300 µΩ-1 Error Amplifier Open-loop Gain 60 dB 15.2 A/V VFB = 0.9V 2.35 V COMP Source Current VFB = 0.8V, VCOMP = 0.8V 17 COMP Sink Current VFB = 1.2V, VCOMP = 0.8V 25 COMP Pin to Switch Current Gain COMP Maximum Voltage µA Internal Power Switch Switch Current Limit Switch Saturation Voltage (Note 1) ISW = -3.9A 3.9 5.1 6.6 A 380 600 mV SC4525F Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TA = TJ < 125°C, RSET = 60.4kΩ. Parameter Conditions Min Typ Max Units Minimum Switch On-time VIN = 10 V, RSW = 10Ω 70 120 230 ns Minimum Switch Off-time VIN = 6 V, RSW = 6Ω 30 75 130 ns 10 µA Switch Leakage Current Minimum Bootstrap Voltage ISW = -3.9A 1.8 2.3 V BST Pin Current ISW = -3.9A 100 150 mA Oscillator Switching Frequency RSET = 60.4kΩ 275 350 425 kHz Foldback Frequency RSET = 60.4kΩ, VFB = 0 35 65 100 kHz 0.2 0.3 0.4 V 0.95 1.2 1.4 V Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current VFB = 0 V VSS/EN = 0 V VSS/EN = 1.5 V 1.9 1.6 Soft-start Discharging Current 2.4 3.2 µA 1.5 µA Hiccup Arming SS/EN Voltage VSS/EN Rising 2.15 V Hiccup SS/EN Overload Threshold VSS/EN Falling 1.9 V Hiccup Retry SS/EN Voltage VSS/EN Falling 0.6 1.0 1.2 V Over Temperature Protection Thermal Shutdown Temperature 165 °C Thermal Shutdown Hysteresis 10 °C Note 1: Switch current limit does not vary with duty cycle. SC4525F Pin Descriptions SO-8 Pin Name Pin Function 1 SW Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. 2 IN Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane with a capacitor. 3 RSET Connect a 60.4kW resistor from this pin to ground. 4 GND Ground pin 5 SS/EN Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. 6 COMP The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. 7 FB The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). 8 BST Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. 9 Exposed Pad The exposed pad serves as a thermal contact to the circuit board. While the exposed pad is electrically isolated, it is suggested to be soldered to the ground plane of the PC board. SC4525F Block Diagram IN SLO PE COMP COMP 6 FB 7 + 2 S + + IS E N 3 .5 3 m W + EA + OC IL IM + 18m V - BST V1 8 + PW M - S R FREQ UENCY FO LD BAC K ROSC Q POW ER T R A N S IS T O R CLK O S C IL L A T O R 3 1 .2 V 1 R R SW O V E R LO A D - PW M A1 + S S /E N 5 1V S O F T -S T A R T AND O VERLO AD H IC C U P CONTROL 1 .9 V REFERENCE & THERM AL SHUTDO W N FAULT GND 4 Figure 2 — SC4525F Block Diagram 1 .9 V S S /E N IC 2 .4mA B4 + S B1 O VERLO AD S OC R PW M R B2 1 V /2 .1 5 V FAULT Q ID 3 .9 mA _ Q B3 Figure 3 — Soft-start and Overload Hiccup Control Circuit SC4525F Typical Characteristics 85 75 70 Efficiency (%) Efficiency (%) V O = 2.5 V VO = 1.5V 65 60 55 45 0 .5 65 60 1 1 .5 2 2 .5 Load Current (A) Feedback Voltage vs Temperature 0 .5 1 1 .5 2 2 .5 Load Current (A) 0 .9 7 -5 0 -2 5 0 25 50 75 o Temperature ( C) 100 125 Normalized Frequency 0 .9 8 1 .1 1 .0 0 .9 0 .8 -5 0 -2 5 0 25 50 75 100 0 .5 1 1 .5 2 Load Current (A) 2.5 3 Foldback Frequency vs V F B 1 .2 5 1 0 .7 5 0 .5 TA = 2 5 o C 0 .2 5 0 125 0 .0 0 Temperature (OC) 0.2 0 0 .4 0 0 .6 0 0 .8 0 1 .0 0 VF B (V) 1 0 0 .0 BST Pin Current vs Switch Current V IN = 1 2V V BST =15V BST Pin Current (mA) Normalized Frequency VFB (V) 0 .9 9 VIN = 3.3V D 2 =B 3 2 0A 0 1 .0 1 1 .0 0 60 40 3 Frequency vs Temperature 1 .2 V IN = 1 2 V VO =1V 65 45 0 1 .0 2 70 50 40 3 75 55 VIN = 5 V D 2 = B 3 2 0A 45 VO =2V 80 V O = 1 .5 V 70 50 40 0 75 55 VIN = 1 2V D 2 =B 3 2 0A 50 85 V O = 2 .5 V 80 Efficiency 90 V O = 3 .3 V 85 V O = 3.3V 80 Efficiency 90 Efficiency (%) Efficiency 90 7 5 .0 -4 0 o C 5 0 .0 125oC 2 5 .0 0 .0 0 0.5 1 1 .5 2 2 .5 3 Switch Current (A) 3 .5 4 SC4525F eshold vs temp (11) Vin Sup Cur vs SSCurve volt 12 Typical Characteristics (Cont.) S S 270 RE V 6-7 S S 2 7 0 R E V 6 -7 S S 270 RE V 6-7 VIN Supply Current vs Soft-Start Voltage VIN Thresholds vs Temperature 2.5 S ta rt 2.8 2.7 2.6 2.5 40 -40 o C -40 o C 1.5 1.0 30 125 o C 20 U VL O 0.5 (14) SS shutdown threshold (15)vs SStemp charge cur vs 10SS volt 0 0.0 2.4 -50 -25 0 25 50 75 100 0 125 0.5 Temperature (o C) 1 1.5 VIN Quiescent Current vs VIN 2.5 0 2 2 4 6 8 10 12 14 16 18 VIN (V) VSS (V) S S 270 R E V 6-7 S S 270 R E V 6-7 S S 270 RE V 6-7 SS Shutdown Threshold vs Temperature 0.40 Soft-Start Charging Current vs Soft-Start Voltage 0.0 125 o C -0.5 SS Threshold (V) -40 o C 1.5 1.0 0.5 0.35 Current (uA) 2.0 Current (mA) V SS = 0 125 o C 2.0 Current (mA) VIN Threshold (V) 2.9 VIN Shutdown Current vs VIN 50 Current (uA) 3.0 0.30 0.20 4 6 8 10 VIN (V) 12 14 16 -40 o C -1.5 -2.0 -2.5 0.0 2 125 o C 0.25 V C OMP = 0 0 -1.0 18 -50 -25 0 25 50 75 o Temperature ( C) 100 125 -3.0 0 0.5 1 1.5 2 VSS (V) SC4525F Applications Information Operation The SC4525F is a 350kHz fixed frequency, peak currentmode, step-down switching regulator with an integrated 3.9A power NPN transistor. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 3.53mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 18mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C1 and the diode D1 in Figure 1) generates such a voltage at the BST pin for driving the power transistor. the internal bias circuit of the SC4525F turns on and the SC4525F draws 2mA from VIN. The 1.9µA charging current turns off and the 2.4µA current source IC in Figure 3 slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision 1V reference and the other non-inverting input is tied to the output of the amplifier A1. Amplifier A1 produces an output V1 = 2(VSS/EN -1.2V). V1 is zero and COMP is forced low when VSS/EN is below 1.2V. During start up, the effective non-inverting input of EA stays at zero until the soft-start capacitor is charged above 1.2V. Once VSS/ exceeds 1.2V, COMP is released. The regulator starts to EN switch when VCOMP rises above 0.4V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V1 during start up. VSS/EN must be at least 1.83V for the output to achieve regulation. Proper soft-start prevents output overshoot. Current drawn from the input supply is also well controlled. Overload / Short-Circuit Protection Table 2 lists various fault conditions and their corresponding protection schemes in the SC4525F. Table 2: Fault conditions and protections Shutdown and Soft-Start The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4525F is summarized in Table 1. Table 1: SS/EN operation modes SS/EN Mode Supply Current <0.2V Shutdown 18uA @ 5Vin 0.4V to 1.2V Not switching 2mA 1.2V to 2.15V Switching & hiccup disabled >2.15V Switching & hiccup armed Load dependent Pulling the SS/EN pin below 0.2V shuts off the regulator and reduces the input supply current to 18µA (VIN = 5V). When the SS/EN pin is released, the soft-start capacitor is charged with an internal 1.9µA current source (not shown in Figure 3). As the SS/EN voltage exceeds 0.4V, Condition Cause of Fault Protective Action Cycle-by-cycle limit at IL>ILimit, V FB>0.8V Over current IL>ILimit, V FB<0.8V Over current VSS/EN Falling Persistent over current frequency foldback Shutdown, then retry SS/EN<1.9V or short circuit (Hiccup) Tj>160C Over temperature Shutdown programmed frequency Cycle-by-cycle limit with As summarized in Table 1, overload shutdown is disabled during soft-start (VSS/EN<2.15V). In Figure 3, the reset input of the overload latch B2 will remain high if the SS/EN voltage is below 2.15V. Once the soft-start capacitor is charged above 2.15V, the output of the Schmitt trigger B1 goes high, the reset input of B2 goes low and hiccup becomes armed. As the load draws more current from the regulator, the current-limit comparator ILIM (Figure 2) will eventually limit the switch current on a cycle-bycycle basis. The over-current signal OC goes high, setting SC4525F Applications Information (Cont.) the latch B3. The soft-start capacitor is discharged with (ID - IC) (Figure 3). If the inductor current falls below the current limit and the PWM comparator instead turns off the switch, then latch B3 will be reset and IC will recharge the soft-start capacitor. If over-current condition persists or OC becomes asserted more often than PWM over a period of time, then the soft-start capacitor will be discharged below 1.9V. At this juncture, comparator B4 sets the overload latch B2. The soft-start capacitor will be continuously discharged with (ID - IC). The COMP pin is immediately pulled to ground. The switching regulator is shut off until the soft-start capacitor is discharged below 1.0V. At this moment, the overload latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start. The regulator will go through softstart, overload shutdown and restart until it is no longer overloaded. In peak current-mode control, the PWM modulating ramp is the sensed current ramp of the power switch. This current ramp is absent unless the switch is turned on. The intersection of this ramp with the output of the voltage feedback error amplifier determines the switch pulse width. The propagation delay time required to immediately turn off the switch after it is turned on is the minimum controllable switch on time (TON(MIN)). Closed-loop measurement shows that the SC4525F minimum on time is about 120ns at room temperature for 1A load current (Figure 4). If the required switch on time is shorter than the minimum on time, the regulator will either skip cycles or it will jitter. If the FB voltage falls below 0.8V because of output overload, then the switching frequency will be reduced. Frequency foldback helps to limit the inductor current when the output is hard shorted to ground. During normal operation, the soft-start capacitor is charged to 2.4V. Setting the Output Voltage The regulator output voltage, VO, is set with an external resistive divider (Figure 1) with its center tap tied to the FB pin. For a given R6 value, R4 can be found by Figure 4. Variation of Minimum On Time with Ambient Temperature 1 V 1 A C = − 20 ⋅ log ⋅ ⋅ FB G CA R S 2headroom, πFC C O VO the minimum operating To allow fortransient VO switch on time should be at least 20% to 30% higher than R4 = R6 −1 1.0 V 1 1 1.0 the worst-case minimum on time. A C = − 20 ⋅ log ⋅ ⋅ = 15.9 − 31 3 −6 V 1 3 . 3 28 ⋅ 6 . 1 ⋅ 10 2 π ⋅ 80 FB ⋅ 10 ⋅ 22 ⋅ 10 A C = − 20 ⋅ log ⋅ ⋅ Minimum On VO +Time VD Consideration G R 2 π F C V Minimum Off Time Limitation C O O CA S D= VOVCESAT The operating duty cycle of a non-synchronous step The PWM latch in Figure 2 is reset every cycle by the V + V − IN D 15.9 R = R6 −1 20 down 4switching in continuous-conduction clock.10The clock also turns off the power 1.0 Vregulator 1 transistor to 1.0 = 22.3k1 R7 A= = − 20 ⋅ log ⋅ ⋅ −3 = 15 C mode (CCM) is given by − 3 3 −time 6 refresh capacitor. This minimum off 0.28 ⋅the 10 bootstrap 3.3 2π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 28 ⋅ 6.1 ⋅ 10 limits the attainable duty cycle of the regulator at a given 1 ( V +VVOD+) ⋅V(D1 − D) C 5 switching = = 0.45nF DILD== O 3 frequency. VIN +FV 2π ⋅ 16 ⋅ 15 10 ⋅ 22.1 ⋅The 10 3measured minimum off time is ⋅ LV1CESAT D − .9 SW 138ns typically. If the required duty cycle is higher than 10 20 = 22.3k then the output voltage will not where VIN is the input voltage, VCESAT is the switch saturation Rthe 7 = attainable−1 3 C 8 = 0.28 ⋅ 10 maximum, = 12pF 3 3 ( V + V ) ⋅ ( 1 − D ) O D voltage, π⋅ 600 10 ⋅ 22 be2able to ⋅reach its .1 set⋅ 10 value in continuous-conduction L 1 = and VD is voltage drop across the rectifying 1 ( V% IOV⋅DF)SW⋅ (1 − D) O ⋅+ diode. DI =20 Cmode. = 0.45nF 5 = 3 L 2π ⋅ 16 ⋅ 10 ⋅ 22.1 ⋅ 10 3 FSW ⋅ L 1 GPWM (1 + sRESR C O ) Vo 1 = = + s / ω )(1 + s3 / ω Q + s 2 3/ ω=212 pF IRMS _ CIN (=V IO+⋅ V D) ⋅⋅((11 −−DD)) Vc C 8 (1 10 p O D 2 π⋅ 600 ⋅ 10 ⋅ 22n .1 ⋅ 10 n ) L1 = 20% ⋅ IO ⋅ FSW VIN + VD − VCESAT R7 = 1 VFB 1 A C = − 20 ⋅ log ⋅ ⋅ ( VOG+CAVRDS) ⋅ (2 1π−FD ) O VO CC C5 = DIL = FSW ⋅ L 1 1 1 1.0 A C = − 20 ⋅ log ⋅ ⋅ = 15 −3 3 −6 3.3 C 8 = ( VO 28 + VD⋅ 6 ) ⋅.(11⋅−10 D) 2π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 L1 = 20% ⋅ IO ⋅ FSW capacitor to satisfy both the ESR and bulk capacitance 15.9 requirements. 10 20 Vo VFB 1 1 R = = −3 = 22.⋅3k A C7 = − ⋅ log ⋅ 0.20 28 ⋅ 10 IRMS _ CIN =GIO R⋅ D 2 ⋅ (π1F−CD) V Vc CA S C O O Output Capacitor 1 CThe = 0.45nF 5 = output ripple 3 voltage DV 3 O of a buck converter can be 2π ⋅ 16 ⋅ 10 ⋅ 22 . 1 ⋅ 10 1 1 1.0 as Aexpressed ⋅ ⋅ = 15 C = − 20 ⋅ log −3 3 −6 3.3 GPWM 281⋅ 6.1 ⋅ 10 12π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 C 8 = DVO = DIL ⋅3 ESR + = 12pF 3 2 π⋅ 600 ⋅ 10 ⋅ 22.1 ⋅810 ⋅ FSW ⋅ C O where CO is 15.9the output capacitance. 10 20 R7 = R7 = = 22.3k − 3 (1 + sR G C ) VSince 0 . 28 ⋅ 10 PWM ESR O current DI increases as D o ripple L = the inductor 2 )( I+1 s / ω Q 1+ s 2 / ω VFB V ( 1 + s / ω decreases (refer to the in the Inductor 1 c = − 20 ⋅ logp n first equation n) O A ⋅ ⋅ C 5C = C IN > G = 0.45 nF C5 = R 2 π F C V 3 3 O voltage is therefore ⋅ DVCA Selection the ⋅SF.1SW⋅output 2π ⋅ 16section), ⋅4 10 ⋅ IN 22 10 C O ripple 1V is at its V 1 maximum. the highest when A C = − 20 R ⋅ log 1 IN ⋅ ⋅ FB 1 1 ωZ = 1 1, .0 C 8 = R S 1 2ωπpFC≈C3 O= 12 V, OpF CGA8PWM == ≈− 20 ⋅ log,G CA 3 ⋅ ⋅ 22.1 ⋅ 10− 3 RC O ⋅ R⋅S10 R ESR−6C O⋅ 3.3 = 15 3 2 πG⋅to 600 CA 47µF AC 22µF X5R ⋅ 6ceramic .1 ⋅ 10 capacitor 2π ⋅ 80 ⋅is10found ⋅ 22adequate ⋅ 10 28 for output filtering in most applications. Ripple current 1 1 1 . 0 AC = 15 Ain − 20 ⋅ a concern ⋅ 20 ⋅ log C =the 3 because − 6 the 10 output 28 capacitor is− 3not 3 . 3 ⋅ 6 . 1 ⋅ 10 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 15 .9 R G (1 + sRESR C O ) Vo7 = 20 PWM inductor directly feeds CO, = g m10current of a buck converter 2 2 = 3kn Q + s / ωn ) VRresulting ω −)(31 =+ 22 s /.ω c7 (1 + s /in low ripple current. Avoid using Z5U 0.28 ⋅ 10pvery 1 15.9 Y5V 20 Cand 5 = 10ceramic 1 capacitors for output filtering because πFZ1 Rof R = 22.3k have Cthese = 2 types =high 0.45temperature nF 7 −capacitors 75 = and1high 33 R⋅ 10 02.π28 ⋅ 16 ⋅ 10 ⋅ 22.1 ω ⋅ 10≈3 1 , Gvoltage ≈ , ω = , coefficients. PWM p Z 1 RC O R ESRC O C 8 = GCA ⋅ RS 11 CC5 == 2 πF R 3 = =0.12 45pF nF 3 P1 ⋅ 710 3 8 3 2 π ⋅ 16 ⋅ 22 . 1 ⋅ 10 2 πA C⋅ 600 ⋅ 10Diode ⋅ 22.1 ⋅ 10 Freewheeling 20 10 of Schottky 1barrier diodes as freewheeling rectifiers RCUse 7 == = 12pF 8 3 m⋅ 600 reduces diode input current spikes, 2g π ⋅ 10reverse ⋅ 22.1 ⋅recovery 10 3 G ( 1 + s R C ) Veasing PWM ESR O o high-side current sensing in the SC4525F. These = 2 1s / ωp )(have V ( 1 + 1 + s /an ωn Q + s 2 / ωforward diodes should average current rating c n) C5 = 2 π F R G ( 1 + s R C ) Vat 1 and 7PWM a reverse voltage of at least a ESR blocking O o least Z3A = 2 2 volts higher than the input voltage. For switching Vfew ( 1 + s / ω ) ( 1 + s / ω Q + s / ω ) 1R p c n 1 n 1 CGregulators 8 = ≈ operating at ω low , ωZlow = output, PWM2 πF R p ≈ duty ,cycles (i.e. P1 ⋅ R 7 RC O ratios), it is beneficial R ESRC O CA input S voltageGto voltage conversion R 1 with somewhat higher 1 use freewheeling diodes Gto , ωp ≈ , ωZ = , PWM ≈ A C 20 ⋅ RS ratings (thus lower RC O forward voltages). R ESRThis CO 10GCA average current R7 = is because g m the diode conduction interval is much longer AC 20 than10 that of the transistor. Converter efficiency will be 1 RCimproved 7 = if the voltage drop across the diode is lower. 5 = g 2 πmF R SC4525F V R4 = R6 O − 1 1 .0 V Applications Information (Cont.) VO + VD InductorVSelection IN + VD − VCESAT The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is D= (V V+ V ) ⋅ (1 − D) RD4 IL= =R6 O O D− 1 1.0FVSW ⋅ L 1 where FSW is the switching frequency (350kHz) and L1 is ( V V+ V+ V) ⋅ (1 − D) the inductance. L 1== O O D D D ⋅ I ⋅ FSW VIN 20 + V% D − OVCESAT An inductor ripple current between 20% to 50% of the maximum load current, IO, gives a good compromise ⋅ )D⋅ (and ⋅ (1− −Dsize. _ CIN amongIRMS efficiency, ( VO= +IOVcost 1 )D) Re-arranging the previous D D I = L euqation and assuming FSW ⋅ L 1 35% inductor ripple current, the VOby inductor is given R4 = R6 − 1 1.0 V ( VO + VD ) ⋅ (1 − D) 1 LD1V= IL V⋅ O ESR + O =D R4 = R635 %⋅ IO−⋅1FSW 8 ⋅ FSW ⋅ C O VO.0+V VD 1 D= If the inputVINvoltage + VD − varies VCESAT over a wide range, then choose L1 based on the input voltage. Always verify VO +nominal VD ID RMS CIN = I O ⋅ D ⋅ (1 − D) =_operation converter at the input voltage extremes. V + VI − V C IN > IN D O CESAT ( V + VD⋅ F) ⋅SW(1 − D) DIL current = 4 ⋅ODVINlimit The peak of SC4525F power transistor is at FSW ⋅ L 1 least 3.9A. The maximum deliverable load current for the 1 V 1 one − D) half of the inductor ripple DVO is= (3.9A DVIOL ⋅+minus ESR D ) ⋅ (+ SC4525F DIL = 8 ⋅F ⋅C ( VO + FVSW 11− D) SW O D ) ⋅⋅(L current. L1 = 20% ⋅ IO ⋅ FSW ( VO + VD ) ⋅ Capacitor (1 − D) InputLDecoupling 1 = The input capacitor 20%IO⋅ IOshould ⋅ FSW be chosen to handle the RMS IRMS = IaO buck ⋅ D ⋅ converter. (1 − D) IN >_ CIN of rippleCcurrent This value is given by 4 ⋅ DV ⋅ F IN SW IRMS _ CIN = IO ⋅ D ⋅ (1 − D) 1 DVOcapacitance = DIL ⋅ ESRmust + The input also be high enough to keep 8 ⋅ F ⋅ C SW O input ripple voltage within specification. This is important 1 from in reducing EMI ESR + the regulator. The DVO = the DIL ⋅conductive 8 ⋅ F ⋅ C SW O input capacitance can be estimated from IO C IN > 4 ⋅ DVIN ⋅ FSW IO whereCDV input ripple voltage. >is the allowable IN IN 4 ⋅ DVIN capacitors, ⋅ FSW Multi-layer ceramic which have very low ESR (a few mW) and can easily handle high RMS ripple current, are the ideal choice for input filtering. A single 4.7µF to 10µF X5R ceramic capacitor is adequate for most applications. For high voltage applications, a small ceramic (1µF or 2.2µF) can be placed in parallel with a low ESR electrolytic Z1 7 11 20BQ030 (International Rectifier), B320A, B330A CCThe 5 = = 2 πF R 8 (Diodes Inc.), SS33 (Vishay), CMSH3-20MA and CMSH3Z 1 7 2 πFP1 R7 40MA (Central-Semi.) are all suitable. 1 C8 = 2 πFP1 R7 The freewheeling diode should be placed close to the SW pin of the SC4525F on the PCB to minimize ringing due to trace inductance. 11 SC4525F Applications Information (Cont.) Bootstrapping the Power Transistor To maximize efficiency, the turn-on voltage across the internal power NPN transistors should be minimized. If these transistors are to be driven into saturation, then their bases will have to be driven from a power supply higher in voltage than VIN. The required driver supply voltage (at least 2.3V higher than the SW voltage) is generated with a bootstrap circuit (the diode D1 and the capacitor C1 in Figure 6). The bootstrapped output (the common node between D1 and C1) is connected to the BST pin of the SC4525F. The minimum BST to SW voltage required to fully saturate the power transistor is shown in Figure 5. The minimum required VC1 increases as temperature decreases. The bootstrap circuit reaches equilibrium when the base charge drawn from C1 during transistor on time is equal to the charge replenished during the off interval. Minimum Bootstrap Voltage vs Temperature 2 .2 Voltage (V) 2 .0 1 .9 1 .8 IS W = -3 .9 A 1 .6 -5 0 -2 5 0 25 50 75 100 The SC4525F can also be bootstrapped from the input [Figure 6(b)]. This configuration is not as efficient as Figure 6(a). However this may be the only option if the output voltage is less than 2.5V and there is no other supply with voltage higher than 2.5V. Voltage stress at the BST pin can be somewhat higher than 2VIN. Figures 6(c) and (d) show how to bootstrap the SC4525F from a second independent power supply VS. The minimum bootstrap capacitance C1 can be estimated as: , ' & ! 2870$; I 96 where VS is the voltage applied to the anode of D1. The inductor current charges the bootstrap capacitor when it pulls the SW node low during the switch off time. If D1 is connected to the converter input, then C1 will be charged as soon as VIN is applied. 2 .1 1 .7 Schottky diode (such as BAT54) for D1 to maximize the bootstrap voltage. 125 Temperature (oC) Figure 5. Typical Minimum Bootstrap Voltage required to Saturate the Transistor (ISW= -3.9A) Figure 6 summarizes various ways of bootstrapping the SC4525F. A fast switching PN diode (such as 1N4148 or 1N914) and a small (0.33μF – 0.47μF) ceramic capacitor can be used. In Figure 6(a) the power switch is bootstrapped from the output. This is the most efficient configuration and it also results in the least voltage stress at the BST pin. The maximum BST pin voltage is about VIN + VOUT. The minimum VOUT required for this bootstrap configuration is 2.5V. If the output voltage is between 2.5V and 3V, then use a small If the bootstrap diode is tied to the converter output [Fig ures 6(a)], then C1 can only be charged from the regulator output through the inductor. Before the converter starts, there is no output voltage or inductor current. Hence it is necessary for the regulator to deliver some inductor current to the output before C1 can be charged. If VIN is not much higher than the programmed VOUT and it ramps up very slowly, then the inductor current will not be high enough for the bootstrap circuit to run, especially at light loads. In order to have some inductor current to charge C1, the converter output needs to be loaded or VIN needs to be increased. Using larger soft-start capacitor CSS will also help in starting bootstrap because there will be current in the inductor over a longer period of time. Figures 7(a) and 7(b) show the minimum input voltage required to start bootstrap and to run before dropping out as a function of the load current. The minimum start-up VIN decreases with higher dVIN/dt or larger soft-start capacitor CSS. The lines labeled “dropout” in these graphs show that once started, the bootstrap circuit is able to sustain itself down to zero load. 12 SC4525F D1 D1 BST V IN BST C1 VOUT V IN SW IN SC4525F SC4525F GND D1 V S > VIN + 2.5V BST V IN D1 BST C1 V OUT SW IN SC4525F GND (c) D2 (b) (a) V S > 2.5V V OUT SW IN D2 GND C1 D2 V IN V OUT SW IN SC4525F GND D2 (d) Figure 6(a)-(d). Methods of Bootstrapping the SC4525F 13 SC4525F Applications Information (Cont.) Substituting the first equation into the second equation, dV0 2I SS = dt C SS where VSS is the soft-start capacitor voltage and ISS is the soft-start charging current. V1 is the voltage defined in Figure 2. To ensure successful startup, the total current drawn from the output must be less than the maximum output capability of the part, (a) V0 dV + C 0 × 0 ≤ 3.5A R dt Substituting the third equation of this section into the previous equation, V0 C + 2I SS × 0 ≤ 3.5A R C SS Rearranging, C SS ≥ (b) Figure 7. The Minimum Input Voltage to Start and to Run Before Dropout. The Regulator is Bootstrapped from its Output [Figure 6(a)]. D1 is 1N4148. (a) VOUT = 5V (b) VOUT = 3.3V Minimum Soft-start Capacitance Css To ensure normal operation, the minimum soft-start capacitance CSS can be calculated in terms of the output capacitance CO and output load current IO according to the following equations. dVSS ISS = dt CSS dV0 dV1 d = = [2(VSS − 1.2V )] dt dt dt 2I SS(MAX) × C 0 V 3.5A − 0 R Therefore the minimum CSS depends on the output capacitance and the load current. Larger CSS is necessary when starting into a heavy load (small R). If the regulator is to be started by turning on a bench power supply, then CSS will be best determined empirically because the rise time of a power supply can range from a few milliseconds to a few hundred milliseconds. With the maximum load applied, the output rise is observed using a 22nF for CSS. Adjust CSS until a linear VOUT ramp is achieved. Loop Compensation The goal of compensation is to shape the frequency response of the converter so as to achieve high DC accuracy and fast transient response while maintaining loop stability. 14 SC4525F Applications Information (Cont.) The block diagram in Figure 8 shows the control loops of a buck converter with the SC4525F. The inner loop (current loop) consists of a current sensing resistor (Rs=3.53mW) and a current amplifier (CA) with gain (GCA=18.5). The outer loop (voltage loop) consists of an error amplifier (EA), a PWM modulator, and a LC filter. Since the current loop is internally closed, the remaining task for the loop compensation is to design the voltage compensator (C5, R7, and C8). C O N T R O LLE R A N D S C H O T T K Y D IO D E REF + Vc EA FB - Rs Io PW M M O D U LA T O R SW V ram p Vo L1 COMP Co C5 C8 R7 R4 R6 R esr Figure 8 — Block diagram of control loops For a converter with switching frequency FSW, output inductance L1, output capacitance CO and loading R, the control (VC) to output (VO) transfer function in Figure 8 is given by: VO G PWM (1 + s R ESR CO ) = VC (1 + s/ωp )(1 + s/ωn Q + s 2 /ω2n ) This transfer function has a finite DC gain G PWM R ≈ G CA × R S an ESR zero FZ at ωZ = 1 R ESR C O It has a dominant low-frequency pole FP at 1 ωp ≈ R CO Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 9, the voltage compensator has a low frequency integrator pole, a zero at FZ1, and a high frequency pole at FP1. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the integrator pole (-90deg) and the dominant pole (-90deg). The high frequency pole nulls the ESR zero and attenuates high frequency noise. *$,1G% CA and double poles at half the switching frequency. Including the voltage divider (R4 and R6), the control to feedback transfer function is found and plotted in Figure 9 as the converter gain. )] )S )S &2 19 (5 7 (5 )F /2 23 * . (1 6$ 72 5* $,1 $,1 *$ ,1 )] . &2 03 . )5(48(1&<+] )VZ . 0 Figure 9 — Bode plots for voltage loop design Therefore, the procedure of the voltage loop design for the SC4525F can be summarized as: . Plot the converter gain, i.e. control to feedback transfer function. 2. Select the open loop crossover frequency, FC, between 10% and 20% of the switching frequency. At FC, find the required compensator gain, AC. In typical applications with ceramic output capacitors, the ESR zero is neglected and the required compensator gain at FC can be estimated by 1 V 1 x x FB AC = − 20 x log GCA RS 2πFC CO VO 15 SC4525F Applications Information (Cont.) 3. Place the compensator zero, FZ1, between 10% and 20% of the crossover frequency, FC. 4. Use the compensator pole, FP1, to cancel the ESR zero, FZ. 5. Then, the parameters of the compensation network can be calculated by the following equations. AC 20 R7 = 10 gm C5 = 1 2 π FZ1 R 7 C8 = 1 2 π FP1 R 7 PC = D × VCESAT × IO 1 PSW = × t S × VIN × IO × FSW 2 I PBST = D × VBST × O 40 Table 3 — Typical switching time Example: Determine the voltage compensator for an 350kHz, 12V to 3.3V/3A converter with 47uF ceramic output capacitor. Choose a loop gain crossover frequency of 35kHz, and place voltage compensator zero and pole at FZ1=7kHz (20% of FC), and FP1= 677kHz. From the equation in step 2, the required compensator gain at FC is shown by the following equation. · § ORJ¨ ¸ ¹ S © For the power transistor inside the SC4525F, the conduction loss PC, the switching loss PSW, and bootstrap circuit loss PBST, can be estimated using the following. where VBST is the BST supply voltage and tS is the equivalent switching time of the NPN transistor (see Table 3). where gm=0.3mA/V is the EA gain of the SC4525F. $& Thermal Considerations G% Then the compensator parameters are 7 10 20 R7 = = 7.4k 0.3 × 10− 3 1 C5 = = 3.1nF 2π × 7 × 103 × 7.4 × 103 1 C8 = = 32pF 2 π× 677 ×10 3 × 7.4 ×10 3 ,QSXW9ROWDJH 9 9 $ QV QV /RDG&XUUHQW $ $ QV QV QV QV In addition, the quiescent current loss is PQ = VIN × 2mA The total power loss of the SC4525F is therefore PTOTAL = PC + PSW + PBST = PQ The temperature rise of the SC4525F is the product of the total power dissipation (previous equation) and qJA (36oC/W), which is the thermal impedance from junction to ambient for the SOIC-8 EDP package. It is not recommended to operate the SC4525F above 125oC junction temperature. Select R7=7.32k, C5=3.3nF, and C8= 33pF for the design. Compensator parameters for various typical applications are listed in Table 4. 16 SC4525F PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse currents (Figure 10). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4525F, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using large vias directly under the device. V IN VO U T Z L Figure 10 — Pulse Current Loop Note: Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized. 17 SC4525F Recommended Component Parameters in Typical Applications Table 4 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 47mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/10. Table 4: SC4525D Compensator Parameters Table 4. Recommended inductance (L1) and compensator (R7, C5, C8) Vin(V) 3.3 5 12 Typical Applications Vo(V) Io(A) 1.0 2.0 1.5 2.5 3.3 1.5 2.5 3.3 5 7.5 3 C2(uF) 47 L1(uH) 3.3 2.2 3.3 4.7 4.7 4.7 6.8 8.2 10 10 Recommended Parameters R7(k) C5(nF) C8(pF) 3.74 6.49 3.74 6.49 7.5 3.74 6.98 8.66 11.5 18.2 6.8 3.3 6.8 4.7 3.3 6.8 4.7 3.3 2.2 2.2 47 68 82 68 47 R7 7.15 12.4 7.15 12.4 14.3 7.15 13.3 16.5 22.1 34.8 18 SC4525F Typical Application Schematics V IN D1 5V C4 4 .7mF B A T 54 C1 0.33mF L1 BST IN SW 4 .7mH S C 4 5 2 5F S S /E N OUT R4 33 .2 k 2.5V /3A FB COMP C7 22nF RSET D2 R5 60 .4k R7 6 .49 k C8 47 pF GND C M S H 3 - 20 M C5 4 .7 nF L1 : C oiltronics D R 73 - 4R 7 R6 22.1k C2 47mF C 2: M urata G R M 31 C R 60J476 M C 4: M urata G R M 31 C R 60J475 K Figure 11. 350kHz 5V to 2.5V/3A Step-down Converter V IN D1 3.3V B A T- 54 C4 4 .7mF C1 0.33mF L1 BST IN SW S C 4 5 2 5F S S /E N 3 .3mH OUT R4 33 .2 k 1.5V /3A FB COMP C7 22 nF C8 47 pF RSET R7 3 .74 k GND R5 60 .4k D2 B 320 A R6 66.5k C2 47mF C5 6 .8 nF L1 : C oiltronics D R 73 - 3 R 3 C 2: M urata G R M 31 C R 60J476 M C 4 : M urata G R M 32 E R 71 H 475 K Figure 12. 350kHz 3.3V to 1.5V/3A Step-down Converter 19 SC4525F F ig.1 2b: S S Typical Performance Characteristics S S 2 7 0AR 12V E V 6 -7to 5V/3A Step-down Converter with 350kHz Switching Frequency) (For Load Characteristic 6 Output Voltage (V) 5 4 12V Input (5V/DIV) 3 2 5V Output (2V/DIV) 1 SS Voltage (1V/DIV) 0 0 0 .5 1 1 .5 2 2 .5 3 3 .5 4 Load Current (A) F ig.1 2d: O C P Load Characteristic 5ms/DIV VIN Start up Transient (IO=3A) 5V Output Short (5V/DIV) 5V Output Response (1V/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV Load Transient Response (IO= 0.3A to 3A) 10ms/DIV Output Short Circuit (Hiccup) 20 SC4525F Outline Drawing - SOIC-8 EDP A D e N 2X E /2 E1 1 E 2 ccc C 2 X N /2 T IP S e /2 B D aaa C S E A T IN G PLANE A2 A C b xN bbb A1 D IM E N S IO N S IN C H E S M ILLIM E T E R S D IM M IN N O M M A X M IN N O M M A X A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc .0 6 9 .0 0 5 .0 6 5 .0 2 0 .0 1 0 .1 9 3 .1 9 7 .1 5 4 .1 5 7 .2 3 6 B S C .0 5 0 B S C .1 1 6 .1 2 0 .1 3 0 .0 8 5 .0 9 5 .0 9 9 .0 1 0 .0 2 0 .0 1 6 .0 2 8 .0 4 1 (.0 4 1 ) 8 0° 8° .0 0 4 .0 1 0 .0 0 8 .0 5 3 .0 0 0 .0 4 9 .0 1 2 .0 0 7 .1 8 9 .1 5 0 C A -B D 1 .7 5 0 .1 3 1 .6 5 0 .5 1 0 .2 5 4 .9 0 5 .0 0 3 .9 0 4 .0 0 6 .0 0 B S C 1 .2 7 B S C 2 .9 5 3 .0 5 3 .3 0 2 .1 5 2 .4 1 2 .5 1 0 .2 5 0 .5 0 0 .4 0 0 .7 2 1 .0 4 (1 .0 5 ) 8 0° 8° 0 .1 0 0 .2 5 0 .2 0 1 .3 5 0 .0 0 1 .2 5 0 .3 1 0 .1 7 4 .8 0 3 .8 0 h F EXPOSED PAD h H H c GAGE PLANE 0 .2 5 L (L1 ) S E E D E T A IL S ID E V IE W A D E T A IL 01 A NO TES: 1. C O N T R O L L IN G D IM E N S IO N S A R E IN M IL L IM E T E R S (A N G L E S IN D E G R E E S ). 2. D A T U M S -A - A N D 3. D IM E N S IO N S "E 1 " A N D "D " D O N O T IN C L U D E M O L D F L A S H , P R O T R U S IO N S O R G ATE BURRS . R E F E R E N C E JE D E C S T D M S -0 1 2 , V A R IA T IO N B A . 4. -B - T O B E D E T E R M IN E D A T D A T U M P L A N E -H - 21 SC4525F Land Pattern - SOIC-8 EDP E SOLDER M ASK D D IM E N S IO N S D IM (C ) F G Z Y T H E R M A L V IA Ø 0 .3 6m m P X C D E F G P X Y Z IN C H E S (.2 0 5) .1 3 4 .2 0 1 .1 0 1 .1 1 8 .0 5 0 .0 2 4 .0 8 7 .2 9 1 M ILLIM E T E R S (5 .2 0 ) 3 .4 0 5 .1 0 2 .5 6 3 .0 0 1 .2 7 0 .6 0 2 .2 0 7 .4 0 NO TES: 1. T H IS L A N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E S O N L Y. C O N S U L T Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R C O M P A N Y 'S M A N U F A C T U R IN G G U ID E L IN E S A R E M E T. 2. R E F E R E N C E IP C -S M -7 8 2 A , R L P N O . 3 0 0 A . 3. T H E R M A L V IA S IN T H E L A N D P A T T E R N O F T H E E X P O S E D P A D S H A L L B E C O N N E C T E D T O A S Y S T E M G R O U N D P L A N E. F A IL U R E T O D O S O M A Y C O M P R O M IS E T H E T H E R M A L A N D/O R F U N C T IO N A L P E R F O R M A N C E O F T H E D E V IC E . 22 SC4525F © Semtech 2013 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. 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