SN65LVDM320 SLLS462 – AUGUST 2001 HIGH-SPEED DIFFERENTIAL 8-BIT REGISTERED TRANSCEIVER D Open-Circuit Differential Receiver Fail Safe FEATURES D 8-Bit Bidirectional Data Storage Register With D D D D D D Assures a Low-Level Output D Reset at Power Up D 12-kV Bus-Pin ESD Protection D Bus Pins Remain High-Impedance When Full Parallel Access Parallel Transfer Rates† – Buffer Mode: Up to 475 Megatransfers – Flip-Flop Mode: Up to 300 Megatransfers – Latch Mode: Up to 300 Megatransfers Operates With a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV Across a 50- Ω Load Bus and Logic Loopback Capability Very Low Radiation Emission Low Skew Performance – Pulse Skew Less Than 100 ps – Output Skew Less Than 320 ps – Part-to-Part Skew Less Than 1 ns Disabled or With VCC Below 1.5 V for Power-Up/Down Glitch-Free Performance and Hot Plugging 5-V Tolerant LVCMOS Inputs D APPLICATIONS D Telecom Switching D Printers and Copiers D Audio Mixing Consoles D Automated Test Equipment logic diagram OEB OMODE1 OMODE2 CLK/LEAB D Q C Q DA D Q C Q LPBK NODE BY BZ IMODE1 IMODE2 CLK/LEBA Q RA OEA LPBK ENR Q D C Q D Q C One-of-Eight Channels Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. †Parallel data transfer through all channels simultaneously as defined by TIA/EIA–644 with tr of tf less than 30%of the unit interval. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 SN65LVDM320 SLLS462 – AUGUST 2001 DESCRIPTION The SN65LVDM320 is an 8-bit data storage register with differential line drivers and receivers that are electrically compatible with ANSI EIA/TIA-644 for multipoint architectures with standard-compliant parallel transfer rates of 475 Mbps. The SN65LVDM320 includes transmitter and receiver data registers that remain active regardless of the state of their associated outputs. The logic element for data flow in each direction is configured by mode-control inputs. IMODE1 and IMODE2 control data flow in the B-to-A (bus side to digital side) direction when configured as a buffer, a D-type flip-flop, or a D-type latch. OMODE1 and OMODE2 control data flow in each of the operating modes for the A-to-B (digital side to bus side) direction. When configured in buffer mode, input data appears at the output port. In the flip-flop mode, data is stored on the rising edge of the appropriate clock input, CLKAB/LEAB or CLKBA/LEBA. In the latch mode, this clock pin also serves as an active-high transparent latch enable. Data flow is further controlled by the A-side loopback (LPBK) input. When LPBK is high, DA input data is looped back to the RA output. B-side bus data is looped back to the bus in latch mode by means of the IMODE and OMODE logic states. The A-side output enable/disable control is provided by OEA. When OEA is low or VCC is less than 2 V, the A side is in the high-impedance state. When OEA is high, the A side is active (high or low logic levels). The B-side output enable/disable control is provided by OEB. When OEB is low or VCC is less than 2 V, the B side is in the high impedance state. When OEB is high, the B side is active (high or low logic levels). The A-to-B and B-to-A logic elements are active regardless of the state of their associated outputs. New data can be entered (in latch and flip-flop modes) or previously stored data can be retained while the associated outputs are in the high-impedance or inactive states. The SN65LVDM320 also includes internally isolated analog (B-side) and digital (A-side) grounds for enhanced operation. The SN65LVDM320 is characterized for operation from – 40°C to 85°C. Table 1. Mode Functions INPUTS CLK/LEBA OEA OEB ENR OMODE1 OMODE2 IMODE1 IMODE2 LPBK X X L L X X X X X X Isolation X X X H X L L X X X A-to-B buffer mode (see Figure 1) ↑ X X H X L H X X X A-to-B flip-flop mode (see Figure 2) X X H X H L X X X A to B latch mode A-to-B (see Figure 3) X X H L L X X L L L B-to-A buffer mode (see Figure 4) X ↑ H L L X X L H L B-to-A flip-flop mode (see Figure 5) H L L X X H L L B to A latch mode B-to-A (see Figure 6) H (B follows A) L (B latched) X H (A follows B) L (A latched) X X L L H H H H H L Bus loopback latch mode (see Figure 7) X X H L H X X X X H DA to RA loopback mode (see Figures 8 through 10) H = high level, L = low level, X = don’t care, ↑ = low-to-high 2 MODE CLK/LEAB www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 pin assignments Table 2. Pin Descriptions SN65LVDM320DGG (Marked as LVDM320) (TOP VIEW) PIN NAME DESCRIPTION NO. AGND 36, 44, 54, 58, 62 1BY–8BY & 1BZ–8BZ 64 & 63, 60 & 59, 56 & 55, 52 & 51, 46 & 45, 42 & 41, 38 & 37, 34 & 33 Analog (B-side) ground CLK/LEBA 18 B-side to A-side clock input or latch enable CLK/LEAB 14 A-side to B-side clock input or latch enable 1DA–8DA 1, 3, 7, 9, 21, 25, 29, 31 Single-ended input 5, 11, 15, 19, 23, 27 Digital (A-side) ground DGND ENR 39 Receiver differential data enable IMODE1 IMODE2 50, 49 B-side to A-side buffer, flip-flop, or latch mode control and bus loopback control (see Table 3) LPBK 48 A-side loopback enable OEA 47 A-side output enable OEB 40 B-side output enable OMODE1, OMODE2 13, 17 RA VCC 1DA 1RA 2DA 2RA DGND VCC 3DA 3RA 4DA 4RA DGND VCC OMODE1 CLK/LEAB DGND VCC OMODE2 CLK/LEBA DGND VCC 5DA 5RA DGND VCC 6DA 6RA DGND VCC 7DA 7RA 8DA 8RA Differential I/O pair A-side to B-side buffer, flip-flop, or latch mode control and bus loopback control (see Table 3) 2, 4, 8, 10, 22, 26, 30, 32 Single-ended output 6, 12, 16, 20, 24, 28, 35, 43, 53, 57, 61 Supply voltage Table 3. IMODE Logic 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 40 26 39 27 38 28 37 29 36 30 35 31 34 32 33 1BY 1BZ AGND VCC 2BY 2BZ AGND VCC 3BY 3BZ AGND VCC 4BY 4BZ IMODE1 IMODE2 LPBK OEA 5BY 5BZ AGND VCC 6BY 6BZ OEB ENR 7BY 7BZ AGND VCC 8BY 8BZ Table 4. OMODE Logic IMODE1 IMODE2 MODE FUNCTION (B SIDE TO A SIDE) IMODE1 IMODE2 MODE FUNCTION (A SIDE TO B SIDE) 0 0 Buffer 0 0 Buffer 0 1 Flip-Flop 0 1 Flip-Flop 1 0 Latch 1 0 Latch 1 1 Bus loopback† 1 1 Bus loopback† † All IMODE and OMODE pins must be high for the differential bus loopback latch mode. www.ti.com 3 SN65LVDM320 SLLS462 – AUGUST 2001 mode function diagrams OEB (High) OMODE1 (Low) OMODE2 (Low) BY BZ DA Figure 1. A-to-B Buffer Mode OEB (High) OMODE1 (Low) OMODE2 (High) CLK/LEAB (↑) D Q BY C BZ DA Figure 2. A-to-B Flip-Flop Mode OEB (High) OMODE1 (High) OMODE2 (Low) CLK/LEAB (Low to High) BY BZ DA D Q C Figure 3. A-to-B Latch Mode 4 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 mode function diagrams (continued) OEB (Low) IMODE1 (Low) IMODE2 (Low) BY BZ RA OEA (High) LPBK (Low) ENR (Low) One-of-Eight Channels Figure 4. B-to-A Buffer Mode OEB (Low) IMODE1 (Low) IMODE2 (High) CLK/LEAB (↑) BY Q D BZ C RA OEA (High) LPBK (Low) ENR (Low) One-of-Eight Channels Figure 5. B-to-A Flip-Flop Mode www.ti.com 5 SN65LVDM320 SLLS462 – AUGUST 2001 mode function diagrams (continued) OEB (Low) IMODE1 (High) IMODE2 (Low) CLK/LEAB (Low to High) BY BZ RA Q D C OEA (High) LPBK (Low) ENR (Low) One-of-Eight Channels Figure 6. B-to-A Latch Mode OEB (Low to Receive, High to Transmit) OMODE1 (High) OMODE2 (High) BY BZ IMODE1 (High) IMODE2 (High) CLK/LEBA Q D C Q D C LPBK (Low) ENR (Low to Receive, High to Transmit) One-of-Eight Channels Figure 7. Bus Loopback Latch Mode 6 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 mode function diagrams (continued) OEB (Low) OMODE1 (Low) OMODE2 (Low) LPBK NODE BY BZ DA IMODE1 (Low) IMODE2 (Low) RA OEA (High) LPBK (High) ENR (High) One-of-Eight Channels Figure 8. DA to RA Buffer Mode OEB (Low) OMODE1 (Low) OMODE2 (High) CLK/LEAB (↑) D Q LPBK NODE BY C BZ DA IMODE1 (Low) IMODE2 (High) CLK/LEBA (↑) Q RA OEA (High) LPBK (High) ENR (High) D C One-of-Eight Channels Figure 9. DA to RA Flip-Flop Mode www.ti.com 7 SN65LVDM320 SLLS462 – AUGUST 2001 mode function diagrams (continued) OEB (Low) OMODE1 (High) OMODE2 (Low) CLK/LEAB (Low to High) LPBK NODE BY BZ D DA Q C IMODE1 (High) IMODE2 (Low) CLK/LEBA (Low to High) RA OEA (High) LPBK (High) ENR (High) Q D Q C One-of-Eight Channels Figure 10. DA to RA Latch Mode 8 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 equivalent input and output schematic diagrams VCC VCC 50 Ω DA, OEB, or ENR Input 5Ω RA Output 7V 7V 300 kΩ VCC VCC 300 kΩ 300 kΩ 10 kΩ 5Ω BY or BZ Output Z Input Y Input 7V 7V 7V Table 5. LVDM Receiver Function Table BUS INPUTS OUTPUT VID = VY – VZ VID ≥ 100 mV H – 100 mV < VID < 100 mV ? VID ≤ – 100 mV Open L L H = high-level, L = low-level, ? = indeterminate www.ti.com 9 SN65LVDM320 SLLS462 – AUGUST 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Voltage range (TTL pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Voltage range BY and BZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Electrostatic discharge: Y, Z, and GND (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 12 kV, B: 600 V All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A: 7 kV, B: 500 V Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (see Dissipation Rating Table) Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. 2. Tested in accordance with MIL-STD-883E Method 3015.7. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C DERATING FACTOR (see Note 3) ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DGG (see Note 4) 2094 mW 16.7 mW/°C 1340 mW 1089 mW DGG (see Note 5) 3765 mW 30.1 mW/°C 2410 mW 1958 mW NOTES: 3. This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. 4. Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51–3. 5. Tested in accordance with the High-K thermal metric definitions of EIA/JESD51–7. recommended operating conditions MIN NOM Supply voltage, VCC 3 3.3 High-level input voltage, VIH 2 0.1 ŤVIDŤ Common-mode input voltage, VIC V 0.8 V 0.6 V 2.4 – 2 Operating free-air temperature, TA UNIT 3.6 V Low-level input voltage, VIL Magnitude of differential input voltage, |VID| MAX – 40 ŤVIDŤ V 2 VCC – 0.8 85 °C supply current PARAMETER TEST CONDITIONS NOM MAX UNIT 75 130 mA 1 3 mA Driver enabled, receiver disabled, RL = 50 Ω (DA, OEB, ENR to VCC, OEA to GND) 60 100 mA Driver disabled, receiver enabled (DA, OEB, ENR to GND, OEA to VCC) 20 40 mA Driver enabled, receiver enabled, RL = 50 Ω (DA, OEA, OEB to VCC, ENR to GND) ICC 10 Supply current Driver disabled, receiver disabled (DA, OEA, OEB to GND, ENR to VCC) www.ti.com MIN SN65LVDM320 SLLS462 – AUGUST 2001 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode B-port output voltage ∆VOC(SS) Change in steady-state common-mode B-port output voltage between logic states VOC(PP) IOZ Peak-to-peak common-mode B-port output voltage IIH IIL DA port high-level input current IOS circuit output current Differential short short-circuit IO(OFF) VIT+ Power-off differential output current VIT– VOH Negative-going differential input voltage threshold VOL Low-level RA port output voltage RA-port high-impedance output current DA port low-level input current Ω RL = 50 Ω, See Figures 11 and 12 See Figure 13 MIN TYP† MAX 247 330 454 – 50‡ 50 1.125 1.375 –50 50 50 VO = 0 V or 3.6 V VIH = 2 V VIL = 0.8 V VOY or VOZ = 0 VOD = 0 VOD = 2.4 V, VCC = 1.5 V mV V mV 150 10 µA 20 µA 10 µA –10 10 mA –10 10 mA –10 10 µA –10 Positive-going differential input voltage threshold 100 See Figure 16 and Table 6 mV –100 IOH = –8 mA IOL = 8 mA 2.4 –35 Input current (Y or Z inputs) VI = 0 V VI = 2.4 V µA –10 µA IID Differential input current IIY – IIZ VIY = 0 and VIZ = 100 mV, VIY = 2.4 V and VIZ = 2.3 V II(OFF) C(INA) Power-off input current (Y or Z inputs) VCC 0 V, VI = 2.4 V VI = 0.4 sin (4E6πt) + 0.5 V II High-level RA port output voltage UNIT DA port Input capacitance V 0.4 –10 –20 5 C(INB) B-port Input capacitance VI = 0.4 sin (4E6πt) + 0.5 V 6 VO(0PX) B-port crosstalk output voltage (zero-to-peak) See Figure 20 0.1 † All typical values are at 25°C and with a 3.3-V supply voltage. ‡ The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. www.ti.com V 10 µA 20 µA pF pF mV 11 SN65LVDM320 SLLS462 – AUGUST 2001 device switching characteristics over recommended operating conditions (unless otherwise noted) FROM (INPUT) TO (OUTPUT) DA (buffer mode) See Figures 1 & 14 BY BZ BY, BY, BZ (buffer mode) See See Figures 4 & 17 RA DA (latch mode) See Figures 3 & 14 BY BZ BY, BY,BZ (latch mode) See Figure 6 RA CLKAB See Figures 2 & 22 BY BZ BY, CLKBA See Figures 5 & 23 RA DA See Figures 8 & 19 RA PARAMETER tPLH tPHL Propagation delay time, low-to-high-level output tPLH Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output tPHL Propagation delay time, high-to-low-level output tPLH tPHL Propagation delay time, low-to-high-level output tPLH Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output MIN TYP MAX 1.4 3.3 5.2 1.4 3.3 5.3 2.5 4.3 6.2 2.5 4.3 6.5 3 5.5 8.5 3 5.5 8.7 4 6.5 9.3 4 6.5 9.8 3.5 6.5 9.5 3.5 6.5 9.5 3.8 6.5 10.5 3.8 6.5 10.5 1.8 3.2 7 1.8 3.2 7 UNIT ns ns ns ns tPHL Propagation delay time, high-to-low-level output tPLH tPHL Propagation delay time, low-to-high-level output tPLH tPHL Propagation delay time, low-to-high-level output tPLH tPHL Propagation delay time, low-to-high-level output tPHZ tPLZ Propagation delay time, high-level-to-high-impedance output 15 26 Propagation delay time, low-level-to-high-impedance output 15 23 tPZH tPZL Propagation delay time, high-impedance-to-high-level output 15 26 Propagation delay time, high-impedance-to-low-level output 15 23 tPHZ tPLZ Propagation delay time, high-level-to-high-impedance output 10 15 10 17 tPZH tPZL Propagation delay time, high-impedance-to-high-level output 10 15 10 17 tr(B) tf(B) Output signal rise time B port tr(A) tf(A) Output signal rise time A port tsk(o)† tsk(p) Output skew channel-to-channel 0.3 ns Pulse skew (|tPHL – tPLH|)—A-port 0.7 ns tsk(p) Pulse skew (|tPHL – tPLH|)—B-port 0.7 ns Propagation delay time, high-to-low-level output Propagation delay time, high-to-low-level output Propagation delay time, high-to-low-level output Propagation delay time, low-level-to-high-impedance output OEA See Figure 20 OEB See Figure 15 Propagation delay time, high-impedance-to-low-level output See Figure 14 Output signal fall time B port RA BY BZ BY, 470 450 ns ns ns ns ns ns ns ps 580 See Figure 17 Output signal fall time A port 630 ps tsk(pp)‡ Part-to-part skew 0.6 ns † tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. ‡ tsk(pp) is the magnitude of the difference delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 12 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 timing requirements over recommended operating conditions (see Figure 21) (unless otherwise noted) MIN fmax tSU th TYP CLK/LEAB or CLK/LEBA in flip-flop mode Setup time Hold time MAX UNIT 300 MHz Setup for flip-flop 0.2 ns Setup for latch 1.0 ns Hold time for flip-flop 1.9 ns Hold time for latch 1.0 ns PARAMETER MEASUREMENT INFORMATION VCC BY II ENABLES OEB OMODE1 OMODE2 IOY IOZ H L L VOY + VC 2 DA VIA VOD VOY BZ VOZ VOC Figure 11. Driver Voltage and Current Definitions 3.75 kΩ BY ENABLES OEB OMODE1 OMODE2 H L L Input DA + _ 50 Ω VOD BZ 0 V ≤ Vtest ≤ 2.4 V 3.75 kΩ Figure 12. VOD Test Circuit 25 Ω ±1% (2 Places) VOBY BY Input VOBZ DA BZ ENABLES OEB OMODE1 OMODE2 CL = 2 pF VOC(PP) VOC(SS) VOC VOC H L L Figure 13. Test Circuit and Definitions for the Differential Common-Mode Output Voltage NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the device under test. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz. www.ti.com 13 SN65LVDM320 SLLS462 – AUGUST 2001 PARAMETER MEASUREMENT INFORMATION BY DA Input CL = 2 pF VOD 50 Ω ±1% BZ VCC VCC/2 Input 0V tPLH tPHL 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the device under test. Figure 14. Test Circuit, Timing, and Voltage Definitions for the DIfferential Output Signal 14 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 25 Ω ± 1% (2 Places) BY CL = 2 pF DA Input VOD + BZ OEB 1.2 V VOBY VOBZ – VOD = (VOBY – VOBZ) VCC VCC/2 Input 0V tPZH tPHZ DA = VCC Output VOD(H) 50 mV ≡0V VCC VCC/2 Input 0V tPZL tPLZ DA = 0 V ≡0V 50 mV Output VOD(L) Figure 15. A-to-B Enable/Disable Time Test Circuit and Definitions Y ENABLES ENR IMODE1 IMODE2 OEA VID L L L H VIC (VIY + VIZ)/2 RA Z VO VIY VIZ Figure 16. Voltage Definitions www.ti.com 15 SN65LVDM320 SLLS462 – AUGUST 2001 PARAMETER MEASUREMENT INFORMATION Table 6. Receiver Minimum and Maximum Fail-Safe Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE VIY 1.25 V VIZ 1.15 V VID 100 mV VIC 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0 .3V RA VID VIY VIZ CL = 10 pF VIY 1.4 V VIZ 1V VID 0.4 V VIC = 0 V VO –0.4 V tPHL VO 80% 20% tPLH VOH VCC/2 VOL tf tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the device under test. Figure 17. Timing Test Circuit and Waveforms 2V VI DA LPBK RA CL = 10 pF VIH VCC/2 VIL VI VO tPHL VO tPLH VOH VCC/2 VOL NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the device under test. Figure 18. LPBK Timing Test Circuit and Waveforms 16 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 PARAMETER MEASUREMENT INFORMATION DA VIH VCC/2 VIL RA VI VI CL = 10 pF VO tPHL tPLH VOH VCC/2 VO VOL NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the device under test. Figure 19. DA to RA Timing Test Circuit and Waveforms BY 1.2 V 500 Ω RA BZ 10 pF OEA VO + _ Vtest NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 m of the device under test. 2.5 V VTEST 1V BY VCC VCC/2 0V OEA tPLZ tPZL 2.5 V 1.4 V VOL + 0.5 V VOL RA 0V VTEST 1.4 V BY VCC VCC/2 0V OEA tPHZ tPZH RA VOH VOH –0.5 V 1.4 V 0V Figure 20. B-to-A Enable/Disable Time Test Circuit and Definitions www.ti.com 17 SN65LVDM320 SLLS462 – AUGUST 2001 PARAMETER MEASUREMENT INFORMATION VI D Input VM GND th th tsu tsu 1/fmax VI CLK/LEAB or CLK/LEBA Input VM GND tW Figure 21. Setup and Hold Time Definition OEB (High) OMODE1 (Low) OMODE2 (High) D DA Q BY CL = 2 pF C CLK/LEAB (↑) BZ VCC VCC/2 DA Input 0V tsu = 0.5 ns CLK/LEAB tPLH tPHL VOD Output ~0 V VOD = VOBY – VOBZ Figure 22. A-to-B Flip-Flop Mode Timing Circuit 18 www.ti.com VOD 50 Ω ±1% SN65LVDM320 SLLS462 – AUGUST 2001 PARAMETER MEASUREMENT INFORMATION IMODE1 (Low) IMODE2 (High) CLK/LEBA (↑) Q D C RA Output 10 pF BY V Input ID BZ OEA (High) LPBK (Low) ENR (Low) VID = VBY – VBZ VBY VBZ 0.4 V 0V VID Input –0.4 V tsu = 0.5 ns CLK/LEBA tPLH tPHL ~VCC VOH RA Output ~VCC/2 ~0 V Figure 23. B-to-A Flip-Flop Mode Timing Circuit www.ti.com 19 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION abstract This section discusses electrical and operational topics not previously covered in this document, such as error detection and the device’s ability to synchronize clock signals or manage data transfer between systems with different clock speeds. Basic applications of the analog and digital system diagnostic loopback functions and timing considerations are also analyzed. The SN65LVDM320 is resistant, although not immune, to the effect of setup and hold-time violations; therefore, the penalties of a violation are also examined. introduction The SN65LVDM320 is a versatile, multifunctional device with many applications. Low EMI, low crosstalk, and high differential-current output makes the SN65LVDM320 ideally suited for sensitive multipoint applications and low-impedance loads. Balanced differential signaling reduces noise coupling and allows high signaling rates. Balanced means that the current flowing in each signal line is equal but opposite in direction, resulting in a field canceling effect. This is one of the keys to the low-noise performance of an LVDS differential bus. Balanced differential input signals eliminate induced noise with efficient common mode rejection (CMR). Internal chip design techniques reduce noise generated by inductive and capacitive mutual coupling, thereby increasing signal integrity. One of the techniques employed to reduce internal noise is the design of separate, dedicated grounds for the single-ended and differential circuitry incorporated within the device. applications The SN65LVDM320 may be used to connect major system blocks, including parallel processors, DRAMs, fast-cache SRAMs, and complex ASIC gate arrays. It effectively transceives the addresses, data, and control signals of these integrated-circuit elements to and from system blocks and backplanes. The SN65LVDM320 not only facilitates extremely-high parallel burst-transfer rates, but in buffer mode, can move a constant stream of data at 475 Mbps through all of the eight channels simultaneously for a total data throughput exceeding 5 Gbps (transfer rate). Deskewing clock signals is a requirement in many complex high-speed circuits, and the SN65LVDM320 performs this function at synchronous parallel transfers of 300 megatransfers per second (Mxferps) with very-low channel-to-channel output skew. The SN65LVDM320 is also ideally suited for connecting system blocks operating at different clock speeds. When OEA and OEB are low, the system on the A-side of the device may be operated independently of the system on the B-side. 20 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION diagnostics and error detection OEB (High) OMODE1 (High) OMODE2 (Low) CLK/LEAB (Low to High) D Q LPBK NODE BY C BZ DA IMODE1 (High) IMODE2 (Low) CLK/LEBA (Low to High) Q RA OEA (High) LPBK (High) ENR (High) D C One-of-Eight Channels Figure 24. Loopback Error Detection It is not a requirement that the driver be disabled (OEB low) during loopback. The driver may be enabled (OEB high) while loopback is engaged at any time without damaging the circuit. The loopback configuration in Figure 24 with the differential driver enabled provides error assessment in which transmitted data is looped back and compared to the original data by the microprocessor/microcontroller host. This may be implemented in buffer, flip-flop, or in the latch mode shown in Figure 24, and in accordance with the logic of Tables 2 and 3. The SN65LVDM320 has been designed to improve a circuit’s fault detection capabilities. 100% of the circuitry of the SN65LVDM320 may be functionally checked by activating the A-side and B-side loopback modes. With this functionality, a problem rack, card, circuit block, and even a chip can be located without the burden of boundary-scan protocols. Traditionally, testability functions such as read-back, pattern insertion, and functional hardware test control require additional part count, connector pins, board space, power, and cost. However, the SN65LVDM320 provides full circuit observability and controllability within the package of an 8-bit LVDM transceiver. www.ti.com 21 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION metastability in latches and flip-flops Interfacing the asynchronous world to synchronous logic systems can cause problems. Latches and flip-flops, or basically, registers which are normally considered to have only two stable states (low and high) actually have a third state, the metastable state. Metastability can occur when the setup or the hold time is violated and the latch remains balanced in its threshold region. While in this metastable state, system noise can trigger either a high or low state. DA D1 D3 Q D4 D2 CLK/LEAB Figure 25. The A-Side to B-Side Signal Path OEB (High) OMODE1 (High) OMODE2 (Low) BY DA BZ D CLK/LEAB Q C Figure 26. SN65LVDM320 D-Type latch The SN65LVDM320 D-type latch circuitry of Figure 26 is shown in Figure 25. When data at pin DA is applied to D1, data is internally applied to D2. Therefore, when the CLK/LEAB pin is low, the outputs of D1 and D2 are high and the D3/D4 R-S latch is latched and stable. When CLK/LEAB transitions to high, the latch is transparent to the data input to DA and Q equals DA. If data changes during the setup to hold time period, it is possible for the D1 and D2 outputs to be in the threshold region of D3 and D4. Under these conditions, D3 and D4 could be perfectly balanced in a metastable condition, allowing system noise to force the latch into a high or low state. This metastable condition can theoretically last as long as 25 ns and cause a system to crash if care is not taken with the asynchronous/synchronous interface. Although the SN65LVDM320 is metastable resistant by design, it is not entirely immune, and the setup and hold times must adhere to those listed in the timing requirements section. 22 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION typical SN65LVDM320 output waveform—the eye pattern Figure 27 displays a receiver’s detection window in a typical LVDS output signal. When a receiver’s differential-input voltage level drops, the system noise margin is reduced. Lowering the height enters the input voltage threshold of a receiver, eventually closing the eye and corrupting the data. Jitter content decreases the available time for accurate reception, and depending upon the application, may exceed 50% of the bit width without any problems. To read more about the terms and sources of jitter, see the Jitter Analysis application report, literature number SLLA075. Noise Margin Receiver Detection Window Noise Margin Allowable Jitter Figure 27. Receiver Detection Window in a Typical LVDS Driver Output www.ti.com 23 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION typical SN65LVDM320 output waveform—the eye pattern (continued) Figure 28. A Receiver Output With All Eight Channels at 630 Megatransfers per Second The highest signaling rate measurable is 630 Mbps due to the limitations of the test circuit and equipment used to capture this oscillograph. It was captured while all eight channels were transmitting data in B-to-A buffer mode from the differential bus to the receiver. The measurement is taken from a receiver output test point across a 1.75-in, 50-Ω characteristic impedance trace of a TI bench evaluation board. test equipment HP 6236B dc power supply provides the required supply voltage of 3.3 V for the LVDM320. A Tektronix HFS9009 signal generator is employed as a nonreturn-to-zero (NRZ), pseudo-random binary sequence (PRBS) signal source for the LVDM320 and is adjusted as follows: D D D D Pattern: NRZ, PRBS Differential input high level: 1.6 V Differential input low level: 0.8 V Transition time: 800 ps At high signaling rates, the influence of the equipment used to measure a signal of concern must be minimized. A Tektronix 794D oscilloscope and Tektronix P6247 differential probes are used in this test. Each probe has a bandwidth of 1 GHz and the probe capacitance is less than 1 pF. 24 www.ti.com SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION DRIVER BUFFER MODE HIGH-TO-LOW-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE 4.0 tPHL – High-to-Low-Level Propagation Time – ns tPLH – Low-to-High-Level Propagation Time – ns DRIVER BUFFER MODE LOW-TO-HIGH-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE VCC = 3.3 V 3.5 VCC = 3.0 V VCC = 3.6 V 3.0 2.5 –40 25 4.0 VCC = 3.3 V VCC = 3.0 V 3.5 VCC = 3.6 V 3.0 2.5 –40 85 Figure 29 Figure 30 6.5 VCC = 3.3 V VCC = 3.0 V 5.5 5.0 VCC = 3.6 V 4.5 25 DRIVER LATCH MODE HIGH-TO-LOW-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE tPHL – High-to-Low-Level Propagation Time – ns tPLH – Low-to-High-Level Propagation Time – ns DRIVER LATCH MODE LOW-TO-HIGH-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE 4.0 –40 85 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C 6.0 25 85 TA – Free-Air Temperature – °C 7.0 6.5 6.0 VCC = 3.0 V 5.5 5.0 VCC = 3.6 V 4.5 4.0 –40 VCC = 3.3 V 25 85 TA – Free-Air Temperature – °C Figure 32 Figure 31 www.ti.com 25 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION 7.5 7.0 VCC = 3.3 V VCC = 3.0 V 6.5 6.0 5.5 VCC = 3.6 V 5.0 4.5 –40 25 DRIVER FLIP-FLOP MODE HIGH-TO-LOW-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE tPHL – High-to-Low-Level Propagation Time – ns tPLH – Low-to-High-Level Propagation Time – ns DRIVER FLIP-FLOP MODE LOW-TO-HIGH-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE 7.5 7.0 VCC = 3.3 V VCC = 3.0 V 6.5 6.0 5.5 VCC = 3.6 V 5.0 4.5 –40 85 TA – Free-Air Temperature – °C 5.0 VCC = 3.3 V VCC = 3.0 V VCC = 3.6 V 4.0 25 RECEIVER BUFFER MODE HIGH-TO-LOW-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE tPHL – High-to-Low-Level Propagation Time – ns tPLH – Low-to-High-Level Propagation Time – ns RECEIVER BUFFER MODE LOW-TO-HIGH-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE 3.5 –40 85 TA – Free-Air Temperature – °C 5.5 VCC = 3.3 V 5.0 VCC = 3.0 V 4.5 VCC = 3.6 V 4.0 3.5 –40 25 TA – Free-Air Temperature – °C Figure 35 26 85 Figure 34 Figure 33 4.5 25 TA – Free-Air Temperature – °C Figure 36 www.ti.com 85 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION RECEIVER LATCH MODE HIGH-TO-LOW-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE 7.5 tPHL – High-to-Low-Level Propagation Time – ns tPLH – Low-to-High-Level Propagation Time – ns RECEIVER LATCH MODE LOW-TO-HIGH-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE VCC = 3.3 V 7.0 VCC = 3.0 V 6.5 6.0 VCC = 3.6 V 5.5 5.0 –40 25 7.5 7.0 VCC = 3.0 V 6.5 VCC = 3.6 V 6.0 VCC = 3.3 V 5.5 –40 85 TA – Free-Air Temperature – °C Figure 37 RECEIVER FLIP-FLOP MODE HIGH-TO-LOW-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE tPHL – High-to-Low-Level Propagation Time – ns tPLH – Low-to-High-Level Propagation Time – ns 8.0 7.0 VCC = 3.3 V VCC = 3.0 V 6.5 VCC = 3.6 V 6.0 5.5 –40 85 Figure 38 RECEIVER FLIP-FLOP MODE LOW-TO-HIGH-LEVEL PROPAGATION TIME vs FREE-AIR TEMPERATURE 7.5 25 TA – Free-Air Temperature – °C 25 85 8.0 7.5 VCC = 3.3 V 7.0 VCC = 3.0 V 6.5 VCC = 3.6 V 6.0 5.5 –40 25 85 TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C Figure 39 Figure 40 www.ti.com 27 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C 3.0 V OH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 3.5 2.5 2.0 1.5 1.0 0.5 3 2.5 2 1.5 1 .5 0 0.0 0 2 4 6 8 10 0 12 IOL – Low-Level Output Current – mA –2 –4 –6 –8 IOH – High-Level Output Current – mA Figure 41 Figure 42 RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C 3.0 VOH – High-Level Output Voltage – V VOL – Low-Level Output Voltage – V 3.5 2.5 2.0 1.5 1.0 0.5 2 1 0 0.0 0 10 20 30 40 50 60 70 80 IOL – Low-Level Output Current – mA Figure 43 28 3 0 –20 –40 –60 IOH – High-Level Output Current – mA Figure 44 www.ti.com –80 SN65LVDM320 SLLS462 – AUGUST 2001 APPLICATION INFORMATION AVERAGE SUPPLY CURRENT vs FREQUENCY AVERAGE SUPPLY CURRENT vs FREQUENCY 160 150 VCC = 3.3 V ICC – Average Supply Current – mA 148 TA = 85°C TA = 25°C 146 144 TA = –40°C 142 140 200 250 300 350 TA = 85°C 155 TA = –40°C 150 145 200 400 TA = 25°C 250 300 350 400 f – Frequency – MHz f – Frequency – MHz Figure 45 Figure 46 AVERAGE SUPPLY CURRENT vs FREQUENCY 170 VCC = 3.6 V ICC – Average Supply Current – mA ICC – Average Supply Current – mA VCC = 3.0 V TA = 85°C 165 TA = 25°C 160 TA = –40°C 155 200 250 300 350 400 f – Frequency – MHz Figure 47 www.ti.com 29 SN65LVDM320 SLLS462 – AUGUST 2001 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°–ā8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. 30 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 www.ti.com PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LVDM320DGG ACTIVE TSSOP DGG 64 SN65LVDM320DGGR ACTIVE TSSOP DGG SN65LVDM320DGGRG4 ACTIVE TSSOP DGG 25 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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