SC4524D 18V 2A Step-Down Switching Regulator POWER MANAGEMENT Features Description Wide input range: 3V to 18V 2A Output Current 200kHz to 2MHz Programmable Frequency Precision 1V Feedback Voltage Peak Current-Mode Control Cycle-by-Cycle Current Limiting Hiccup Overload Protection with Frequency Foldback Soft-Start and Enable Thermal Shutdown Thermally Enhanced 8-pin SOIC Package Fully RoHS and WEEE compliant Applications XDSL and Cable Modems Set Top Boxes Point of Load Applications CPE Equipment DSP Power Supplies LCD and Plasma TVs The SC4524D is a constant frequency peak current-mode step-down switching regulator capable of producing 2A output current from an input ranging from 3V to 18V. The switching frequency of the SC4524D is programmable up to 2MHz, allowing the use of small inductors and ceramic capacitors for miniaturization, and high input/ output conversion ratio. The SC4524D is suitable for next generation XDSL modems, high-definition TVs and various point of load applications. Peak current-mode PWM control employed in the SC4524D achieves fast transient response with simple loop compensation. Cycle-by-cycle current limiting and hiccup overload protection reduces power dissipation during output overload. Soft-start function reduces input startup current and prevents the output from overshooting during power-up. The SC4524D is available in SOIC-8 EDP package. S S 2 7 0 RE V 4 Typical Application Circuit Efficiency 10V – 16V C4 2.2PF SW 6.8PH SC4524D SS/EN 85 1N4148 C1 0.33PF L1 BST IN 90 R4 102k 5V/2A FB COMP C7 10nF C8 10pF ROSC R7 30.1k GND R5 15.8k D2 20BQ030 80 OUT R6 25.5k Efficiency (%) V IN D1 C2 22PF C5 1nF V IN = 12V 75 70 65 60 55 50 45 40 L1: Wurth 744 778 9006 C2: Murata GRM31CR60J226K C4: Murata GRM31CR61E225K 0 0.5 © 2013 Semtech Corporation 1.5 Load Current (A) Figure 1 — 1MHz 10V-16V to 5V/2A Step-down Converter Rev. 2.1 1 2 SC4524D Pin Configuration Ordering Information SW 1 8 BST IN 2 7 FB ROSC 3 6 COMP GND 4 5 S S /E N 9 Device Package SC4524DSETRT(1)(2) SOIC-8 EDP SC4524DEVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 2,500 devices. (2) Available in lead-free package only. Device is fully WEEE and RoHS compliant and halogen-free. (8 - Pin SOIC - EDP) Marking Information yyww=Date code (Example: 0752) xxxxx=Semtech Lot No. (Example: E9010) SC4524D Absolute Maximum Ratings Thermal Information VIN Supply Voltage ……………………………… -0.3 to 24V Junction to Ambient (1) ……………………………… 36°C/W BST Voltage ……………………………………………… 40V Junction to Case (1) ………………………………… BST Voltage above SW …………………………………… 36V Maximum Junction Temperature……………………… 150°C 5.5°C/W Storage Temperature ………………………… -65 to +150°C SS Voltage ……………………………………………-0.3 to 3V FB Voltage …………………………………………… -0.3 to 7V Lead Temperature (Soldering) 10 sec ………………… 300°C Recommended Operating Conditions SW Voltage ………………………………………… -0.6 to VIN SW Transient Spikes (10ns Duration)……… -2.5V to VIN +1.5V Input Voltage Range ……………………………… 3V to 18V Peak IR Reflow Temperature …………………………. Maximum Output Current ……………………………… 2A 260°C ESD Protection Level ………………………………… 2000V (2) Operating Ambient Temperature …………… -40 to +105°C Operating Junction Temperature …………… -40 to +125°C Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES(1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ. Parameter Conditions Min Typ Max Units 18 V 2.95 V Input Supply Input Voltage Range VIN Start Voltage 3 VIN Rising 2.70 VIN Start Hysteresis VIN Quiescent Current VIN Quiescent Current in Shutdown 2.82 225 mV VCOMP = 0 (Not Switching) 2 2.6 mA VSS/EN = 0, VIN = 12V 40 52 µA 1.000 1.020 V Error Amplifier Feedback Voltage Feedback Voltage Line Regulation FB Pin Input Bias Current 0.980 VIN = 3V to 18V 0.005 VFB = 1V, VCOMP = 0.8V -170 %/V -340 nA Error Amplifier Transconductance 300 µΩ-1 Error Amplifier Open-loop Gain 60 dB COMP Pin to Switch Current Gain 10 A/V VFB = 0.9V 2.4 V COMP Source Current VFB = 0.8V, VCOMP = 0.8V 17 COMP Sink Current VFB = 1.2V, VCOMP = 0.8V 25 COMP Maximum Voltage µA Internal Power Switch Switch Current Limit Switch Saturation Voltage (Note 1) ISW = -2.6A 2.6 3.3 4.3 A 250 400 mV SC4524D Electrical Characteristics (Cont.) Unless otherwise noted, VIN = 12V, VBST = 15V, VSS = 2.2V, -40°C < TJ < 125°C, ROSC = 12.1kΩ. Parameter Conditions Min Typ Max Units Minimum Switch On-time 135 ns Minimum Switch Off-time 100 ns Switch Leakage Current 10 µA Minimum Bootstrap Voltage ISW = -2.6A 1.8 2.3 V BST Pin Current ISW = -2.6A 60 95 mA Oscillator Switching Frequency Foldback Frequency ROSC = 12.1kΩ 1.04 1.3 1.56 MHz ROSC = 73.2kΩ 230 300 370 kHz ROSC = 12.1kΩ, VFB = 0 100 ROSC = 73.2kΩ, VFB = 0 35 60 90 0.2 0.3 0.4 V 0.95 1.2 1.4 V 250 kHz Soft Start and Overload Protection SS/EN Shutdown Threshold SS/EN Switching Threshold Soft-start Charging Current VFB = 0 V VSS/EN = 0 V VSS/EN = 1.5 V 1.9 1.6 Soft-start Discharging Current 2.4 3.2 µA 1.5 µA Hiccup Arming SS/EN Voltage VSS/EN Rising 2.15 V Hiccup SS/EN Overload Threshold VSS/EN Falling 1.9 V Hiccup Retry SS/EN Voltage VSS/EN Falling 0.6 1.0 1.2 V Over Temperature Protection Thermal Shutdown Temperature 165 °C Thermal Shutdown Hysteresis 10 °C Note 1: Switch current limit does not vary with duty cycle. SC4524D Pin Descriptions SO-8 Pin Name Pin Function 1 SW Emitter of the internal NPN power transistor. Connect this pin to the inductor, the freewheeling diode and the bootstrap capacitor. 2 IN Power supply to the regulator. It is also the collector of the internal NPN power transistor. It must be closely bypassed to the ground plane. 3 ROSC An external resistor from this pin to ground sets the oscillator frequency. 4 GND Ground pin 5 SS/EN Soft-start and regulator enable pin. A capacitor from this pin to ground provides soft-start and overload hiccup functions. Hiccup can be disabled by overcoming the internal soft-start discharging current with an external pullup resistor connected between the SS/EN and the IN pins. Pulling the SS/EN pin below 0.2V completely shuts off the regulator to low current state. 6 COMP The output of the internal error amplifier. The voltage at this pin controls the peak switch current. A RC compensation network at this pin stabilizes the regulator. 7 FB The inverting input of the error amplifier. If VFB falls below 0.8V, then the switching frequency will be reduced to improve short-circuit robustness (see Applications Information for details). 8 BST Supply pin to the power transistor driver. Tie to an external diode-capacitor bootstrap circuit to generate drive voltage higher than VIN in order to fully enhance the internal NPN power transistor. 9 Exposed Pad The exposed pad serves as a thermal contact to the circuit board. It is to be soldered to the ground plane of the PC board. SC4524D Block Diagram IN SLO PE COMP COMP 6 + 2 + S + IS E N 6 .1m W FB + EA + 7 + IL IM - OC 2 0m V BST V1 8 + PW M - S R FREQ UENCY F O LD B A C K ROSC Q POW ER T R A N S IS T O R CLK O S C IL L A T O R 3 1 R R SW O VERLO AD - PW M A1 1.2 3 V + S S /E N 5 1V 1 .9V REFERENCE & THERM AL SHUTDO W N FAULT S O F T- S T A R T AND O VERLO AD H IC C U P CONTROL GND 4 Figure 2. SC4524D Block Diagram 1.9 V S S /E N IC 2mA B4 + Q B1 O VERLO AD R 1V /2 .1 5V FAULT S ID 3.5mA B2 _ Q S OC R PW M B3 Figure 3. Soft-start and Overload Hiccup Control Circuit SC4524D Typical Characteristics V O = 5V 85 70 V O = 1.5V 65 60 55 45 40 75 1 .0 1 V O = 1.5V 70 65 V O = 1.0 V 60 55 1 M H z,VIN = 1 2V D 2 = 2 0B Q 0 3 0 50 V IN = 1 2 V V O = 2 .5V 80 V O = 2.5V 75 Efficiency (%) Efficiency (%) 80 1 .0 2 V O = 3.3 V 85 V O = 3.3V Feedback Voltage vs Temperature Efficiency 90 VFB (V) Efficiency 90 1M H z, V IN =5 V D 2 = 20 B Q 030 50 45 0 .5 1 1.5 0 2 0.5 Load Current (A) Frequency Setting Resistor vs Frequency 1000 1 1 .5 Load Current (A) 0 .9 7 2 -5 0 Frequency vs Temperature Normalized Frequency Normalized Frequency ROSC (k) 1 .1 R O S C = 7 3.2 k 1 .0 R O S C = 1 2.1 k 0 .9 0 25 50 75 100 125 Foldback Frequency vs VFB 1 .2 5 V IN = 1 2V 10 -2 5 Temperature (oC) 1 .2 100 0 .9 9 0 .9 8 40 0 1 .0 0 1 R O S C = 7 3.2 k 0 .7 5 0 .5 TA = 2 5o C 0 .2 5 R O S C = 1 2 .1 k 1 0 0 .8 0 0 .2 5 0.5 0 .7 5 1 1 .2 5 1 .5 1 .7 5 2 -5 0 -2 5 0 Frequency (MHz) 50 75 100 0 .0 0 125 0 .2 0 0 .4 0 O 0 .6 0 0 .8 0 1 .0 0 VF B (V) Temperature ( C) Switch Saturation Voltage vs Switch Current 300 25 Switch Current Limit vs Temperature 4 .5 1 0 0.0 BST Pin Current vs Switch Current V IN = 1 2 V 25o C 200 -4 0 oC 150 4 .0 BST Pin Current (mA) V CESAT (mV) 250 Current Limit (A) 1 2 5o C 3 .5 3 .0 100 2 .5 50 0 .0 0.5 1 .0 1.5 2 .0 Switch Current (A) 2 .5 V BST =15V 7 5 .0 5 0 .0 -4 0 o C 1 2 5o C 2 5 .0 0 .0 -5 0 -2 5 0 25 50 75 Temperature ( OC) 100 125 0 0 .5 1 1 .5 2 2 .5 3 Switch Current (A) SC4524D Curve 12 Curve 11 Typical Characteristics (Cont.) S S 270 RE V 6-7 S S 2 7 0 R E V 6 -7 S S 270 RE V 6-7 VIN Supply Current vs Soft-Start Voltage VIN Thresholds vs Temperature 2.5 S ta rt 2.8 2.7 2.6 40 -40 o C -40 o C 1.5 1.0 Curve 14 0.5 2.4 0.0 U VL O 2.5 -50 -25 0 25 50 75 100 0 125 0.5 0 1 1.5 0 2 2 4 6 10 12 14 16 18 S S 270 RE V 6-7 Soft-Start Charging Current vs Soft-Start Voltage SS Shutdown Threshold vs Temperature VIN Quiescent Current vs VIN 0.40 125 o C 8 VIN (V) S S 270 R E V 6-7 2.5 125 o C 20 VSS (V) Temperature ( C) S S 270 RE V 6-7 30 10 Curve 15 o 0.0 -0.5 o SS Threshold (V) -40 C 1.5 1.0 0.5 0.35 Current (uA) 2.0 Current (mA) V SS = 0 125 o C 2.0 Current (mA) VIN Threshold (V) 2.9 VIN Shutdown Current vs VIN 50 Current (uA) 3.0 0.30 6 8 10 VIN (V) 12 14 16 -2.0 -3.0 0.20 4 -40 o C -1.5 -2.5 0.0 2 125 o C 0.25 V C OMP = 0 0 -1.0 18 -50 -25 0 25 50 75 o Temperature ( C) 100 125 0 0.5 1 1.5 2 VSS (V) SC4524D Applications Information Operation The SC4524D is a constant-frequency, peak currentmode, step-down switching regulator with an integrated 18V, 2.6A power NPN transistor. Programmable switching frequency makes the regulator design more flexible. With the peak current-mode control, the double reactive poles of the output LC filter are reduced to a single real pole by the inner current loop. This simplifies loop compensation and achieves fast transient response with a simple Type-2 compensation network. As shown in Figure 2, the switch collector current is sensed with an integrated 5.5mW sense resistor. The sensed current is summed with a slope-compensating ramp before it is compared with the transconductance error amplifier (EA) output. The PWM comparator trip point determines the switch turn-on pulse width. The current-limit comparator ILIM turns off the power switch when the sensed signal exceeds the 18mV current-limit threshold. Driving the base of the power transistor above the input power supply rail minimizes the power transistor saturation voltage and maximizes efficiency. An external bootstrap circuit (formed by the capacitor C1 and the diode D1 in Figure 1) generates such a voltage at the BST pin for driving the power transistor. When the SS/EN pin is released, the soft-start capacitor is charged with an internal 1.9µA current source (not shown in Figure 3). As the SS/EN voltage exceeds 0.4V, the internal bias circuit of the SC4524D turns on and the SC4524D draws 2mA from VIN. The 1.9µA charging current turns off and the 2.4µA current source IC in Figure 3 slowly charges the soft-start capacitor. The error amplifier EA in Figure 2 has two non-inverting inputs. The non-inverting input with the lower voltage predominates. One of the non-inverting inputs is biased to a precision 1V reference and the other non-inverting input is tied to the output of the amplifier A1. Amplifier A1 produces an output V1 = 2(VSS/EN -1.2V). V1 is zero and COMP is forced low when VSS/EN is below 1.2V. During start up, the effective non-inverting input of EA stays at zero until the soft-start capacitor is charged above 1.2V. Once VSS/EN exceeds 1.2V, COMP is released. The regulator starts to switch when VCOMP rises above 0.4V. If the soft-start interval is made sufficiently long, then the FB voltage (hence the output voltage) will track V1 during start up. VSS/EN must be at least 1.83V for the output to achieve regulation. Proper soft-start prevents output overshoot. Current drawn from the input supply is also well controlled. Overload / Short-Circuit Protection Table 2 lists various fault conditions and their corresponding protection schemes in the SC4524D. Shutdown and Soft-Start Table 2: Fault conditions and protections The SS/EN pin is a multiple-function pin. An external capacitor (4.7nF to 22nF) connected from the SS pin to ground sets the soft-start and overload shutoff times of the regulator (Figure 3). The effect of VSS/EN on the SC4524D is summarized in Table 1. Table 1: SS/EN operation modes SS/EN Mode Supply Current <0.2V Shutdown 18uA @ 5Vin 0.4V to 1.2V Not switching 2mA 1.2V to 2.15V Switching & hiccup disabled >2.15V Switching & hiccup armed Load dependent Pulling the SS/EN pin below 0.2V shuts off the regulator and reduces the input supply current to 18µA (VIN = 5V). Condition Fault Protective Action Cycle-by-cycle limit at IL>ILimit, V FB>0.8V Over current IL>ILimit, V FB<0.8V Over current VSS/EN Falling Persistent over current frequency foldback Shutdown, then retry SS/EN<1.9V or short circuit (Hiccup) Tj>160C Over temperature Shutdown programmed frequency Cycle-by-cycle limit with As summarized in Table 1, overload shutdown is disabled during soft-start (VSS/EN<2.15V). In Figure 3, the reset input of the overload latch B2 will remain high if the SS/EN voltage is below 2.15V. Once the soft-start capacitor is charged above 2.15V, the output of the Schmitt trigger B1 goes high, the reset input of B2 goes low and hiccup SC4524D Applications Information (Cont.) If the FB voltage falls below 0.8V because of output overload, then the switching frequency will be reduced. Frequency foldback helps to limit the inductor current when the output is hard shorted to ground. Fig.4 During normal operation, the soft-start capacitor is charged to 2.4V. Setting the Output Voltage The regulator output voltage is set with an external resistive divider (Figure 1) with its center tap tied to the FB pin. For a given R6 value, R4 can be found by V R4 = R6 O − 1 1 .0 V VO + VD Frequency SettingDthe = Switching VIN + VD − VCESAT The switching frequency of the SC4524D is set with an external resistor from the ROSC pin to ground. Table 3 lists standard( Vresistor + VD )values ⋅ (1 − Dfor ) typical frequency setting. DIL = O FSW ⋅ L 1 L1 = ( VO + VD ) ⋅ (1 − D) 20% ⋅ IO ⋅ FSW Table 3: Resistor for Typical Switching Frequency ROSC (k) Freq. (k) ROSC (k) Freq. (k) ROSC (k) Freq. (k) 200 110 700 25.5 1400 9.76 250 84.5 800 21.5 1500 8.87 300 69.8 900 18.2 1600 8.06 350 57.6 1000 15.8 1700 7.15 400 49.9 1100 14.0 1800 6.34 500 38.3 1200 12.4 1900 5.62 600 30.9 1300 11.0 2000 5.23 Minimum On Time Consideration AC = V The operating duty cycle of a non-synchronous stepR = R6 O − 1 down 4switching regulator in continuous-conduction 1 . 0 V mode (CCM) is given by AC = VO + VD D= VIN + VD − VCESAT where VCESAT is the switch saturation voltage and VD is voltage drop across the rectifying diode. ( V + VD ) ⋅ (1 − D) DIL = O FSW ⋅ L 1 control, the PWM modulating In peak current-mode ramp is the sensed current ramp of the power switch. This current( Vramp + VD is ) ⋅ (absent 1 − D) unless the switch is turned L1 = O on. The intersection this ramp with the output of the 20% ⋅ IO of ⋅ FSW voltage feedback error amplifier determines the switch pulse width. The propagation delay time required to immediately the IRMS _ CINturn = IO off ⋅ D ⋅ (1switch − D) after it is turned on is the Sminimum S 270 RE V 6-7controllable switch on time (T ). ON(MIN) Minumum On Time vs Temperature 180 R7 = C5 = C8 = Vo = Vc GPWM 1 DVO = DIL ⋅ ESR + 8 ⋅ FSW ⋅ C O 200 V O = 1.5V , IO = 1A , 1M Hz 1 V 1 R7 = A C = − 20 ⋅ log ⋅ ⋅ FB VO 160 G CA R S 2πFC C O IO C IN >140 = 1 1.0 C =5 15 4 ⋅ DVIN ⋅ F1 SW A C = − 20 ⋅ log ⋅ ⋅ 28 ⋅ 6.1 ⋅ 10 − 3 2π ⋅ 80 ⋅ 10 3 ⋅ 22 ⋅ 10 −6 3.3 120 C8 = TON_MIN (ns) becomes armed. As the load draws more current from the regulator, the current-limit comparator ILIM (Figure 2) will eventually limit the switch current on a cycle-bycycle basis. The over-current signal OC goes high, setting the latch B3. The soft-start capacitor is discharged with (ID - IC) (Figure 3). If the inductor current falls below the current limit and the PWM comparator instead turns off the switch, then latch B3 will be reset and IC will recharge the soft-start capacitor. If over-current condition persists or OC becomes asserted more often than PWM over a period of time, then the soft-start capacitor will be discharged below 1.9V. At this juncture, comparator B4 sets the overload latch B2. The soft-start capacitor will be continuously discharged with (ID - IC). The COMP pin is immediately pulled to ground. The switching regulator is shut off until the soft-start capacitor is discharged below 1.0V. At this moment, the overload latch is reset. The soft-start capacitor is recharged and the converter again undergoes soft-start. The regulator will go through softstart, overload shutdown and restart until it is no longer overloaded. 15.9 20 10 100 -50 =-25 R7 = 22.30k 25 50 75 100 125 0.28 ⋅ 10 −3 Temperature (OC) 1 C5 = = 0.45nF 3 3 Minimum On Time 2π Figure ⋅ 16 ⋅ 104. Variation ⋅ 22.1 ⋅ 10of with Ambient Temperature 1 C8 = = 12pF 2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3 10 VO + VD VIN + VD − VCESAT ( V + VD ) ⋅ (1 − D) DIL = O FSW ⋅ L 1 ( V + VD ) ⋅ (1 − D) DIL = O ( VO + FVSW 11− D) D ) ⋅⋅(L L1 = 20% ⋅ IO ⋅ FSW ( V + VD )Capacitor ⋅ (1 − D) Input Decoupling L1 = O The input capacitor 20% ⋅ IOshould ⋅ FSW be chosen to handle the RMS I = I ⋅ D ⋅ converter. (1 − D) RMS _ CIN O ripple current of a buck This value is given by D= Applications Information (Cont.) Closed-loop measurement shows that the SC4524D minimum on time is about 120ns at room temperature (Figure 4). If the required switch on time is shorter than the minimum on time, the regulator will either skip cycles or it will jitter. To allow for transient headroom, the minimum operating switch on time should be at least 20% to 30% higher than the worst-case minimum on time. Minimum Off Time Limitation The PWM latch in Figure 2 is reset every cycle by the clock. The clock also turns off the power transistor to refresh the bootstrap capacitor. This minimum off time limits the attainable duty cycle of the regulator at a given switching frequency. The measured minimum off time is 100ns typically. If the required duty cycle is higher than VO the attainable R4 = R6 maximum, − 1 then the output voltage will not V set value in continuous-conduction 1.0its be able to reach mode. VO + VD D= Inductor Selection VIN + VD − VCESAT The inductor ripple current for a non-synchronous stepdown converter in continuous-conduction mode is (V V + V ) ⋅ (1 − D) RD4IL==R6 O O D − 1 FSW V ⋅ L 1 1.0 where FSW is the switching frequency and L1 is the ( V V+ V+ )V⋅ (1 − D) inductance. LD1== O O D D FSW VIN 20 + V%D ⋅−IOV⋅CESAT An inductor ripple current between 20% to 50% of the maximum load current gives a good compromise among IRMS _ CIN ) efficiency, cost the previous ( VO= I+Oand V⋅ D )D⋅ (⋅size. 1(1−−DD)Re-arranging D I = equationL and assuming 35% inductor ripple current, the FSW ⋅ L 1 inductor is given by ( V + V D ) ⋅ (1 − D) 1 LD1VO= = DOIL ⋅ ESR + 35% ⋅ IO ⋅ FSW8 ⋅ FSW ⋅ C O If the input voltage varies over a wide range, then choose L1 based on the nominal input voltage. Always verify IRMS _ CIN = IO ⋅ D ⋅ (1 − D) converter operation at the input voltage extremes. IO C IN > 4 ⋅ DV ⋅ F The peak current INlimitSWof SC4524D power transistor is at least 2.6A. The maximum deliverable load current for the 1 D V = D I ⋅ ESR + O L SC4524D is 2.6A minus 8 one half ⋅ FSW ⋅ C Oof the inductor ripple current. I SC4524D IRMS _ CIN = IO ⋅ D ⋅ (1 − D) R7 = R C75 == CC5 == 8 C8 = Vo = Vc Vo = Vc GPWM 1 DVOcapacitance = DIL ⋅ ESRmust + The input also be high enough to keep 8 ⋅ FSW ⋅ C O input ripple voltage within specification. This is important G PWM 1 from in reducing EMI ESR + the regulator. The R AC = = DVO = the DIL ⋅conductive 7 ⋅ FSW ⋅ C O from input capacitance can be8estimated V R4 = R6 OI − 1 RC7 == C IN > 1.0OV A 5C = 4 ⋅ DVIN ⋅ FSW V Iallowable +O V whereCDV is the input ripple voltage. CC5 == DIN=IN> 4 ⋅ DOV ⋅ DF 8 IN SW VIN + VD − VCESAT 1 V 1 FB ceramic capacitors, have very low ESR R = AMulti-layer ⋅ ⋅which C = − 20 ⋅ log G R 2 π F C V CA S C O O can easily handle high RMS ripple current, C 87 = (a few mW) and are the ideal ( VOchoice + VD ) ⋅for (1 −input D) filtering. A single 4.7µF D I = 1 1 1.0 C 5 = X5R ceramic capacitor is adequate for 500kHz or higher L A C = − 20 ⋅ log FSW ⋅ L 1 − 3 ⋅ ⋅ = 15 3 −6 switching frequency and⋅ 10 10µF⋅ 22 is adequate 3.3 ⋅ 10 2π ⋅ 80 ⋅ 10 28 ⋅ 6.1applications, for 200kHz to 500kHz switching frequency. For high C = 8 ( V + VD ) ⋅ a(1small − D) ceramic (1µF or 2.2µF) can be voltageL 1applications, =15.9 O 20 20% ⋅ IO ⋅ FSW placed 10 in parallel a low ESRVelectrolytic capacitor to =1with R7 = 22.3k 1 − 3 ESR Asatisfy −.28 20 ⋅⋅ 10 log ⋅ bulk capacitance ⋅ FB both the and requirements. C =0 Vo G CA R S 2πFC C O VO = 1 I = I ⋅ D ⋅ ( 1 − D ) COutput = = 0 . 45 nF Vc RMS _ CIN 3 O 5 Capacitor 3 2π ⋅ 16 ⋅ 10 .11 ⋅ 10 1 1.0 ⋅ 22 output ripple voltage DVO⋅ of a buck converter can ⋅be AThe = 15 C = − 20 ⋅ log −3 3 −6 3.3 28 ⋅ 6 . 1 ⋅ 10 2 π ⋅ 80 ⋅ 10 ⋅ 22 ⋅ 10 1 expressed as C8 = = 12pF 2 π⋅ 600 ⋅ 10 3 ⋅ 22.1 ⋅ 10 3 1 GPWM DVO15=.9 DIL ⋅ ESR + 8 ⋅ FSW ⋅ C O 10 20 R7 = = 22 . 3 k − 3 (1 + sR Gthe Vwhere PWMoutput ESR C O ) o CO ⋅is10 capacitance. = 0.28 R7 = Vc (1 + s / ωp )(11 + s / ωn Q + s 2 / ωn2 ) C5 = = 0.45nF Since2πthe ⋅ 16 inductor ⋅ 10 3 ⋅IO22.ripple 1 ⋅ 10 3 current DIL increases as D C IN >(see first inductor selection equation), the C 5 = decreases V ⋅F R 4 ⋅ D1 1 1 is ω therefore VIN is, G ≈ ripple voltage , 3IN SW ,the ωZ when = Coutput pF highest PWM p ≈ 3 = 12 8 = G ⋅ R R C R CO 2 π ⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 CA S O ESR at its maximum. C8 = AC A 10µF 10 20to 47µF X5R ceramic capacitor is found adequate RV7o = GPWM (1 + sRESR C O ) for= output Ripple current g m filtering in most applications. 2 2 Vin (1 +output s / ωp )(1 + s / ω Q + s / ω ) c the n n capacitor is not a concern because the 1 current of a buck converter directly feeds CO, Cinductor = 5 2 π F R Z 1 7 resulting Rin very low ripple current. Avoid using1Z5U 1 Gand ≈ 1ceramic , capacitors ωp ≈ for output , ωZ = because, filtering PWM Y5V GCA ⋅ RS RC O R ESRC O Cthese 8 = types capacitors have high temperature and high 2 πFP1 Rof 7 voltageA Ccoefficients. 10 20 R7 = 11 gm SC4524D Applications Information (Cont.) Use of Schottky barrier diodes as freewheeling rectifiers reduces diode reverse recovery input current spikes, easing high-side current sensing in the SC4524D. These diodes should have an average forward current rating at least 2A and a reverse blocking voltage of at least a few volts higher than the input voltage. For switching regulators operating at low duty cycles (i.e. low output voltage to input voltage conversion ratios), it is beneficial to use freewheeling diodes with somewhat higher average current ratings (thus lower forward voltages). This is because the diode conduction interval is much longer than that of the transistor. Converter efficiency will be improved if the voltage drop across the diode is lower. The freewheeling diode should be placed close to the SW pin of the SC4524D to minimize ringing due to trace inductance. 20BQ030 (International Rectifier), B230A (Diodes Inc.), SS13, SS23 (Vishay), CMSH1-40M, CMSH140ML and CMSH2-40M (Central-Semi.) are all suitable. The freewheeling diode should be placed close to the SW pin of the SC4524D on the PCB to minimize ringing due to trace inductance. A small ceramic capacitor (0.33uF - 0.47uF) is adequate for bootstrapping. Minimum Bootstrap Voltage vs Temperature 2.2 2.1 Voltage (V) Freewheeling Diode 2.0 1.9 1.8 IS W = -2 .6 A 1.7 1.6 -50 25 50 75 100 125 Figure 5 — Typical Minimum Bootstrap Voltage required to Saturate Transistor (ISW= -2.6A). D1 BST V IN C1 3V < VO < 8V SW IN SC4524D D2 GND The typical minimum BST-SW voltage required to fully saturate the power transistor is shown in Figure 5, which is about 1.96V at room temperature. The bootstrap diode D1 can be a fast switching PN diode (1N4148 or 1N914) if VO falls between 3V and 8V as shown in Figure 6(a). If the converter output voltage is between 2.5V and 3V or higher than 8V, then use a low forward drop Schottky diode (BAT54 or similar) for D1 (Figure 6(c)). If VO is less than 2.5V, then it will be necessary to bootstrap the SC4524D from VIN (Figure 6(b)). D1 is a PN junction diode as in Figure 6(a). 0 Temperature (o C) Bootstrapping the Power Transistor The BST-SW voltage is supplied by a bootstrap circuit powered from either the input or the output of the converter (Figure 6(a), 6(b) and 6(c)). To maximize efficiency, tie the bootstrap diode to the converter output if VO > 2.5V as shown in Figure 6(a) and 6(c). Since the bootstrap supply current is proportional to the converter load current, using a lower voltage to power the bootstrap circuit reduces driving loss and improves efficiency. -25 (a) D1 BST V IN C1 V O < 2 .5 V SW IN SC4524D D GND 2 (b) D1 BST C1 V IN 2.5 V < V O < 3V or V O > 8V SW IN SC4524D GND D2 (C) Figure 6 — Methods of Bootstrapping the SC4524D 12 SC4524D Applications Information (Cont.) Fig.7 Minimum Soft-start Capacitance CSS Loop Compensation To ensure normal operation, the minimum soft-start capacitance CSS can be calculated in terms of the output capacitance CO and output load current IO according to the following equations. The goal of compensation is to shape the frequency response of the converter so as to achieve high DC accuracy and fast transient response while maintaining loop stability. G9 66 GW ,66 &66 G9 2 GW G9 GW C O N T RO LLE R A N D S C H O TT K Y D IO D E CA G > 966 9 @ GW REF Substituting the first equation into the second equation, G9 R GW ,66 &66 PW M M O D U LATO R SW V ram p L1 Vo V 92 Ru4 G9 = R26 d VOO − −1 1 &2R $ 4 = R6 1..0 0V V 5 GW 1 V + +V VD D D= = thirdVOOequation D Substituting the VIN + +V VD − −V VCESAT of this section into the V D CESAT previous equation,IN & 92 1− −D D)) ,66DIu = ((2VVOOd++VVDD))$⋅⋅ ((1 L DIL & = 66 F ⋅ L 5 SW ⋅ L 1 1 FSW ( V + V ) ⋅ (1 − D) = ( VOO + VDD ) ⋅ (1 − D) LL11 = 20 % ⋅⋅ IIO ⋅⋅ FFSW ,660$; u20 &% SW 2 O §9 · $ ¨ 2 ¸ ¨ 5= I ¸ ⋅ D ⋅ (1 − D) RMS __ CIN CIN IIRMS © = IOO¹ ⋅ D ⋅ (1 − D) C8 R7 R4 Co C5 To ensure successful startup, the total current drawn from the output must be less than the maximum output capability of the part, &66 t Vc - COMP where VSS is the soft-start capacitor voltage and ISS is the soft-start charging current. V1 is the voltage defined in Figure 2. Rearranging, Io + EA FB Rs R esr R6 Figure 7 — Block diagram of control loops VFB 1 1 1 V 1 FB AC = =diagram − 20 20 ⋅⋅ log log The block inFigure 7⋅⋅shows the⋅⋅ control loops of a A − C G R 2 π F C V CA R S S 2πFC CC O O O G V CA O buck converter with the SC4524D. The innerloop (current loop) consists of a current sensing resistor (Rs=5.5mW) and 1 gain (G =18.5). The 1 outer 1 with1 a current AC = =amplifier − 20 20 ⋅⋅ log log(CA) ⋅ CA A − ⋅ − 3 −6 C 28 ⋅⋅ 6 6..1 1of⋅⋅ 10 10 2π π amplifier 80 ⋅⋅ 10 10 33 (EA), 22 ⋅⋅ 10 2 ⋅⋅ 80 ⋅⋅ 22 28 loop (voltage loop) consists an− 3error a10 −6 PWM modulator, and a LC filter. 1..0 0 1 ⋅⋅ 3. 3.3 15.9 20.9 10 1520 10 Since the current loop is= internally closed, the remaining R = 22.3k R7 = −3 3 = 22.3k − 0loop 28 ⋅⋅ 10 10 task for 7the0 compensation is to design the voltage ..28 1 C8). compensator (C5, R7, and 1 C5 = = =0 0..45 45nF nF C = 3 5 3 2π π ⋅⋅ 16 16 ⋅⋅ 10 10 ⋅⋅ 22 22..1 1 ⋅⋅ 10 10 33 2 For a converter with switching frequency FSW, output 1 1 inductance C3O = loading R, the C8 = = L1, output capacitance =and 12pF pF C 12 3 8 3 3 2 π ⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 2 π ⋅ 600 ⋅ 10 ⋅ 22 . 1 ⋅ 10 control (VC) to output (VO) transfer function in Figure 7 is given by: GPWM ((1 1+ + ssR RESR C C O )) Vo G V PWM ESR O o = = Vc ((1 1+ + ss // ω ωp ))((1 1+ + ss // ω ωn Q Q + s22 / ωn22 )) V c p n + s / ωn This transfer function has a finite DC gain Therefore the minimum CSS depends on the output current. Larger 1 C is necessary capacitance and 1 SS DV VOthe =D Dload IL ⋅⋅ ESR ESR + + D = I O L 8 ⋅⋅ FFSW R). ⋅C C O when starting into a heavy load (small 8 ⋅ SW O R GPWM ≈ ≈ R ,, G PWM GCA ⋅⋅ R RS G CA S 1 ωp ≈ ≈ 1 ,, ω p RC CO R O 1 ωZ = = 1 ,, ω Z R ESRC CO R ESR O A AC C 20 10 20 10 R = R77 = g gm IIOO C IN > > C IN 4 ⋅⋅ D DV VIN ⋅⋅ FFSW 4 IN SW m 1 1 C5 = = C 5 2π πFFZ1 R R7 2 Z1 7 13 15.9 0 20 = 22.3k −3 ⋅ 10 = 12 pF 3 1 = 0.45nF 3 16 ⋅ 10 ⋅ 22.1 ⋅ 10 3 SC4524D 1 = 12pF Applications Information (Cont.) ⋅ 22.1 ⋅ 10 3 2 2 3 /ω 600 ⋅ 10 n) an ESR zero FZ at (2) Select the open loop crossover frequency, FC, between 10% and 20% of the switching frequency. At FC, find the required compensator gain, AC. In typical applications with ceramic output capacitors, the ESR zero is neglected and the required compensator gain at FC can be estimated by 1GPWM (1 + sRESR C O ) 1 , ωZ = , R/CωOp )(1 + s / ωn Q + sR2ESR / ωCn2O) a dominant low-frequency pole FP at R , A ⋅ RS 1 , RC O ωZ = 1 R ESRC O , 1 V 1 AC = − 20 ⋅ log ⋅ ⋅ FB GCA RS 2πFC CO VO and double poles at half the switching frequency. R7 1 1 R7 Including the voltage divider (R4 and R6), the control to feedback transfer function is found and plotted in Figure 8 as the converter gain. Since the converter gain has only one dominant pole at low frequency, a simple Type-2 compensation network is sufficient for voltage loop compensation. As shown in Figure 8, the voltage compensator has a low frequency integrator pole, a zero at FZ1, and a high frequency pole at FP1. The integrator is used to boost the gain at low frequency. The zero is introduced to compensate the excessive phase lag at the loop gain crossover due to the integrator pole (-90deg) and the dominant pole (-90deg). The high frequency pole nulls the ESR zero and attenuates high frequency noise. 30 Fz1 Fp1 Fp 0 CO NV -30 -60 1K (3) Place the compensator zero, FZ1, between 10% and 20% of the crossover frequency, FC. (4) Use the compensator pole, FP1, to cancel the ESR zero, FZ. (5) Then, the parameters of the compensation network can be calculated by AC 10 20 R7 = gm C5 = 1 2 πFZ1 R7 C8 = 1 2 πFP1 R7 where gm=0.3mA/V is the EA gain of the SC4524D. 60 GAIN (dB) 1 ωp ≈ 10K ER T ER Fc LO CO MP OP G EN SA TO RG Example: Determine the voltage compensator for an 800kHz, 12V to 3.3V/2A converter with 22uF ceramic output capacitor. AIN Choose a loop gain crossover frequency of 80kHz, and place voltage compensator zero and pole at FZ1=16kHz (20% of FC), and FP1=600kHz. From the equation in step (2), the required compensator gain at FC is AIN GA IN Fz Fsw/2 100K FREQUENCY (Hz) 1M 10M 1 1 1.0 AC = − 20 ⋅ log ⋅ ⋅ = 11.4 dB 18.5⋅ 5.5 ⋅ 10− 3 2π ⋅ 80 ⋅ 103 ⋅ 22 ⋅ 10−6 3.3 Figure 8 — Bode plots for voltage loop design Therefore, the procedure of the voltage loop design for the SC4524D can be summarized as: (1) Plot the converter gain, i.e. control to feedback transfer function. 14 SC4524D Applications Information (Cont.) Then the compensator parameters are R7 = 10 11 . 4 20 0 . 3 x 10 − 3 = 12 . 4 k 1 C5 = = 0.8nF 3 2 π x 16 x 10 x 12 . 4 x 10 3 C8 = 1 = 21pF 2 π x 600 x 10 3 x 12 . 4 x 10 3 Table 4. Typical switching time Input Voltage 1A Load Current 2A 12V 12.5ns 15.3ns In addition, the quiescent current loss is PQ = VIN x 2mA The total power loss of the SC4524D is therefore Select R7=12.4k, C5=1nF, and C8=22pF for the design. Compensator parameters for various typical applications are listed in Table 5. A MathCAD program is also available upon request for detailed calculation of the compensator parameters. Thermal Considerations For the power transistor inside the SC4524D, the conduction loss PC, the switching loss PSW, and bootstrap circuit loss PBST, can be estimated as follows: PC = D ⋅ VCESAT ⋅ IO PSW = PTOTAL = PC + PSW + PBST + PQ The temperature rise of the SC4524D is the product of the total power dissipation (see previous equation) and qJA (36oC/W), which is the thermal impedance from junction to ambient for the SOIC-8 EDP package. It is not recommended to operate the SC4524D above 125oC junction temperature. In the applications with high input voltage and high output current, the switching frequency may need to be reduced to meet the thermal requirement. 1 ⋅ t S ⋅ VIN ⋅ IO ⋅ FSW 2 PBST = D ⋅ VBST ⋅ IO 40 where VBST is the BST supply voltage and tS is the equivalent switching time of the NPN transistor (see Table 4). 15 SC4524D Applications Information (Cont.) PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation, the size of the loop formed by these components should be minimized. Since the power switch is already integrated within the SC4524D, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. V IN VO U T Z L Figure 9 — Pulse current Loop Note: Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized 16 SC4524D Recommended Component Parameters in Typical Applications Table 5 lists the recommended inductance (L1) and compensation network (R7, C5, C8) for common input and output voltages. The inductance is determined by assuming that the ripple current is 35% of load current IO. The compensator parameters are calculated by assuming a 22mF low ESR ceramic output capacitor and a loop gain crossover frequency of FSW/10. Table 5. Recommended inductance (L1) and compensator (R7, C5, C8) Vin (V) 3.3 5 12 Typical Applications Vo (V) Io (A) Fsw (KHz) 500 1 1000 1.5 500 2 1000 500 1 1000 2.5 500 2 1000 500 1 1000 1.5 500 2 1000 500 1 1000 2.5 500 2 1000 500 1 1000 3.3 500 2 1000 1 500 1.5 2 500 500 1 1000 2.5 500 2 1000 500 1 1000 3.3 500 2 1000 500 1 1000 5 500 2 1000 500 1 1000 7.5 500 2 1000 500 1 1000 10 500 2 1000 C2 (uF) 22 Recommended Parameters L1 (uH) R7 (K) C5 (nF) 6.8 4.02 3.3 3.3 7.5 0.82 3.3 4.02 3.3 1.5 7.5 0.82 4.7 13.3 0.82 2.2 21.5 0.68 2.2 11 0.82 1.5 21.5 0.68 6.8 4.02 3.3 3.3 7.68 0.82 3.3 4.02 3.3 2.2 7.68 0.82 8.2 6.81 2.2 4.7 14.3 0.68 4.7 6.81 1.5 2.2 12.1 0.68 6.8 9.09 1 3.3 16.2 0.68 3.3 9.09 1 2.2 17.8 0.68 8.2 4.32 3.3 4.7 4.32 3.3 15 6.81 1.5 6.8 12.1 0.82 6.8 6.81 1.5 3.3 12.1 0.68 15 9.09 1 8.2 18.7 0.68 8.2 9.09 1 4.7 18.7 0.68 15 14.3 0.82 10 24.9 0.68 8.2 14.3 0.82 4.7 27.4 0.68 15 21.5 0.82 8.2 38.3 0.68 8.2 21.5 0.82 4.7 38.3 0.68 10 25.5 0.82 4.7 51.1 0.68 4.7 25.5 0.82 2.2 51.1 0.68 C8 (pF) 10 22 22 10 22 10 22 10 22 10 17 SC4524D Typical Application Schematics V IN D1 5V C4 4.7PF 1N4148 C1 0.33PF L1 BST IN SW 2.2PH SC4524D SS/EN OUT 3.3V/2A R4 33.2k FB COMP C7 10nF C8 10pF ROSC GND D2 20BQ030 R5 15.8k R7 17.8k R6 14.3k C2 22PF C5 0.68nF L1: Coiltronics LD1-2R2 C2: Murata GRM31CR60J226K C4: Murata GRM31CR60J475K Figure 10. 1MHz 5V to 3.3V/2A Step-down Converter V IN D1 10V – 16V 1N4148 C4 4.7PF C1 0.33PF L1 BST IN SW 4.7PH SC4524D SS/EN OUT R4 33.2k 1.5V/2A FB COMP C7 10nF C8 33pF ROSC R7 4.32k GND R5 38.3k D2 20BQ030 R6 66.5k C2 22PF C5 3.3nF L1: Coiltronics DR73-4R7 C2: Murata GRM31CR60J226K C4: Murata GRM31CR60J475K Figure 11. 500kHz 10V-16V to 1.5V/2A Step-down Converter 18 SC4524D SS Typical Performance Characteristics (For A 12V to 5V/2A Step-down Converter with 1MHz Switching Frequency) SS 2 7 0 R E V 6 -7 Load Characteristic 6 Output Voltage (V) 5 12V Input (5V/DIV) 4 3 5V Output (2V/DIV) 2 1 SS Voltage (1V/DIV) 0 0 0 .5 1 1 .5 2 2 .5 3 10ms/DIV Load Current (A) Load Characteristic OCP VIN Start up Transient (IO=2A) 5V Output Short (5V/DIV) 5V Output Response (500mV/DIV, AC Coupling) Inductor Current (1A/DIV) Retry Inductor Current (2A/DIV) SS Voltage (2V/DIV) 40us/DIV Load Transient Response (IO= 0.3A to 2A) 20ms/DIV Output Short Circuit (Hiccup) 19 SC4524D Outline Drawing - SOIC-8 EDP A D e N 2X E /2 E1 1 E 2 ccc C 2 X N /2 T IP S e /2 B D aaa C S E A T IN G PLANE A2 A C b xN bbb A1 D IM E N S IO N S IN C H E S M ILLIM E T E R S D IM M IN N O M M A X M IN N O M M A X A A1 A2 b c D E1 E e F H h L L1 N 01 aaa bbb ccc .0 6 9 .0 0 5 .0 6 5 .0 2 0 .0 1 0 .1 9 3 .1 9 7 .1 5 4 .1 5 7 .2 3 6 B S C .0 5 0 B S C .1 1 6 .1 2 0 .1 3 0 .0 8 5 .0 9 5 .0 9 9 .0 1 0 .0 2 0 .0 1 6 .0 2 8 .0 4 1 (.0 4 1 ) 8 0° 8° .0 0 4 .0 1 0 .0 0 8 .0 5 3 .0 0 0 .0 4 9 .0 1 2 .0 0 7 .1 8 9 .1 5 0 C A -B D 1 .7 5 0 .1 3 1 .6 5 0 .5 1 0 .2 5 4 .9 0 5 .0 0 3 .9 0 4 .0 0 6 .0 0 B S C 1 .2 7 B S C 2 .9 5 3 .0 5 3 .3 0 2 .1 5 2 .4 1 2 .5 1 0 .2 5 0 .5 0 0 .4 0 0 .7 2 1 .0 4 (1 .0 5 ) 8 0° 8° 0 .1 0 0 .2 5 0 .2 0 1 .3 5 0 .0 0 1 .2 5 0 .3 1 0 .1 7 4 .8 0 3 .8 0 h F EXPOSED PAD h H H c GAGE PLANE 0 .2 5 L (L1 ) S E E D E T A IL S ID E V IE W A D E T A IL 01 A NO TES: 1. C O N T R O L L IN G D IM E N S IO N S A R E IN M IL L IM E T E R S (A N G L E S IN D E G R E E S ). 2. D A T U M S -A - A N D 3. D IM E N S IO N S "E 1 " A N D "D " D O N O T IN C L U D E M O L D F L A S H , P R O T R U S IO N S O R G ATE BURRS . R E F E R E N C E JE D E C S T D M S -0 1 2 , V A R IA T IO N B A . 4. -B - T O B E D E T E R M IN E D A T D A T U M P L A N E -H - 20 SC4524D Land Pattern - SOIC-8 EDP E SOLDER M ASK D D IM E N S IO N S D IM (C ) F G Z Y T H E R M A L V IA Ø 0 .3 6m m P X C D E F G P X Y Z IN C H E S (.2 0 5) .1 3 4 .2 0 1 .1 0 1 .1 1 8 .0 5 0 .0 2 4 .0 8 7 .2 9 1 M ILLIM E T E R S (5 .2 0 ) 3 .4 0 5 .1 0 2 .5 6 3 .0 0 1 .2 7 0 .6 0 2 .2 0 7 .4 0 NO TES: 1. T H IS L A N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E S O N L Y. C O N S U L T Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R C O M P A N Y 'S M A N U F A C T U R IN G G U ID E L IN E S A R E M E T. 2. R E F E R E N C E IP C -S M -7 8 2 A , R L P N O . 3 0 0 A . 3. T H E R M A L V IA S IN T H E L A N D P A T T E R N O F T H E E X P O S E D P A D S H A L L B E C O N N E C T E D T O A S Y S T E M G R O U N D P L A N E. F A IL U R E T O D O S O M A Y C O M P R O M IS E T H E T H E R M A L A N D/O R F U N C T IO N A L P E R F O R M A N C E O F T H E D E V IC E . 21 SC4524D © Semtech 2013 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. 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