PDF Data Sheet Rev. 0

700 MHz to 2700 MHz Rx Mixer with Integrated
IF DGA, Fractional-N PLL, and VCO
ADRF6620
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
LOIN+
LOIN–
PFD CHARGE CP
PUMP
+
÷1, ÷2,
÷4, ÷8
VTUNE
LDO
2.5 V
SERIAL
PORT
INTERFACE
LDO
VCO
LDO
3.3V
DECL4
DECL1
LOCK_DET
VPTAT
÷2
CS
SCLK
SDIO
MUXOUT
LOIN+
LOIN–
VTUNE
CP
DECL2
FRAC
N = INT +
MOD
11489-001
REFIN
÷8
÷4
÷2
×1
×2
RFSW1
APPLICATIONS
IFOUT1–
IFOUT1+
IFOUT2–
IFOUT2+
RFIN0
RFIN1
RFIN2
RFIN3
RFSW0
Integrated fractional-N phase-locked loop (PLL)
RF input frequency range: 700 MHz to 2700 MHz
Internal local oscillator (LO) frequency range: 350 MHz to
2850 MHz
Input P1dB: 17 dBm
Output IP3: 45 dBm
Single-pole four-throw (SP4T) RF input switch
Digital step attenuator (DSA) range: 0 dB to 15 dB
Integrated RF tunable balun allowing single-ended 50 Ω input
Multicore integrated voltage controlled oscillator (VCO)
Digitally programmable variable gain amplifier (DGA)
−3 dB bandwidth: >600 MHz
Balanced 150 Ω IF output impedance
Programmable via 3-wire serial port interface (SPI)
Single 5 V supply
MXOUT+
MXOUT–
IFIN+
IFIN–
FEATURES
Figure 1.
Wireless receivers
Digital predistortion (DPD) receivers
GENERAL DESCRIPTION
The ADRF6620 is a highly integrated active mixer and synthesizer
that is ideally suited for wireless receiver subsystems. The feature
rich device consists of a high linearity broadband active mixer;
an integrated fractional-N PLL; low phase noise, multicore VCO;
and IF DGA. In addition, the ADRF6620 integrates a 4:1 RF
switch, an on-chip tunable RF balun, programmable RF attenuator,
and low dropout (LDO) regulators. This highly integrated device
fits within a small 7 mm × 7 mm footprint.
The high isolation 4:1 RF switch and on-chip tunable RF balun
enable the ADRF6620 to support four single-ended 50 Ω
terminated RF inputs. A programmable attenuator ensures
optimal RF input drive to the high linearity mixer core. The
integrated DSA has an attenuation range of 0 dB to 15 dB with
a step size of 1 dB.
Rev. 0
The ADRF6620 offers two alternatives for generating the differential LO input signal: externally, via a high frequency, low
phase noise LO signal, or internally, via the on-chip fractional-N
PLL synthesizer. The integrated synthesizer enables continuous
LO coverage from 350 MHz to 2850 MHz. The PLL reference
input can support a wide frequency range because the divide and
multiply blocks can be used to increase or decrease the reference
frequency to the desired value before it is passed to the phase
frequency detector (PFD).
The integrated high linearity DGA provides an additional gain
range from 3 dB to 15 dB in steps of 0.5 dB for maximum flexibility
in driving an analog-to-digital converter (ADC).
The ADRF6620 is fabricated using an advanced silicon-germanium
BiCMOS process. It is available in a 48-lead, RoHS-compliant,
7 mm × 7 mm LFCSP package with an exposed pad. Performance
is specified over the −40°C to +85°C temperature range.
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Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADRF6620
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Port Interface (SPI) ......................................................... 27
Applications ....................................................................................... 1
Basic Connections ...................................................................... 28
Functional Block Diagram .............................................................. 1
RF Input Balun Insertion Loss Optimization ......................... 30
General Description ......................................................................... 1
IP3 and Noise Figure Optimization ......................................... 31
Revision History ............................................................................... 2
Interstage Filtering Requirements ............................................ 35
Specifications..................................................................................... 3
IF DGA vs. Load......................................................................... 38
RF Input to IF DGA Output System Specifications ................. 3
ADC Interfacing ......................................................................... 39
Synthesizer/PLL Specifications ................................................... 4
Power Modes ............................................................................... 40
RF Input to Mixer Output Specifications .................................. 6
Layout .......................................................................................... 40
IF DGA Specifications ................................................................. 7
Register Map ................................................................................... 41
Digital Logic Specifications ......................................................... 8
Register Address Descriptions ...................................................... 42
Absolute Maximum Ratings ............................................................ 9
Register 0x00, Reset: 0x00000, Name: SOFT_RESET ........... 42
Thermal Resistance ...................................................................... 9
Register 0x01, Reset: 0x8B7F, Name: Enables ........................ 42
ESD Caution .................................................................................. 9
Register 0x02, Reset: 0x0058, Name: INT_DIV ..................... 43
Pin Configuration and Function Descriptions ........................... 10
Register 0x03, Reset: 0x0250, Name: FRAC_DIV ................. 43
Typical Performance Characteristics ........................................... 11
Register 0x04, Reset: 0x0600, Name: MOD_DIV .................. 43
RF Input to DGA Output System Performance ..................... 11
Register 0x20, Reset: 0x0C26, Name: CP_CTL ...................... 44
Phase-Locked Loop (PLL)......................................................... 13
Register 0x21, Reset: 0x0003, Name: PFD_CTL .................... 45
RF Input to Mixer Output Performance ................................. 17
Register 0x22, Reset: 0x000A, Name: FLO_CTL ................... 46
IF DGA ........................................................................................ 20
Register 0x23, Reset: 0x0000, Name: DGA_CTL................... 47
Spurious Performance................................................................ 22
Register 0x30, Reset: 0x00000, Name: BALUN_CTL ............ 48
Theory of Operation ...................................................................... 24
Register 0x31, Reset: 0x08EF, Name: MIXER_CTL .............. 48
RF Input Switches ....................................................................... 24
Register 0x40, Reset: 0x0010, Name: PFD_CTL2 .................. 49
Tunable Balun ............................................................................. 25
Register 0x42, Reset: 0x000E, Name: DITH_CTL1 ............... 50
RF Digital Step Attenuator (DSA) ............................................ 25
Register 0x43, Reset: 0x0001, Name: DITH_CTL2 ............... 50
Active Mixer ................................................................................ 25
Outline Dimensions ....................................................................... 51
Digitally Programmable Variable Gain Amplifier (DGA) .... 25
Ordering Guide .......................................................................... 51
LO Generation Block ................................................................. 26
REVISION HISTORY
7/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
Data Sheet
ADRF6620
SPECIFICATIONS
VCCx = 5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
LO INPUT
Internal LO Frequency Range
External LO Frequency Range
LO Input Level
LO Input Impedance
RF INPUT
Input Frequency
Input Return Loss
Input Impedance
RF DIGITAL STEP ATTENUATOR
Attenuation Range
POWER SUPPLY
Power Consumption
Test Conditions/Comments
Min
LO_DIV_A = 00
350
350
−6
Typ
0
50
700
Max
Unit
2850
3200
+6
MHz
MHz
dBm
Ω
2700
MHz
dB
Ω
15
5.25
dB
V
12
50
Step size = 1 dB
0
4.75
LO output buffer disabled
External LO + IF DGA enabled
Internal LO + IF DGA enabled
Only IF DGA enabled
5.0
1.3
1.7
0.6
6
Power-Down Current
W
W
W
mA
RF INPUT TO IF DGA OUTPUT SYSTEM SPECIFICATIONS
VCCx = 5 V, TA = 25°C, high-side LO injection, fIF = 200 MHz, internal LO frequency, IF DGA output load = 150 Ω, and 2 V p-p differential
output with third-order low-pass filter, unless otherwise noted. For mixer settings for maximum linearity, see Table 16. All losses from
input and output traces and baluns are de-embedded from results
Table 2. RF Switch + Balun + RF Attenuator + Mixer + IF DGA
Parameter
DYNAMIC PERFORMANCE AT fRF = 900 MHz
Voltage Conversion Gain
Output P1dB
Output IP3
Output IP2
Noise Figure
DYNAMIC PERFORMANCE AT fRF = 1900 MHz
Voltage Conversion Gain
Output P1dB
Output IP3
Output IP2
Noise Figure
DYNAMIC PERFORMANCE AT fRF = 2100 MHz
Voltage Conversion Gain
Output P1dB
Output IP3
Output IP2
Noise Figure
DYNAMIC PERFORMANCE AT fRF = 2700 MHz
Voltage Conversion Gain
Output P1dB
Output IP3
Output IP2
Noise Figure
Test Conditions/Comments
fIF = 200 MHz
1 V p-p each output tone, 1 MHz tone spacing
1 V p-p each output tone, 1 MHz tone spacing
Noise figure optimized
fIF = 200 MHz
1 V p-p each output tone, 1 MHz tone spacing
1 V p-p each output tone, 1 MHz tone spacing
Noise figure optimized
fIF = 200 MHz
1 V p-p each output tone, 1 MHz tone spacing
1 V p-p each output tone, 1 MHz tone spacing
Noise figure optimized
fIF = 200 MHz
1 V p-p each output tone, 1 MHz tone spacing
1 V p-p each output tone, 1 MHz tone spacing
Noise figure optimized
Rev. 0 | Page 3 of 52
Min
Typ
Max
Unit
12
18
43
78
16
dB
dBm
dBm
dBm
dB
11
18
45
75
18.5
10.5
18
45
66
19
dB
dBm
dBm
dBm
dB
dB
dBm
dBm
dBm
dBm
dB
9
18
44
74
21
dB
dBm
dBm
dBm
dB
ADRF6620
Data Sheet
SYNTHESIZER/PLL SPECIFICATIONS
VCCx = 5 V, TA = 25°C, fREF = 153.6 MHz, fREF power = 4 dBm, fPFD = 38.4 MHz, and loop filter bandwidth = 120 kHz, unless otherwise noted.
Table 3.
Parameter
PLL REFERENCE
PLL Reference Frequency
PLL Reference Level
PFD FREQUENCY
INTERNAL VCO RANGE
OPEN-LOOP VCO PHASE NOISE
fVCO2 = 3.4 GHz
fVCO1 = 4.6 GHz
fVCO0 = 5.5 GHz
SYNTHESIZER SPECIFICATIONS
fLO = 1.710 GHz, fVCO2 = 3.420 GHz
fPFD Spurs
Closed-Loop Phase Noise
Integrated Phase Noise
Figure of Merit (FOM) 1
Test Conditions/Comments
For PLL lock condition
VTUNE = 2 V, LO_DIV_A = 00
1 kHz offset
10 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
6 MHz offset
10 MHz offset
40 MHz offset
VCO sensitivity (KV)
1 kHz offset
10 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
6 MHz offset
10 MHz offset
40 MHz offset
VCO sensitivity (KV)
1 kHz offset
10 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
6 MHz offset
10 MHz offset
40 MHz offset
VCO sensitivity (KV)
Measured at LO output, LO_DIV_A = 01
fREF = 153.6 MHz, fPFD = 38.4 MHz, 120 kHz loop filter
fPFD × 1
fPFD × 2
fPFD × 3
fPFD × 4
1 kHz offset
10 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
6 MHz offset
10 MHz offset
40 MHz offset
10 kHz to 40 MHz integration bandwidth
Rev. 0 | Page 4 of 52
Min
12
−15
24
2800
Typ
+4
Max
Unit
464
+14
58
5700
MHz
dBm
MHz
MHz
−39
−81
−103
−123
−125
−143
−147
−155
88
−39
−74
−101
−123
−125
−143
−147
−156
89
−39
−69
−99
−121
−124
−142
−146
−155
72
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz/V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz/V
−83
−89
−90
−93
−97
−110
−107
−128
−132
−144
−152
−158
0.21
−222
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
dBc/Hz
Data Sheet
Parameter
fLO = 2.305 GHz, fVCO1 = 4.610 GHz
fPFD Spurs
Closed-Loop Phase Noise
Integrated Phase Noise
Figure of Merit1
fLO = 2.75 GHz, fVCO2 = 5.5 GHz
fPFD Spurs
Closed-Loop Phase Noise
Integrated Phase Noise
Figure of Merit1
1
ADRF6620
Test Conditions/Comments
Min
Typ
Max
Unit
fPFD × 1
fPFD × 2
fPFD × 3
fPFD × 4
1 kHz offset
10 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
6 MHz offset
10 MHz offset
40 MHz offset
10 kHz to 40 MHz integration bandwidth
−84
−87
−91
−92
−93
105
−103
−116
−130
−144
−152
−156
0.3
−222
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
dBc/Hz
fPFD × 1
fPFD × 2
fPFD × 3
fPFD × 4
1 kHz offset
10 kHz offset
100 kHz offset
800 kHz offset
1 MHz offset
6 MHz offset
10 MHz offset
40 MHz offset
10 kHz to 40 MHz integration bandwidth
−82
−88
−93
−96
−93
−101
−99
−122
−128
−144
−151
−154
0.38
−222
dBc
dBc
dBc
dBc
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
° rms
dBc/Hz
Figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10 log 10(fPFD) – 20 log 10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 160 MHz
and fREF power = 4 dBm (500 V/µs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset.
Rev. 0 | Page 5 of 52
ADRF6620
Data Sheet
RF INPUT TO MIXER OUTPUT SPECIFICATIONS
VCCx = 5 V, TA = 25°C, high-side LO injection, fIF = 200 MHz, external LO frequency, and RF attenuation = 0 dB, unless otherwise noted.
Mixer settings configured for maximum linearity (see Table 16). All losses from input and output traces and baluns are de-embedded
from results.
Table 4. RF Switch + Balun + RF Attenuator + Mixer
Parameter
VOLTAGE GAIN
MIXER OUTPUT IMPEDANCE
DYNAMIC PERFORMANCE AT fRF= 900 MHz
Voltage Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation1
DYNAMIC PERFORMANCE AT fRF =1900 MHz
Voltage Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation1
DYNAMIC PERFORMANCE AT fRF = 2100 MHz
Voltage Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation1
DYNAMIC PERFORMANCE AT fRF = 2700 MHz
Voltage Conversion Gain
Input P1dB
Input IP3
Input IP2
Noise Figure
LO to RF Leakage
RF to LO Leakage
LO to IF Leakage
RF to IF Leakage
Isolation1
1
Test Conditions/Comments
Differential 255 Ω load
Differential (see Figure 87)
−5 dBm each input tone, 1 MHz tone spacing
−5 dBm each input tone, 1 MHz tone spacing
With respect to 0 dBm RF input power
Isolation between RFIN0 and RFIN3
−5 dBm each input tone, 1 MHz tone spacing
−5 dBm each input tone, 1 MHz tone spacing
With respect to 0 dBm RF input power
Isolation between RFIN0 and RFIN3
−5 dBm each input tone, 1 MHz tone spacing
−5 dBm each input tone, 1 MHz tone spacing
With respect to 0 dBm RF input power
Isolation between RFIN0 and RFIN3
−5 dBm each input tone, 1 MHz tone spacing
−5 dBm each input tone, 1 MHz tone spacing
With respect to 0 dBm RF input power
Isolation between RFIN0 and RFIN3
Min
Typ
−4
255
Max
Unit
dB
Ω
−2
17
40
65
15
−70
−60
−32
−45
−52
dB
dBm
dBm
dBm
dB
dBm
dBc
dBm
dBc
dBc
−3
17
40
62
17
−60
−50
−35
−43
−47
dB
dBm
dBm
dBm
dB
dBm
dBc
dBm
dBc
dBc
−3.5
18
40
54.5
18
−60
−40
−35
−40
−45
dB
dBm
dBm
dBm
dB
dBm
dBc
dBm
dBc
dBc
−4.7
19
40
56
21
−60
−45
−40
−42
−41
dB
dBm
dBm
dBm
dB
dBm
dBc
dBm
dBc
dBc
Isolation between RF inputs. An input signal was applied to RFIN0 while RFIN1 to RFIN3 were terminated with 50 Ω. The IF signal amplitude was measured at the mixer
output. The internal switch was then configured for RFIN3, and the feedthrough was measured as a delta from the fundamental.
Rev. 0 | Page 6 of 52
Data Sheet
ADRF6620
IF DGA SPECIFICATIONS
VCCx = 5 V, TA = 25°C, RS = RL = 150 Ω differential, fIF = 200 MHz, 2 V p-p differential output,unless otherwise noted. All losses from
input and output traces and baluns are de-embedded from results.
Table 5.
Parameter
BANDWIDTH
−1 dB Bandwidth
−3 dB Bandwidth
SLEW RATE
INPUT STAGE
Input P1dB
Input Impedance
Common-Mode Input Voltage
Common-Mode Rejection Ratio (CMRR)
GAIN
Power/Voltage Gain, Step Size = 0.5 dB
Gain Flatness
Gain Conformance Error
Gain Temperature Sensitivity
Gain Step Response
OUTPUT STAGE
Output P1dB
Output Impedance
NOISE/HARMONIC PERFORMANCE at 200 MHz
Output IP3
Output IP2
HD2
HD3
Noise Figure
Test Conditions/Comments
Min
Typ
Max
Unit
VOUT = 2 V p-p
VOUT = 2 V p-p
500
700
5.5
MHz
MHz
V/ns
At minimum gain
17
150
1.5
50
dBm
Ω
V
dB
3
50 MHz < fC < 200 MHz
See Figure 88
1 V p-p each output tone, 1 MHz tone spacing
1 V p-p each output tone, 1 MHz tone spacing
VOUT = 2 V p-p
VOUT = 2 V p-p
Rev. 0 | Page 7 of 52
0.2
±0.1
0.008
15
15
dB
dB
dB
dB/C
ns
18
150
dBm
Ω
45
63
−87
−84
10
dBm
dBm
dBc
dBc
dB
ADRF6620
Data Sheet
DIGITAL LOGIC SPECIFICATIONS
Table 6.
Parameter
SERIAL PORT INTERFACE TIMING
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Serial Clock Period
Setup Time Between Data and Rising Edge of SCLK
Hold Time Between Data and Rising Edge of SCLK
Setup Time Between Falling Edge of CS and SCLK
Hold Time Between Rising Edge of CS and SCLK
Minimum Period SCLK Can Be in Logic High State
Minimum Period SCLK Can Be in Logic Low State
Maximum Time Delay Between Falling Edge of SCLK and Output
Data Valid for a Read Operation
Maximum Time Delay Between CS Deactivation and SDIO Bus
Return to High Impedance
Symbol
Test Conditions/Comments
VIH
VIL
VOH
VOL
tSCLK
tDS
tDH
tS
tH
tHIGH
tLOW
tACCESS
Min
Typ
Max
1.4
231
V
V
V
V
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
0.70
IOH = −100 µA
IOL = +100 µA
2.3
0.2
38
8
8
10
10
10
10
tZ
Unit
Timing Diagram
tHIGH
tDS
tS
tH
tSCLK
tACCESS
tLOW
tDH
CS
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
tZ
A6
A5
A4
A3
A2
A1
A0
R/W
D15
D14
D13
Figure 2. Serial Port Interface Timing
Rev. 0 | Page 8 of 52
D3
D2
D1
D0
DON'T CARE
11489-002
SCLK
Data Sheet
ADRF6620
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
VCCx
RFSW0, RFSW1
RFIN0, RFIN1, RFIN2, RFIN3
LOIN−, LOIN+
REFIN
IFIN−, IFIN+
CS, SCLK, SDIO
VTUNE
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Table 8. Thermal Resistance
Rating
−0.5 V to +5.5 V
−0.3 V to +3.6 V
20 dBm
16 dBm
−0.3 V to +3.6 V
−1.2 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−40°C to +85°C
−65°C to +150°C
150°C
Package Type
48-Lead LFCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 9 of 52
θJC
1.62
Unit
°C/W
ADRF6620
Data Sheet
48
47
46
45
44
43
42
41
40
39
38
37
GND
VTUNE
DECL4
LOIN+
LOIN–
MUXOUT
SDIO
SCLK
CS
RFSW1
RFSW0
DECL3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VCC1 1
DECL1 2
ADRF6620
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
GND
RFIN0
GND
GND
RFIN1
GND
GND
RFIN2
GND
GND
RFIN3
GND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO A GROUND
PLANE WITH LOW THERMAL IMPEDANCE.
11489-003
VCC3
VCC4
IFIN–
IFIN+
GND
MXOUT+
MXOUT–
GND
LOOUT+
LOOUT–
GND
VCC5
13
14
15
16
17
18
19
20
21
22
23
24
CP 3
GND 4
GND 5
REFIN 6
DECL2 7
IFOUT1+ 8
IFOUT1– 9
IFOUT2+ 10
IFOUT2– 11
VCC2 12
PIN 1
INDICATOR
Figure 3. Pin Configuration
Table 9. Pin Function Descriptions 1
Pin No.
1, 12, 13, 14, 24
2, 7, 37, 46
3
4, 5, 17, 20, 23, 25, 27,
28, 30, 31, 33, 34, 36, 48
6
8 to 11
15, 16
18, 19
21, 22
26, 29, 32, 35
Mnemonic
VCC1, VCC2, VCC3,
VCC4, VCC5
DECL1, DECL2,
DECL3, DECL4
CP
GND
Description
5 V Power Supplies. Decouple all power supply pins to ground, using 100 pF and 0.1 µF
capacitors. Place the decoupling capacitors near the pins.
Decouple all DECLx pins to ground, using 100 pF, 0.1 µF, and 10 µF capacitors. Place the
decoupling capacitors near the pins.
Synthesizer Charge Pump Output. Connect this pin to the VTUNE pin through the loop filter.
Ground.
REFIN
IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
Synthesizer Reference Frequency Input.
IF DGA Outputs. Connect the positive pins such that IFOUT1+ and IFOUT2+ are tied
together. Similarly, connect the negative pins such that IFOUT1− and IFOUT2− are tied
together. Refer to the Layout section for a recommended layout that minimizes parasitic
capacitance and optimizes performance.
Differential IF DGA Inputs. AC couple the mixer outputs to the IF DGA inputs.
Differential Mixer Outputs. AC couple the mixer outputs to the IF DGA inputs.
Differential LO Outputs. The differential output impedance is 50 Ω.
RF Inputs. These single-ended RF inputs have a 50 Ω input impedance and must be
ac-coupled.
External Pin Control of RF Input Switches. For logic high, connect these pins to 2.5 V logic.
SPI Chip Select, Active Low. 3.3 V tolerant logic levels.
SPI Clock. 3.3 V tolerant logic levels.
SPI Data Input or Output. 3.3 V tolerant logic levels.
Multiplexer Output. This output pin provides the PLL reference signal or the PLL lock
detect signal.
Differential Local Oscillator Inputs. The differential input impedance is 50 Ω.
VCO Tuning Voltage. Connect this pin to the CP pin through the loop filter.
Exposed Pad. The exposed pad must be connected to a ground plane with low thermal
impedance.
38, 39
40
41
42
43
IFIN−, IFIN+
MXOUT+, MXOUT−
LOOUT+, LOOUT−
RFIN3, RFIN2,
RFIN1, RFIN0
RFSW0, RFSW1
CS
SCLK
SDIO
MUXOUT
44, 45
47
49
LOIN−, LOIN+
VTUNE
EPAD
1
For more connection information about these pins, see Table 14.
Rev. 0 | Page 10 of 52
Data Sheet
ADRF6620
TYPICAL PERFORMANCE CHARACTERISTICS
RF INPUT TO DGA OUTPUT SYSTEM PERFORMANCE
VCCx = 5 V, TA = 25°C, RFDSA_SEL = 00 (0 dB), RFSW_SEL = 00 (RFIN0), BAL_CIN and BAL_COUT optimized for maximum gain;
MIXER_BIAS, MIXER_RDAC, and MIXER_CDAC optimized for highest linearity, DGA at maximum gain; third-order low-pass filter
between the mixer output and IF DGA input; high-side LO, internal LO frequency, IF frequency = 200 MHz, unless otherwise noted. All
losses from input and output traces and baluns are de-embedded from results.
15
15
14
14
13
TA = –40°C
RF FREQUENCY = 1900MHz
GAIN (dB)
11
10
RF FREQUENCY = 2100MHz
10
TA = +25°C
TA = +85°C
9
RF FREQUENCY = 2700MHz
9
8
7
6
5
8
4
7
3
2
6
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
0
50
11489-004
1000
250
300
350
400
450
500
22
20
TA = +85°C
TA = +25°C
18
18
TA = –40°C
16
OP1dB (dBm)
14
12
10
8
14
12
10
8
6
6
4
4
2
2
1000
1400
1800
2200
RF FREQUENCY (MHz)
Figure 5. OP1dB vs. RF Frequency
2600
3000
0
50
11489-005
0
600
200
Figure 6. Gain vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
22
16
150
IF FREQUENCY (MHz)
Figure 4. Gain vs. RF Frequency; IF Frequency = 200 MHz
20
100
11489-007
1
5
600
RF
RF
RF
RF
FREQUENCY = 900MHz
FREQUENCY = 1900MHz
FREQUENCY = 2100MHz
FREQUENCY = 2700MHz
100
150
200
250
300
350
IF FREQUENCY (MHz)
400
450
500
11489-008
GAIN (dB)
RF FREQUENCY = 900MHz
12
11
12
OP1dB (dBm)
13
Figure 7. OP1dB vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
Rev. 0 | Page 11 of 52
ADRF6620
Data Sheet
95
85
75
75
OIP2 (dBm), OIP3 (dBm)
85
65
TA = –40°C
TA = +25°C
55
TA = +85°C
OIP3 (dBm)
45
35
OIP3 (dBm)
45
35
15
15
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
5
50
RF
RF
RF
RF
FREQUENCY = 900MHz
FREQUENCY = 1900MHz
FREQUENCY = 2100MHz
FREQUENCY = 2700MHz
100
150
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
Figure 11. OIP2/OIP3 vs. IF Frequency; LO Sweep with Fixed RF,
IF Roll-Off; Measured on 1 V p-p on Each Tone at DGA Output
Figure 8. OIP2/OIP3 vs. RF Frequency; Measured on 1 V p-p on Each Tone
at DGA Output
15
95
14
LO FREQUENCY = 1100MHz
13
85
LO FREQUENCY = 2100MHz
12
OIP2 (dBm)
75
OIP2 (dBm), OIP3 (dBm)
11
10
GAIN (dB)
55
25
5
600
OIP2 (dBm)
65
25
11489-006
OIP2 (dBm), OIP3 (dBm)
OIP2 (dBm)
11489-009
95
LO FREQUENCY = 2300MHz
9
8
7
6
5
4
65
LO FREQUENCY = 1100MHz
LO FREQUENCY = 2300MHz
55
45
OIP3 (dBm)
35
LO FREQUENCY = 2100MHz
25
3
2
15
100
150
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
5
50
11489-110
0
50
Figure 9. Gain vs. IF Frequency; RF Sweep with Fixed LO;
IF and RF Roll-Off; Measured on 1 V p-p on Each Tone at DGA Output
200
250
300
350
400
450
500
Figure 12. OIP2/OIP3 vs. IF Frequency; RF Sweep with Fixed LO;
IF and RF Roll-Off; Measured on 1 V p-p on Each Tone at DGA Output
500
450
85
OIP2 (dBm)
TA = +85°C
400
SUPPLY CURRENT (mA)
75
65
55
OIP3 (dBm)
45
35
25
350
300
TA = +25°C
TA = –40°C
250
200
150
100
15
0
1
FREQUENCY = 900MHz
FREQUENCY = 1900MHz
FREQUENCY = 2100MHz
FREQUENCY = 2700MHz
2
3
4
5
6
7
50
8
RFDSA
9
10 11 12 13 14 15
0
600
11489-111
RF
RF
RF
RF
1000
1400
1800
2200
2600
RF FREQUENCY (MHz)
Figure 10. OIP2/OIP3 vs. RFDSA; Measured on 1 V p-p on Each Tone at
DGA Output
Rev. 0 | Page 12 of 52
Figure 13. Supply Current vs. RF Frequency
3000
11489-113
OIP2 (dBm), OIP3 (dBm)
150
IF FREQUENCY (MHz)
95
5
100
11489-112
1
Data Sheet
ADRF6620
PHASE-LOCKED LOOP (PLL)
VCCx = 5 V, TA = 25°C, 120 kHz loop filter, fREF = 153.6 MHz, PLL reference amplitude = 4 dBm, fPFD = 38.4 MHz, measured at LO
output, unless otherwise noted.
10M
100M
Figure 14. VCO2 Open-Loop VCO Phase Noise vs. Offset Frequency;
fVCO2 = 3.4 GHz, LO_DIV_A = 00, VTUNE = 2 V
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
100k
1M
10M
100M
OFFSET FREQUENCY (Hz)
Figure 15. VCO1 Open-Loop Phase Noise vs. Offset Frequency;
fVCO1 = 4.6 GHz, LO_DIV_A = 00, VTUNE = 2 V
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
100k
1M
10M
100M
OFFSET FREQUENCY (Hz)
Figure 16. VCO0 Open-Loop Phase Noise vs. Offset Frequency;
fVCO0 = 5.5 GHz, LO_DIV_A = 00, VTUNE = 2 V
100M
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
LO_DIV_A = 00
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
10k
100k
1M
10M
100M
Figure 18. VCO1 Closed-Loop Phase Noise for Various LO_DIV_A Dividers vs.
Offset Frequency; fVCO1 = 4.6 GHz
11489-012
10k
10M
OFFSET FREQUENCY (Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k
1M
Figure 17. VCO2 Closed-Loop Phase Noise for Various LO_DIV_A Dividers vs.
Offset Frequency; fVCO2 = 3.4 GHz
11489-011
10k
100k
OFFSET FREQUENCY (Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k
10k
11489-014
1M
LO_DIV_A = 00
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
LO_DIV_A = 00
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
100M
11489-015
100k
OFFSET FREQUENCY (Hz)
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
1k
11489-013
PHASE NOISE (dBc/Hz)
10k
11489-010
PHASE NOISE (dBc/Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
1k
Figure 19. VCO0 Closed-Loop Phase Noise for Various LO_DIV_A Dividers vs.
Offset Frequency; fVCO0 = 5.532 GHz
Rev. 0 | Page 13 of 52
ADRF6620
Data Sheet
3.0
200
TA = –40°C
TA = +25°C
TA = +85°C
2.6
2.4
210
VTUNE (V)
FOM (dBc/Hz/Hz)
205
TA = –40°C
TA = +25°C
TA = +85°C
2.8
215
220
2.2
2.0
1.8
1.6
1.4
225
2000
2200
2400
2600
2800
1.0
2800
LO FREQUENCY (MHz)
3200
PHASE NOISE (dBc/Hz)
10kHz OFFSET
100kHz OFFSET
800kHz OFFSET
5600
–120
1MHz OFFSET
–125
–130
–135
–140
10MHz OFFSET
–150
6MHz OFFSET
40MHz OFFSET
–155
5379
5779
–160
2579
PHASE NOISE (dBc/Hz)
50kHz OFFSET
400kHz OFFSET
1MHz OFFSET
10MHz OFFSET
2784
3379
3779
4179
4579
4979
5379
5779
Figure 24. Open-Loop Phase Noise vs. VCO Frequency;
LO_DIV_A = 00
1kHz OFFSET
2584
2979
VCO FREQUENCY (MHz)
11489-018
PHASE NOISE (dBc/Hz)
5200
–115
–145
11489-017
PHASE NOISE (dBc/Hz)
–110
1kHz OFFSET
1984
2184
2384
LO FREQUENCY (MHz)
4800
TA = –40°C
TA = +25°C
TA = +85°C
–105
Figure 21. Open-Loop Phase Noise vs. VCO Frequency;
LO_DIV_A = 00
–85
TA = –40°C
–90
TA = +25°C
–95
TA = +85°C
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
1384
1584
1784
4400
Figure 23. VTUNE vs. VCO Frequency
–100
3779 4179 4579 4979
VCO FREQUENCY (MHz)
4000
VCO FREQUENCY (MHz)
Figure 20. PLL Figure of Merit (FOM) vs. LO Frequency
0
TA = –40°C
–10
TA = +25°C
–20
TA = +85°C
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
2579 2979 3379
3600
11489-020
1800
–85
TA = –40°C
–90
TA = +25°C
–95
TA = +85°C
–100
100kHz OFFSET
–105
–110
–115
–120
800kHz OFFSET
–125
–130
–135
–140
6MHz OFFSET
–145
–150
40MHz OFFSET
–155
–160
–165
1384
1584
1784
1984
2184
2384
2584
2784
LO FREQUENCY (MHz)
Figure 22. 120 kHz Bandwidth Loop Phase Noise, LO_DIV_A = 01;
Offset = 1 kHz, 50 kHz, 400 kHz, 1 MHz, and 10 MHz
Figure 25. 120 kHz Bandwidth Loop Phase Noise, LO_DIV_A = 01;
Offset = 100 kHz, 800 kHz, 6 MHz, and 40 MHz
Rev. 0 | Page 14 of 52
11489-021
1600
11489-016
230
1400
11489-019
1.2
Data Sheet
0.7
0.6
LO_DIV_A = 11
LO_DIV_A = 10
LO_DIV_A = 01
0.5
0.4
0.3
0.7
0.6
0.5
0.4
0.3
0.2
0.2
0.1
0.1
3168
3568
3968
4368
4768
5168
5568
VCO FREQUENCY (MHz)
Figure 26. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency;
LO_DIV_A = 01, 10, and 11, Including Spurs, for Various LO Divider Ratios
–85
–90
–95
–100
–105
3568
3968
4368
4768
5168
5568
–75
4368
4768
5168
5568
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
TA = –40°C
TA = +25°C
TA = +85°C
–80
–85
–90
–95
–100
–105
–110
2768
3168
3568
3968
4368
4768
5168
5568
VCO FREQUENCY (MHz)
Figure 30. fPFD Spurs vs. VCO Frequency;
2× PFD Offset; Measured at LO Output
–70
–70
–80
–85
–90
–95
–100
–105
3168
3568
3968
4368
4768
5168
VCO FREQUENCY (MHz)
5568
Figure 28. fPFD Spurs vs. VCO Frequency;
3× PFD Offset; Measured at LO Output
–75
TA = –40°C
TA = +25°C
TA = +85°C
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
–80
–85
–90
–95
–100
–105
–110
–115
–120
2768
3168
3568
3968
4368
4768
5168
VCO FREQUENCY (MHz)
Figure 31. fPFD Spurs vs. VCO Frequency;
4× PFD Offset; Measured at LO Output
Rev. 0 | Page 15 of 52
5568
11489-032
REFERENCE SPURS (dBc), 4× PFD OFFSET
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
TA = –40°C
TA = +25°C
TA = +85°C
11489-029
REFERENCE SPURS (dBc), 3× PFD OFFSET
3968
Figure 29. 10 kHz to 40 MHz Integrated Phase Noise vs. VCO Frequency;
LO_DIV_A = 01, 10, and 11, Excluding Spurs, for Various LO Divider Ratios
Figure 27. fPFD Spurs vs. VCO Frequency;
1× PFD Offset; Measured at LO Output
–110
2768
3568
VCO FREQUENCY (MHz)
11489-028
3168
VCO FREQUENCY (MHz)
–75
3168
11489-031
LO_DIV_A = 01
LO_DIV_A = 10
LO_DIV_A = 11
TA = –40°C
TA = +25°C
TA = +85°C
–80
–110
2768
0
2768
REFERENCE SPURS (dBc), 2× PFD OFFSET
–75
LO_DIV_A = 11
LO_DIV_A = 10
LO_DIV_A = 01
–70
–70
REFERENCE SPURS (dBc), 1× PFD OFFSET
0.8
11489-128
0.8
0
2768
TA = –40°C
TA = +25°C
TA = +85°C
0.9
11489-126
INTEGRATED PHASE NOISE,
WITH SPUR (° rms)
0.9
1.0
TA = –40°C
TA = +25°C
TA = +85°C
INTEGRATED PHASE NOISE,
WITHOUT SPUR (° rms)
1.0
ADRF6620
ADRF6620
Data Sheet
10
300
TA = –40°C
TA = +25°C
TA = +85°C
290
8
LO AMPLITUDE (dBm)
230
2
0
LO_DRV_LVL = 01
–2
–4
220
–6
210
–8
200
350
850
1350
1850
2350
2850
LO FREQUENCY (MHz)
–10
350
REFERENCE SPURS (dBc), 1× PFD OFFSET
–70
–10
–20
–30
–40
–50
–60
–70
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
2863.2
2858.2
2853.2
2848.2
2843.2
2838.2
2833.2
2828.2
75
100
125
150
TIME (µs)
175
200
225
250
11489-137
2823.2
50
2850
–74
–76
–78
–80
–82
–84
–86
–88
–90
–92
–94
–96
–98
1584
1784
1984
2184
2384
2584
2784
Figure 36. fPFD Spurs, LO_DIV_A = 01, 1× PFD Offset;
Measured on LO Output and DGA Output
2868.2
25
2350
LO FREQUENCY (MHz)
Figure 33. RF to LO Output Feedthrough, LO_DRV_LVL = 00
0
1850
LO OUTPUT
DGA OUTPUT
–72
–100
1384
11489-136
–80
600
1350
Figure 35. LO Amplitude vs. LO Frequency; LO_DRV_LVL = 00, 01, 10, and 11
0
RF TO LO FEEDTHROUGH (dBc)
850
LO FREQUENCY (MHz)
Figure 32. Supply Current vs. LO Frequency; LO_DRV_LVL = 00, 01, 10, and 11
LO FREQUENCY (MHz)
LO_DRV_LVL = 00
TA = –40°C
TA = +25°C
TA = +85°C
11489-135
250 LO_DRV_LVL = 00
LO_DRV_LVL = 01
240 LO_DRV_LVL = 10
LO_DRV_LVL = 11
4
Figure 34. LO Frequency Settling Time, Loop Filter Bandwidth = 120 kHz
Rev. 0 | Page 16 of 52
11489-023
260
11489-132
SUPPLY CURRENT (mA)
270
2818.2
LO_DRV_LVL = 11
LO_DRV_LVL = 10
6
280
Data Sheet
ADRF6620
RF INPUT TO MIXER OUTPUT PERFORMANCE
VCCx = 5 V, TA = 25°C, RL = 250 Ω, external LO, PLO = 0 dBm, RFDSA_SEL = 00 (0 dB), RFSW_SEL = 00 (RFIN0), BAL_CIN and
BAL_COUT optimized, MIXER_BIAS, MIXER_RDAC, and MIXER_CDAC optimized for highest linearity, DGA and LO output disabled,
unless otherwise noted. All losses from input and output traces and baluns are de-embedded from results.
0
0
–1
–1
RF
RF
RF
RF
–40°C
–2
FREQUENCY = 900MHz
FREQUENCY = 1900MHz
FREQUENCY = 2100MHz
FREQUENCY = 2700MHz
–2
+85°C
–4
–5
–6
–6
–7
–7
1400
1800
2200
2600
3000
–8
0
20
18
18
16
16
14
14
IP1dB (dBm)
22
20
12
10
8
6
4
4
TA = –40°C
TA = +25°C
TA = +85°C
2600
3000
600
700
800
900
1000
FREQUENCY = 900MHz
FREQUENCY = 1900MHz
FREQUENCY = 2100MHz
FREQUENCY = 2700MHz
0
11489-035
2200
RF FREQUENCY (MHz)
0
100
200
300
400
500
600
700
800
900
1000
IF FREQUENCY (MHz)
Figure 41. Mixer IP1dB vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
Figure 38. Mixer IP1dB vs. RF Frequency
100
100
TA = –40°C
TA = +25°C
TA = +85°C
90
80
80
IIP2 (dBm), IIP3 (dBm)
IIP2 (dBm)
70
60
50
IIP3 (dBm)
40
30
70
60
50
30
10
10
1800
2200
2600
3000
RF FREQUENCY (MHz)
11489-036
20
1400
IIP3 (dBm)
40
20
1000
IIP2 (dBm)
RF
RF
RF
RF
0
0
100
200
300
400
500
FREQUENCY = 900MHz
FREQUENCY = 1900MHz
FREQUENCY = 2100MHz
FREQUENCY = 2700MHz
600
700
800
900
1000
IF FREQUENCY (MHz)
Figure 42. Mixer IIP2/IIP3 vs. IF Frequency; PIN = −5 dBm/Tone,
1 MHz Spacing, LO Sweep with Fixed RF, IF Roll-Off
Figure 39. Mixer IIP2/IIP3 vs. RF Frequency; PIN = −5 dBm/Tone,
1 MHz Spacing
Rev. 0 | Page 17 of 52
11489-039
90
0
600
RF
RF
RF
RF
2
1800
500
10
6
1400
400
12
8
1000
300
IF FREQUENCY (MHz)
22
0
600
200
Figure 40. Mixer Gain vs. IF Frequency; LO Sweep with Fixed RF, IF Roll-Off
Figure 37. Mixer Gain vs. RF Frequency
2
100
11489-038
1000
RF FREQUENCY (MHz)
IP1dB (dBm)
–4
–5
–8
600
IIP2 (dBm), IIP3 (dBm)
–3
11489-037
GAIN (dB)
–3
11489-034
GAIN (dB)
+25°C
ADRF6620
0
–1
Data Sheet
100
RFSW_SEL = 00
RFSW_SEL = 01
RFSW_SEL = 10
RFSW_SEL = 11
90
RFSW_SEL = 00
RFSW_SEL = 01
RFSW_SEL = 10
RFSW_SEL = 11
IIP2 (dBm)
80
IIP2 (dBm), IIP3 (dBm)
GAIN (dB)
–2
–3
–4
–5
70
60
IIP3 (dBm)
50
40
30
–6
20
–7
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
Figure 43. Mixer Gain vs. RF Frequency; RFSW_SEL = 00, 01, 10, and 11
0
ISOLATION RFSW_SEL = 00 TO 11
ISOLATION RFSW_SEL = 00 TO 01
ISOLATION RFSW_SEL = 00 TO 10
–5
–10
ISOLATION (dBc)
ISOLATION (dBc)
–30
–35
–40
–45
–50
–20
–25
–30
–35
–40
–65
–55
–70
–60
1400
1800
2200
2600
3000
–65
600
11489-142
1000
RF FREQUENCY (MHz)
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
Figure 44. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 00 Driven
Figure 47. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 11 Driven
0
ISOLATION RFSW_SEL = 01 TO 11
ISOLATION RFSW_SEL = 01 TO 00
ISOLATION RFSW_SEL = 01 TO 10
–5
–10
–15
–20
–20
ISOLATION (dBc)
–15
–25
–30
–35
–40
–45
–30
–35
–40
–45
–50
–55
–55
–60
–60
–65
ISOLATION RFSW_SEL = 10 TO 11
ISOLATION RFSW_SEL = 10 TO 00
ISOLATION RFSW_SEL = 10 TO 01
–25
–50
–65
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
11489-141
ISOLATION (dBc)
ISOLATION RFSW_SEL = 11 TO 11
ISOLATION RFSW_SEL = 11 TO 00
ISOLATION RFSW_SEL = 11 TO 01
–50
–60
–70
600
3000
–45
–55
–10
2600
–15
–25
0
2200
Figure 46. Mixer IIP2/IIP3 vs. RF Frequency; RFSW_SEL = 00, 01, 10, and 11
–20
–5
1800
RF FREQUENCY (MHz)
–15
–75
600
1400
11489-145
–10
1000
Figure 45. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 01 Driven
–70
600
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
Figure 48. Mixer Input to Mixer Output Isolation vs. RF Frequency;
RFSW_SEL = 10 Driven
Rev. 0 | Page 18 of 52
11489-144
0
–5
0
600
11489-143
10
11489-140
–8
600
LO TO IF FEEDTHROUGH (dBm)
Data Sheet
ADRF6620
0
300
–5
275
INTERNAL LO
250
–10
225
–15
200
–20
EXTERNAL LO
ICC (mA)
175
150
–25
125
–30
100
–35
75
50
–45
25
1200
1600
2000
2400
2800
3200
LO FREQUENCY (MHz)
0
600
11489-146
–50
800
TA = –40°C
TA = +25°C
TA = +85°C
1000
1400
1800
2200
2600
3000
RF FREQUENCY (MHz)
11489-149
–40
Figure 52. ICC vs. RF Frequency; DGA and LO Output Disabled
Figure 49. LO to IF Feedthrough at Mixer Output Without Filtering
24
0
23
–5
21
SSB NOISE FIGURE (dB)
RF TO IF FEEDTHROUGH (dBc)
22
–10
–15
–20
–25
–30
–35
–40
20
OPTIMIZED FOR
HIGH LINEARITY
19
18
17
16
15
NOISE FIGURE
OPTIMIZED
14
13
–45
12
–50
1600
2000
2400
2800
3200
RF FREQUENCY (MHz)
Figure 50. RF to IF Feedthrough at Mixer Output Without Filtering;
Mixer Input Power = 0 dBm
0
LO TO RF FEEDTHROUGH (dBm)
–20
–30
–40
–50
EXTERNAL LO
–70
INTERNAL LO
–80
–90
600
850
1100 1350 1600 1850 2100 2350 2600 2850
LO FREQUENCY (MHz)
11489-148
–100
–110
350
1000
1400
1800
2200
2600
RF FREQUENCY (MHz)
Figure 53. SSB Noise Figure vs. RF Frequency (see Table 16)
–10
–60
10
600
Figure 51. LO to RF Feedthrough; PLO = 0 dBm
Rev. 0 | Page 19 of 52
11489-150
1200
11489-147
11
–55
800
ADRF6620
Data Sheet
IF DGA
GAIN = 7dB
GAIN = 3dB
TA = +85°C
100
150
200
TA = +25°C
250
300
TA = –40°C
350
400
450
500
IF FREQUENCY (MHz)
0.1
0
–0.1
–0.2
–0.3
–0.4
3
4
20
18
18
16
16
14
14
12
12
OP1dB (dB)
5
6
7
8
9
10
11
12
13
14
15
–0.5
10
8
10
8
6
4
TA = +85°C
TA = +25°C
TA = –40°C
100
150
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
TA = +85°C
TA = +25°C
TA = –40°C
2
0
11489-152
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GAIN (dB)
Figure 55. DGA OP1dB vs. Frequency and Temperature; Maximum Gain
11489-155
4
Figure 58. DGA OP1dB vs. Gain Setting and Temperature
70
65
60
OIP2 (dBm)
OIP2 (dBm)
OIP2 (dBm), OIP3 (dBm)
55
OIP3 (dBm)
50
45
40
OIP3 (dBm)
35
30
25
20
15
10
TA = +85°C
TA = +25°C
TA = –40°C
150
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
11489-153
100
TA = +85°C
TA = +25°C
TA = –40°C
5
Figure 56. DGA OIP2/OIP3 vs. IF Frequency and Temperature;
Maximum Gain
0
3
4
5
6
7
8
9
10
11
12
13
14
15
GAIN (dB)
Figure 59. DGA OIP2/OIP3 vs. Gain Setting and Temperature
Rev. 0 | Page 20 of 52
11489-156
OP1dB (dB)
0.2
GAIN (dB)
6
OIP2 (dBm), OIP3 (dBm)
0.3
20
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
50
0.4
Figure 57. DGA Gain and Gain Step Error vs. Gain Setting and Temperature
Figure 54. DGA Gain vs. IF Frequency and Temperature
0
50
0.5
TA = –40°C
TA = +25°C
TA = +85°C
GAIN STEP ERROR (dB)
GAIN = 11dB
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
11489-259
GAIN = 15dB
GAIN (dB)
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
50
11489-151
GAIN (dB)
VCCx = 5 V, TA = 25°C, RS = RL = 150 Ω, IF = 200 MHz, 2 V p-p differential output, unless otherwise noted. All losses from input and
output traces and baluns are de-embedded from results.
Data Sheet
ADRF6620
–60
–20
–70
–20
–80
–30
–80
–30
–50
–110
–60
–120
–70
–80
–130
–80
–90
–140
–90
–50
–110
–60
–120
–70
–130
–140
200
250
300
350
400
450
IF FREQUENCY (MHz)
–150
3
8
9
10
11
12
13
–100
15
14
OIP2 (dBm)
65
60
–90
–40
–100
–50
–110
–60
–120
–70
–130
–80
–140
–90
55
OIP2 (dBm), OIP3 (dBm)
–30
HD3 (dBc)
–20
–80
1
2
3
4
5
6
7
8
45
40
OIP3 (dBm)
35
30
25
20
GAIN = 15dB
GAIN = 11dB
GAIN = 7dB
GAIN = 3dB
10
5
0
–7
11489-158
–7 –6 –5 –4 –3 –2 –1 0
50
15
–100
–150
9 10
POUT (dBm)
–6
–5
–4
–3
–5
–1
0
1
2
3
4
5
POUT (dBm)
Figure 61. DGA HD2/HD3 vs. Output Power (POUT) and Gain Setting
Figure 64. DGA OIP2/OIP3 vs. Output Power (POUT) and Gain Setting
0
0
TA = +85°C
TA = +25°C
TA = –40°C
TA = +85°C
TA = +25°C
TA = –40°C
–10
–20
–40
–50
IMD2 (dBc)
–60
–70
–80
–30
–40
–50
–70
–80
IMD3 (dBc)
–90
–90
–100
–100
50
100
150
IMD2 (dBc)
–60
200
250
300
350
400
450
500
IF FREQUENCY (MHz)
Figure 62. DGA IMD2/IMD3 vs. IF Frequency and Temperature;
Maximum Gain
IMD3 (dBc)
3
4
5
6
7
8
9
10
11
12
13
GAIN (dB)
Figure 65. DGA IMD2/IMD3 vs. Gain Setting
Rev. 0 | Page 21 of 52
14
15
11489-162
IMD2 (dBc), IMD3 (dBc)
–20
–30
11489-159
IMD2 (dBc), IMD3 (dBc)
7
70
–10
–70
–10
6
Figure 63. DGA HD2/HD3 vs. Gain Setting and Temperature
0
GAIN = 15dB
GAIN = 11dB
GAIN = 7dB
GAIN = 3dB
–60
5
GAIN (dB)
Figure 60. DGA HD2/HD3 vs. IF Frequency and Temperature; Maximum Gain
–50
4
11489-161
150
11489-157
100
–100
500
HD2 (dBc)
–40
–40
HD3 (dBc)
–90
–100
–90
–100
50
–10
HD3 (dBc)
–10
–70
–150
HD2 (dBc)
0
TA = +85°C
TA = +25°C
TA = –40°C
11489-160
TA = +85°C
TA = +25°C
TA = –40°C
–60
HD2 (dBc)
–50
0
–50
ADRF6620
Data Sheet
SPURIOUS PERFORMANCE
(N × fRF) − (M × fLO) spur measurements were made using the standard evaluation board. Mixer spurious products were measured in decibels
(dB) relative to the carrier (dBc) from the IF output power level. Data is shown for all spurious components greater than −115 dBc and
frequencies of less than 3 GHz.
915 MHz Performance
VCCx = 5 V, TA = 25°C, RF power = 0 dBm, internal LO, fRF = 914 MHz, fLO = 1114 MHz
M
0
N
0
1
2
3
4
5
6
−43
−72
−102
1
−34
0
−60
−73
−102
2
−35
−52
−72
−103
<−115
<−115
3
4
5
6
−16
−67
−78
<−115
−105
<−115
−74
<−115
<−115
<−115
<−115
−80
<−115
<−115
<−115
<−115
<−115
1910 MHz Performance
VCCx = 5 V, TA = 25°C, RF power = 0 dBm, internal LO, fRF = 1910 MHz, fLO = 2110 MHz.
M
0
N
0
1
2
3
4
5
6
1
−38.208
−0.001
−59.208
−40.462
2
−50.9
−69.655
−106.741
3
4
−62.35
−74.322
<−115
<−115
−106.429
<−115
<−115
5
6
<−115
−110.954
<−115
<−115
2140 MHz Performance
VCCx = 5 V, TA = 25°C, RF power = 0 dBm, internal LO, fRF = 2140 MHz, fLO = 2340 MHz.
M
0
N
0
1
2
3
4
5
6
−36
1
−40
0
−58
2
−45
−67
<−115
3
−59
−74
<−115
Rev. 0 | Page 22 of 52
4
<−115
<−115
<−115
5
6
<−115
<−115
<−115
<−115
<−115
Data Sheet
ADRF6620
2700 MHz Performance
VCCx = 5 V, TA = 25°C, RF power = 0 dBm, internal LO, fRF = 2700 MHz, fLO = 2500 MHz.
M
0
N
0
1
2
3
4
5
6
−40.126
1
−38.613
−0.001
−58.299
2
−43.84
−67.06
3
−62.116
−73.603
Rev. 0 | Page 23 of 52
4
<−115
<−115
5
<−115
<−115
6
<−115
<−115
ADRF6620
Data Sheet
THEORY OF OPERATION
The ADRF6620 integrates the essential elements of a multichannel loopback receiver that is typically used in digital
predistortion systems. The main features of the ADRF6620
include a single-pole four throw (SP4T) RF input switch with
tunable balun, variable attenuation, a wideband active mixer,
and digitally programmable variable gain amplifier (DGA).
In addition, the ADRF6620 integrates a local oscillator (LO)
generation block consisting of a synthesizer and a multicore
voltage controlled oscillator (VCO) with an octave range and
low phase noise. The synthesizer uses a fractional-N phase-locked
loop (PLL) to enable continuous LO coverage from 350 MHz to
2850 MHz.
Putting all the building blocks of the ADRF6620 together,
the signal path through the device starts at the RF input, where
one of four single-ended RF inputs is selected by the input mux
and converted to a differential signal via a tunable balun. The
differential RF signal is attenuated to an optimal input level via
the digital step attenuator with 15 dB of attenuation range in steps
of 1 dB. The RF signal is then mixed via a Gilbert cell mixer with
the LO signal down to an IF frequency. The 255 Ω terminated
differential output of the mixer is brought off chip to a pair of
inductors and passed through an IF filter. The output of the IF
filter is ac-coupled off chip and fed to an on-chip digital attenuator
and IF DGA. The output of the IF DGA is then passed to an
off-chip analog-to-digital converter (ADC).
100 ns. When serial port control is used, the switch time is 100 ns,
plus the latency of the SPI programming.
The RFSW_MUX bit (Register 0x23, Bit 11) selects whether the
RF input switch is controlled via the external pins or the SPI port.
By default at power-up, the device is configured for serial control.
Writing to the RFSW_SEL bits (Register 0x23, Bits[10:9]) allows
selection of one of the four RF inputs. Alternatively, by setting
the RFSW_MUX bit high, the RFSW0 and RFSW1 pins can be
used to select the RF input. Table 10 summarizes the different
control options for the RF inputs.
To maintain good channel-to-channel isolation, ensure that unused
RF inputs are properly terminated. The RFINx ports are internally
terminated with 50 Ω resistors and have a dc bias level of 2.5 V.
To avoid disrupting the dc level, the recommended termination
is a dc blocking capacitor to GND. Figure 66 shows the recommended configuration when only RFIN0 is used, and the other
RF input ports are properly terminated.
RFIN0 35
50Ω
RFIN1
32
0.1µF
50Ω
RFIN2
29
0.1µF
The ADRF6620 integrates a SP4T switch where one of four RF
inputs is selected. The desired RF input can be selected using
either pin control or register writes via the SPI. Compared to the
serial write approach, pin control allows faster control over the
switch. When the RFSW0 pin (Pin 38) and the RFSW1 pin
(Pin 39) are used, the RF switches can switch at speeds of up to
50Ω
RFIN3
26
0.1µF
50Ω
11489-168
RF INPUT SWITCHES
Figure 66. Terminating Unused RF Input Ports
Table 10. RF Input Selection Table
RFSW_MUX (Register Address 0x23[11])
Bit 11
0
0
0
0
1
1
1
1
1
SPI Control, RFSW_SEL
(Register Address 0x23[10:9])
Bit 10
Bit 9
0
0
0
1
1
0
1
1
X1
X1
X1
X1
X1
X1
X1
X1
X = don’t care.
Rev. 0 | Page 24 of 52
Pin Control
RFSW1, Pin 39
RFSW0, Pin 38
X1
X1
1
X
X1
1
X
X1
X1
X1
0
0
0
1
1
0
1
1
RF Input
RFIN0
RFIN1
RFIN2
RFIN3
RFIN0
RFIN1
RFIN2
RFIN3
Data Sheet
ADRF6620
TUNABLE BALUN
+5V
9
IFIN+
RS
RIN
gm
AMP
ROUT
8
11
10
LOGIC
IFOUT1–
IFOUT1+
IFOUT2–
IFOUT2+
REF
RL
Figure 68. Simplified IF DGA Schematic
An independent internal voltage reference circuit sets the dc
voltage level at the input of the amplifier to approximately 1.5 V.
This reference is not accessible and cannot be adjusted.
11489-040
BAL_COUT
REG 0x30[7:5]
15
ATTENUATOR
IFIN–
RFINx
BAL_CIN
REG 0x30[3:1]
16
11489-041
The ADRF6620 integrates a programmable balun operating over
a frequency range from 700 MHz to 2700 MHz. The tunable
balun offers the benefit of ease of drivability from a single-ended
50 Ω RF input, and the single-ended-to-differential conversion
of the balun optimizes common-mode rejection.
Figure 67. Integrated Tunable Balun
The RF balun is tuned by switching parallel capacitances on the
primary and secondary sides by writing to Register 0x30. The
added capacitance, in parallel with the inductive windings of the
balun, changes the resonant frequency of the inductive capacitive
(LC) tank. Therefore, selecting the proper combination of BAL_
CIN (Register 0x30, Bits[3:1]) and BAL_COUT (Register 0x30,
Bits[7:5]) sets the desired frequency and minimizes the insertion
loss of the balun. Under most circumstances, the input and output
can be tuned together; however, sometimes for matching reasons,
it may be advantageous to tune them separately. See the RF Input
Balun Insertion Loss Optimization section for the recommended
BAL_CIN and BAL_COUT settings.
The IF DGA consumes 35 mA through the VCC2 pin (Pin 12)
and 75 mA through the two output choke inductors. The IF
DGA can be powered down by disabling the IF_AMP_EN bit
(Register 0x01, Bit 11). In its power-down state, the IF DGA
current reduces to 6 mA. The dc bias level at the input remains
at approximately 1.5 V when the DGA is disabled.
At minimum attenuation, the gain of the IF DGA is 15 dB when
driving a 150 Ω load. The source and load resistance of the
amplifier is set to 150 Ω in a matched condition. If the load or
the source resistance is not equal to 150 Ω, the following equations
can be used to determine the resulting gain and input/output
resistances.
RF DIGITAL STEP ATTENUATOR (DSA)
Voltage Gain = AV = 0.044 × (1000||RL)
The RF DSA follows the tunable balun. The attenuation range is
0 dB to 15 dB with a step size of 1 dB. DSA attenuation is set using
the RFDSA_SEL bits (Register 0x23, Bits[8:5]).
RIN = (1000 + RL)/(1 + 0.044 × RL)
ACTIVE MIXER
The double balanced mixer uses high performance SiGe NPN
transistors. This mixer is based on the Gilbert cell design of four
cross-connected transistors.
The mixer output has a 255 Ω differential output resistance.
Bias the mixer outputs using either a pair of supply referenced
RF chokes or an output transformer with the center tap connected
to the positive supply.
DIGITALLY PROGRAMMABLE VARIABLE GAIN
AMPLIFIER (DGA)
The ADRF6620 integrates a differential IF DGA consisting of a
150 Ω digitally controlled passive attenuator followed by a highly
linear transconductance amplifier with feedback. The attenuation
range is 12 dB, and the transconductor amplifier has a fixed gain
of 15 dB. Therefore, at minimum attenuation, the gain of the IF
DGA is 15 dB; at maximum attenuation, the gain is 3 dB. The
attenuation is controlled by addressing the IF_ATTN bits in
Register 0x23, Bits[4:0]. The attenuation step size is 0.5 dB.
S21 (Gain) = 2 × RIN/(RIN + RS) × AV
ROUT = (1000 + RS)/(1 + 0.044 × RS)
The dc current to the outputs of each amplifier is supplied
through two external choke inductors. The inductance of the
chokes and the resistance of the load, in parallel with the output
resistance of the device, add a low frequency pole to the response.
The parasitic capacitance of the chokes adds to the output capacitance of the part. This total capacitance, in parallel with the
load and output resistance, sets the high frequency pole of the
device. In general, the larger the inductance of the choke, the
higher the parasitic capacitance. Therefore, this trade-off must be
considered when the value and type of the choke are selected.
For each polarity, the amplifier has two output pins that are
oriented in an alternating fashion: IFOUT1+ (Pin 8), IFOUT1−
(Pin 9), IFOUT2+ (Pin 10), and IFOUT2− (Pin 11). When
designing the board, minimize the parasitic capacitance caused
by routing the corresponding outputs together. See the Layout
section for the recommended printed circuit board (PCB)
layout.
Rev. 0 | Page 25 of 52
ADRF6620
Data Sheet
LO GENERATION BLOCK
Internal LO Mode
The ADRF6620 offers two modes for sourcing the LO signal to
the mixer. The first mode uses the on-chip PLL and VCO. This
mode of operation provides a high quality LO that meets the
performance requirements of most applications. Using the onchip synthesizer and VCO removes the burden of generating
and distributing a high frequency LO signal.
The ADRF6620 includes an on-chip VCO and PLL for LO
synthesis. The PLL, shown in Figure 69, consists of a reference
input, phase and frequency detector (PFD), charge pump, and a
programmable integer divider with prescaler. The reference path
takes in a reference clock and divides it down by a factor of 1, 2, 4,
or 8 or multiplies it by a factor of 2 before passing it to the PFD.
The PFD compares this signal to the divided down signal from the
VCO. Depending on the PFD polarity selected, the PFD sends an
up/down signal to the charge pump if the VCO signal is slow/fast
compared to the reference frequency. The charge pump sends
a current pulse to the off-chip loop filter to increase or decrease
the tuning voltage (VTUNE).
The second mode bypasses the integrated LO generation block
and allows the LO to be supplied externally. This second mode
can provide a very high quality signal directly to the mixer core.
Sourcing the LO signal externally may be necessary in demanding
applications that require the lowest possible phase noise
performance.
The ADRF6620 integrates three VCO cores that cover an octave
range from 2.8 GHz to 5.7 GHz. Table 11 summarizes the frequency range for each VCO. The desired VCO can be selected
by addressing the VCO_SEL bits (Register 0x22, Bits[2:0]).
External LO Mode
External or internal LO mode can be selected via the VCO_SEL
bits (Register 0x22, Bits[2:0]). To configure for external LO mode,
set Register 0x22, Bits[2:0] to 011 and apply the differential LO
signals to Pin 44 (LOIN−) and Pin 45 (LOIN+). The external LO
frequency range is 350 MHz to 3.2 GHz. The ADRF6620 offers the
flexibility of using a higher LO frequency signal and dividing it
down before it drives the mixer. The LO divider can be found in
the LO_DIV_A bits (Register 0x22, Bits[4:3]), where options
include ÷1, ÷2, ÷4, or ÷8.
VCO_SEL (Register 0x22, Bits[2:0])
000
001
010
011
The external LO input pins present a broadband differential 50 Ω
input impedance. The LOIN+ and LOIN− input pins must be
ac-coupled. When not in use, LOIN+ and LOIN− can be left
unconnected.
The N-divider divides down the differential VCO signal to the PFD
frequency. The N-divider can be configured for fractional mode or
integer mode by addressing the DIV_MODE bit (Register 0x02,
Bit 11). The default configuration is set for fractional mode.
Table 11. VCO Range
Frequency Range (GHz)
5.2 to 5.7
4.1 to 5.2
2.8 to 4.1
External LO
VCO_SEL
REG 0x22[2:0]
REFSEL
REG 0x21[2:0]
LOIN+
÷8
÷4
÷2
PFD_POLARITY
REG 0x21[3]
PFD
+
CP
CHARGE
PUMP
LO_DIV_A
REG 0x22[4:3]
LOIN–
÷1, ÷2,
÷4, ÷8
VTUNE
LOOUT+ TO MIXER
LOOUT– TO MIXER
LPF
×1
×2
CP_CTRL
REG 0x20[13:0]
N = INT +
FRAC
MOD
DIV_MODE: REG 0x02[11]
INT_DIV: REG 0x02[10:0]
FRAC_DIV: REG 0x03[10:0]
MOD_DIV: REG 0x04[10:0]
Figure 69. LO Generation Block Diagram
Rev. 0 | Page 26 of 52
÷2
11489-042
REFIN
EXTERNAL
LOOP
FILTER
Data Sheet
ADRF6620
The following equations can be used to determine the N value and
PLL frequency:
f PFD =
f LO =
Additional LO Controls
f VCO
2× N
N = INT +
FRAC
MOD
f PFD × 2 × N
LO_DIVIDER
where:
fPFD is the phase frequency detector frequency.
fVCO is the voltage controlled oscillator frequency.
N is the fractional divide ratio (INT + FRAC/MOD)
INT is the integer divide ratio programmed in Register 0x02.
FRAC is the fractional divider programmed in Register 0x03.
MOD is the modulus divide ratio programmed in Register 0x04.
fLO is the LO frequency going to the mixer core when the loop is
locked.
LO_DIVIDER is the final divider block that divides the VCO
frequency down by 1, 2, 4, or 8 before it reaches the mixer
(see Table 12). This control is located in the LO_DIV_A bits
(Register 0x22, Bits[4:3]).
Table 12. LO Divider
LO_DIV_A (Register 0x22, Bits[4:3])
00
01
10
11
captures these effects. In general, higher bandwidth loops tend
to lock more quickly than lower bandwidth loops.
To access the LO signal going to the mixer core through the
LOOUT+ and LOOUT− pins (Pin 21 and Pin 22), enable the
LO_DRV_EN bit in Register 0x01, Bit 7. This setting offers direct
monitoring of the LO signal to the mixer for debug purposes; or the
LO signal can be used to daisy-chain many devices synchronously.
One ADRF6620 can serve as the master where the LO signal is
sourced, and the subsequent slave devices share the same LO signal
from the master. This flexibility substantially eases the LO requirements of a system with multiple LOs.
The LO output drive level is controlled by the LO_DRV_LVL
bits (Register 0x22, Bits[8:7]). Table 13 shows the available drive
levels.
Table 13. LO Drive Level
LO_DRV_LVL (Register 0x22, Bits[8:7])
00
01
10
11
Amplitude (dBm)
−4
0.5
3
4.5
SERIAL PORT INTERFACE (SPI)
The SPI port of the ADRF6620 allows the user to configure the
device through a structured register space provided inside the
chip. Registers are accessed via the serial port interface and can
be written to or read from via the serial port interface.
LO_DIVIDER
1
2
4
8
The lock detect signal is available as one of the selectable outputs
through the MUXOUT pin; a logic high indicates that the loop
is locked. The MUXOUT pin is controlled by the REF_MUX_SEL
bits (Register 0x21, Bits[6:4]); the PLL lock detect signal is the
default configuration.
To ensure that the PLL locks to the desired frequency, follow the
proper write sequence of the PLL registers. The PLL registers must
be configured accordingly to achieve the desired frequency, and the
last writes must be to Register 0x02 (INT_DIV), Register 0x03
(FRAC_DIV), or Register 0x04 (MOD_DIV). When one of these
registers is programmed, an internal VCO calibration is initiated,
which is the last step in locking the PLL.
The time it takes to lock the PLL after the last register is written
can be broken down into two parts: VCO band calibration and
loop settling.
After the last register is written, the PLL automatically performs
a VCO band calibration to choose the correct VCO band. This
calibration takes approximately 5120 PFD cycles. For a 40 MHz
fPFD, this corresponds to 128 µs. After calibration is complete, the
feedback action of the PLL causes the VCO to eventually lock to
the correct frequency. The speed with which this locking occurs
depends on the nonlinear cycle-slipping behavior, as well as the
small-signal settling of the loop. For an accurate estimation of
the lock time, download the ADIsimPLL tool, which correctly
The serial port interface consists of three control lines: SCLK,
SDIO, and CS. SCLK (serial clock) is the serial shift clock. The
SCLK signal clocks data on its rising edge. SDIO (serial data
input/output) is an input or output depending on the instruction
being sent and the relative position in the timing frame. CS
(chip select bar) is an active low control that gates the read and
write cycles. The falling edge of CS, in conjunction with the rising
edge of SCLK, determines the start of the frame. All SCLK and
SDIO activity is ignored when CS is high. Table 6 and Figure 2
show the serial timing and its definitions.
The ADRF6620 protocol consists of seven register address bits,
followed by a read/write indicator and 16 data bits. Both the
address and data fields are organized from MSB to LSB.
On a write cycle, up to 16 bits of serial write data are shifted in,
MSB to LSB. If the rising edge of CS occurs before the LSB of
the serial data is latched, only the bits that were clocked in are
written to the device. If more than 16 data bits are shifted in,
the 16 most recent bits are written to the device. The ADRF6620
input logic level for the write cycle supports a logic level as low
as 1.8 V.
On a read cycle, up to 16 bits of serial read data are shifted out,
MSB to LSB. Data shifted out beyond 16 bits is undefined. It is
not necessary for readback content at a given register address to
correspond with the write data of the same address. The output
logic level for a read cycle is 2.5 V.
Rev. 0 | Page 27 of 52
ADRF6620
Data Sheet
BASIC CONNECTIONS
+5V
DNP 0.1µF
(0402)
4
RFSW1
RFSW0
RFIN0
RFIN2
RFIN3
100pF
(0402)
REF_IN
RFIN3
REFIN
11
10
29
21
26
6
49.9Ω
(0402)
MUXOUT
MUXOUT
0Ω
(0402)
43
EXPOSED
PADDLE
LOIN+
LOIN–
÷8
÷4
÷2
×1
×2
PFD CHARGE
PUMP
+
CP
22
÷1, ÷2,
÷4, ÷8
VTUNE
FRAC
N = INT +
MOD
÷2
LOCK_DET
VPTAT
44
LDO
VCO
LDO
LO
LDO
2.5V
46
37
7
LDO
3.3V
47
3
24
14
13
VCC5
1
12
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
100pF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
0.1µF
(0402)
10µF
(0603)
3
4
IFOUT2+
LOOUT+
100pF
(0402)
LOOUT–
LOIN+
DNP
TC1-1-43A+
3
4
1
LOOUT
6
100pF
(0402)
TC1-1-43A+
3
4
LOIN–
1
VTUNE
100pF
(0402)
CP
22pF
(0402)
LOIN
6
10kΩ
(0402)
3kΩ
(0402)
10kΩ
(0402)
6.8pF
(0402)
OPEN
(0402)
VTUNE_TP
OPEN
22pF
(0402)
2.7nF
(0603)
100pF
(0402)
0.1µF
(0402)
100pF
(0402)
0.1µF
(0402)
0.1µF
(0402)
10µF
(0603)
10µF
(0603)
100pF
(0402)
11489-043
10µF
(0603)
6
2
100pF
0Ω
(0402) (0402)
IFOUT2–
2
100pF
(0402)
+5V
RED
LOIN
100pF
(0402)
45
TCM3-1T+
0.1µF
(0402) 1
DNP
IFOUT1+
DECL1
100pF
(0402)
32
DECL2
RFIN2
8
RFIN1
1µH
100pF
0Ω
(0402) (0402)
9 IFOUT1–
DECL3
RFIN1
100pF
(0402)
1µH
35
DECL4
100pF
(0402)
+5V
42 41 40
SPI
INTERFACE
VCC1
RFIN0
18 19 15 16
ADRF6620
38
VCC2
S1
17 20 23 25 27 28 30 31 33 34 36 48
VCC3
100pF
(0402)
5
CSB
SCLK
SDIO
39
VCC4
10kΩ S2
(0402)
SDIO
10kΩ
(0402)
3.3V
MXOUT–
MXOUT+
GND
3.3V
CS
39nH
(0402)
IFIN+
0.1µF
(0402)
IFIN–
DNP
39nH
(0402)
SCLK
470nH
(0603)
470nH
(0603)
Figure 70. Basic Connection Diagram
Table 14. Basic Connections
Pin No.
5 V Power
1
12
13
14
24
PLL/VCO
3
Mnemonic
Description
Basic Connection
VCC1
VCC2
VCC3
VCC4
VCC5
LO, VCO, mixer power supply
IF DGA power supply
Factory calibration pin
Factory calibration pin
RF front-end power supply
Decouple all power supply pins to ground using 100 pF and 0.1 µF
capacitors. Place the decoupling capacitors close to the pins.
CP
Synthesizer charge pump
output
Synthesizer reference
frequency input
Connect this pin to the VTUNE pin through the loop filter.
6
REFIN
21, 22
LOOUT+, LOOUT−
Differential LO outputs
The nominal input level of this pin is 1 V p-p. The input range is
12 MHz to 464 MHz. This pin is internally biased and must be accoupled and terminated externally with a 50 Ω resistor. Place
the ac coupling capacitor between the pin and the resistor.
When driven from an 50 Ω RF signal generator, the recommended
input level is 4 dBm.
The differential output impedance of these pins is 50 Ω. The pins
Rev. 0 | Page 28 of 52
Data Sheet
Pin No.
ADRF6620
Mnemonic
Description
44, 45
LOIN−, LOIN+
Differential LO inputs
43
MUXOUT
PLL multiplex output
47
VTUNE
VCO tuning voltage
RFIN3, RFIN2
RFIN1, RFIN0
RF inputs
RFSW0, RFSW1
Pin control of the RF inputs
IFOUT1+, IFOUT1−,
IFOUT2+, IFOUT2−
IF DGA outputs
IFIN−, IFIN+
IF DGA inputs
MXOUT+, MXOUT−
Differential mixer outputs
The output stage of the mixer is an open collector configuration
that requires a dc bias of 5 V. Use bias choke inductors to achieve
this configuration. Carefully choose the bias choke inductors
such that they can handle a maximum current of 50 mA on each
side. The differential output impedance of the mixer is 255 Ω.
CS
SCLK
SDIO
SPI chip select
SPI clock
SPI data input and output
Active low. 3.3 V logic levels.
3.3 V tolerant logic levels.
3.3 V tolerant logic levels.
DECL1
DECL2
DECL3
DECL4
3.3 V LDO decoupling
2.5 V LDO decoupling
LO LDO decoupling
VCO LDO decoupling
Decouple all DECLx pins to ground using 100 pF, 0.1 µF, and 10 µF
capacitors. Place the decoupling capacitors close to the pin.
GND
Ground
Connect these pins to the GND of the PCB.
Exposed pad (EPAD)
The exposed thermal pad is on the bottom of the package.
The exposed pad must be soldered to ground.
RF Inputs
26, 29, 32, 35
38, 39
IF DGA
8, 9, 10, 11
15, 16
Mixer Outputs
18, 19
Serial Port Interface
40
41
42
LDO Decoupling
2
7
37
46
GND
4, 5, 17, 20, 23, 25,
27, 28, 30, 31, 33,
34, 36, 48
49 (EPAD)
Basic Connection
are internally biased to 2.5 V and must be ac-coupled.
The differential input impedance of these pins is 50 Ω. The pins
are internally biased to 2.5 V and must be ac-coupled.
This output pin provides the PLL reference signal or the PLL lock
detect signal.
This pin is driven by the output of the loop filter; its nominal
input voltage range is 1.5 V to 2.5 V.
The single-ended RF inputs have a 50 Ω input impedance and
are internally biased to 2.5 V. These pins must be ac-coupled.
Terminate unused RF inputs with a dc blocking capacitor to
GND to improve isolation. Refer to the Layout section for the
recommended PCB layout for optimized channel-to-channel
isolation.
See Table 10 for the pin settings for RF input pin control. For
logic high, connect these pins to 2.5 V logic.
The differential IF DGA outputs have two output pins for each
polarity. They are oriented in alternating fashion: IFOUT1+ (Pin 8),
IFOUT1− (Pin 9), IFOUT2+ (Pin 10), and IFOUT2− (Pin 11).
Connect the positive pins such that IFOUT1+ and IFOUT2+ are
tied together. Similarly, connect the negative pins such that
IFOUT1− and IFOUT2− are tied together. Refer to the Layout
section for a recommended layout that minimizes parasitic
capacitance and optimizes on performance.
The output stage of the IF DAG is an open-collector configuration
that requires a dc bias of 5 V. Use bias choke inductors to
achieve this configuration. Choose the bias choke inductors
such that they can handle a maximum current of 50 mA on
each side. By design, the IF DGA is optimized for linearity when
the source and load are terminated with 150 Ω.
AC couple the mixer outputs to the IF DGA inputs. See the
Interstage Filtering Requirements section for the recommended
filter designs.
Rev. 0 | Page 29 of 52
ADRF6620
Data Sheet
RF INPUT BALUN INSERTION LOSS OPTIMIZATION
As shown in Figure 71 to Figure 74, the gain of the ADRF6620
mixer has been characterized for every combination of BAL_CIN
and BAL_COUT (Register 0x30). As shown, a range of BAL_CIN
and BAL_COUT values can be used to optimize the gain of the
ADRF6620. The optimized values do not change with temperature.
After the values are chosen, the absolute gain changes over temperature; however, the signature of the BAL_CIN and BAL_COUT
values is fixed.
0
At lower input frequencies, more capacitance is needed. This
increase is achieved by programming higher codes into BAL_CIN
and BAL_COUT. At high frequencies, less capacitance is required;
therefore, lower BAL_CIN and BAL_COUT codes are appropriate.
Table 16 provides a list of recomended BAL_CIN and BAL_COUT
codes for popular radio frequencies. Use Figure 71 to Figure 74
and Table 16 only as guides; do not interpret them in the absolute
sense because every application and PCB design varies. Additional fine-tuning may be necessary to achieve the maximum gain.
0
–40°C
+25°C
+85°C
–1
–2
–3
–2
–4
GAIN (dB)
GAIN (dB)
–40°C
+25°C
+85°C
–1
–3
–5
–6
–4
–7
–8
–5
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 BAL_CIN
BAL_COUT
0
1
2
3
4
5
6
7
BAL_CIN/BAL_COUT
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 BAL_CIN
BAL_COUT
0
1
2
3
4
5
6
7
BAL_CIN/BAL_COUT
Figure 71. Gain vs. BAL_CIN and BAL_COUT at RF = 900 MHz
0
11489-045
–6
11489-044
–9
–10
Figure 73. Gain vs. BAL_CIN and BAL_COUT at RF = 1900 MHz
0
–40°C
+25°C
+85°C
–2
–40°C
+25°C
+85°C
–2
–4
GAIN (dB)
–6
–6
–8
–8
–10
–12
–14
–10
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 BAL_CIN
BAL_COUT
0
1
2
3
4
5
6
7
BAL_CIN/BAL_COUT
–18
Figure 72. Gain vs. BAL_CIN and BAL_COUT at RF = 2100 MHz
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 BAL_CIN
BAL_COUT
0
1
2
3
4
5
6
7
BAL_CIN/BAL_COUT
Figure 74. Gain vs. BAL_CIN and BAL_COUT at RF = 2700 MHz
Rev. 0 | Page 30 of 52
11489-047
–16
–12
11489-046
GAIN (dB)
–4
Data Sheet
ADRF6620
IP3 AND NOISE FIGURE OPTIMIZATION
The ADRF6620 can be configured for either improved performance or reduced power consumption. In applications where
performance is critical, the ADRF6620 offers IP3 or noise figure
optimization. However, if power consumption is the priority, the
mixer bias current can be reduced to save on the overall power
at the expense of degraded performance. Whatever the application
specific needs are, the ADRF6620 offers configurability that
balances performance and power consumption.
Adjustments to the mixer bias setting have the most impact on
performance and power. For this reason, mixer bias should be
the first adjustment. The active mixer core of the ADRF6620 is a
linearized transconductor. With increased bias current, the
transconductor becomes more linear, resulting in higher IP3.
The improved IP3, however, is at the expense of degraded noise
figure and increased power consumption (see Figure 75). For a
1-bit change of the mixer bias (MIXER_BIAS, Register 0x31,
Bits[11:9]), the current increases by 7.71 mA.
Inevitably, there is a limit on how much the bias current can
increase before the improvement in linearity no longer justifies the
increase in power and noise. The mixer core reaches a saturation
point where further increases in bias current do not translate to
improved performance. When that point is reached, it is best to
decrease the bias current to a level where the desired performance
is achieved. Depending on the system specifications of the customer, a balance between linearity, noise figure, and power can
be attained.
In addition to bias optimization, the ADRF6620 also has
configurable distortion cancellation circuitry. The linearized
transconductor input of the ADRF6620 is made up of a main path
and a secondary path. Through adjustments of the amplitude and
phase of the secondary path, the distortion generated by the main
path can be canceled, resulting in improved IPd3 performance.
The amplitude and phase adjustments are located in the following
serial interface bits: MIXER_RDAC (Register 0x31, Bits[8:5])
and MIXER_CDAC (Register 0x31, Bits[4:0]).
220
RF FREQ:
900MHz
1900MHz
210
2100MHz
2600MHz
205
215
200
190
185
Δ7.71 mA
180
Δ1
175
170
165
160
155
150
0
1
2
3
4
5
6
7
MIXER BIAS
11489-057
ICC (mA)
195
Figure 75. Change in Current Consumption vs. MIXER_BIAS
Rev. 0 | Page 31 of 52
ADRF6620
Data Sheet
Figure 76 to Figure 83 show the IIP3 and noise figure sweeps for
all MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS combinations. The IIP3 vs. MIXER_RDAC and MIXER_CDAC figures
show both a surface and a contour plot in one figure. The contour
plot is located directly underneath the surface plot. The best
approach for reading the figure is to localize the peaks on the
surface plot, which indicate maximum IIP3, and to follow the
same color pattern to the contour plot to determine the optimized
MIXER_RDAC and MIXER_CDAC values. The overall shape
of the IIP3 plot does not vary with the MIXER_BIAS setting;
therefore, only MIXER_BIAS = 011 is displayed.
The data shows that MIXER_BIAS has the largest impact on
performance. As previously mentioned and evident in the data,
IIP3 improves with increased MIXER_BIAS, and noise figure is
optimized at the lowest bias setting. Taking a more detailed look
at the data, the different MIXER_RDAC and MIXER_CDAC
combinations can result in a ~5 dB to +10 dB change in IIP3, but
the noise figure changes by only ~0.5 dB. These trends become
very important in deciding the trade-offs between IP3, noise figure,
and power consumption. The total current consumption of the
ADRF6620 does not change with MIXER_RDAC and MIXER_
CDAC and varies only with the mixer bias settings (see Figure 75).
19.5
40
19.0
18.5
NOISE FIGURE (dB)
30
25
20
0
18.0
17.5
17.0
16.5
16.0
10
15
5
0
10
11489-093
15.5
C
A
D
_C
ER
IX
M
5
15
MIXER_RDAC
15.0
0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15
0
Figure 76. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 900 MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MIXER_RDAC
MIXER_CDAC
11489-062
IIP3 (dBm)
35
MIXER BIAS
900-0
900-6
900-2
900-7
900-4
Figure 78. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 900 MHz
40
22.0
21.5
21.0
20.5
NOISE FIGURE (dB)
30
25
20
15
20.0
19.5
19.0
18.5
18.0
17.5
17.0
AC
RD
R_
XE
16.0
5
15.5
0
0
5
10
15
MIXER_CDAC
11489-094
MI
16.5
10
15.0
Figure 77. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 1900 MHz
MIXER BIAS
1900-0
1900-6
1900-2
1900-7
1900-4
0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MIXER_RDAC
MIXER_CDAC
Figure 79. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 1900 MHz
Rev. 0 | Page 32 of 52
11489-063
IIP3 (dBm)
35
ADRF6620
45
NOISE FIGURE (dB)
35
30
25
20
15
10 C
A
RD
R_
5
5
10
MIXER_CDAC
15
0
MI
XE
11489-060
15
0
0
Figure 80. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 2100 MHz
NOISE FIGURE (dB)
35
30
25
20
AC
RD
_
ER
IX
M
10
5
10
MIXER_CDAC
15
0
11489-061
IIP3 (dBm)
40
15
0
2
3
4
7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15
5
6
7
8
9
10
11
12
13
14
15
MIXER_RDAC
MIXER_CDAC
Figure 82. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 2100 MHz
45
20
1
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0 MIXER BIAS
16.5
2600-0
2600-6
16.0
2600-2
2600-7
15.5
2600-4
15.0 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0
0
1
2
3
4
7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15
5
6
7
8
9
10
11
12
13
14
15
MIXER_RDAC
MIXER_CDAC
Figure 83. Noise Figure vs. MIXER_RDAC, MIXER_CDAC, and
Various MIXER_BIAS Values at RF Frequency = 2700 MHz
Figure 81. IIP3 vs. MIXER_RDAC, MIXER_CDAC; MIXER_BIAS = 011
at RF Frequency = 2700 MHz
Rev. 0 | Page 33 of 52
11489-065
IIP3 (dBm)
40
23.5
23.0
22.5
22.0
21.5
21.0
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5 MIXER BIAS
16.0
2100-6
2100-0
2100-7
2100-2
15.5
2100-4
15.0 0 7 15 0 7 15 0 7 15 0 7 15 0 7 15 0
11489-064
Data Sheet
ADRF6620
Data Sheet
specific MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS
settings are shown in Figure 84.
50
IIP3
45
40
35
30
25
20
15
10
NOISE
FIGURE
5
0
0.6
1.1
IIP3: OPT IIP3
IIP3: OPT NOISE FIGURE
IIP3: IIP3 AND NOISE FIGURE BALANCE
NF: OPT IIP3
NF: OPT NOISE FIGURE
NF: IIP3 AND NOISE FIGURE BALANCE
1.6
2.1
2.6
RF FREQUENCY (GHz)
11489-066
IIP3 (dBm)/NOISE FIGURE (dB)
As an example, the MIXER_RDAC, MIXER_CDAC, and MIXER_
BIAS settings of the ADRF6620 were carefully selected, based on
three individual goals that resulted in three sets of MIXER_RDAC,
MIXER_CDAC, and MIXER_BIAS values. The first goal was for
optimized IIP3. To achieve the most optimal IIP3 performance,
the MIXER_BIAS was set to a higher current setting, and MIXER_
RDAC and MIXER_CDAC were selected at the peaks. This
configuration allowed for the most optimal IIP3 performance.
However, it also consumed the most power, and the noise figure
was degraded. The second goal was to achieve a balance among
IIP3, the noise figure, and power consumption. Finally, the third
goal was for an optimized noise figure. This configuration resulted
in the lowest power consumption while IIP3 was not optimized.
Table 15 summarizes the test conditions; Table 16 shows the corresponding MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS
values. The resulting IIP3 and noise figure performance for the
Figure 84. Example IIP3 and Noise Figure Optimization
Table 15. Mixer Optimization Summary
Parameter
Optimized IIP3
Noise Figure, IIP3, and
Power Consumption
Balance
Optimized Noise Figure
Test Conditions/Comments
MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS were configured for optimized IIP3 performance.
MIXER_BIAS was limited to 0, 1, or 2 decimal for improved noise figure while allowing IIP3 to degrade. MIXER_RDAC and
MIXER_CDAC were chosen for optimized IIP3 because MIXER_RDAC and MIXER_CDAC have a larger impact on IIP3
than on noise figure.
MIXER_BIAS was set to 0 decimal for the best noise figure. MIXER_RDAC and MIXER_CDAC were chosen for optimized
IIP3 because they have a larger impact on IIP3 than on noise figure.
Table 16. Recommended BAL_CIN, BAL_COUT, MIXER_RDAC, MIXER_CDAC, and MIXER_BIAS Settings (in Decimal)
RF Frequency
(MHz)
600
700
800
900
940
1000
1100
1200
1300
1400
1500
1600
1700
1800
1840
1900
2000
2100
2140
2200
2300
2400
2500
2600
2700
2800
2900
3000
BAL_CIN
7
7
5
3
3
2
1
1
0
0
0
0
0
0
0
0
0
1
1
2
2
1
1
1
1
1
1
0
BAL_COUT
7
7
5
4
3
3
2
2
2
2
2
2
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
Optimized IIP3
RDAC
CDAC
BIAS
6
10
4
5
14
4
3
13
3
0
15
0
5
12
4
5
11
4
5
10
4
5
9
4
8
8
4
6
7
4
6
7
4
8
7
4
6
6
4
9
6
4
9
6
5
9
6
5
7
5
5
9
5
5
9
5
4
7
4
4
7
4
4
7
4
4
7
4
4
7
4
4
7
4
4
7
4
4
7
4
4
7
4
4
IIP3 and Noise Figure Balance
RDAC
CDAC
BIAS
4
15
2
4
15
2
3
14
2
3
13
2
5
11
2
4
10
2
3
10
1
3
9
1
3
9
1
4
8
1
5
7
2
5
7
2
5
6
2
5
6
2
5
6
2
6
5
2
3
6
0
5
5
1
5
5
1
5
5
1
5
5
1
5
5
1
5
5
1
5
5
1
5
5
1
4
15
2
4
15
2
3
14
2
Rev. 0 | Page 34 of 52
Optimized Noise Figure
RDAC
CDAC
BIAS
4
15
0
4
15
0
2
15
0
2
14
0
2
13
0
3
11
0
2
11
0
2
10
0
2
10
0
2
9
0
3
8
0
2
8
0
4
7
0
4
7
0
3
7
0
3
7
0
3
6
0
3
6
0
3
6
0
3
6
0
3
6
0
3
6
0
3
6
0
3
6
0
3
6
0
4
15
0
4
15
0
2
15
0
Data Sheet
ADRF6620
INTERSTAGE FILTERING REQUIREMENTS
MXOUT+
L1
RF
19
MXOUT–
15
C2
C1
L4
LO
16
L3
MXOUT+
IFIN+
11489-048
10 IFOUT2+
8
270
7
250
PARALLEL RESISTANCE
6
230
5
4
210
3
Figure 85. Low-Pass IF Filter
When designing the low-pass filter, it is important to consider
the output impedance of the mixer and the input impedance of
the IF DGA. The output impedance of the mixer has both a real
and reactive component, and its equivalent model is shown in
Figure 86. Correspondingly, Figure 87 shows the impedance vs.
frequency for the mixer output.
190
PARALLEL CAPACITANCE
2
170
1
0
100
200
300
400 500 600 700
FREQUENCY (MHz)
800
900
150
1000
11489-050
0
PARALLEL RESISTANCE (Ω)
290
9
Figure 87. Mixer Output Impedance vs. Frequency
Likewise, Figure 88 shows the impedance vs. frequency for the
IF DGA. The four-port S parameter files for the IF DGA and
mixer are available on analog.com and can serve as a useful tool
to accurately capture the input and output impedance when
designing the interstage filter. As a first-order approximation
at low frequencies, the mixer output has a fixed impedance of
approximately 255 Ω, and the input impedance of the IF DAG is
approximately 150 Ω. Therefore, design the low-pass filter to
have an input impedance of 255 Ω and an output impedance of
150 Ω.
IFIN–
11 IFOUT2–
11489-049
10
16
500
OUTPUT CAPACITANCE
INPUT CAPACITANCE
450
OUTPUT RESISTANCE
INPUT RESISTANCE
400
14
350
12
300
18
IFOUT1+
1.1pF
MXOUT–
20
0.1µF
+
Figure 86. Equivalent Model of the Mixer Output Impedance
0.1µF
9 IFOUT1–
8
90Ω
82.5Ω
PARALLEL CAPACITANCE (pF)
18
L2
+
10
Rev. 0 | Page 35 of 52
250
PARALLEL RESISTANCE
8
200
6
150
4
PARALLEL RESISTANCE (Ω)
+5V
2.5pF
100
PARALLEL CAPACITANCE
50
2
0
0
100
200
300
400
500
600
700
800
900
0
1000
FREQUENCY (MHz)
Figure 88. IF DGA Input/Output Impedance vs. Frequency
11489-051
The low-pass filter resides between the mixer outputs and the IF
DGA inputs, as shown in Figure 85. The signal flow starts with the
differential outputs of the mixer being dc biased to positive
supply (5 V) via a pair of pull-up inductors, L1 and L2. The
inductor value is determined by the low frequency cutoff of the
signal band of interest. Next, the third-order low-pass filter
attenuates the high frequency sum term. The combination of
the pull-up inductors and the low-pass filter results in a bandpass filter profile. The outputs of the filter are then ac-coupled
through series capacitors and routed to the on-chip IF DGA via
the IFIN+ and IFIN− pins.
82.5Ω
PARALLEL CAPACITANCE (pF)
Filtering at the mixer output may be necessary for improved
linearity performance. For applications where the frequency plan
requires low RF frequency inputs and IF outputs, the resulting sum
term at the mixer outputs, fRF + fLO, may fall within the band of
interest. The unwanted sum term may cause the IF DGA to
operate in its nonlinear region because of the unnecessary presence
of additional signal power. As a result, the linearity performance
degrades where OIP3 and OIP2 decrease substantially. For this
reason, a low-pass filter is necessary to attenuate the unwanted
signal while maintaining the integrity of the wanted signal within
the band of interest. In addition, the low-pass filter serves to
suppress the LO feedthrough. Because of the absence of blockers
in a typical DPD receive application, a lower order filter, such as
a third-order Chebyshev, is typically adequate.
ADRF6620
Data Sheet
Most important, the low-pass interstage filter must attenuate the
sum term (fRF + fLO) and LO feedthrough to prevent unnecessary
overdrive of the DGA. The level of attenuation that is required to
achieve optimal OIP3 performance is shown in Figure 89, where
OIP3 vs. (fRF + fLO) amplitude is plotted. To maintain performance,
attenuate the amplitude of the sum term to at least −16 dBm (see
Figure 89). Beyond this point, the OIP3 degrades decibel per
decibel for increased amplitudes.
Table 17. Example Filter Design
Parameter
RS
RL
Pass-Band Edge
Attenuation at Pass-Band Edge
Stop-Band Edge
Attenuation at Stop-Band Edge
Filter Type
46
Using filter equations from a textbook or filter design software,
a third-order Chebyshev filter can be designed to satisfy all the
specifications in Table 17, as shown in Figure 91. The mixer output
capacitance of 1.1 pF can be absorbed into the filter, resulting in a
reduction in C1 from 2 pF to 0.8 pF. In addition, depending on the
PCB board stack-up, C2 can be further reduced, or eliminated,
because the capacitance of the PCB board can be used as the
third pole of the filter. The components used in the simulation
were the Coilcraft 0805CS inductors and Murata GRM15 series
capacitors. Figure 90 shows the filter profile that satisfies all the
filter specifications in Table 17.
44
42
38
36
34
–18
–16
–14
–12
–10
–8
–6
AMPLITUDE (dBm)
–4
11489-052
32
0
Figure 89. OIP3 vs. (fRF + fLO) Amplitude
–5
The ADRF6620 is optimized for use in digital predistortion
(DPD) receivers. An example filter design for DPD is shown in
Figure 91. Table 17 lists the interstage filter design targets.
In most DPD systems for cellular transmission, the pass band
is between 50 MHz and 500 MHz. For this reason, the pull-up
inductors have a low frequency cutoff of 50 MHz, and the passband edge of the interstage low-pass filter is 500 MHz. This results
in a band-pass filter profile with a maximally flat pass band from
50 MHz to 500 MHz. The stop-band attenuation at 1400 MHz is
20 dB, which typically provides the necessary attenuation of the
mixer sum term with some margin.
AMPLITUDE (dBm)
–10
–15
–20
–25
–30
–35
–40
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
11489-054
OIP3 (dBm)
40
30
–20
Value
255 Ω
150 Ω
500 MHz
0.5 dB
1400 MHz
20 dB
Third-order Chebyshev
Figure 90. Third-Order Chebyshev Filter Profile
+5V
L1
470nH
RL
L2
470nH
MXOUT+
+
2.5pF
90Ω
+
L3
24nH
82.5Ω
+
C1 +
0.8pF
1.1pF
82.5Ω
MXOUT–
C2
1pF
150Ω
+
L4
24nH
0.1µF
+
MIXER OUTPUT IMPEDANCE
EQUIVALENT MODEL
THIRD-ORDER CHEBYSHEV
FILTER
Figure 91. Low-Pass Interstage Filter Design
Rev. 0 | Page 36 of 52
IFIN+
0.1µF
DC BLOCKING
CAPS
IFIN–
IDEAL IF AMP
INPUT IMPEDANCE
11489-053
RS
Data Sheet
ADRF6620
12
11
L3 = L4 = 47nH, C1 = C2 = OPEN
L3 = L4 = 39nH, C1 = C2 = OPEN
Because the capacitance of the ADRF6620 evaluation board
closely approximates the C1 and C2 capacitors, they can be
removed from the design. However, this may not be the case
for every PCB design with different stack-ups.
Figure 93 compares the OIP3 and OIP2 performance of the
ADRF6620 with and without filtering at the mixer output.
85
OIP2 (dBm)/OIP3 (dBm)
Maintaining the same third-order Chebyshev filter design shown
in Figure 91, the component values can be tuned to optimize
performance with some trade-offs. To achieve maximally flat passband response, the trade-off is signal bandwidth (see Figure 92).
The L3 and L4 inductors are replaced with 47 nH, and the
capacitors are not populated. This configuration results in the
flattest pass-band ripple; however, the signal bandwidth starts to
roll off at 300 MHz. A narrower bandwidth translates to more
attenuation of the mixer sum and LO leakage, which is a desirable
effect if the wider signal bandwidth is not a requirement. Use the
results shown in Figure 92 only as a guide, and design the interstage
filter to the specific PCB board conditions. The plots in Figure 92
were measured using the ADRF6620 evaluation board.
75
OIP2 WITH FILTER
65
OIP2 WITH NO FILTER
55
OIP3 WITH FILTER
45
35
OIP3 WITH NO FILTER
10
100
150
200
250
300
350
IF FREQUENCY (MHz)
450
500
Figure 93. OIP2/OIP3 Performance With and Without Filtering at
the DGA Output; RF Frequency = 900 MHz; High-Side LO Injection, LO Sweep
7
6
5
4
50
400
11489-056
15
50
L3 = L4 = 24nH, C1 = 0.8pF, C2 = 1pF
8
100
150
200
250
300
350
400
450
IF FREQUENCY (MHz)
500
11489-055
GAIN (dB)
25
9
Figure 92. Interstage Filter Design Trade-Offs
Rev. 0 | Page 37 of 52
ADRF6620
Data Sheet
IF DGA VS. LOAD
20
By design, the IF DGA is optimized for performance in a matched
condition where the source and load resistances are both 150 Ω.
If the load or the source resistance is not equal to 150 Ω (see the
Digitally Programmable Variable Gain Amplifier (DGA) section),
use the following equations to determine the resulting gain and
input/output resistances:
18
RL = 73Ω
10
8
6
S21 (Gain) = 2 × RIN/(RIN + RS) × AV
2
ROUT = (1000 + RS)/(1 + 0.044 × RS)
0
In a configuration where the mixer outputs of the ADRF6620
are routed to the IF DGA inputs, the matched condition is no
longer satisfied because the source impedance, as seen by the IF
DGA, is the 255 Ω output impedance of the mixer outputs. As a
result, the gain and output resistance of the amplifier vary from
the expected 15 dB (see Figure 94).
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
Figure 95. IF DGA Gain vs. Frequency for Different Loads
–20
–30
–40
IF DGA IMD3 (dBc)
11489-067
RL
Figure 94. Mixer Loading of the IF DGA
The ideal load is 150 Ω for the matched condition; however, this
may not be the most readily available load impedance.
As a result, load vs. performance trade-offs must be considered.
In the matched condition, the IF DGA is optimized for linearity;
therefore, the third-order intermodulation product degrades with
load. Table 18 shows some common output loads, and Figure 95,
Figure 96, and Figure 97 show the effects of loading on gain,
IMD2, and IMD3.
–50
RL = 50Ω
–60
–70
RL = 73Ω
–80
–90
RL = 500Ω
–110
40
120
200
RL = 150Ω
280
360
440
520
FREQUENCY (MHz)
600
680
11489-069
–100
Figure 96. IF DGA IMD3 vs. Frequency for Different Loads
–20
150Ω LOAD
50Ω LOAD
500Ω LOAD
73Ω LOAD
–30
As the equations in this section indicate, the manner in which
the IF DGA is loaded affects the input resistance, RIN, of the
amplifier. RIN, in turn, determines the load resistance of the
interstage filter between the mixer outputs and the IF DGA
inputs. The interstage filter has a source impedance of 255 Ω from
the mixer outputs and a load impedance of RIN for the particular
RL load (see Table 18). As a result of the impedance mismatch,
the insertion loss of the interstage filter must be included in the
level planning calculations.
IF DGA IMD2 (dBc)
–40
–50
–60
–70
–80
–90
FREQUENCY (MHz)
11489-070
680
640
600
560
520
480
440
400
360
320
280
240
200
160
80
–110
120
–100
40
ROUT
RL = 50Ω
11489-068
4
RIN
RL = 150Ω
12
RIN = (1000 + RL)/(1 + 0.044 × RL)
255Ω
RL = 500Ω
14
IF DGA GAIN (dB)
Voltage Gain = AV = 0.044 × (1000||RL)
16
Figure 97. IF DGA IMD2 vs. Frequency for Different Loads
Table 18. Common Output Loads
RS (Ω)
255
255
255
255
RIN (Ω)
65
151
255
328
AV (Linear)
14.7
5.7
3
2.1
AV (dB)
23.3
15.2
9.5
6.4
S21 (Linear)
6
4.3
3
2.4
Rev. 0 | Page 38 of 52
S21 (dB)
15.5
12.6
9.5
7.5
ROUT (Ω)
102.7
102.7
102.7
102.7
RL (Ω)
500
150
73
50
Data Sheet
ADRF6620
The parallel combination of the 176 Ω with the 1 kΩ of the ADC
input impedance results in an equivalent 150 Ω differential output
load as seen by the IF DGA of the ADRF6620. In addition, the
input capacitance of the AD9434 can be used as the fourth pole
of the antialiasing filter. The final schematic design is shown in
Figure 99. The antialiasing filter is maximally flat, with a passband bandwidth of 500 MHz. Table 19 shows the component
values for the antialiasing filter design for DPD. Figure 98 shows
the simulated antialiasing filter design.
ADC INTERFACING
The integrated IF DGA of the ADRF6620 provides variable and
sufficient drive capability for both buffered and unbuffered ADCs.
It also provides isolation between the sampling edges of the ADC
and the mixer core. As result, only an antialiasing filter is required
when interfacing with an ADC.
The ADRF6620 is optimized for use in cellular base station digital
predistortion (DPD) systems. Predistortion is used to improve
the linearity of transmitter power amplifiers (PA). Because the
input signal to the DPD path is the known transmitted signal, the
hardware specifications are not typically as stringent as the main
receive path. The signal-to-noise ratio (SNR) of the ADC is not
paramount, due to the autocorrelation with the known transmitted
signal. For this reason, lower resolution ADCs are usually adequate,
and 11-bit to 14-bit resolution typically suffices. A more critical
consideration is the analog bandwidth of the converter. Traditional
DPD systems require 3× to 5× the transmit bandwidth. Therefore,
for a 100 MHz Tx bandwidth, the DPD bandwidth must be at
least 500 MHz for fifth-order correction.
Table 19. Component Values for 500 MHz Antialiasing Filter
Design
Parameter
L1 = L2
C1
L3 = L4
C2
L5 = L6
L7 = L8
C3
L9 = L10
The AD9434 complements the ADRF6620 very well in a DPD
design. The AD9434 is a 12-bit, 370 MSPS/500 MSPS buffered
ADC. Its full power analog bandwidth is 1 GHz, making it wide
enough for fifth-order correction with substantial margin. The
sampling rate of the AD9434 is insufficient in satisfying the
sampling theorem; however, this may be acceptable in DPD
applications where undersampling is often permissible. Because
the receive signal in the DPD path is the known transmitted signal,
the desired signal and its aliases are clearly distinguished.
–10
AMPLITUDE (dB)
–15
–20
–25
–30
–35
–40
–50
0
200
400
600
800
1000 1200 1400 1600 1800 2000
FREQUENCY (MHz)
11489-100
–45
Figure 98. Simulated Antialiasing Filter Design
+5V
L6
0.1µF
0.1µF
+
L3
L7
L9
C2
+
C1
88Ω
+
+
0.1µF
+
L4
0.1µF
ADRF6620
IF AMP
Figure 99. ADRF6620 Interface to the AD9434
Rev. 0 | Page 39 of 52
L8
AD9434
88Ω
C3
L10
1kΩ
1.3pF
11489-071
L5
+
L2
+
+
255Ω
Manufacturer
Coilcraft
Murata
Coilcraft
Murata
Coilcraft
Coilcraft
Murata
Coilcraft
0
+5V
L1
Type
0805CS
GRM15
0805CS
GRM15
0805LS
0805CS
GRM15
0805CS
–5
The antialiasing filter resides between the ADRF6620 and the
AD9434. Because aliasing is common practice in a DPD receive
chain, the antialiasing filter requirements can be relaxed. A
second-order or third-order filter is sufficient in reducing the
high frequency noise from folding back into the band of interest.
When designing the antialiasing filter, it is important to consider
the output impedance of the IF DGA of the ADRF6620 and the
input impedance of the AD9434. The differential resistance of
the AD9434 is 1 kΩ, and the parallel capacitance is 1.3 pF. For the
matched load condition, where the IF DGA is optimized for gain
and linearity, load the IF DGA with 150 Ω. To do this, place a
176 Ω resistor in parallel with the input of the ADC.
ADRF6620
MIXER
OUTPUT
Value
470 nH
DNP
39 nH
DNP
1 µH
15 nH
2.7 pF
27 nH
ADRF6620
Data Sheet
POWER MODES
The ADRF6620 has many building blocks, and these blocks can
be independently powered off by writing to Register 0x01 (see
Table 23).
External LO Mode
In external LO mode, the internal PLL and VCO are disabled,
which reduces the current consumption by approximately 100 mA.
Table 20 lists the register settings that are required to configure
external LO mode.
traces as far away from each other as possible (and at an angle,
if possible) to prevent cross coupling.
The input impedance of the RF inputs is 50 Ω, and the traces
leading to the pin must also have a 50 Ω characteristic impedance.
Terminate unused RF inputs with a dc blocking capacitor to
ground.
Table 20. Serial Port Configuration for External LO Mode
State
On
On
Off
Off
On
Off
Off
On
On
On
On
External LO
RFIN 0
Register
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x01 = 0x8B53
0x22, Bits[2:0] = 011
GND
GND
RFIN 1
GND
GND
RFIN 2
GND
GND
RFIN 3
GND
11489-072
Bit Name
LDO_3P3_EN
VCO_LDO_EN
CP_EN
DIV_EN
VCO_EN
REF_BUF_EN
LO_DRV_EN
LO_PATH_EN
MIX_EN
IF_AMP_EN
LO_LDO_EN
VCO_SEL
GND
Figure 100. Recommended Layout for the RF Inputs
IF DGA Disable Mode
In applications where the IF DGA is not used, it can be powered
down. Power-down is achieved by disabling the IF_AMP_EN bit
(Register 0x01, Bit 11 = 0). By disabling the amplifier, the current
consumption of the ADRF6620 decreases by approximately 25 mA,
along with a 35 mA to 50 mA current savings through each bias
inductor at the output of the amplifier. When the IF DGA is
disabled, its input and output impedance is high-Z. For this reason,
the input and output pins can be left open. If the preference is
not to leave the nodes open, the alternative option is to terminate
the pins to ground via a 1 kΩ resistor.
The IF DGA outputs on the ADRF6620 have two output pins for
each polarity, and they are oriented in an alternating fashion, as
follows: IFOUT1+ (Pin 8), IFOUT1− (Pin 9), IFOUT2+ (Pin 10),
and IFOUT2− (Pin 11). When designing the board, minimize the
parasitic capacitance due to the routing that connects the corresponding outputs together. A good practice is to avoid any ground
or power plane under this routing region and under the chokes
to minimize the parasitic capacitance. Figure 101 shows the
recommended layout. The IF DGA output pins with the same
polarity are tied together on the bottom of the board with the
blue traces and vias.
LAYOUT
Rev. 0 | Page 40 of 52
IFOUT1+
IFOUT1–
IFOUT2+
IFOUT2–
11489-073
Careful layout of the ADRF6620 is necessary for optimizing
performance and minimizing stray parasitics. Because the
ADRF6620 supports four RF inputs, the layout of the RF section
is critical in achieving isolation between each channel. Figure 100
shows the recommended layout for the RF inputs. Each RF input,
RFIN0 to RFIN3, is isolated between ground pins, and the best
layout approach is to keep the traces short and direct. To achieve
this layout, connect the pins directly to the center ground pad
of the exposed pad of the ADRF6620. This approach minimizes
the trace inductance and promotes better isolation between the
channels. In additional, for improved isolation, do not route the
RFIN0 to RFIN3 traces in parallel to each other; instead, spread
the traces immediately after each one leaves the pins. Keep the
Figure 101. Recommended Layout for the IF DGA Outputs
(Green traces are routings on top of the board,
and blue traces are routings on the bottom of the board.)
Data Sheet
ADRF6620
REGISTER MAP
Table 21. Register Map Summary Table
Reg Name
0x00 SOFT_RESET
0x01 Enables
0x02 INT_DIV
0x03 FRAC_DIV
0x04 MOD_DIV
0x20 CP_CTL
0x21 PFD_CTL
0x22 FLO_CTL
0x23 DGA_CTL
0x30 BALUN_CTL
0x31 MIXER_CTL
0x40 PFD_CTL2
0x42 DITH_CTL1
0x43 DITH_CTL2
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 10
Bit 9
Bit 8
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED
RESERVED
SOFT_RESET
LO_LDO_EN
RESERVED RESERVED
RESERVED IF_AMP_EN
RESERVED MIX_EN
LO_PATH_EN
LO_DRV_EN
RESERVED REF_BUF_EN VCO_EN DIV_EN
CP_EN
VCO_LDO_EN LDO_3P3_EN
RESERVED
DIV_MODE
INT_DIV[10:8]
INT_DIV[7:0]
RESERVED
FRAC_DIV[10:8]
FRAC_DIV[7:0]
RESERVED
MOD_DIV[10:8]
MOD_DIV[7:0]
RESERVED
RESERVED
CSCALE
RESERVED
RESERVED
BLEED_DIR
BLEED
RESERVED
RESERVED
REF_MUX_SEL
PFD_POLARITY
REFSEL
RESERVED
LO_DRV_LVL[1]
LO_DRV_LVL[0]
RESERVED
LO_DIV_A
VCO_SEL
RESERVED
RFSW_MUX
RFSW_SEL
RFDSA_SEL[3]
RFDSA_SEL[2:0]
IF_ATTN
RESERVED
BAL_COUT
RESERVED
BAL_CIN
RESERVED
RESERVED
MIXER_BIAS
MIXER_RDAC[3]
MIXER_RDAC[2:0]
RESERVED
MIXER_CDAC
RESERVED
RESERVED
ABLDLY
CPCTRL
CLKEDGE
RESERVED
RESERVED
DITH_EN
DITH_MAG
DITH_VAL
DITH_VAL[15:8]
DITH_VAL[7:0]
Rev. 0 | Page 41 of 52
Reset
RW
0x00000 W
0x8B7F
RW
0x0058
RW
0x0250
RW
0x0600
RW
0x0C26 RW
0x0003
RW
0x000A RW
0x0000
RW
0x00000 RW
0x08EF
RW
0x0010
RW
0x000E
RW
0x0001
RW
ADRF6620
Data Sheet
REGISTER ADDRESS DESCRIPTIONS
REGISTER 0x00, RESET: 0x00000, NAME: SOFT_RESET
Table 22. Bit Descriptions for SOFT_RESET
Bit
0
Bit Name
SOFT_RESET
Settings
Description
Soft reset
Reset
0x0000
Access
W
REGISTER 0x01, RESET: 0x8B7F, NAME: ENABLES
Table 23. Bit Descriptions for Enables
Bits
15
11
9
8
7
5
4
3
2
1
0
Bit Name
LO_LDO_EN
IF_AMP_EN
MIX_EN
LO_PATH_EN
LO_DRV_EN
REF_BUF_EN
VCO_EN
DIV_EN
CP_EN
VCO_LDO_EN
LDO_3P3_EN
Settings
Description
Power up LO LDO
IF DGA enable
Mixer enable
External LO path enable
LO driver enable
Reference buffer enable
Power up VCOs
Power up dividers
Power up charge pump
Power up VCO LDO
Power up 3.3 V LDO
Rev. 0 | Page 42 of 52
Reset
0x1
0x1
0x1
0x1
0x0
0x1
0x1
0x1
0x1
0x1
0x1
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Data Sheet
ADRF6620
REGISTER 0x02, RESET: 0x0058, NAME: INT_DIV
Table 24. Bit Descriptions for INT_DIV
Bits
11
Bit Name
DIV_MODE
Settings
Description
Reset
0x0
Access
RW
0x58
RW
Description
Set divider FRAC value
Reset
0x250
Access
RW
Description
Set divider MOD value
Reset
0x600
Access
RW
0
1
[10:0]
INT_DIV
Fractional
Integer
Set divider INT value
REGISTER 0x03, RESET: 0x0250, NAME: FRAC_DIV
Table 25. Bit Descriptions for FRAC_DIV
Bits
[10:0]
Bit Name
FRAC_DIV
Settings
REGISTER 0x04, RESET: 0x0600, NAME: MOD_DIV
Table 26. Bit Descriptions for MOD_DIV
Bits
[10:0]
Bit Name
MOD_DIV
Settings
Rev. 0 | Page 43 of 52
ADRF6620
Data Sheet
REGISTER 0x20, RESET: 0x0C26, NAME: CP_CTL
Table 27. Bit Descriptions for CP_CTL
Bits
[13:10]
Bit Name
CSCALE
Settings
0001
0011
0111
1111
5
BLEED_DIR
0
1
[4:0]
BLEED
00000
00001
…
…
…
11110
11111
Description
Charge pump current
250 μA
500 μA
750 μA
1000 μA
Charge pump bleed direction
Sink
Source
Charge pump bleed
0 μA
15.625 μA
N × 15.625 μA
468.75 μA
484.375 μA
Rev. 0 | Page 44 of 52
Reset
0x3
Access
RW
0x1
RW
0x06
RW
Data Sheet
ADRF6620
REGISTER 0x21, RESET: 0x0003, NAME: PFD_CTL
Table 28. Bit Descriptions for PFD_CTL
Bits
[6:4]
Bit Name
REF_MUX_SEL
Settings
000
001
010
011
100
101
110
111
3
PFD_POLARITY
0
1
[2:0]
REFSEL
000
001
010
011
100
Description
Set REF output divide ratio/VPTAT/LOCK_DET
LOCK_DET
VPTAT
REFCLK
REFCLK/2
REFCLK × 2
RESERVED
REFCLK/4
RESERVED
Set PFD polarity
Positive KV VCO
Negative KV VCO
Set REF input divide ratio
×2
×1
DIV2
DIV4
DIV8
Rev. 0 | Page 45 of 52
Reset
0x0
Access
RW
0x0
RW
0x3
RW
ADRF6620
Data Sheet
REGISTER 0x22, RESET: 0x000A, NAME: FLO_CTL
Table 29. Bit Descriptions for FLO_CTL
Bits
[8:7]
Bit Name
LO_DRV_LVL
Settings
00
01
10
11
[4:3]
LO_DIV_A
00
01
10
11
[2:0]
VCO_SEL
000
001
010
011
100
101
110
111
Description
LO amplitude
−4 dBm
0.5 dBm
+3 dBm
+4.5 dBm
LO_DIV_A
DIV1
DIV2
DIV4
DIV8
Select VCO core/external LO
5.2 GHz to 5.7 GHz
4.1 GHz to 5.2 GHz
2.8 GHz to 4.1 GHz
EXT LO
VCO_PWRDWN
VCO_PWRDWN
VCO_PWRDWN
VCO_PWRDWN
Rev. 0 | Page 46 of 52
Reset
0x0
Access
RW
0x1
RW
0x2
RW
Data Sheet
ADRF6620
REGISTER 0x23, RESET: 0x0000, NAME: DGA_CTL
Table 30. Bit Descriptions for DGA_CTL
Bits
11
Bit Name
RFSW_MUX
Settings
0
1
[10:9]
RFSW_SEL
00
01
10
11
[8:5]
RFDSA_SEL
0000
0001
...
1110
1111
[4:0]
IF_ATTN
00000
00001
...
10111
11000
Description
Set switch control.
Serial CNTRL
Pin CNTRL
Set RF input.
RFIN0
RFIN1
RFIN2
RFIN3
Set RFDSA attenuation. Range: 0 dB to 15 dB in steps of 1 dB.
0 dB
1 dB
14 dB
15 dB
IF Attenuation. Range: 3 dB to 15 dB in steps of 0.5 dB.
3 dB
3.5 dB
14.5 dB
15 dB
Rev. 0 | Page 47 of 52
Reset
0x0
Access
RW
0x0
RW
0x0
RW
0x0
RW
ADRF6620
Data Sheet
REGISTER 0x30, RESET: 0x00000, NAME: BALUN_CTL
Table 31. Bit Descriptions for BALUN_CTL
Bits
[7:5]
Bit Name
BAL_COUT
Settings
000
...
111
[3:1]
BAL_CIN
000
...
111
Description
Set balun output capacitance
Minimum capacitance
...
Maximum capacitance
Set balun input capacitance
Minimum capacitance
...
Maximum capacitance
Reset
0x0
Access
RW
0x0
RW
Reset
0x4
Access
RW
0x7
0xF
RW
RW
REGISTER 0x31, RESET: 0x08EF, NAME: MIXER_CTL
Table 32. Bit Descriptions for MIXER_CTL
Bits
[11:9]
Bit Name
MIXER_BIAS
Settings
000
...
111
[8:5]
[3:0]
MIXER_RDAC
MIXER_CDAC
Description
Set mixer bias value
Minimum
Maximum
Set mixer RDAC value
Set mixer CDAC value
Rev. 0 | Page 48 of 52
Data Sheet
ADRF6620
REGISTER 0x40, RESET: 0x0010, NAME: PFD_CTL2
Table 33. Bit Descriptions for PFD_CTL2
Bits
[6:5]
Bit Name
ABLDLY
Settings
00
01
10
11
[4:2]
CPCTRL
000
001
010
011
100
[1:0]
CLKEDGE
00
01
10
11
Description
Set antibacklash delay
0 ns
0.5 ns
0.75 ns
0.9 ns
Set charge pump control.
Both on
Pump down
Pump up
Tristate
PFD
Set PFD edge sensitivity
Div and REF down edge
Div down edge, REF up edge
Div up edge, REF down edge
Div and REF up edge
Rev. 0 | Page 49 of 52
Reset
0x0
Access
RW
0x4
RW
0x0
RW
ADRF6620
Data Sheet
REGISTER 0x42, RESET: 0x000E, NAME: DITH_CTL1
Table 34. Bit Descriptions for DITH_CTL1
Bits
3
Bit Name
DITH_EN
Settings
0
1
[2:1]
0
DITH_MAG
DITH_VAL
Description
Set dither enable
Disable
Enable
Set dither magnitude
Set dither value
Reset
0x1
Access
RW
0x3
0x0
RW
RW
Description
Set dither value
Reset
0x1
Access
RW
REGISTER 0x43, RESET: 0x0001, NAME: DITH_CTL2
Table 35. Bit Descriptions for DITH_CTL2
Bits
[15:0]
Bit Name
DITH_VAL
Settings
Rev. 0 | Page 50 of 52
Data Sheet
ADRF6620
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
0.45
0.40
0.35
EXPOSED
PAD
24
SEATING
PLANE
5.65
5.50 SQ
5.35
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PIN 1
INDICATOR
0.20 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
06-06-2012-B
7.10
7.00 SQ
6.90
Figure 102. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
7 mm × 7 mm Body, Very Very Thin Quad
(CP-48-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADRF6620ACPZ-R7
ADRF6620-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 51 of 52
Package Option
CP-48-9
ADRF6620
Data Sheet
NOTES
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11489-0-7/13(0)
Rev. 0 | Page 52 of 52