Product Specification PE9601 2200 MHz UltraCMOS™ Integer-N PLL for Rad Hard Applications Product Description Peregrine’s PE9601 is a high performance integer-N PLL capable of frequency synthesis up to 2200 MHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9601 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. The PE9601 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit/ day. Fabricated in Peregrine’s UltraCMOS™ process technology, the PE9601 offers excellent RF performance and intrinsic radiation tolerance. Features • 2200 MHz operation • 10/11 prescaler • Internal phase detector with charge pump • Serial, parallel or hardwired programmable • Low power – 25 mA at 3 V • Targeted at Q3236 PLL replacement • 100 Krad total dose • 44-lead CQFJ Figure 2. Package Type 44-lead CQFJ Figure 1. Block Diagram Fin Fin Prescaler 10/11 Main Counter fp 13 D(7:0) 8 Sdata Pre_en M(6:0) A(3:0) R(3:0) Primary 20-bit 20 Latch Secondary 20-bit Latch 20 20 fr Document No. 70-0025-05 │ www.psemi.com Phase Detector 20 16 6 PD_U PD_D Charge Pump CP 6 R Counter fc ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 14 PE9601 Product Specification VDD 2 1 GND R0 3 GND R1 4 fr R2 5 LD R3 6 Enh GND Figure 3. Pin Configuration 44 43 42 41 40 D0, M0 7 39 fc D1, M1 8 38 VDD_fc D2, M2 9 37 N/C D3, M3 10 36 CP VDD 11 35 VDD VDD 12 34 Cext S_WR, D4, M4 13 33 VDD Sdata, D5, M5 14 32 Dout Sclk, D6, M6 15 31 VDD_fp FSELS, D7, Pre_en 16 30 fp GND 17 29 GND 18 19 20 21 22 23 24 25 26 27 28 Fin Fin Hop_WR A_WR M1_WR VDD Bmode Smode, A3 M2_WR, A2 E_WR, A1 FSELP, A0 Table 1. Pin Descriptions Pin No. Pin Name Interface Mode Type Description 1 VDD ALL (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. 2 R0 Direct Input R Counter bit0 (LSB). 3 R1 Direct Input R Counter bit1. 4 R2 Direct Input R Counter bit2. 5 R3 Direct Input R Counter bit3. 6 GND ALL (Note 1) Ground. D0 Parallel Input Parallel data bus bit0 (LSB). M0 Direct Input M Counter bit0 (LSB). D1 Parallel Input Parallel data bus bit1. M1 Direct Input M Counter bit1. D2 Parallel Input Parallel data bus bit2. M2 Direct Input M Counter bit2. D3 Parallel Input Parallel data bus bit3. M3 Direct Input M Counter bit3. 11 VDD ALL (Note 1) Same as pin 1. 12 VDD ALL (Note 1) Same as pin 1. 7 8 9 10 ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 14 Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions PE9601 Product Specification Table 1. Pin Descriptions (continued) Pin No. Pin Name Interface Mode Type Description S_WR Serial Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. D4 Parallel Input Parallel data bus bit4 M4 Direct Input M Counter bit4 Sdata Serial Input Binary serial data input. Input data entered MSB first. D5 Parallel Input Parallel data bus bit5. M5 Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. D6 Parallel Input Parallel data bus bit6. M6 Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. D7 Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. GND ALL FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. A0 Direct Input A Counter bit0 (LSB). Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. A1 Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. A2 Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). A3 Direct Input A Counter bit3 (MSB). 22 Bmode ALL Input Selects direct interface mode (Bmode=1). 23 VDD ALL (Note 1) Same as pin 1. 24 M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. 25 A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. 26 Hop_WR Serial, Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. 27 Fin ALL Input Prescaler input from the VCO. Input voltage = 223 mV RMS for guaranteed operation. 28 Fin ALL Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. 29 GND ALL 13 14 15 16 17 Ground. 18 E_WR 19 20 21 Document No. 70-0025-05 │ www.psemi.com Ground. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 14 PE9601 Product Specification Table 1. Pin Descriptions (continued) Pin No. Pin Name Interface Mode Type Description 30 fp ALL Output Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31. 31 VDD-fp ALL (Note 2) VDD for fp. 32 Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. 33 VDD ALL (Note 1) Same as pin 1. 34 Cext ALL Output Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kW series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 35 VDD ALL (Note 1) Same as pin 1. 36 CP ALL Output Charge pump current is sourced for “up” when fc leads fp and sinked for “down” when fc lags fp. 37 NC ALL 38 VDD-fc ALL (Note 2) VDD for fc 39 fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. 40 GND ALL Ground. 41 GND ALL Ground. 42 fr ALL Input Reference frequency input. See Figure 4. 43 LD ALL Output, OD Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). 44 Enh Serial, Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. No connection. Note 1: VDD pins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level. Note 2: VDD pins 31 and 38 are used to enable test modes and should be left floating. Note 3: All digital input pins have 70k ohm pull-down resistors to ground. Figure 4. Looking into the device PIN 42 - fr PIN 42 125K 2.8pF ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 14 Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions PE9601 Product Specification Table 2. Absolute Maximum Ratings Symbol VDD VI Parameter/Conditions Min Table 4. ESD Ratings Max Units Symbol VESD Supply voltage -0.3 4.0 V Voltage on any input -0.3 VDD + 0.3 V Note 1: II DC into any input -10 +10 mA IO DC into any output -10 +10 mA Storage temperature range -65 150 °C Tstg Absolute Maximum Ratings are those values listed in the above table. Exceeding these values may cause permanent device damage. Functional operation should be restricted to the limits in the DC Electrical Specifications table. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3. Operating Ratings Symbol Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C Document No. 70-0025-05 │ www.psemi.com Parameter/Conditions ESD voltage (Human Body Model) – Note 1 Level Units 1000 V Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Electrostatic Discharge (ESD) Precautions When handling this UTSi device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 14 PE9601 Product Specification Table 5. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter IDD Operational supply current; Test Program Name IDD_T_oper_at_2 GHz Conditions Min High level input voltage VIL Low level input voltage IIH High level input current IIL (Pull-down resistor on input) Low level input current Max 24 LEVELS_”xxx”_VIH(V) where “xxx” is name of pin being tested LEVELS_”xxx”_VIL(V) where “xxx” is name of pin being tested IIH_”xxx”_(A) where “xxx” is name of pin being tested Units VDD = 2.85 to 3.15 V Prescaler enabled 2 GHz center frequency with 10 MHz reference input. Digital Inputs: All except fr, R0, Fin, Fin VIH Typ VDD = 2.85 to 3.15 V 0.7 x VDD V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V IIL_”xxx”_(A) where “xxx” is name of pin being tested VIL = 0, VDD = 3.15 V mA 0.3 x VDD V +100 µA µA -1 Reference Divider input: fr IIHR High level input current IIH_FR_(A) VIH = VDD = 3.15 V IILR Low level input current IIL_FR_(A) VIL = 0, VDD = 3.15 V +50 µA µA -50 R0 Input (Pull-up Resistor): R0 IIHR High level input current IIH_R0_(A) VIH = VDD = 3.15 V IILR (Pull-down resistor on input) Low level input current IIL_R0_(A) VIL = 0, VDD = 3.15 V LEVELS_”xxx”_VOL(V) where “xxx” is name of pin being tested LEVELS_”xxx”_VOH(V) where “xxx” is name of pin being tested Iout = 6 mA +100 µA µA -3 Counter and phase detector outputs: fc, fp. VOLD Output voltage LOW VOHD Output voltage HIGH 0.4 Iout = -3 mA VDD - 0.4 V V Lock detect outputs: Cext, LD VOLC Output voltage LOW, Cext VOHC Output voltage HIGH, Cext LEVELS_CEXT_VOH(V) Iout = -0.1 mA VOLLD Output voltage LOW, LD LEVELS_ LD_VOL(V) Iout = 6 mA LEVELS_CEXT_VOL(V) Iout = 0.1 mA 0.4 VDD - 0.4 V V 0.4 V Charge Pump output: CP ICP - Source Drive current CP_src_at_0.5 VDD (A) VCP = VDD / 2 -2.6 -2 -1.4 mA ICP – Sink Drive current CP_snk_at_0.5 VDD (A) VCP = VDD / 2 1.4 2 2.6 mA Leakage current CP_lkg_PD_DX (A) -1 1 µA ICP – Source vs. ICP Sink Sink vs. source mismatch CP_srcvsnk_at_0.5 VDD 1.0 V < VCP < VDD – 1.0 V VCP = VDD / 2, 25 % ICP vs. VCP Output current magnitude variation vs. voltage CP_snk_var, TA = 25° C 1.0V < VCP < VDD – 25 % CP_src_var 1.0 V TA = 25° C ICPL ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 14 Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions PE9601 Product Specification Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Test Program Name Conditions Min Max Units 10 MHz Control Interface and Latches (see Figure 5 and Figure 6) fClk Serial data clock frequency tClkH Serial clock HIGH time t_clk_H (s) 30 ns tClkL Serial clock LOW time t_clk_L (s) 30 ns tDSU Sdata set-up time after Sclk rising edge, D[7:0] set-up time to M1_WR, M2_WR, A_WR, E_WR rising edge Sdata hold time after Sclk rising edge, D[7:0] hold time to M1_WR, M2_WR, A_WR rising edge S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width t_dsu_”xxx” (s) where “xxx” is name of pin being tested 10 ns t_dhid_”xxx” (s) where “xxx” is name of pin being tested t_pw_”xxx” (s) where “xxx” is name of pin being tested t_cwr_”xxx” (s) where “xxx” is name of pin being tested 10 ns 30 ns 30 ns t_ce (s) 30 ns t_wrc_”xxx” (s) where “xxx” is name of pin being tested 30 ns t_ec (s) 30 ns 200 2200 MHz 0 5 dBm 20 220 MHz -5 5 dBm 100 MHz tDHLD tPW Sclk rising edge to S_WR rising edge. S_WR, M1_WR, M2_WR, A_WR falling edge to Hop_WR rising edge Sclk falling edge to E_WR tCE transition S_WR falling edge to Sclk rising tWRC edge. Hop_WR falling edge to S_WR, M1_WR, M2_WR, A_WR rising edge E_WR transition to Sclk rising tEC edge Main Divider (Including Prescaler) tCWR (Note 1) Fin Operating frequency RF_sens PFin Input level range RF_sens External AC coupling Main Divider (Prescaler Bypassed) Fin Operating frequency PFin Input level range External AC coupling Reference Divider fr Operating frequency Fc_sens (Note 3) Pfr Reference input power (Note 2) Fc_sens Single ended input -2 dBm Phase Detector fc Comparison frequency (Note 3) 20 MHz Note 1: Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification. Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested. Document No. 70-0025-05 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 14 PE9601 Product Specification Functional Description The PE9601 consists of a prescaler, counters, a phase detector, a charge pump and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals, which are implemented as a pulse width modulated current by the charge pump. The control logic includes a selectable chip interface. Data can be written via serial bus, parallel bus, or hardwired direct to the pins. There are also various operational and test modes and lock detect. Figure 5. Functional Block Diagram R Counter (6-bit) fr D(7:0) Sdata Control Pins Control Logic fc PD_U R(5:0) Phase Detector M(8:0) PD_D Charge Pump C A(3:0) LD Cext 2k Modulus Select Fin Fin 10/11 Prescaler ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 14 M Counter (9-bit) fp Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions PE9601 Product Specification Main Counter Chain The main counter chain divides the RF input frequency, Fin, by an integer derived from the user defined values in the “M” and “A” counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9 bit M counter. Setting Pre_en “low” enables the 10/11 prescaler. Setting Pre_en “high” allows Fin to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] where A ≤ M + 1, M ¹ 0 (1) When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) where A ≤ M + 1, M ¹ 0 (2) A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of “1” will result in a minimum M Counter divide ratio of “2”. In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6 bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) where R > 0 (3) Note that programming R equal to “0” will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low (“0”). Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input “low” and the Smode input “low”. Document No. 70-0025-05 │ www.psemi.com Parallel input data, D[7:0], are latched in a parallel fashion into one of three, 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 6. Data are transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for “ping-pong” counter control is programmed via the FSELP input. When FSELP is “high”, the primary register contents set the counter inputs. When FSELP is “low”, the secondary register contents are utilized. The FSELP input is synchronized with the loading of the counters in order to minimize glitches in the “ping-pong” case. Due to this attribute, applications using a single register should use the secondary register (i.e. tie FSELP “low”) to avoid problems with the prescaler powering up in the disabled state. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 6. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input “low”. Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input “high”. Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M7 and M8, and R Counter inputs R4 and R5 are internally forced low (“0”) Serial Interface Mode Serial Interface Mode is selected by setting the Bmode input “low” and the Smode input “high”. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figure 6 and Figure 7. Data are transferred to the counters as shown in Table 7 on page 10. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 14 PE9601 Product Specification The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 7. After the falling edge of E_WR, the data provide control bits as shown in Table 8 with bit functionality enabled by asserting the Enh input “low”. The double buffering provided by the primary and secondary registers allows for “ping-pong” counter control using the FSELS input. When FSELS is “high”, the primary register contents set the counter inputs. When FSELS is “low”, the secondary register contents are utilized. While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. Table 7. Primary Register Programming Interface Mode Enh Bmode Smode Parallel 1 0 0 R5 R4 M8 M7 Pre_en M6 M2_WR rising edge load D3 D2 D1 D0 M5 M4 M3 M2 M1 M0 R3 R2 M1_WR rising edge load D7 D6 D5 D4 D3 R1 R0 A3 A2 A1 A0 A_WR rising edge load D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial* 1 0 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 Direct 1 1 X 0 0 0 0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 8. Enhancement Register Programming Interface Mode Enh Bmode Smode Parallel 0 X 0 Serial* 0 X 1 Reserved Reserved Reserved D7 D6 D5 B0 B1 B2 Power down Counter load E_WR rising edge load D4 D3 B3 B4 MSEL output Prescaler output fc, fp OE D2 D1 D0 B5 B6 B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. MSB (first in) ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 14 (last in) LSB Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions PE9601 Product Specification Figure 6. Parallel Interface Mode Timing Diagram tDSU t DH LD D [7 : 0] tP W tCWR tWRC M1_WR M2_WR A_WR E_WR tP W Hop_WR Figure 7. Serial Interface Mode Timing Diagram Sdata E_WR tEC tCE Sclk S_WR tDSU Document No. 70-0025-05 │ www.psemi.com tDHLD tClkH tClkL tCWR tPW tWRC ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 14 PE9601 Product Specification Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Bit Function Bit 0 Reserved** Bit 1 Reserved** Bit 2 Reserved** Description Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Bit 7 fp, fc OE Drives the raw internal prescaler output (fmain) onto the Dout output. fp, fc outputs disabled. ** Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “high”. If the divided reference leads the divided VCO in phase or frequency (fr leads fp), PD_U pulses “high”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The signals from the phase detector couple directly to a charge pump. PD_U controls a current source at pin CP with constant amplitude and pulse duration approximately the same as PD_U. PD_D similarly drives a current sink at pin CP. ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 14 The current pulses from pin CP are low pass filtered externally and then connected to the VCO tune voltage. PD_U pulses result in a current source, which increases the VCO frequency and PD_D results in a current sink, which decreases VCO frequency. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “OR” of PD_U and PD_D waveforms, which is driven through a series 2 k ohm resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “NOR” function of PD_U and PD_D. Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions PE9601 Product Specification Figure 8. Package Drawing 44-lead CQFJ All dimensions are in mils Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method 9601-01 PE9601 Engineering Samples 44-pin CQFJ 40 units / Tray 9601-11 PE9601 Flight Units 44-pin CQFJ 40 units / Tray 9601-00 PE9601EK Evaluation Board 1 / Box Document No. 70-0025-05 │ www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 14 PE9601 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corp. Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor Europe Commercial Products: Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 Space and Defense Products: 180 Rue Jean de Guiramand 13852 Aix-En-Provence cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). ©2005 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 14 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions