Product Specification PE9702 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications Product Description Peregrine’s PE9702 is a high-performance integer-N PLL capable of frequency synthesis up to 3000 MHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. Features • 3000 MHz operation • ÷10/11 dual modulus prescaler • Internal phase detector • Serial, parallel or hardwired The PE9702 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. programmable • Ultra-low phase noise • SEU < 10-9 errors / bit-day The PE9702 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. It is manufactured on Peregrine’s UltraCMOS™ process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering excellent RF performance and intrinsic radiation tolerance. • 100 Krad (Si) total dose • 44-lead CQFJ Figure 1. Block Diagram Fin Prescaler 10 / 11 Fin Main Counter fp 13 D(7:0) 8 Sdata Pre_en M(6:0) A(3:0) R(3:0) Primary 20-bit 20 Latch Secondary 20-bit Latch fr Document No. 70-0036-02 │ www.psemi.com 20 20 Phase Detector 20 PD_U PD_D 16 6 6 R Counter fc ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 PE9702 Product Specification VDD 2 1 44-lead CQFJ GND R0 3 Figure 3. Package Type GND R1 4 fr R2 5 LD R3 6 Enh GND Figure 2. Pin Configurations (Top View) 44 43 42 41 40 D0, M0 7 39 fc D1, M1 8 38 VDD_fc D2, M2 9 37 PD_U D3, M3 10 36 PD_D VDD 11 35 VDD VDD 12 34 Cext S_W R, D4, M4 13 33 VDD Sdata, D5, M5 14 32 Dout Sclk, D6, M6 15 31 VDD_fp FSELS, D7, Pre_en 16 30 fp GND 17 29 GND 18 19 20 21 22 23 24 25 26 27 28 Fin Fin Hop_WR A_WR M1_WR VDD Bmode Smode, A3 M2_WR, A2 E_WR, A1 FSELP, A0 Table 1. Pin Descriptions Pin No. Pin Name Interface Mode Type Description 1 VDD ALL (Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. 2 R0 Direct Input R Counter bit0 (LSB). 3 R1 Direct Input R Counter bit1. 4 R2 Direct Input R Counter bit2. 5 R3 Direct Input R Counter bit3. 6 GND ALL (Note 1) Ground. D0 Parallel Input Parallel data bus bit0 (LSB). M0 Direct Input M Counter bit0 (LSB). D1 Parallel Input Parallel data bus bit1. M1 Direct Input M Counter bit1. D2 Parallel Input Parallel data bus bit2. M2 Direct Input M Counter bit2. D3 Parallel Input Parallel data bus bit3. M3 Direct Input M Counter bit3. 11 VDD ALL (Note 1) Same as pin 1. 12 VDD ALL (Note 1) Same as pin 1. S_WR Serial Input D4 M4 Parallel Direct Input Input 7 8 9 10 13 ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 13 Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data is transferred to the secondary register on S_WR or Hop_WR rising edge. Parallel data bus bit4 M Counter bit4 Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions PE9702 Product Specification Table 1. Pin Descriptions (continued) Pin No. Pin Name Interface Mode Type Description Sdata Serial Input Binary serial data input. Input data entered MSB first. D5 Parallel Input Parallel data bus bit5. M5 Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. D6 Parallel Input Parallel data bus bit6. M6 Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. D7 Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. GND ALL FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. A0 Direct Input A Counter bit0 (LSB). Serial Input Parallel Input A1 Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. A2 Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). A3 Direct Input A Counter bit3 (MSB). 22 Bmode ALL Input Selects direct interface mode (Bmode=1). 23 VDD ALL (Note 1) Same as pin 1. 24 M1_WR Parallel Input 25 A_WR Parallel Input 26 Hop_WR Serial, Parallel Input 27 Fin ALL Input Prescaler input from the VCO. 3.0 GHz max frequency. 28 Fin ALL Input Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor should be placed as close as possible to this pin and be connected directly to the ground plane. 29 GND ALL 30 fp ALL 14 15 16 17 Ground. 18 E_WR 19 20 21 Document No. 70-0036-02 │ www.psemi.com Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Ground. Output Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 13 PE9702 Product Specification Table 1. Pin Descriptions (continued) Pin No. Pin Name Interface Mode Type Description 31 VDD-fp ALL (Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output. 32 Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. 33 VDD ALL (Note 1) Same as pin 1. 34 Cext ALL Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 35 VDD ALL (Note 1) Same as pin 1. 36 PD_D ALL Output PD_D is pulse down when fp leads fc. 37 PD_U ALL 38 VDD-fc ALL (Note 1) VDD for fc. Can be left floating or connected to GND to disable the fc output. 39 fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. 40 GND ALL Ground. 41 GND ALL Ground. 42 fr ALL Input Reference frequency input. 43 LD ALL Output, OD Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). 44 Enh Serial, Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. PD_U is pulse down when fc leads fp. Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. VDD pins 31 and 38 are used to enable test modes and should be left floating. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 13 Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions PE9702 Product Specification Table 4. ESD Ratings Table 2. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Min Max Units Supply voltage -0.3 4.0 V V Symbol Parameter/Conditions Level Units VESD ESD voltage (Human Body Model) – Note 1 1000 V VI Voltage on any input -0.3 VDD + 0.3 II DC into any input -10 +10 mA DC into any output -10 +10 mA Electrostatic Discharge (ESD) Precautions Storage temperature range -65 150 °C Parameter/Conditions Min Max Units When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. VDD Supply voltage 2.85 3.15 V TA Operating ambient temperature range -40 85 °C IO Tstg Note 1: Table 3. Operating Ratings Symbol Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol IDD Parameter Operational supply current; Prescaler disabled Prescaler enabled Conditions Min Typ Max Units 10 24 31 mA mA VDD = 2.85 to 3.15 V Digital Inputs: All except fr, Fin, Fin VIH High level input voltage VDD = 2.85 to 3.15 V VIL Low level input voltage VDD = 2.85 to 3.15 V IIH High level input current VIH = VDD = 3.15 V IIL Low level input current VIL = 0, VDD = 3.15 V 0.7 x VDD V 0.3 x VDD V +70 µA µA -1 Reference Divider input: fr IIHR High level input current VIH = VDD = 3.15 V IILR Low level input current VIL = 0, VDD = 3.15 V IIHR High level input current VIH = VDD = 3.15 V IILR Low level input current VIL = 0, VDD = 3.15 V +100 µA µA -100 R0 Input: R0 +70 µA µA -5 Counter and phase detector outputs: fc, fp. VOLD Output voltage LOW Iout = 6 mA VOHD Output voltage HIGH Iout = -3 mA 0.4 VDD - 0.4 V V Lock detect outputs: Cext, LD VOLC Output voltage LOW, Cext Iout = 100 µA VOHC Output voltage HIGH, Cext Iout = -100 µA VOLLD Output voltage LOW, LD Iout = 6 mA Document No. 70-0036-02 │ www.psemi.com 0.4 VDD - 0.4 V V 0.4 V ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 13 PE9702 Product Specification Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Max Units 10 MHz Control Interface and Latches (see Figures 4, 5, 6) fClk Serial data clock frequency tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tDSU Sdata set-up time after Sclk rising edge, D[7:0] set-up time to M1_WR, M2_WR, A_WR, E_WR rising edge 10 ns tDHLD Sdata hold time after Sclk rising edge, D[7:0] hold time to M1_WR, M2_WR, A_WR, E_WR rising edge 10 ns tPW S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width 30 ns tCWR Sclk rising edge to S_WR rising edge. S_WR, M1_WR, M2_WR, A_WR falling edge to Hop_WR rising edge 30 ns Sclk falling edge to E_WR transition 30 ns S_WR falling edge to Sclk rising edge. Hop_WR falling edge to S_WR, M1_WR, M2_WR, A_WR rising edge 30 ns E_WR transition to Sclk rising edge 30 ns tCE tWRC tEC MSEL data out delay after Fin rising edge tMDO (Note 1) CL = 12 pf 8 ns 500 3000 MHz -5 5 dBm 50 300 MHz -5 5 dBm 100 MHz Main Divider (Including Prescaler) Fin Operating frequency PFin Input level range External AC coupling Main Divider (Prescaler Bypassed) Fin Operating frequency PFin Input level range External AC coupling Reference Divider fr Operating frequency (Note 3) Pfr Reference input power (Note 2) Single-ended input Comparison frequency (Note 3) -2 dBm Phase Detector fc Note 1: 20 MHz Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification. Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 13 Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions PE9702 Product Specification Functional Description The PE9702 consists of a prescaler, counters, a phase detector, and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via serial bus, parallel bus, or hardwired directly to the pins. There are also various operational and test modes and a lock detect output. Figure 4. Functional Block Diagram R Counter (6-bit) fr D(7:0) Sdata Control Pins Control Logic R(5:0) fc Phase Detector M(8:0) A(3:0) PD_U PD_D LD Cext Modulus Select Fin Fin 10/11 Prescaler Document No. 70-0036-02 │ www.psemi.com M Counter (9-bit) fp ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 13 PE9702 Product Specification Main Counter Chain Reference Counter Normal Operating Mode The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The main counter chain divides the RF input frequency, Fin, by an integer derived from the user-defined values in the “M” and “A” counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9-bit M counter. Setting Pre_en “low” enables the 10/11 prescaler. Setting Pre_en “high” allows Fin to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] where A ≤ M + 1, 1 ≤ M ≤ 511 (1) When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) where A ≤ M + 1, 1 ≤ M ≤ 511 (2) In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. In this mode, the M value is limited to 1 ≤ M ≤ 127. Prescaler Bypass Mode Setting Pre_en “high” allows Fin to bypass and power down the prescaler. In this mode, the 10/11 prescaler and A register are not active, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency, fr: (3) In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. In this mode, the M value is limited to 1 ≤ M ≤ 127. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 13 fc = fr / (R + 1) where 0 ≤ R ≤ 63 (4) Note that programming R with “0” will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low (“0”). In this mode, the R value is limited to 0 ≤ R ≤ 15. Register Programming Parallel Interface Mode A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of “1” will result in a minimum M Counter divide ratio of “2”. Fin = (M + 1) x (fr / (R+1)) ) where 1 ≤ M ≤ 511 The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: Parallel Interface Mode is selected by setting the Bmode input “low” and the Smode input “low”. Parallel input data, D[7:0], are latched in a parallel fashion into one of three 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 9. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 6. Data is transferred to the counters as shown in Table 7 on page 9. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for “ping-pong” counter control is programmed via the FSELP input. When FSELP is “high”, the primary register contents set the counter inputs. When FSELP is “low”, the secondary register contents are utilized. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 5. This data provides control bits as shown in Table 8 on page 9 with bit functionality enabled by asserting the Enh input “low”. Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions PE9702 Product Specification Serial Interface Mode B7, is clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially-entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 5. After the falling edge of E_WR, the data provides control bits as shown in Table 8 with bit functionality enabled by asserting the Enh input “low”. Serial Interface Mode is selected by setting the Bmode input “low” and the Smode input “high”. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, is clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figure 6. Data is transferred to the counters as shown in Table 7. The double buffering provided by the primary and secondary registers allows for “ping-pong” counter control using the FSELS input. When FSELS is “high”, the primary register contents set the counter inputs. When FSELS is “low”, the secondary register contents are utilized. While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input “high”. Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M7 and M8, and R Counter inputs R4 and R5 are internally forced low (“0”). Table 7. Primary Register Programming Interface Mode Enh Bmode Smode Parallel 1 0 0 Serial* 1 0 Direct 1 1 R5 R4 M8 M7 Pre_en M6 M2_WR rising edge load M5 M4 M3 M2 M1 M0 R3 R2 M1_WR rising edge load R1 R0 A3 A2 A1 A0 A_WR rising edge load D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 X 0 0 0 0 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 8. Enhancement Register Programming Interface Mode Enh Bmode Smode Parallel 0 0 0 Serial* 0 0 1 Power down Reserved Reserved Reserved D7 D6 D5 D4 B0 B1 B2 B3 Counter load MSEL output Prescaler output fc, fp OE D3 D2 D1 D0 B4 B5 B6 B7 E_WR rising edge load *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. MSB (first in) Document No. 70-0036-02 │ www.psemi.com (last in) LSB ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 13 PE9702 Product Specification Figure 5. Parallel Interface Mode Timing Diagram tDSU tDHLD D [7 : 0] tPW tCWR tWRC M1_WR M2_WR A_WR E_WR tPW Hop_WR Figure 6. Serial Interface Mode Timing Diagram Sdata E_WR tEC tCE Sclk S_WR tDSU tDHLD ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 13 tClkH tClkL tCWR tPW tWRC Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions PE9702 Product Specification Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Bit Function Description Bit 0 Reserved** Bit 1 Reserved** Bit 2 Reserved** Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Bit 7 fp, fc OE Drives the raw internal prescaler output (fmain) onto the Dout output. fp, fc outputs disabled. ** Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fr leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is 430 mV / radian. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. Document No. 70-0036-02 │ www.psemi.com PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2k ohm resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. See Figure 4 for a schematic of this circuit. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 13 PE9702 Product Specification Figure 7. Package Drawing 44-lead CQFJ All dimensions are in mils Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method 9702-01 PE9702 ES Engineering Samples 44-pin CQFJ 40 units / Tray 9702-11 PE9702 Flight Units 44-pin CQFJ 40 units / Tray 9702-00 PE9702 EK Evaluation Kit ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 13 1 / Box Document No. 70-0036-02 │ UltraCMOS™ RFIC Solutions PE9702 Product Specification Sales Offices The Americas North Asia Pacific Peregrine Semiconductor Corporation Peregrine Semiconductor K.K. 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Europe Peregrine Semiconductor, Korea Peregrine Semiconductor Europe #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-47-41-91-73 Fax : +33-1-47-41-91-73 South Asia Pacific Space and Defense Products Peregrine Semiconductor, China Americas: Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Document No. 70-0036-02 │ www.psemi.com The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. ©2003-2006 Peregrine Semiconductor Corp. All rights reserved. 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