Advance Information PE97632 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications Product Description Peregrine’s PE97632 is a high performance fractional-N PLL capable of frequency synthesis up to 3.2 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with the existing commercial space PLLs. The PE97632 features a 10/11 dual modulus prescaler, counters, a delta sigma modulator, and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial interface or directly hard-wired. The PE97632 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE97632 offers excellent RF performance and intrinsic radiation tolerance. Features • 3.2 GHz operation • ÷10/11 dual modulus prescaler • Phase detector output • Serial or Direct mode access • Frequency selectivity: Comparison frequency / 218 • Low power — 50 mA at 3.3 V • Rad-Hard • Ultra-low phase noise • 68-lead CQFJ Figure 1. Block Diagram Fin Fin Prescaler 10/11 M8:0 A3:0 R5:0 13 + 20 Pre_en Primary 21-bit Latch Sdata Main Counter Secondary 20-bit Latch Auxiliary 20-bit Latch fr 13 20 19 PD_U Phase Detector PD_D 4 18 DSM 6 6 R Counter 18 K17:0 Direct Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 16 PE97632 Advance Information GND K1 K0 R5 R4 R3 R2 R1 R0 RAND_EN MS2_SEL NC ENH VDD VDD FR GND Figure 2. Pin Configuration and package photo 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VDD 10 60 VDD K2 11 59 VDD K3 12 58 GND K4 13 57 PD_U K5 14 56 NC K6 15 55 PD_D K7 16 54 GND K8 17 53 VDD K9 18 52 DOUT K10 19 51 LD K11 20 50 CEXT K12 21 49 GND K13 22 48 FIN K14 23 47 FIN 24 46 VDD K16 25 45 GND K17 26 44 VDD K15 43 PRE_EN 42 DIRECT 41 A3 40 A2 39 A1 38 A0 37 M8 36 M7 35 M6 34 M5 33 M4 32 M3 31 M 2 30 M 1 29 M 0 28 GND 27 V DD Table 1. Pin Descriptions Pin No. Pin Valid Name Mode Type Description 1 R0 Direct Input R Counter bit0 (LSB). 2 R1 Direct Input R Counter bit1. 3 R2 Direct Input R Counter bit2. 4 R3 Direct Input R Counter bit3. 5 R4 Direct Input R Counter bit4. 6 R5 Direct Input R Counter bit5 (MSB). 7 K0 Direct Input K Counter bit0 (LSB). 8 K1 Direct Input K Counter bit1. 9 GND 10 VDD 11 K2 12 Downbond Ground (Note 1) Digital core VDD. Direct Input K Counter bit2. K3 Direct Input K Counter bit3. 13 K4 Direct Input K Counter bit4. 14 K5 Direct Input K Counter bit5. 15 K6 Direct Input K Counter bit6. ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 16 Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Pin No. Pin Valid Name Mode Type Description 16 K7 Direct Input K Counter bit7. 17 K8 Direct Input K Counter bit8. 18 K9 Direct Input K Counter bit9. 19 K10 Direct Input K Counter bit10. 20 K11 Direct Input K Counter bit11. 21 K12 Direct Input K Counter bit12. 22 K13 Direct Input K Counter bit13. 23 K14 Direct Input K Counter bit14. 24 K15 Direct Input K Counter bit15. 25 K16 Direct Input K Counter bit16. 26 K17 Direct Input K Counter bit17 (MSB). 27 VDD 28 GND 29 M0 Direct Input M Counter bit0 (LSB). 30 M1 Direct Input M Counter bit1. 31 M2 Direct Input M Counter bit2 32 M3 Direct Input M Counter bit3. M4 Direct Input M Counter bit4. Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. 33 S_WR (Note 1) Downbond Serial Digital core VDD. Ground M5 Direct Input M Counter bit5. SDATA Serial Input Binary serial data input. Input data entered MSB first. M6 Direct Input M Counter bit6. Input Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. 34 35 SCLK Serial 36 M7 Direct Input M Counter bit7. 37 M8 Direct Input M Counter bit8 (MSB). 38 A0 Direct Input A Counter bit0 (LSB). A1 Direct Input A Counter bit1. Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. 39 E_WR Serial 40 A2 Direct Input A Counter bit2. 41 A3 Direct Input A Counter bit3 (MSB). 42 DIRECT Both Input Direct mode select. “High” enables direct mode. “Low” enables serial mode. 43 Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. 44 VDD 45 GND (Note 1) Downbond Document No. 70-0205-02 │ www.psemi.com Digital core VDD. Ground ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 16 PE97632 Advance Information Pin No. Pin Valid Name Mode Type (Note 1) Description 46 VDD 47 Fin Both 48 Fin Both 49 GND Downbond 50 CEXT Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. 51 LD Output Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). 52 DOUT Output Data out function, enabled in enhancement mode. 53 VDD 54 GND 55 PD_D Both 56 NC Both 57 PD_U Both 58 GND 59 VDD (Note 1) Output driver/V DD. 60 VDD (Note 1) Phase detector VDD. 61 GND 62 fr 63 VDD (Note 1) Reference VDD. 64 VDD (Note 1) Digital core VDD. Both Both Both Input Prescaler input from the VCO. 3.2 GHz max frequency. Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor directly to the ground plane. (Note 1) Downbond Output Output Downbond GND Ground Output driver/V DD. Ground PD_D pulses down when fp leads fc . PD_U is driven to GND when CPSEL = “High”. No Connect Downbond Both Prescaler VDD. Input Downbond PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”. Ground Ground Reference frequency input. Ground 65 ENH Both 66 NC Both 67 MS2_SEL Both Input MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode. 68 RND_SEL Both Input K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit is the phase detector comparison frequency / 219. Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. No Connect Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground. ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 16 Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Table 2. Absolute Maximum Ratings Symbol VDD Parameter/Conditions Min Supply voltage Electrostatic Discharge (ESD) Precautions Max Units -0.3 4.0 V V VI Voltage on any input -0.3 VDD + 0.3 II DC into any input -10 +10 mA IO DC into any output -10 +10 mA Storage temperature range -65 150 °C Tstg Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS™ devices are immune to latch-up. Table 3. Operating Ratings Symbol When handling this UltraCMOS™ device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Parameter/Conditions Min Max Units VDD Supply voltage 2.85 3.45 V TA Operating ambient temperature range -40 85 °C Table 4. ESD Ratings Symbol Parameter/Conditions Level Units VESD ESD voltage human body model (Note 1) 1000 V Note 1: Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2 Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 16 PE97632 Advance Information Table 5. DC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Typ IDD Operational supply current; Prescaler enabled VDD = 2.85 to 3.45 V 50 IDD Operational supply current; Prescaler disabled VDD = 2.85 to 3.45 V 10 Max Units mA mA All Digital inputs: K[17:0], R[5:0], M[8:0], A[3:0], Direct, Pre_en, Rand_en, M2_sel, Cpsel, Enh (contains a 70 kΩ pull-down resistor) VIH High level input voltage VDD = 2.85 to 3.45 V VIL Low level input voltage VDD = 2.85 to 3.45 V IIH High level input current VIH = VDD = 3.45 V IIL Low level input current VIL = 0, VDD = 3.45 V 0.7 x VDD V 0.3 x VDD V +100 µA µA -1 Reference Divider input: fr IIHR High level input current VIH = VDD = 3.45 V +100 IILR Low level input current VIL = 0, VDD = 3.45 V µA µA -100 Counter and phase detector outputs: PD_D, PD_U VOLD Output voltage LOW Iout = 6 mA VOHD Output voltage HIGH Iout = -3 mA 0.4 VDD - 0.4 V V Digital test outputs: Dout VOLD Output voltage LOW Iout = 200 µA VOHD Output voltage HIGH Iout = -200 µA 0.4 VDD - 0.4 V V Lock detect outputs: (Cext, LD) VOLC Output voltage LOW, Cext Iout = 0.1 mA VOHC Output voltage HIGH, Cext Iout = -0.1 mA VOLLD Output voltage LOW, LD Iout = 1 mA ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 16 0.4 VDD - 0.4 V V 0.4 V Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Table 6. AC Characteristics VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units fClk Serial data clock frequency tClkH Serial clock HIGH time 30 10 MHz ns tClkL Serial clock LOW time 30 ns ns Control Interface and Latches (see Figures 3, 4) (Note 1) tDSU Sdata set-up time to Sclk rising edge 10 tDHLD Sdata hold time after Sclk rising edge 10 ns tPW S_WR pulse width 30 ns tCWR Sclk rising edge to S_WR rising edge 30 ns tCE Sclk falling edge to E_WR transition 30 ns tWRC S_WR falling edge to Sclk rising edge 30 ns tEC E_WR transition to Sclk rising edge 30 ns Fin Operating frequency PFin Input level range Fin Operating frequency PFin Input level range Main Divider (Including Prescaler) (Note 4) External AC coupling 275 3200 MHz -5 5 dBm 50 300 MHz -5 5 dBm 100 MHz Main Divider (Prescaler Bypassed) (Note 4) External AC coupling Reference Divider fr Operating frequency (Note 3) Pfr Reference input power (Note 2) Single ended input -2 dBm Phase Detector fc Comparison frequency (Note 3) 50 MHz SSB Phase Noise (Fin = 1.9 GHz, fr = 20 MHz, fc = 20 MHz, LBW = 50 kHz, VDD = 3.3 V, Temp = 25° C) (Note 4) ΦN Phase Noise 1 kHz Offset -97 dBc/Hz ΦN Phase Noise 10 kHz Offset -102 dBc/Hz Note 1: fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification. Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80mV/ns. Note 3: Parameter is guaranteed through characterization only and is not tested. Note 4: Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow. Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 16 PE97632 Advance Information Functional Description The PE97632 consists of a prescaler, counters, an 18-bit delta-sigma modulator (DSM) and a phase detector. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters “R” and “M” divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter (“A”) is used in the modulus select logic. The DSM modulates the “A” counter outputs in order to achieve the desired fractional step. The phase-frequency detector generates up and down frequency control signals. Data is written into the internal registers via the three wire serial bus. There are also various operational and test modes and a lock detect output. Figure 3. Functional Block Diagram R Counter (6-bit) fr fc R(5:0) PD_U M(8:0) Sdata Control Pins Control Logic Phase Detector K(17:0) PD_D A(3:0) DSM + Logic LD Modulus Select Fin Fin 10/11 Prescaler ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 16 Cext 2 kΩ M Counter (9-bit) fp Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Main Counter Chain Normal Operating Mode Setting the Pre_en control bit “low” enables the ÷10/11 prescaler. The main counter chain then divides the RF input frequency (Fin) by an integer or fractional number derived from the values in the “M”, “A” counters and the DSM input word K. The accumulator size is 18 bit, so the fractional value is fixed from the ratio K/218. There is an additional bit in the DSM that acts like an extra bit (19th bit). This bit is enabled by asserting the pin RAND_SEL to “high”. Enabling this bit has the benefit of reducing the spurious levels. However, a small frequency offset will occur. This positive frequency offset is calculated with the following equation. foffset = (fr / (R + 1)) / 219 (1) All of the following equations do not take into account this frequency offset. If this offset is important to a specific frequency plan, appropriate account needs to be taken. In the normal mode, the output from the main counter chain (fp) is related to the VCO frequency (Fin) by the following equation: fp = Fin / [10 x (M + 1) + A + K/218] where A ≤ M + 1, 1 ≤ M ≤ 511 (2) Fin = (M + 1) x (fr / (R+1)) where 1 ≤ M ≤ 511 (4) (*) Only integer mode In frequency bypass mode, neither A counter or K counter is used. Therefore, only integer-N operation is possible. Reference Counter The reference counter chain divides the reference frequency fr down to the phase detector comparison frequency fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) where 0 ≤ R ≤ 63 (5) Note that programming R with “0” will pass the reference frequency (fr) directly to the phase detector. Register Programming Serial Interface Mode When the loop is locked, Fin is related to the reference frequency (fr) by the following equation: Fin = [10 x (M + 1) + A + K/218] x (fr / (R+1)) where A ≤ M + 1, 1 ≤ M ≤ 511 In this mode, the prescaler and A counter are powered down, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency fr: (3) A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. The A counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in M. Programming the M counter with the minimum allowed value of “1” will result in a minimum M counter divide ratio of “2”. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B20, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The LSB is used as address bit. When “0”, the contents from the primary register are transferred into the secondary register on the rising edge of either S_WR according to the timing diagrams shown in Figure 4. When “1”, data is transferred to the auxiliary register according to the same timing diagram. The secondary register is used to program the various counters, while the auxiliary register is used to program the DSM. Data are transferred to the counters as shown in Table 8 on page 10. Prescaler Bypass Mode (*) Setting the frequency control register bit Pre_en “high” allows Fin to bypass the ÷10/11 prescaler. Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 16 PE97632 Advance Information Direct Interface Mode While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 4. After the falling edge of E_WR, the data provide control bits as shown in Table 9 on page 10 will have their bit functionality enabled by asserting the Enh input “low”. Direct Interface Mode is selected by setting the “Direct” input “high”. Counter control bits are set directly at the pins as shown in Table 7 and Table 8. Table 7. Secondary Register Programming Interface Mode Enh R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 Addr Direct 1 R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 X Serial* 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 0 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 8. Auxiliary Register Programming Interface Mode Enh K17 K16 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0 Rsrv Rsrv Addr Direct 1 K17 K16 K15 K14 K13 K12 K11 K10 K9 K8 K7 K6 K5 K4 K3 K2 K1 K0 X X X Serial* 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 1 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. MSB (first in) (last in) LSB Table 9. Enhancement Register Programming Interface Mode Enh Reserved Reserved fp output Power Down Counter load MSEL output fc output LD Disable Serial* 0 B0 B1 B2 B3 B4 B5 B6 B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. (last in) LSB MSB (first in) ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 16 Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Figure 4. Serial Interface Mode Timing Diagram Sdata E_WR tEC tCE Sclk S_WR tDSU tDHLD tClkH tClkL tCWR tPW tWRC Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 10. Enhancement Register Bit Functionality Bit Function Description Bit 0 Reserve ** Reserved. Bit 1 Reserve ** Reserved. Bit 2 fp output Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 fc output Bit 7 LD Disable Drives the M counter output onto the Dout output. Drives the reference counter output onto the Dout output. Disables the LD pin for quieter operation. ** Program to 0 Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 16 PE97632 Advance Information Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. For the UP and DOWN mode, PD_U and PD_D drive an active loop filter which controls the VCO tune voltage. The phase detector gain is equal to VDD / 2 п. PD_U pulses cause an increase in VCO frequency and PD_D pulses cause a decrease in VCO frequency, for a positive Kv VCO. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kΩ resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Figure 5. Typical Phase Noise A typical phase noise plot is shown below. “Trace 1” is the smoothed average, and “Trace 2” is the raw data. Test Conditions: A typical phase noise plot is shown below. “Trace 1” is the smoothed average, and “Trace 2” is the raw data. Test Conditions: Fout = 1.9204 GHz in MASH 1-1 mode, Fcomparison = 20 MHz, VDD = 3.3 V, Temp = 25 C, Loop bandwidth = 50 kHz. ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 12 of 16 Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Figure 6. Typical Spurious Plot Test Conditions: Frequency step = 400 KHz, Loop bandwidth = 50 kHz, Fout = 1.9204 GHz, Fcomparison = 20 MHz, MASH 1-1, VDD = 3.3 V, Temp = 25C. Document No. 70-0205-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 13 of 16 PE97632 Advance Information Figure 7. PE97632 Cobalt-60 Radiation Effect on Phase Noise (Fvco = 1.92 GHz, Fcomp = 20 MHz, LBW = 100 kHz, VDD = 3.3) -85 Pre-Rad 25C Phase Noise (dBc/Hz) 100 kRad 25C -90 -95 -100 -105 0.1 1 10 Frequency Offset from Carrier ( kHz ) ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 14 of 16 Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions PE97632 Advance Information Figure 8. Package Drawing Package dimensions: 68-lead CQFJ Table 11. Ordering Information Order Code Part Marking Description Packaging Shipping Method 97632-01 PE97632 ES Engineering Samples 68-lead CQFJ Tray 97632-11 PE97632 Flight Units 68-lead CQFJ Tray 97632-00 Document No. 70-0205-02 │ www.psemi.com Evaluation Kit 1/Box ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 16 PE97632 Advance Information Sales Offices The Americas Peregrine Semiconductor Corporation Peregrine Semiconductor, Asia Pacific (APAC) 9450 Carroll Park Drive San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 Space and Defense Products Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Peregrine Semiconductor K.K., Japan Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Americas: Tel: 858-731-9453 Europe, Asia Pacific: 180 Rue Jean de Guiramand 13852 Aix-En-Provence Cedex 3, France Tel: +33-4-4239-3361 Fax: +33-4-4239-7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). ©2006 Peregrine Semiconductor Corp. All rights reserved. Page 16 of 16 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. Document No. 70-0205-02 │ UltraCMOS™ RFIC Solutions