PEREGRINE PE3236

Product Specification
PE3236
2200 MHz UltraCMOS™ Integer-N PLL
for Low Phase Noise Applications
Product Description
Peregrine’s PE3236 is a high performance integer-N PLL
capable of frequency synthesis up to 2.2 GHz. The
superior phase noise performance of the PE3236 is ideal
for applications such as LMDS / MMDS / WLL basestations
and demanding terrestrial systems.
Features
The PE3236 features a 10/11 dual modulus prescaler,
counters and a phase comparator as shown in Figure 1.
Counter values are programmable through either a serial or
parallel interface and can also be directly hard wired. This
programming flexibility, combined with the dual latch
architecture enabling ping-pong loading of the main divide
counter, makes these PLLs well suited as the core for
fractional-N or sigma-delta implementation.
• Serial, parallel or hardwired
• 2.2 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
programmable
• Low power— 22 mA at 3 V
• Q3236 PLL replacement
• Ultra-low phase noise
• Available in 44-lead PLCC package
The PE3236 is optimized for terrestrial applications. It is
manufactured on Peregrine’s UltraCMOS™ process, a
patented variation of silicon-on-insulator (SOI) technology
on a sapphire substrate, offering the performance of GaAs
with the economy and integration of conventional CMOS.
Figure 1. Block Diagram
Fin
Prescaler
10 / 11
Fin
Main
Counter
fp
13
D(7:0)
8
Sdata
Pre_en
M(6:0)
A(3:0)
R(3:0)
Primary
20-bit
20
Latch
Secondary
20-bit
Latch
fr
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20
20
Phase
Detector
20
PD_U
PD_D
16
6
6
R Counter
fc
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 15
PE3236
Product Specification
VDD
2
1
44-lead PLCC
GND
R0
3
Figure 3. Package Type
GND
R1
4
fr
R2
5
LD
R3
6
Enh
GND
Figure 2. Pin Configurations (Top View)
44 43 42 41 40
D0, M0
7
39
fc
D1, M1
8
38
VDD_fc
D2, M2
9
37
PD_U
D3, M3
10
36
PD_D
VDD
11
35
VDD
VDD
12
34
Cext
S_WR, D4, M4
13
33
VDD
Sdata, D5, M5
14
32
Dout
Sclk, D6, M6
15
31
VDD_fp
FSELS, D7, Pre_en
16
30
fp
GND
17
29
GND
18 19 20 21 22 23 24 25 26 27 28
Fin
Fin
Hop_WR
A_WR
M1_WR
VDD
Bmode
Smode, A3
M2_WR, A2
E_WR, A 1
FSELP, A0
Table 1. Pin Descriptions
Pin No.
Pin Name
Interface Mode
Type
Description
1
VDD
ALL
(Note 1)
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
2
R0
Direct
Input
R Counter bit0 (LSB).
3
R1
Direct
Input
R Counter bit1.
4
R2
Direct
Input
R Counter bit2.
5
R3
Direct
Input
R Counter bit3.
6
GND
ALL
(Note 1)
Ground.
D0
Parallel
Input
Parallel data bus bit0 (LSB).
M0
Direct
Input
M Counter bit0 (LSB).
D1
Parallel
Input
Parallel data bus bit1.
M1
Direct
Input
M Counter bit1.
D2
Parallel
Input
Parallel data bus bit2.
M2
Direct
Input
M Counter bit2.
D3
Parallel
Input
Parallel data bus bit3.
M3
Direct
Input
M Counter bit3.
11
VDD
ALL
(Note 1)
Same as pin 1.
12
VDD
ALL
(Note 1)
Same as pin 1.
7
8
9
10
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Interface Mode
Type
Description
S_WR
Serial
Input
D4
Parallel
Input
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or Hop_WR
rising edge.
Parallel data bus bit4.
M4
Direct
Input
M Counter bit4.
Sdata
Serial
Input
Binary serial data input. Input data entered MSB first.
D5
Parallel
Input
Parallel data bus bit5.
M5
Direct
Input
M Counter bit5.
Sclk
Serial
Input
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
D6
Parallel
Input
Parallel data bus bit6.
M6
Direct
Input
M Counter bit6.
FSELS
Serial
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
D7
Parallel
Input
Parallel data bus bit7 (MSB).
Pre_en
Direct
Input
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
GND
ALL
FSELP
Parallel
Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A0
Direct
Input
A Counter bit0 (LSB).
Serial
Input
Parallel
Input
A1
Direct
Input
A Counter bit1.
M2_WR
Parallel
Input
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising
edge of M2_WR.
A2
Direct
Input
A Counter bit2.
Smode
Serial, Parallel
Input
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A3
Direct
Input
A Counter bit3 (MSB).
22
Bmode
ALL
Input
Selects direct interface mode (Bmode=1).
23
VDD
ALL
(Note 1)
Same as pin 1.
24
M1_WR
Parallel
Input
25
A_WR
Parallel
Input
26
Hop_WR
Serial, Parallel
Input
27
Fin
ALL
Input
Prescaler input from the VCO. 2.2 GHz max frequency.
28
Fin
ALL
Input
Prescaler complementary input. A bypass capacitor in series with a 51 Ω resistor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
29
GND
ALL
13
14
15
16
17
Ground.
18
E_WR
19
20
21
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Enhancement register write enable. While E_WR is “high”, Sdata can be serially
clocked into the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the
rising edge of E_WR.
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising
edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge
of A_WR.
Hop write. The contents of the primary register are latched into the secondary
register on the rising edge of Hop_WR.
Ground.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 15
PE3236
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin Name
Interface Mode
Type
Description
30
fp
ALL
Output
Monitor pin for main divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 31.
31
VDD-fp
ALL
(Note 2)
VDD for fp.
32
Dout
Serial, Parallel
Output
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
33
VDD
ALL
(Note 1)
Same as pin 1.
34
Cext
ALL
Output
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
35
VDD
ALL
(Note 1)
Same as pin 1.
36
PD_D
ALL
Output
PD_D is pulse down when fp leads fc.
37
PD_U
ALL
38
VDD-fc
ALL
(Note 2)
VDD for fc.
39
fc
ALL
Output
Monitor pin for reference divider output. Switching activity can be disabled through
enhancement register programming or by floating or grounding VDD pin 38.
40
GND
ALL
Ground.
41
GND
ALL
Ground.
42
fr
ALL
Input
Reference frequency input.
43
LD
ALL
Output,
OD
44
Enh
Serial, Parallel
Input
Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
PD_U is pulse down when fc leads fp.
Note 1:
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
Note 2:
VDD pins 31 and 38 are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp
and fc outputs.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 15
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
VDD
Table 4. ESD Ratings
Parameter/Conditions
Min
Max
Units
Symbol
Supply voltage
-0.3
4.0
V
VESD
V
VI
Voltage on any input
-0.3
VDD +
0.3
II
DC into any input
-10
+10
mA
IO
DC into any output
-10
+10
mA
Storage temperature range
-65
150
°C
Min
Max
Units
Tstg
Table 3. Operating Ratings
Symbol
Parameter/Conditions
VDD
Supply voltage
2.85
3.15
V
TA
Operating ambient
temperature range
-40
85
°C
Note 1:
Parameter/Conditions
ESD voltage (Human Body
Model)
Level
Units
1000
V
Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
IDD
Parameter
Operational supply current;
Prescaler enabled
Conditions
Min
VDD = 2.85 to 3.15 V
Typ
Max
Units
22
35
mA
Digital Inputs: All except fr, R0, Fin, Fin
VIH
High level input voltage
VDD = 2.85 to 3.15 V
VIL
Low level input voltage
VDD = 2.85 to 3.15 V
IIH
High level input current
VIH = VDD = 3.15 V
IIL
Low level input current
VIL = 0, VDD = 3.15 V
0.7 x VDD
V
0.3 x VDD
V
+1
µA
µA
-1
Reference Divider input: fr
IIHR
High level input current
VIH = VDD = 3.15 V
IILR
Low level input current
VIL = 0, VDD = 3.15 V
+100
µA
µA
-100
R0 Input (Pull-up Resistor): R0
IIHRO
High level input current
VIH = VDD = 3.15 V
IILRO
Low level input current
VIL = 0, VDD = 3.15 V
+5
µA
µA
-5
Counter and phase detector outputs: fc, fp
VOLD
Output voltage LOW
Iout = 6 mA
VOHD
Output voltage HIGH
Iout = -3 mA
0.4
VDD - 0.4
V
V
Lock detect outputs: Cext, LD
VOLC
Output voltage LOW, Cext
Iout = 0.1 mA
VOHC
Output voltage HIGH, Cext
Iout = -0.1 mA
VOLLD
Output voltage LOW, LD
Iout = 1 mA
Document No. 70-0026-03 │ www.psemi.com
0.4
VDD - 0.4
V
V
0.4
V
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 15
PE3236
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
10
MHz
Control Interface and Latches (see Figures 4, 5, 6)
fClk
Serial data clock frequency
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
30
ns
tDSU
Sdata set-up time to Sclk rising edge, D[7:0] set-up time to
M1_WR, M2_WR, A_WR rising edge
10
ns
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
tPW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
30
ns
tCWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
30
ns
Sclk falling edge to E_WR transition
30
ns
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
30
ns
E_WR transition to Sclk rising edge
30
ns
tCE
tWRC
tEC
(Note 1)
Main Divider (Including Prescaler)
Fin
Operating frequency
PFin
Input level range
External AC coupling
200
2200
MHz
-5
5
dBm
20
220
MHz
-5
5
dBm
100
MHz
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
PFin
Input level range
External AC coupling
Reference Divider
fr
Operating frequency
(Note 3)
Pfr
Reference input power (Note 2)
Single ended input
Comparison frequency
(Note 3)
-2
dBm
Phase Detector
fc
20
MHz
100 Hz Offset
-75
dBc/Hz
1 kHz Offset
-85
dBc/Hz
SSB Phase Noise (Fin = 1.3 GHz, fr = 10 MHz, fc = 1.25 MHz, LBW = 70 kHz, V DD = 3.0 V, Temp = -40° C)
Note 1:
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
Note 2:
CMOS logic levels can be used to drive the reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
Note 3:
Parameter is guaranteed through characterization only and is not tested.
phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 15
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
Functional Description
The PE3236 consists of a prescaler, counters, a
phase detector and control logic. The dual
modulus prescaler divides the VCO frequency by
either 10 or 11, depending on the value of the
modulus select. Counters “R” and “M” divide the
reference and prescaler output, respectively, by
integer values stored in a 20-bit register. An
additional counter (“A”) is used in the modulus
select logic. The phase-frequency detector
generates up and down frequency control signals.
The control logic includes a selectable chip
interface. Data can be written via serial bus,
parallel bus, or hardwired direct to the pins. There
are also various operational and test modes and
lock detect.
Figure 4. Functional Block Diagram
R Counter
(6-bit)
fr
D(7:0)
Sdata
Control
Pins
Control
Logic
R(5:0)
fc
Phase
Detector
M(8:0)
A(3:0)
PD_U
PD_D
LD
Cext
Modulus
Select
Fin
Fin
10/11
Prescaler
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M Counter
(9-bit)
fp
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Page 7 of 15
PE3236
Product Specification
Main Counter Chain
Register Programming
The main counter chain divides the RF input
frequency, Fin, by an integer derived from the user
defined values in the “M” and “A” counters. It is
composed of the 10/11 dual modulus prescaler,
modulus select logic, and 9 bit M counter. Setting
Pre_en “low” enables the 10/11 prescaler. Setting
Pre_en “high” allows Fin to bypass the prescaler
and powers down the prescaler.
Parallel Interface Mode
The output from the main counter chain, fp, is
related to the VCO frequency, Fin, by the following
equation:
fp = Fin / [10 x (M + 1) + A]
where A ≤ M + 1, 1 ≤ M ≤ 511
(1)
When the loop is locked, Fin is related to the
reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1))
where A ≤ M + 1, 1 ≤ M ≤ 511
(2)
A consequence of the upper limit on A is that Fin
must be greater than or equal to 90 x (fr / (R+1)) to
obtain contiguous channels. Programming the M
Counter with the minimum value of “1” will result in
a minimum M Counter divide ratio of “2”.
When the prescaler is bypassed, the equation
becomes:
Fin = (M + 1) x (fr / (R+1))
where 1 ≤ M ≤ 511
(3)
Parallel input data, D[7:0], are latched in a
parallel fashion into one of three, 8-bit primary
register sections on the rising edge of M1_WR,
M2_WR, or A_WR per the mapping shown in
Table 7 on page 9. The contents of the primary
register are transferred into a secondary register
on the rising edge of Hop_WR according to the
timing diagram shown in Figure 5. Data are
transferred to the counters as shown in Table 7
on page 9.
The secondary register acts as a buffer to allow
rapid changes to the VCO frequency. This
double buffering for “ping-pong” counter control
is programmed via the FSELP input. When
FSELP is “high”, the primary register contents
set the counter inputs. When FSELP is “low”, the
secondary register contents are utilized.
Parallel input data, D[7:0], are latched into the
enhancement register on the rising edge of
E_WR according to the timing diagram shown in
Figure 5. This data provides control bits as
shown in Table 8 on page 9 with bit functionality
enabled by asserting the Enh input “low”.
Serial Interface Mode
Serial Interface Mode is selected by setting the
Bmode input “low” and the Smode input “high”.
In Direct Interface Mode, main counter inputs M7
and M8 are internally forced low.
Reference Counter
The reference counter chain divides the reference
frequency, fr, down to the phase detector
comparison frequency, fc.
The output frequency of the 6-bit R Counter is
related to the reference frequency by the following
equation:
fc = fr / (R + 1)
where 0 ≤ R ≤ 63
Parallel Interface Mode is selected by setting the
Bmode input “low” and the Smode input “low”.
(4)
While the E_WR input is “low” and the S_WR
input is “low”, serial input data (Sdata input), B0
to B19, are clocked serially into the primary
register on the rising edge of Sclk, MSB (B0)
first. The contents from the primary register are
transferred into the secondary register on the
rising edge of either S_WR or Hop_WR
according to the timing diagram shown in
Figures 5-6. Data are transferred to the counters
as shown in Table 7 on page 9.
Note that programming R equal to “0” will pass the
reference frequency, fr, directly to the phase
detector.
The double buffering provided by the primary
and secondary registers allows for “ping-pong”
counter control using the FSELS input. When
FSELS is “high”, the primary register contents
set the counter inputs. When FSELS is “low”, the
secondary register contents are utilized.
In Direct Interface Mode, R Counter inputs R4 and
R5 are internally forced low (“0”).
While the E_WR input is “high” and the S_WR
input is “low”, serial input data (Sdata input), B0
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 8 of 15
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
to B7, are clocked serially into the enhancement
register on the rising edge of Sclk, MSB (B0) first.
The enhancement register is double buffered to
prevent inadvertent control changes during serial
loading, with buffer capture of the serially entered
data performed on the falling edge of E_WR
according to the timing diagram shown in Figure
6. After the falling edge of E_WR, the data provide
control bits as shown in Table 8 on with bit
functionality enabled by asserting the Enh input
“low”.
Direct Interface Mode
Direct Interface Mode is selected by setting the
Bmode input “high”.
Counter control bits are set directly at the pins as
shown in Table 7. In Direct Interface Mode, main
counter inputs M7 and M8, and R Counter inputs
R4 and R5 are internally forced low (“0”).
Table 7. Primary Register Programming
Interface
Mode
Enh
Bmode
Smode
Parallel
1
0
0
R5
R4
M8
M7
Pre_en
M6
M2_WR rising edge load
M5
M4
M3
M2
M1
M0
R3
R2
M1_WR rising edge load
R1
R0
A3
A2
A1
A0
A_WR rising edge load
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Serial*
1
0
1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
Direct
1
1
X
0
0
0
0
Pre_en
M6
M5
M4
M3
M2
M1
M0
R3
R2
R1
R0
A3
A2
A1
A0
*Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface
Mode
Enh
Bmode
Smode
Parallel
0
X
0
Reserved
Reserved
Reserved
Power
down
Counter
load
MSEL
output
Prescaler
output
fc, fp OE
E_WR rising edge load
Serial*
0
X
1
D7
D6
D5
D4
D3
D2
D1
D0
B0
B1
B2
B3
B4
B5
B6
B7
*Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
MSB (first in)
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(last in) LSB
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 15
PE3236
Product Specification
Figure 5. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
D [7 : 0]
tPW
tCWR
tWRC
M1_WR
M2_WR
A_WR
E_WR
tPW
Hop_WR
Figure 6. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC
tCE
Sclk
S_WR
tDSU
tDHLD
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 10 of 15
tClkH
tClkL
tCWR
tPW
tWRC
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 9. Enhancement Register Bit Functionality
Bit Function
Description
Bit 0
Reserved**
Bit 1
Reserved**
Bit 2
Reserved**
Bit 3
Power down
Power down of all functions except programming interface.
Bit 4
Counter load
Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs.
Bit 5
MSEL output
Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output.
Bit 6
Prescaler output
Bit 7
fp, fc OE
Drives the raw internal prescaler output onto the Dout output.
fp, fc outputs disabled.
** Program to 0
Phase Detector
The phase detector is triggered by rising edges
from the main Counter (fp) and the reference
counter (fc). It has two outputs, namely PD_U,
and PD_D. If the divided VCO leads the divided
reference in phase or frequency (fp leads fc),
PD_D pulses “low”. If the divided reference leads
the divided VCO in phase or frequency (fc leads
fp), PD_U pulses “low”. The width of either pulse
is directly proportional to phase offset between the
two input signals, fp and fc.
A lock detect output, LD is also provided, via the
pin Cext. Cext is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kΩ resistor. Connecting Cext to an external
shunt capacitor provides integration. Cext also
drives the input of an internal inverting comparator
with an open drain output. Thus LD is an “AND”
function of PD_U and PD_D.
PD_U and PD_D drive an active loop filter which
controls the VCO tune voltage. PD_U pulses
result in an increase in VCO frequency and PD_D
results in a decrease in VCO frequency.
Document No. 70-0026-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 15
PE3236
Product Specification
Figure 7. PE3236 Typical Phase Noise vs. Offset (VDD = 3.0 V, Temp = 25° C)
-60
-70
Frequency = 1915MHz.
Reference Frequency = 10MHz.
Loop Band Width = 40kHz.
Comparison Frequency = 1MHz.
-80
-90
-100
-110
-120
100
10 4
1000
10 5
10 6
Offset From Carrier (Hz.)
Figure 8. PE3236 Typical Input Sensitivity vs. Frequency (VDD = 3.0 V, Temp = 25° C)
10
0
-10
-20
-30
-40
500
1000
1500
2000
Frequency (Hz.)
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 12 of 15
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
Handling Requirements
All surface mount products which do not meet
Level 1 moisture sensitivity requirements are
processed through dry bake and pack procedure.
The necessary data is recorded on the caution
label of each shipment. The 44-lead PLCC
package is moisture sensitivity Level 3.
Level 3 Caution Label
The caution label should contain the following
information for Level 3 devices:
1. Calculated shelf life in sealed bag: 12 months
at <40 °C and <90% relative humidity (RH)
2. Peak package body temperature is 225 °C.
3. After bag is opened, devices that will be
subjected to reflow solder or other high
temperature process must
Level and Body temperature defined by:
IPC/JEDEC-J-STD-020
For Dry Bake Procedures, see:
IPC/JEDEC-J-STD-033
Operator must observe ESD precautions per
ESD Control Procedure and Parts Handling and
shipping Procedure.
a) Be mounted within 168 hours of factory
conditions <30 °C/60% RH, or
b) Be stored at <10% RH
4. Devices require bake, before mounting, if:
a) Humidity Indicator Card is > 10% when
read at 23 ± 5 °C
b) 3a or 3b are not met
5. If baking is required, devices may be baked for
48 hours at 125 +5/-0 °C
Note: If device containers cannot be subjected to
high temperature or shorter bake times are
desired, reference IPC/JEDEC-J-STD-033 for
bake procedure.
Document No. 70-0026-03 │ www.psemi.com
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 15
PE3236
Product Specification
Figure 9. Package Drawing
44-lead PLCC
0.690±0.005
0.653±0.003
0.045 X 45°
0.010 X 45°
1*
0.020 MIN.
R0.025
0.653±0.003
PIN 1
SURFACE
MOUNT
POINT
0.050
0.690±0.005
4*
0.610 ±0.020
2*
0.050
3*
BOTTOM VIEW
DETAIL
AA
0.027 (WIDTH OF LEAD SLOT)
*EJECT PIN POSITION
Ø0.040
DIMENSIONS ARE IN INCHES
TOLERANCES ARE ± 0.004
50X 45°
0.070
0.180 MAX.
0.070
0.004
0.010
SEE DETAIL A
Table 10. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
3236-21
PE3236
PE3236-44PLCC-27A
44-lead PLCC
27 units / Tube
3236-22
PE3236
PE3236-44PLCC-500C
44-lead PLCC
500 units / T&R
3236-00
PE3236EK
PE3236-44PLCC-EVAL KIT
44-lead PLCC
1 / Box
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 14 of 15
Document No. 70-0026-03 │ UltraCMOS™ RFIC Solutions
PE3236
Product Specification
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corporation
Peregrine Semiconductor K.K.
9450 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
Peregrine Semiconductor, Korea
Peregrine Semiconductor Europe
#B-2402, Kolon Tripolis, #210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-480 S. Korea
Tel: +82-31-728-4300
Fax: +82-31-728-4305
Bâtiment Maine
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-47-41-91-73
Fax : +33-1-47-41-91-73
South Asia Pacific
Space and Defense Products
Peregrine Semiconductor, China
Americas:
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Tel: 858-731-9453
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence Cedex 3, France
Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
Document No. 70-0026-03 │ www.psemi.com
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved.
Page 15 of 15