13 NC 14 NC 15 NC FUNCTIONAL BLOCK DIAGRAM HMC8038 VDD 1 12 RF2 50Ω VCTL 2 11 GND 50Ω 10 GND 9 NC 8 NC 7 NC 4 RF1 PACKAGE BASE 13554-001 RFC 3 NC 6 Nonreflective, 50 Ω design High isolation: 60 dB typical Low insertion loss: 0.8 dB typical High power handling 34 dBm through path 29 dBm terminated path High linearity 0.1 dB compression (P0.1dB): 35 dBm typical Input third-order intercept (IP3): 60 dBm typical ESD ratings 4 kV human body model (HBM), Class 3A 1.25 kV charged device model (CDM) Single positive supply 3.3 V to 5 V 1.8 V-compatible control All off state control 16-lead, 4 mm × 4 mm LFCSP (16 mm2) Pin compatible with the HMC849ALP4CE 16 NC FEATURES EN 5 Data Sheet High Isolation, Silicon SPDT, Nonreflective Switch, 0.1 GHz to 6.0 GHz HMC8038 Figure 1. APPLICATIONS Cellular/4G infrastructure Wireless infrastructure Automotive telematics Mobile radios Test equipment GENERAL DESCRIPTION The HMC8038 is a high isolation, nonreflective, 0.1 GHz to 6.0 GHz, silicon, single-pole, double-throw (SPDT) switch in a leadless, surface-mount package. The switch is ideal for cellular infrastructure applications, yielding up to 62 dB of isolation up to 4.0 GHz, a low 0.8 dB of insertion loss up to 4.0 GHz, and 60 dBm of input third-order intercept. Power handling is excellent up to 6.0 GHz, and it offers an input power for an 0.1 dB compression point (P0.1dB) of 35 dBm (VDD = 5 V). On-chip circuitry operates a single, positive supply voltage from 3.3 V to 5 V, as well as a Rev. A single, positive voltage control from 0 V to 1.8 V/3.3 V/5.0 V at very low dc currents. An enable input (EN) set to logic high places the switch in an all off state, in which RFC is reflective. The HMC8038 has ESD protection on all device pins, including the RF interface, and can stand 4 kV HMB and 1.25 kV CDM. The HMC8038 offers very fast switching and RF settling times of 150 ns and 170 ns, respectively. The device comes in a RoHScompliant, compact 4 mm × 4 mm LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC8038 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Insertion Loss, Isolation, and Return Loss ................................7 General Description ......................................................................... 1 Input Compression and Input Third-Order Intercept .............8 Revision History ............................................................................... 2 Theory of Operation .........................................................................9 Specifications..................................................................................... 3 Applications Information .............................................................. 10 Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 11 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 11 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 11/15—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 9/15—Revision 0: Initial Version Rev. A | Page 2 of 11 Data Sheet HMC8038 SPECIFICATIONS VDD = 3.3 V to 5 V, VCTL = 0 V/VDD, TA = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter INSERTION LOSS ISOLATION RFC to RF1/RF2 (Worst Case) RETURN LOSS On State Off State SWITCHING SPEED tRISE, tFALL tON, tOFF RF SETTLING TIME INPUT POWER 1 dB Compression (P1dB) 0.1 dB Compression (P0.1dB) INPUT THIRD-ORDER INTERCEPT (IP3) RECOMMENDED OPERATING CONDITIONS Bias Voltage Range (VDD) Control Voltage Range (VCTL, EN) Maximum RF Input Power 1 TCASE = 105°C TCASE = 85°C TCASE = 25°C TCASE = −40°C Test Conditions/Comments 0.1 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 4.0 GHz to 6.0 GHz 0.1 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 4.0 GHz to 6.0 GHz 55 50 40 Typ 0.7 0.8 0.9 70 60 51 Max 1.0 1.1 1.3 Unit dB dB dB dB dB dB 0.1 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 4.0 GHz to 6.0 GHz 0.1 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 4.0 GHz to 6.0 GHz 24 18 18 23 22 16 dB dB dB dB dB dB 10%/90% RFOUT 50% VCTL to 10%/90% RFOUT 50% VCTL to 0.1 dB margin of final RFOUT 60 150 170 ns ns ns VDD = 3.3 V VDD = 5 V VDD = 3.3 V VDD = 5 V Two-tone input power = 14 dBm/tone 34 36 33 35 60 dB dB dB dB dBm 3.0 0 Through Path (5 V/3.3 V) Terminated Path Hot Switching Through Path (5 V/3.3 V) Terminated Path Hot Switching Through Path (5 V/3.3 V) Terminated Path Hot Switching Through Path (5 V/3.3 V) Terminated Path Hot Switching Case Temperature Range (TCASE) 1 Min 31/30 24 24 34/33 27 27 34/33 29 27 34/33 29 27 −40 5.4 VDD V V +105 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm °C Exposure to levels between the recommended operating conditions and the absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 3 of 11 HMC8038 Data Sheet Table 2. Digital Control Voltages State Input Control Voltage Low (VIL) High (VIH) VDD = 3.3 V (±5% VDD, TCASE = −40°C to +105°C) VDD = 5 V (±5% VDD, TCASE = −40°C to +105°C) 0 V to 0.85 V at <1 µA, typical 1.15 V to 3.3 V at <1 µA, typical 0 V to 1.20 V at <1 µA, typical 1.55 V to 5.0 V at <1 µA, typical Table 3. Bias Voltage vs. Supply Current Parameter SUPPLY CURRENT VDD = 3.3 V VDD = 5 V Symbol IDD Min Typ 0.14 0.16 Rev. A | Page 4 of 11 Max Unit Typical IDD (mA) mA mA 0.14 0.16 Data Sheet HMC8038 ABSOLUTE MAXIMUM RATINGS Table 4. 35 dBm 30 dBm 30 dBm 135°C −65°C to +150°C 40 35 110°C/W 100°C/W 30 25 AMR OPERATING 5V OPERATING 3.3V 4 kV (Class 3A) 1.25 kV 20 0 1 2 3 4 5 FREQUENCY (GHz) For recommended operating conditions, see Table 1. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Figure 2. Through Path, Power Handling vs. Frequency ESD CAUTION Rev. A | Page 5 of 11 6 13554-002 1 Rating −0.3 V to +5.5 V −0.5 V to VDD + (+0.5 V) INPUT POWER (dBm) Parameter Bias Voltage Range (VDD) Control Voltage Range (VCTL, EN) RF Input Power1 (see Figure 2) Through Path Terminated Path Hot Switching Channel Temperature Storage Temperature Range Thermal Resistance (Channel to Package Bottom) Through Path Terminated Path ESD Sensitivity HBM CDM During the through mode of operation, the supply voltage scales the maximum allowed input power. The power handling vs. frequency for the 3.3 V and 5 V supplies is shown in Figure 2. HMC8038 Data Sheet 13 NC 14 NC 16 NC 15 NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 RFC 3 12 RF2 HMC8038 11 GND TOP VIEW (Not to Scale) 10 GND 9 RF1 NC 8 NC 7 EN 5 NC 6 NC 4 NOTES 1. NC = NO CONNECT. THE PINS ARE NOT CONNECTED INTERNALLY; HOWEVER, ALL DATA SHOWN HEREIN WAS MEASURED WITH THESE PINS CONNECTED TO RF/DC GROUND EXTERNALLY. 2. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 13554-003 VCTL 2 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic VDD VCTL 3 4, 6 to 8, 13 to 16 5 RFC NC 9 10, 11 RF1 GND 12 RF2 EPAD EN Description Supply Voltage Pin. Control Input Pin. See Figure 5 for the VCTL interface schematic. Refer to Table 6 and the recommended input control voltage range in Table 2. RF Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Not Internally Connected. These pins are not internally connected; however, all data shown in this data sheet is measured with the NC pins externally connected to RF/dc ground on the evaluation board. Enable Input Pin. See Figure 5 for the EN interface schematic. Refer to Table 6 and the recommended input control voltage range in Table 2. RF Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF ground. See Figure 4 for the GND interface schematic. RF Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor is required on this pin. Exposed Pad. Exposed pad must be connected to RF/dc ground. INTERFACE SCHEMATICS Table 6. Truth Table 13554-004 GND Figure 4. GND Interface Schematic VCTL, EN 13554-005 VDD Control Input VCTL State EN State Low Low High Low Low High High High Figure 5. Logic Control Interface Schematic Rev. A | Page 6 of 11 Signal Path State RFC to RF1 RFC to RF2 Off On On Off Off Off Off Off Data Sheet HMC8038 TYPICAL PERFORMANCE CHARACTERISTICS 0 –0.5 –0.5 –1.0 –1.5 +105°C +85°C +25°C –40°C –2.0 1 2 –1.5 +105°C +85°C +25°C –40°C –2.0 –2.5 0 –1.0 3 4 5 6 7 FREQUENCY (GHz) –2.5 0 1 2 3 4 5 6 7 FREQUENCY (GHz) 13554-009 INSERTION LOSS (dB) 0 13554-006 INSERTION LOSS (dB) INSERTION LOSS, ISOLATION, AND RETURN LOSS Figure 9. Insertion Loss vs. Frequency over Temperatures, VDD = 3.3 V Figure 6. Insertion Loss vs. Frequency over Temperatures, VDD = 5 V 0 0 RF1 RF2 ALL OFF –20 RFC TO RF1 ON RFC TO RF2 ON –10 ISOLATION (dB) ISOLATION (dB) –20 –40 –60 –30 –40 –50 –60 –80 0 1 2 3 4 5 6 7 FREQUENCY (GHz) –80 13554-007 –100 Figure 7. Isolation Between RFC and RF1/RF2 vs. Frequency at VDD = 3.3 V to 5 V 0 –15 –20 –25 –30 RFC RF1, RF2 OFF RF1, RF2 ON 1 2 3 4 5 6 FREQUENCY (GHz) 7 13554-008 RETURN LOSS (dB) –10 0 3 4 5 6 7 Figure 10. Isolation Between RF1 and RF2 vs. Frequency at VDD = 3.3 V to 5 V –5 –40 2 FREQUENCY (GHz) 0 –35 1 13554-010 –70 Figure 8. Return Loss vs. Frequency at VDD = 3.3 V to 5 V Rev. A | Page 7 of 11 HMC8038 Data Sheet 40 38 38 36 34 32 +105°C +85°C +25°C –40°C 1 2 3 4 5 6 FREQUENCY (GHz) 0 38 INPUT COMPRESSION (dBm) 38 34 32 +105°C +85°C +25°C –40°C 28 1 2 3 4 5 6 FREQUENCY (GHz) Figure 12. Input Compression 1 dB Point vs. Frequency over Temperature, VDD = 3.3 V +105°C +85°C +25°C –40°C 32 30 26 0 IP3 (dBm) 3 FREQUENCY (GHz) 4 5 6 Figure 13. Input Third-Order Intercept (IP3) Point vs. Frequency, VDD = 5 V 4 5 6 +105°C +85°C +25°C –40°C 45 13554-013 2 3 55 50 +105°C +85°C +25°C –40°C 45 2 Figure 15. Input Compression 0.1 dB Point vs. Frequency over Temperature, VDD = 3.3 V 60 55 1 FREQUENCY (GHz) 60 1 6 34 65 0 5 36 65 50 4 28 26 0 3 Figure 14. Input Compression 0.1 dB Point vs. Frequency over Temperature, VDD = 5 V 40 36 2 1 FREQUENCY (GHz) 40 30 +105°C +85°C +25°C –40°C 26 13554-012 INPUT COMPRESSION (dBm) Figure 11. Input Compression 1 dB Point vs. Frequency over Temperature, VDD = 5 V IP3 (dBm) 30 28 26 0 32 13554-015 28 34 0 1 2 3 FREQUENCY (GHz) 4 5 6 13554-016 30 36 13554-014 INPUT COMPRESSION (dBm) 40 13554-011 INPUT COMPRESSION (dBm) INPUT COMPRESSION AND INPUT THIRD-ORDER INTERCEPT Figure 16. Input Third-Order Intercept (IP3) Point vs. Frequency, VDD = 3.3 V Rev. A | Page 8 of 11 Data Sheet HMC8038 THEORY OF OPERATION The HMC8038 requires a single-supply voltage applied to the VDD pin. Bypassing capacitors are recommended on the supply line to minimize RF coupling. The HMC8038 is controlled via two digital control voltages applied to the VCTL pin and the EN pin. A small bypassing capacitor is recommended on these digital signal lines to improve the RF signal isolation. The HMC8038 is internally matched to 50 Ω at the RF input port (RFC) and the RF output ports (RF1 and RF2); therefore, no external matching components are required. The RFx pins are dc-coupled, and dc blocking capacitors are required on the RF lines. The design is bidirectional; the input and outputs are interchangeable. With the EN pin is logic low, the HMC8038 has two operation modes: on and off. Depending on the logic level applied to the VCTL pin, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path is provided from the input to the output, as the other RF output port (for example, RF2) is set to off mode, by which the output is isolated from the input. When the RF output port (RF1 or RF2) is in isolation mode, internally terminate it to 50 Ω, and the port absorbs the applied RF signal. When the EN pin is logic high, the EN pin sets the HMC8038 switch to off mode. In off mode, both output ports are isolated from the input, and the RFC port is open reflective. The ideal power-up sequence is as follows: 1. 2. 3. 4. Power up GND. Power up VDD. Power up the digital control inputs. The relative order of the logic control inputs are not important. Powering the digital control inputs before the VDD supply can inadvertently forward bias and damage ESD protection structures. Power up the RF input. Table 7. Switch Operation Mode Digital Control Inputs VEN VCTL 0 0 0 1 1 X1 1 Switch Mode RFC to RF1 RFC to RF2 Off mode. The RF1 port is isolated from the RFC port and On mode. A low insertion loss path from the RFC is internally terminated to a 50 Ω load to absorb the port to the RF2 port. applied RF signals. On mode. A low insertion loss path from the RFC port to Off mode. The RF2 port is isolated from the RFC port the RF1 port. and is internally terminated to a 50 Ω load to absorb the applied RF signals. All in off mode. Both the RF1 and RF2 ports are isolated from the RFC port, and the RFC port is reflective. X stands for don’t care. Rev. A | Page 9 of 11 HMC8038 Data Sheet APPLICATIONS INFORMATION Generate the evaluation PCB used in the application shown in Figure 17 with proper RF circuit design techniques. Signal lines at the RF port must have a 50 Ω impedance, and the package ground leads and backside ground slug must connect directly to the ground plane, as shown in Figure 18. The evaluation board shown in Figure 18 is available from Analog Devices, Inc. upon request. Table 8. Bill of Materials for Evaluation Board EV1HMC8038LP4C1 Reference Designator J1 to J3 C1 to C6 C7 R1, R2 U1 PCB2 Description PCB mount SMA connector 100 pF capacitor, 0402 package 0.1 μF capacitor, 0402 package 0 Ω resistor, 0402 package HMC8038 SPDT switch 600-01267-00 evaluation PCB 1 14 13 11 50Ω 3 10 4 9 100pF C6 EN 100pF RF2 GND C2 GND RF1 100pF PACKAGE BASE 100pF 13554-017 RFC 2 C3 12 50Ω 8 C5 100pF C1 1 7 VCTL 16 C4 100pF 6 C7 0.1µF 5 Figure 17. HMC8038 Application Circuit 13554-018 VDD 15 Reference to this evaluation board number when ordering the complete evaluation board. 2 Circuit board material: Roger 4350 or Arlon 25FR. Figure 18. EV1HMC8038LP4C Evaluation Board Rev. A | Page 10 of 11 Data Sheet HMC8038 OUTLINE DIMENSIONS PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.39 0.33 0.27 16 13 0.65 BSC PIN 1 INDICATOR (0.30) 1 12 2.55 2.40 SQ 2.25 EXPOSED PAD 9 4 1.00 0.90 0.80 BOTTOM VIEW 0.20 MIN 1.95 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-000000 5 8 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC 08-14-2015-A TOP VIEW 0.70 0.60 0.50 Figure 19. 16-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.90 mm Package Height (CP-16-40) Dimensions shown in millimeters ORDERING GUIDE Model 1 HMC8038LP4CE Temperature Range −40°C to +105°C MSL Rating2 MSL3 Package Description 16-lead Lead Frame Chip Scale Package [LFCSP] Package Option CP-16-40 HMC8038LP4CETR −40°C to +105°C MSL3 16-lead Lead Frame Chip Scale Package [LFCSP] CP-16-40 EV1HMC8038LP4C −40°C to +105°C 1 2 3 Evaluation Board RoHs-Compliant Part. The maximum peak reflow temperature is 260°C. 4-digit lot number: XXXX. ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13554-0-11/15(A) Rev. A | Page 11 of 11 Branding 3 8038 XXXX 8038 XXXX