SmartFusion2 SoC and IGLOO2 FPGA Fabric UG0445 User Guide SmartFusion2 SoC and IGLOO2 FPGA Fabric Table of Contents About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 Fabric Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Fabric Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interface Logic Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 FPGA Routing Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Fabric Array Coordinate System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2 LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LSRAM Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Two-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 32 34 35 36 How to Use LSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LSRAM Use Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3 Micro SRAM (uSRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 uSRAM Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision 4 2 Table of Contents Port List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Port Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 59 60 62 How to Use uSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 4 Mathblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Mathblock Resource Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 How to Use Mathblocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Mathblock Use Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Coding Style Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5 I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Transmit Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 93 95 95 I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Single-Ended Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 I/O Programmable Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Programmable Slew-Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Programmable Input Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Programmable Weak Pull-Up and Pull-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Programmable Schmitt Trigger Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Programmable Pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Bus Keeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Receiver ODT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Receiver ODT Configuration for MSIO and MSIOD Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Receiver ODT Configuration for DDRIO Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Driver Impedance Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Driver Impedance Configuration for MSIO/MSIODs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Driver Impedance Configuration for DDRIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I/O Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Internal Clamp Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Low-Power Signature Mode and Activity Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5 V Input Tolerance and Output Driving Compatibility (only MSIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS/HPMS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 3 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric DDRIOs with MDDR/FDDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDRIOs with Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSIOs/MSIODs with MSS or HPMS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSIOs/MSIODs with Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 114 114 114 JTAG I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Dedicated I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Device Reset I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Crystal Oscillator I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 SERDES I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 A List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 B Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 122 122 122 122 Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Revision 4 4 About this Guide Purpose SmartFusion®2 system-on-chip (SoC) and IGLOO®2 field programmable gate array (FPGA)s integrate fourth generation flash-based FPGA fabric. The FPGA fabric composed of 4-input look-up table (LUT) logic elements, includes embedded memories and mathblocks for DSP processing capabilities. This document describes the SmartFusion2 and IGLOO2 FPGA fabric architecture, embedded memories, mathblocks, fabric routing, and I/Os. Contents This user guide contains the following chapters: • Chapter 1 - Fabric Architecture • Chapter 2 - LSRAM • Chapter 3 - Micro SRAM (uSRAM) • Chapter 4 - Mathblocks • Chapter 5 - I/Os Additional Documentation Table 3 lists additional documentation available on SmartFusion2 SoC and IGLOO2 FPGAs. Refer to the web page for a complete and up-to-date listing: www.microsemi.com/index.php?option=com_content&id=2034&lang=en&view=article#documents. Table 3 • Additional Documents Documents Description SmartFusion2 SoC FPGA Product Brief This product brief provides an overview of SmartFusion2 family, features, and development tools. IGLOO2 FPGA Product Brief This product brief provides an overview of IGLOO2 family, features, and development tools. SmartFusion2 and IGLOO2 FPGA Datasheet This datasheet contains SmartFusion2 and IGLOO2 DC and switching characteristics. SmartFusion2 and IGLOO2 Pin Descriptions This document contains SmartFusion2 and IGLOO2 pin descriptions, package outline drawings, and links to pin tables in Excel format. IGLOO2 High Performance Memory Subsystem User SmartFusion2 and IGLOO2 devices integrate a hard high Guide performance memory subsystem (HPMS) that consists of embedded memories, DMA engines, and FPGA fabric interfaces. This document describes the SmartFusion2 MSS and IGLOO2 HPMS and its internal peripherals. SmartFusion2 and IGLOO2 FPGA High Speed DDR SmartFusion2 SoC and IGLOO2 devices integrate hard Interfaces User Guide high-speed DDR memory controllers for accessing external bulk memories. This document describes the SmartFusion2 and IGLOO2 high-speed external memory interfaces. Revision 4 5 About this Guide Table 3 • Additional Documents (continued) Documents Description SmartFusion2 and IGLOO2 FPGA High Speed Serial SmartFusion2 and IGLOO2 devices integrate hard high Interfaces User Guide speed serial interfaces (PCIe, XAUI/XGXS, SERDES) for accessing external bulk memories. This document describes the SmartFusion2 and IGLOO2 high-speed serial interfaces. SmartFusion2 and IGLOO2 Clocking Resources User SmartFusion2 and IGLOO2 clocking resources include Guide oscillators, FPGA fabric global network, and clock conditioning circuitry (CCCs) with dedicated phase-locked loops (PLLs). These clocking resources provide flexible clocking schemes to the on-chip hard IP blocks—HPMS, fabric DDR (FDDR) subsystem, and high-speed serial interfaces (PCIe, XAUI/XGXS, SERDES)—and logic implemented in the FPGA fabric. SmartFusion2 and IGLOO2 Low Power Design User In addition to low static power consumption during normal Guide operation, SmartFusion2 and IGLOO2 devices support an ultra-low-power Static mode (Flash*Freeze mode) with power consumption less than 1 mW. Flash*Freeze mode retains all the SRAM and register data which enables fast recovery to Active mode. This document describes the SmartFusion2 and IGLOO2 Flash*Freeze mode entry and exit mechanisms. SmartFusion2 and IGLOO2 Reliability and Security The SmartFusion2 and IGLOO2 device family incorporates User Guide essentially all the security features that made third generation Microsemi® SoC devices the gold standard for security in the PLD industry. Also included are unique design and data security features and use models new to the PLD industry. SmartFusion2 and IGLOO2 flash-based FPGA fabric has zero FIT configuration rate due to its single event upset (SEU) immunity, which is critical in reliability applications. This document describes the SmartFusion2 and IGLOO2 security features and error detection and correction (EDAC) capabilities. SmartFusion2 and IGLOO2 System Controller User The system controller manages programming of the Guide SmartFusion2 and IGLOO2 device and handles system service requests. The subsystems, interfaces, and system services in the system controller are discussed in this user's guide. SmartFusion2 and IGLOO2 Programming User Guide Describes different programming modes supported in SmartFusion2 and IGLOO2 devices. High level schematics of these programming methods are also provided as a reference. Important board-level considerations are discussed. Libero SoC User Guide 6 Libero® System-on-Chip (SoC) is the most comprehensive and powerful FPGA design and development software available, providing start-to-finish design flow guidance and support for novice and experienced users alike. Libero SoC combines Microsemi SoC Products Group tools with such EDA powerhouses as Synplify®, ModelSim®, and ViewDraw®. This user guide discusses the usage of the software and design flow. R e vi s i o n 4 1 – Fabric Architecture Introduction The SmartFusion2 SoC and IGLOO2 FPGA fabric comprises an array of logic blocks and embedded hard blocks such as large static random access memory (LSRAM), micro SRAM (uSRAM), and mathblocks for digital signal processing (DSP) capability. These elements are arranged as several rows inside the fabric, interconnected by the clustered routing architecture of the SmartFusion2 and IGLOO2 device. Each element in the fabric has a distinct logical coordinate value assigned to it. Figure 1-1 on page 8 shows the simple layout of the SmartFusion2 SoC and IGLOO2 FPGA fabric architecture. Three types of resources constitute the major part of the fabric logic blocks: • Logic elements • Interface logic elements • I/O modules The logic element is the basic element used for implementing the combinatorial circuits, arithmetic functions, and sequential circuits inside the fabric. Each logic module consists of a 4-input LUT, a D-flipflop, and a dedicated carry chain. The interface logic is the logic element that interfaces the embedded hard blocks to the fabric routing. The interface logic enables the accessibility of the embedded hard block through the fabric routing. The interface logic is structurally similar to the logic element except that it does not contain the dedicated carry chain. The interface logic can also be used to implement the combinatorial and sequential circuits, if the associated embedded hard block is not being used by the design. The I/O module forms the digital part of the fabric user I/Os, also called as multi-standard inputs/outputs (MSIOs). The I/O module enables the user I/Os to be connected to the fabric routing. The SmartFusion2 and IGLOO2 fabric use a clustered routing architecture to interconnect the various elements inside the fabric. In clustered architecture, various logic elements are grouped together to form the clusters. There are three types of clusters in the SmartFusion2 SoC and IGLOO2 FPGA fabric: • Logic clusters • Interface clusters • I/O clusters The logic cluster is composed of 12 logic elements; the interface cluster is composed of 12 interface logic elements. I/O clusters are composed of 3 to 4 I/O modules, which are distributed on four4 sides of the device, as shown in Figure 1-1 on page 8 (north, south, east, and west I/O clusters). Revision 4 7 Fabric Architecture Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element Logic Element One Logic Cluster One Logic Element Fabric Layout North I/O Clusters Logic Cluster Lo Logic gic Cluster Mathblocks CCC(x2) West I/O Clusters East I/O Clusters uSRAM LSRAM Logic Clusters Interface Clusters Chip Layout South I/O Clusters Figure 1-1 • SmartFusion2/IGLOO2 Fabric Architecture for M2S050/M2GL050 8 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Fabric Resources Table 1-1 and Table 1-2 list the fabric resources available on SmartFusion2 and IGLOO2 devices. Table 1-1 • Fabric Resources for SmartFusion2 Devices Fabric Resource M2S005 M2S010 M2S025 M2S050 M2S090 M2S150 6,060 12,084 27,696 56,340 86,316 146,124 LSRAM 18K blocks 10 21 31 69 109 236 uSRAM 1K blocks 11 22 34 72 112 240 Mathblocks 11 22 34 72 84 240 PLLs and CCCs 2 2 6 6 6 8 Logic elements (4-input LUT + Flip-Flop) Table 1-2 • Fabric Resources for IGLOO2 Devices Fabric Resource M2GL005 M2GL010 M2GL025 M2GL050 M2GL090 M2GL150 6,060 12,084 27,696 56,340 86,316 146,124 LSRAM 18K blocks 10 21 31 69 109 236 uSRAM 1K blocks 11 22 34 72 112 240 Mathblocks 11 22 34 72 84 240 PLLs and CCCs 2 2 6 6 6 8 Logic elements (4-input LUT + Flip-Flop) Architecture Overview The following sections of this chapter describe the SmartFusion2 SoC and IGLOO2 FPGA fabric architecture in detail. • Logic Element • Interface Logic Element • I/O Module • FPGA Routing Architecture Logic Element The logic elements can be used as a combinational logic element (CLE), and/or sequential logic element (SLE) in the design. Each logic element consists of: • A 4-input LUT • A dedicated carry chain based on the carry look-ahead technique • A separate flip-flop which can be used independently from the LUT Revision 4 9 Fabric Architecture Figure 1-2 shows the functional block diagram of the logic element with carry chain. S (SUM) Y Q LOGIC ELEMENT Cin Cout Cout LOGIC ELEMENT LOGIC ELEMENT Q data D Y FF 4-input LUT with Carry Chain Cin EN CLK SLDATA ALDATA A B C clrsel ldsel clock enasel D2 D1 Routing MUXes Figure 1-2 • Functional Block Diagram of Logic Element The 4-input LUT can be configured to implement any 4-input combinatorial function or to implement an arithmetic function, where the LUT output is XORed with carry input (Cin) to generate the sum (S) output. The sum output, S, is typically used as an output for arithmetic functions but can also be used as an output for logical functions along with the other output, Y, when the LUT is used to implement combinatorial functions. Each logic element has a dedicated 3-bit look-ahead carry implementation, which is used to implement a dedicated carry chain between the logic elements when the LUT is used to implement arithmetic operations. The carry chain has hardwired routing nets running between the logic elements, which reduces the carry propagation delay through the carry chain, thus giving better performance. The logic element also contains a dedicated flip-flop, which can be used in conjunction with or independently from the LUT. The flip-flop can be configured as a register or latch. It has asynchronous and synchronous load and clock enable inputs. The data input of the flip-flop can be fed from the direct input (D1) or from the outputs of the 4-input LUT inside the logic element. Interface Logic Element Embedded hard blocks (LSRAM blocks, uSRAM blocks, and mathblocks) contain a dedicated interface logic. The embedded hard blocks are connected to the fabric routing structure through LUTs and flipflops on their inputs and outputs, and these together form the interface logic element. Each embedded hard block is associated with 36 interface logic elements. This interface logic element is structurally equivalent to a logic element but does not have a dedicated carry chain. When a given embedded hard block is used by the target design, the interface logic is used to connect the embedded hard block’s I/Os to the fabric routing. If an embedded hard block is not used by the design, the interface logic element is available for use as a normal logic elements for implementing combinatorial and sequential circuits. These are in addition to logic elements available in the fabric. 10 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric I/O Module The I/O module includes the I/O digital (IOD) circuitry and the associated routing interface. Each user I/O pad is connected to its own dedicated I/O module. The I/O module interfaces the user I/Os with the fabric routing and enables the routing of external signals coming in through the I/Os to reach all the logic elements. The I/O modules also enable the internal signals to reach the I/Os. Figure 1-3 shows the functional diagram of the complete MSIO with the IOD and I/O analog (IOA) sections. The IOD consists of the input registers, output registers, output enable registers, and routing multiplexers (MUXes). The output register provides the registered version of the output signals to the I/Os. In the same way, the input registers are used to register the inputs received from the I/Os. The output enable acts as a control signal for the output, if the I/O is configured as a tristated or bidirectional I/O. These registers in the I/O modules are similar to the D-flip-flops available in the logic element. The usage of the output registers in the I/O modules for registering the output signals at I/Os enables better design performance. Also, in the case of a signal bus, these registers ensure that all the bits of the signal bus are synchronized to the clock signal when being sent out through the I/Os. At the input side, the input registers allow capturing the input signals and synchronizing them to the design clock. I/O Module (IOD) IOA Weak pull-up/pull-down resistor control PAD_P DO_P TX Output data outreg OCLK RX OE_P Differential ODT Output enable outreg ODT 0 1 DO_N Output data 0 1 outreg TX PAD_N OE_N 0 1 RX Output enable outreg VREF ODT non-registered input data registered input data DI_P inreg ICLK non-registered input data DI_N registered input data inreg DIFF_IN DIFF_OUT Figure 1-3 • Functional Block Diagram of MSIO Revision 4 11 Fabric Architecture FPGA Routing Architecture The SmartFusion2 SoC and IGLOO2 FPGA fabric has a clustered routing architecture. Clustering is a hierarchical grouping of fabric resources that allows a more area-efficient implementation of designs while maintaining optimal performance. It also helps in reducing the run-time of the place-and-route software. The SmartFusion2 and IGLOO2 fabric routing architecture is composed of three types of clusters: • Logic Cluster • Interface Cluster • I/O Cluster Logic Cluster The logic cluster is a combination of 12 logic elements with a dedicated hardwired carry chain implemented for all 12 logic elements. The logic clusters contain routing MUXes. Each routed signal is driven by a unique logic element output or routing MUX. All the logic elements are interconnected with feedback from outputs to inputs. The intra-routing inside the logic clusters has a very low propagation delay as compared to the routing outside the logic clusters. Each LUT, D-flip-flop, and the carry-circuit in the logic cluster have an individual X-Y logical coordinate assigned, and this makes them independently addressable. Figure 1-4 shows the top-level logic cluster layout diagram. Dedicated Carry Chain Cluster Carry IN Cluster Carry Out Logic Elements Intra-cluster Routing Buffers Figure 1-4 • Logic Cluster Top-Level Layout Interface Cluster The interface cluster is similar to the logic cluster except that it is a combination of 12 interface logic elements. These clusters are used to interface the inputs and outputs of the embedded hard blocks (LSRAM, uSRAM, mathblocks, and CCCs) to fabric routing. Each embedded hard block is spanned by 3 interface clusters, as shown in Figure 1-5 on page 13. The interface logic can be used as a logic elements (without carry chain) when the associated embedded hard block is not used by the design. 12 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Embedded Hard Blocks-LSRAMs, µSRAMs, Mathblocks, CCCs 3 Clusters Wide 12 Interface Logic 12 Interface Logic Interface Logic LUT+ FF Interface Logic LUT+ FF Routing Routing Interface Cluster Interface Cluster Figure 1-5 • Interface Cluster I/O Cluster I/O clusters are combinations of I/O modules and the associated routing interfaces. The north and south I/O clusters each contain four I/O modules. The east and west I/O clusters, each contain three I/O modules. Each I/O pad is associated with its own dedicated I/O module. Routing Structure The routing of any design is completed automatically by the software, thus, the utilization of the routing resources is completely transparent to the user. The selection among various routing resources by the placement-and-routing software is impacted by the design constraints provided. Refer to SmartFusion2 and IGLOO2 SmartTime, I/O Editor and ChipPlanner User Guide for more details on how to use the constraints using Libero SoC software. Knowledge of the routing architecture and functional modules can be useful in providing effective design constraints to the software, so that it can be guided to do an optimal design implementation on the SmartFusion2 and IGLOO2 fabric. In the SmartFusion2 and IGLOO2 device, the fabric routing is segregated into two parts: • Inter-cluster routing • Intra-cluster routing Revision 4 13 Fabric Architecture Figure 1-6 shows the fabric routing structure for the SmartFusion2 and IGLOO2 device. From Other Clusters To Other Clusters Inter-Cluster Routing Logic Elements Cluster Intra-Cluster Routing (3 Levels of Routing Muxes) From Adjacent Clusters Output MUXes To Adjacent Clusters From Other Clusters Inter-Cluster Routing To Other Clusters Figure 1-6 • Fabric Routing Structure Inter-cluster routing spans the clusters and connects them together. The inter-cluster routing resource is common to all the clusters inside the fabric and is universal across the clusters. Intra-cluster routing spans the modules that constitute a cluster. Intra-cluster routing is not unique and varies from cluster to cluster, depending upon the functionality of the cluster. For example, the intracluster routing for an interface cluster is different from that of a logic cluster. There are differences in the routing of the various interface clusters, depending upon the embedded hard block to which they interface. Inter-cluster routing and intra-cluster routing are completely separate. Inter-cluster routing never drives the inputs of the functional modules (logic elements, interface logic elements, or I/O modules) directly and the outputs of the functional modules do not drive the inter-cluster routing directly. Inter-cluster routing has to pass through the intra-cluster routing to reach the functional modules. That makes SmartFusion2 and IGLOO2 routing a fully clustered routing architecture. The global network can also drive intra-cluster routing through special routing MUXes. These global routing MUXes bring in flip-flop control signals such as clock, enable, and sets/resets. There are a few short routing lines between the adjacent clusters and between the inter-cluster and intra-cluster routing MUXes. These short paths are provided to provide better performance to the signals routed through these lines. 14 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Fabric Array Coordinate System Every element in the SmartFusion2 SoC and IGLOO2 FPGA fabric has individual logical X-Y coordinates associated with the fabric array coordinate system. These logical coordinates are used by the place-and-route software while implementing the design using the fabric elements. The place-and-route software can be constrained to occupy the design components in specific locations inside the fabric using this coordinate system. Regions can be created inside the fabric and a particular part of the design can be assigned to that region using the Libero SoC floor-planner software. The boundaries of these regions can be specified using the array coordinates. Similarly, the embedded hard block is also addressable through the fabric coordinate system. The array coordinates are measured from the bottom-left corner to the top-right corner of the FPGA fabric. Table 1-3 on page 17 provides the array coordinates of logical modules and embedded hard blocks of SmartFusion2 and IGLOO2 devices. Figure 1-7, Figure 1-8 on page 16, and Figure 1-9 on page 16 show the array coordinates of an M2S050/M2GL050, M2S025/M2GL025, and M2S010/M2GL010 devices. For more information on how to use array coordinates for region/placement constraints, refer to the Libero SoC User Guide or online help (available in the software) for SmartFusion2 and IGLOO2 Libero SoC tools. (0,206) (887,206) LSRAM (36,194) (851,194) Mathblocks (0,158) (887,158) uSRAM (0,146) (887,146) LSRAM (0,134) (887,134) Mathblocks (0,95) (887,95) uSRAM (0,83) (887,83) Mathblocks (0,59) (887,59) uSRAM (0,47) (887,47) LSRAM (36,11) (887,11) (0,0) (887,0) Figure 1-7 • M2S050/M2GL050 Fabric Logical Coordinates Revision 4 15 Fabric Architecture (0,146) (635,146) LSRAM (36,194) (599,194) Mathblocks (0,110) (635,110) uSRAM (0,98) (635,98) Mathblocks (0,35) (635,35) uSRAM (0,23) (635,23) LSRAM (36,11) (635,11) (0,0) (635,0) Figure 1-8 • M2S025/M2GL025 Fabric Logical Coordinates (407,104) (0,104) (371,92) LSRAM (0,92) Mathblocks (0,80) (407,80) uSRAM (0,68) (407,68) LSRAM (0,47) (407,47) Mathblocks (0,23) (407,23) uSRAM (0,11) (407,11) (407,0) (0,0) Figure 1-9 • M2S010/M2GL010 Fabric Logical Coordinates 16 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 1-3 • Fabric Array Coordinate Systems Logic Elements Min Max uSRAM LSRAM Mathblocks Bottom Middle Top Bottom Middle Top Bottom Middle Top Device X Y X Y (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) (X,Y) M2S005 M2GL005 0 0 407 56 NA NA (0,11) NA NA (0,44) NA NA (0,23) M2S010 M2GL010 0 0 407 104 (0,11) NA (0,68) (0,47) NA (0,92) (0,23) NA (0,80) M2S025 M2GL025 0 0 635 146 (0,23) NA (0,98) (36,11) NA (36,134) (0,35) NA (0,110) M2S050 M2GL050 0 0 887 206 (0,47) (0,83) (0,146) (36,11) (0,134) (36,194) (0,59) (0,95) (0,158) M2S090 M2GL090 0 0 1031 266 (0, 23) (0, 59) (0, 194) (0, 242) (36, 11) (0, 119) (0, 170) (36, 254) (0, 35) (0, 71) (0, 206) M2S150 M2GL150 0 0 1463 314 (0, 35) (0, 59) (0, 107) (0, 182) (0, 230) (0, 278) (36, 11) (0, 95) (0, 143) (0, 218) (0, 266) (36, 302) (0, 47) (0, 71) (0, 119) (0, 194) (0, 242) (0, 290) Revision 4 17 Fabric Architecture List of Changes The following table shows important changes made in this document for each revision. Date Changes Revision 3 (May 2015) Revision 2 (March 2014) Page Removed M2GL100 device from Table 1-1 and Table 1-3 (SAR 62858). 15, 23 Merging the SmartFusion2 SoC and IGLOO2 FPGA Fabric user guide. NA Updated "Introduction" section, "Architecture Overview" section, and Table 1-3 • Fabric Array Coordinate Systems (SAR 55075). 7, 9, 17 Glossary Acronyms uSRAM Micro static random access memory CCC Clock conditioning circuits LSRAM Large static random access memory Terminology Clusters Clusters are formed by grouping a certain number of logic elements and interconnecting them. This is related to the clustered routing architecture of SmartFusion2 SoC and IGLOO2 FPGA fabric. Interface Cluster An interface cluster is formed by grouping 12 interface logic elements. I/O Cluster I/O cluster is formed by grouping either 3 or 4 I/O modules. Interface Logic The logic element consists of a 4-input LUT and a D flip-flop. This logic element interfaces the hard macros (LSRAMs, uSRAMs, and mathblocks) to fabric routing. I/O Module The logic element consists of flip-flops and routing MUXes. This logic element interfaces the user I/Os to fabric routing. Inter-cluster Routing Inter-cluster routing refers to routing resources between various types of clusters. Intra-cluster Routing Intra-cluster routing refers to routing resources existing inside a specific cluster. Logic Cluster A logic cluster is formed by grouping 12 logic elements. Logic Element The basic logic element in SmartFusion2 SoC and IGLOO2 FPGA fabric consists of a 4-input LUT, a Dflip-flop, and a dedicated carry chain. 18 R e visio n 4 2 – LSRAM Introduction The SmartFusion2 SoC and IGLOO2 FPGA fabric has embedded 18 Kbit SRAM blocks used for storing data. These large SRAM blocks (LSRAMs) are arranged in multiple rows within the FPGA fabric and can be accessed through the fabric routing architecture. The number of LSRAM blocks available depends upon the specific SmartFusion2 and IGLOO2 device, as shown in Table 2-1 on page 20. For example, in the M2S050 or M2GL050 device, there are 69 LSRAM blocks available, which are spread across three rows inside the fabric. Features The SmartFusion2 and IGLOO2 LSRAM blocks have the following features: • Each LSRAM block can store up to 18,432 bits of data and can be configured in any of the following depth x width combinations: 512 x 36, 512 x 32, 1k x 18, 1k x 16, 2k x 9, 2k x 8, 4k x 4, 8k x 2, or 16k x 1. • Each LSRAM block contains two independent data ports—Port A and Port B. • The LSRAM is synchronous for both read and write operations. These operations are triggered on the rising edge of the clock. • Supports maximum frequency up to 400 MHz. • An optional pipeline register is available at the read data port to improve the clock-to-out delay. • LSRAM supports two types of read operations: • • – Flow-through read (or non-pipelined) – Pipelined read LSRAM supports two types of write operations: – Simple write – Feed-through write (write-bypass write) LSRAM can be operated in two memory modes: – Dual-port mode – Two-port mode • A write operation requires one clock cycle. • A read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output data appears in the next cycle. • Read from both ports at the same location is allowed. • Read and write on the same location at the same time is not allowed. There is no built in collision prevention or detection circuit in LSRAM. Revision 4 19 LSRAM LSRAM Resources Table 2-1 lists LSRAM rows and 18k blocks available in SmartFusion2 and IGLOO2 devices. Table 2-1 • SmartFusion2 and IGLOO2 LSRAM (18Kb Blocks) Resource Table Device M2S005/ M2GL005 M2S010/ M2GL010 M2S025/ M2GL025 M2S050/ M2GL050 M2S090/ M2GL090 M2S150/ M2GL150 Rows 1 2 2 3 4 6 LSRAM 18 K Blocks 10 21 31 69 109 236 Note: All numbers given above are per device. Functional Description This section provides the detailed description of the following: • Architecture Overview • Port List • Port Descriptions Architecture Overview SmartFusion2 and IGLOO2 LSRAM embedded memory includes the RAM1Kx18 macro. Figure 2-1 shows a simplified block diagram of the LSRAM memory block and Table 2-2 on page 21 provides the port descriptions. Figure 2-1 displays two independent data ports, the pipeline registers for read data delay, and the feed-through multiplexers to enable immediate access to the write data. 20 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric A _ DIN[ 17 : 0 ] A _ ADDR[ 13: 0 ] A _WEN[ 1 : 0 ] A _ BLK [ 2 : 0 ] Port A Row Decode Write Control Feed-through MUX A _ ARST_ N A _ CLK A _DOUT[ 17 : 0 ] Column Decode A_DOUT_LAT A_WMODE Memory Array A_ DOUT_ CLK 1 K x 18 Column B_DOUT[ 17 : 0 ] Decode B_WMODE B_ ADDR[ 13: 0 ] B_WEN [ 1: 0 ] ` B_BLK[ 2: 0 ] B_DOUT_LAT B_ DOUT_ CLK Port B Row Decode Write Control B_ ARST_ N B_ CLK Pipeline Register B_ DIN [ 17: 0 ] Figure 2-1 • Simplified Functional Block Diagram for LSRAM Port List Table 2-2 • Port List for LSRAM Macro (RAM1KX18) Direction Type1 Input Static Input Dynamic Port A Write enable High A_ADDR[13:0] Input Dynamic Port A Address input – A_DIN[17:0] Input Dynamic Port A Data input – Output Dynamic Port A Data output – A_BLK[2:0] Input Dynamic Port A Block select High A_WMODE Input Static Port A Feed-through write select High A_CLK Input Dynamic Port Name Description Polarity PORT A A_WIDTH[2:0] A_WEN[1:0] 2 A_DOUT[17:0] Port A Width/depth mode select Port A Clock – Rising Notes: 1. Static inputs are defined at design time and can be or are controlled by flash configuration bits. 2. If LSRAM is configured in Two-port mode with a write data width of x36/x32 and read data width of x36/x32, both the bits of A_WEN and B_WEN must be tied to logic 1 and should not be dynamically changed. Revision 4 21 LSRAM Table 2-2 • Port List for LSRAM Macro (RAM1KX18) (continued) Port Name Direction Type1 A_ARST_N Input Dynamic Port A Asynchronous reset A_DOUT_CLK Input Dynamic Port A Pipeline register clock Rising A_DOUT_LAT Input Static Port A Pipeline register Select Low A_DOUT_ARST_N Input Dynamic Port A Pipeline register asynchronous reset Low A_DOUT_EN Input Dynamic Port A Pipeline register enable High A_DOUT_SRST_N Input Dynamic Port A Pipeline register synchronous reset Low B_WIDTH[2:0] Input Static B_WEN[1:0]2 Input Dynamic Port B Write enable High B_ADDR[13:0] Input Dynamic Port B Address input – B_DIN[17:0] Input Dynamic Port B Data input – Output Dynamic Port B Data output – B_BLK[2:0] Input Dynamic Port B Block select High B_WMODE Input Static Port B Feed-through write select High B_CLK Input Dynamic Port B Clock B_ARST_N Input Dynamic Port B Asynchronous reset B_DOUT_CLK Input Dynamic Port B Pipeline register clock Rising B_DOUT_LAT Input Static Port B Pipeline register select Low B_DOUT_ARST_N Input Dynamic Port B Pipeline register asynchronous reset Low B_DOUT_EN Input Dynamic Port B Pipeline register enable High B_DOUT_SRST_N Input Dynamic Port B Pipeline register synchronous reset Low A_EN Input Static Port A power-down Low B_EN Input Static Port B power-down Low SII_LOCK Input Static Lock access to SII High Output Dynamic Busy signal from SII High Description Polarity Low PORT B B_DOUT[17:0] Port B Width/depth mode select – Rising Low Common Signals BUSY Notes: 1. Static inputs are defined at design time and can be or are controlled by flash configuration bits. 2. If LSRAM is configured in Two-port mode with a write data width of x36/x32 and read data width of x36/x32, both the bits of A_WEN and B_WEN must be tied to logic 1 and should not be dynamically changed. 22 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Port Descriptions A_WIDTH[2:0] and B_WIDTH[2:0] These signals represent the depth x width mode selections for each port. Table 2-3 shows the depth x width based on ports width selection. Table 2-3 • Depth/Width Mode Selection A_WIDTH/B_WIDTH Depth/Width 000 16K x 1 001 8K x 2 010 4k x 4 011 2K x 9 2K x 8 100 1K x 18 1K x 16 101 110 111 (Two-port) 512 x 36 512 x 32 A_WEN[1:0] and B_WEN[1:0] These signals represent the write enables for each port to select read/write operations. Table 2-4 shows the depth x width operations based on port write enable selection. Table 2-4 • Read/Write Operation Selection1,2 Depth x Width A_WEN/B_WEN Operation 16K x 1 00 Read operation 01 Write operation 01 Write [7:0] 10 Write [15:8] 11 Write [15:0] 8K x 2 4K x 4 2K x 8 2K x 9 1K x 16 1K x 18 16K x 1 8K x 2 4K x 4 2K x 8 2K x 9 1K x 16 Notes: 1. In Dual-port mode, every port reads when the corresponding write enable (A_WEN/B_WEN) is "00" and corresponding port select (A_BLK/B_BLK) is active. 2. In Two-port mode, the read port (Port A) reads in every clock cycle if A_BLK is active. Revision 4 23 LSRAM Table 2-4 • Read/Write Operation Selection1,2 (continued) Depth x Width A_WEN/B_WEN Operation 1K x 18 01 Write [8:0] 10 Write [17:9] 11 Write [17:0] 512 x 32 A_WEN[1:0] = “11” Write [31:0] (Two-port write-Port B) B_WEN[1:0] = “11” 512 x 36 A_WEN[1:0] = “11” (Two-port write-Port B) B_WEN[1:0] = “11” Write [35:0] Notes: 1. In Dual-port mode, every port reads when the corresponding write enable (A_WEN/B_WEN) is "00" and corresponding port select (A_BLK/B_BLK) is active. 2. In Two-port mode, the read port (Port A) reads in every clock cycle if A_BLK is active. A_ADDR[13:0] and B_ADDR[13:0] These signals represent the address buses for the two ports. In x1 mode 14 bits are used to address the 16,384 independent locations. In wider modes (x2, x4, etc.) fewer address bits are used. The used address bits are the most significant bits (MSB). The unused bits are the least significant bits (LSBs) and they must be grounded. Table 2-5 shows the address bus used and unused bits for depth x width selections. Table 2-5 • Address Bus Used and Unused Bits A_ADDR/B_ADDR Depth x Width Used Bits Unused bits (to be grounded) 16K x 1 [13:0] None 8K x 2 [13:1] [0] 4K x 4 [13:2] [1:0] 2K x 9 [13:3] [2:0] [13:4] [3:0] [13:5] [4:0] 2K x 8 1K x 18 1K x 16 512 x 36 A_DIN[17:0] and B_DIN[17:0] These signals represent the data input buses for the two ports. In Dual-port mode, the data width can range from 1 bit to 18 bits. In Two-port mode, Port B becomes the write-only port. Giving a write data width of 36 bits, A_DIN[17:0] becomes write data[35:18] and B_DIN[17:0] becomes write data[17:0]. The used bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded. Table 2-6 shows the data input buses used and unused bits for depth x width selections. Table 2-6 • Data Input Buses Used and Unused Bits A_DIN/B_DIN Depth x Width Used Bits Unused bits (to be grounded) 16K x 1 [0] [17:1] 8K x 2 [1:0] [17:2] 4K x 4 [3:0] [17:4] 24 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 2-6 • Data Input Buses Used and Unused Bits (continued) A_DIN/B_DIN Depth x Width Used Bits Unused bits (to be grounded) 2K x 8 [7:0] [17:8] 2K x 9 [8:0] [17:9] 1K x 16 [16:9] is [15:8] [17] [7:0] is [7:0] [8] 1K x 18 [17:0] None 512 x 32 A_DIN[16:9] is [31:24] A_DIN[17] A_DIN[7:0] is [23:16] A_DIN[8] B_DIN[16:9] is [15:8] B_DIN[17] B_DIN[7:0] is [7:0] B_DIN[8] A_DIN[17:0] is [35:18] None 512 x 36 B_DIN[17:0] is [17:0] A_DOUT[17:0] and B_DOUT[17:0] These signals represent the data output buses for the two ports. In Dual-port mode, the data width can range from 1 bit to 18 bits. In Two-port mode, Port A becomes the read-only port. Giving a read data width of 36 bits, A_DOUT[17:0] becomes read data[35:18] and B_DOUT[17:0] becomes read data[17:0]. The used bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded. Table 2-7 shows the data output buses used and unused bits for depth x width selections. Table 2-7 • Data Output Buses Used and Unused Bits Depth x Width A_DOUT/B_DOUT Used Bits Unused bits (to be grounded) 16K x 1 [0] [17:1] 8K x 2 [1:0] [17:2] 4K x 4 [3:0] [17:4] 2K x 8 [7:0] [17:8] 2K x 9 [8:0] [17:9] 1K x 16 1K x 18 512 x 32 512 x 36 [16:9] is [15:8] [17] [7:0] is [7:0] [8] [17:0] None A_DOUT[16:9] is [31:24] A_DOUT[17] A_DOUT[7:0] is [23:16] A_DOUT[8] B_DOUT[16:9] is [15:8] B_DOUT[17] B_DOUT[7:0] is [7:0] B_DOUT[8] A_DOUT[17:0] is [35:18] None B_DOUT[17:0] is [17:0] Revision 4 25 LSRAM A_BLK[2:0] and B_BLK[2:0] These signals represent the port select control signals for each port. Table 2-8 shows operations (Read, Write, and No operation) based on selection of port select control signals. Table 2-8 • Port Select Control Signals Port Select Signal Value Result A_BLK[2:0] 111 Perform read or write operation on Port A. A_BLK[2:0] 000 No operation in memory from Port A. Port A output is forced to logic 0. 001 010 011 100 101 110 B_BLK[2:0] 111 Perform read or write operation on Port B. B_BLK[2:0] 000 No operation in memory from Port B. Port B output is forced to logic 0. 001 010 011 100 101 110 A_WMODE and B_WMODE These signals represent the Write mode control signals for Port A and Port B. • Logic 0: Output data port holds the previous value. • Logic 1: Feed-through; write data appears on the corresponding output data port. In Two-port mode, feed-through write is not supported. A_CLK and B_CLK These signals represent the clock inputs for Port A and Port B. All inputs must be set up before the rising edge of the clock. The read or write operation begins with the rising edge. A_ARST_N and B_ARST_N These signals represent Active Low, asynchronous reset inputs for Port A and Port B. Assertion of these resets during read operation forces the data output lines to logic 0. Assertion of these resets during write operation results in garbage values written into the memory. A_DOUT_ARST_N and B_DOUT_ARST_N These signals represent Active Low, asynchronous reset inputs for the output pipeline registers for Port A and Port B. Assertion of these reset signals forces the data output to logic 0. In Non-pipelined mode, these inputs should be tied to logic 1. A_DOUT_LAT and B_DOUT_LAT These signals represent Latch mode inputs for the output pipeline registers for Port A and Port B. 26 • Logic 0: Register operation • Logic 1: Latch operation R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric A_DOUT_EN and B_DOUT_EN These signals represent Active High; enable inputs for the output pipeline registers for Port A and Port B. • Logic 1: Normal register operation • Logic 0: Register holds previous data A_DOUT_SRST_N and B_DOUT_SRST_N These signals represent Active Low, synchronous reset inputs for the output pipeline registers for Port A and Port B. Assertion of these reset signals forces the data output to logic 0. In Non-pipelined mode, these inputs should be tied to logic 1. A_EN and B_EN These are Active Low, power-down configuration bits for each port. SII_LOCK This control signal, when asserted to logic 1, locks the entire LSRAM memory for being accessed by the system controller interface bus (SII). The system controller can access the LSRAM for the following purposes: • Testing the memory • Moving data between LSRAM and embedded nonvolatile memory (eNVM) or external memories • Moving data between various LSRAMs or between uSRAMs and LSRAMs • LSRAMs cannot be accessed when the system controller is accessing them BUSY This signal acts as a Status signal when the system controller is accessing the particular LSRAM. Logic 1 on this signal indicates system controller access. This signal can be used to monitor the completion of LSRAM access. Memory Modes LSRAM can be configured as a dual-port SRAM or two-port SRAM. Dual-Port Mode LSRAM configured as dual-port SRAM provides a data storage capability of 18 Kbits with two independent access ports: Port A and Port B (Figure 2-2 on page 28). Read and write operations can be done from both the ports independently at any location as long as there is no collision. In Dual-port mode, the maximum data width can be x18 for either port. In Dual-port mode, each port of the LSRAM can be configured in the following depth x width configurations: • 1k x 18, 1k x 16 • 2k x 9, 2k x 8 • 4k x 4 • 8k x 2 • 16k x 1 Revision 4 27 LSRAM Figure 2-2 shows the data path for the dual-port SRAM (DPSRAM). A_DIN 18 B_DIN 18 PORT A PORT B DATA In A DATA In B Port B Signals Port A Signals DATA Out A Pipeline Register A DATA Out B Pipeline Register B 18 18 A_DOUT B_DOUT Figure 2-2 • Data Path for Dual-Port Mode Data can be written to either or both ports and also can be read from either or both ports. Each port has its own address, data in, data out, clock, block select, and write enable. The read and write operations are synchronous and require a clock edge. There is no collision detection or prevention circuit built into LSRAM. Simultaneous write operations from both the ports to the same address location result in data uncertainty. Simultaneous read and write operations from both the ports to the same address location results in correct data written into the memory but garbage values being read out. The read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output data appears in the next cycle. The write operation requires one clock cycle. When the read operation is configured with output pipeline registers, the input clock sourcing the pipeline registers has to be synchronized to the LSRAM's clock input; that is, A_DOUT_CLK should be synchronized to A_CLK and B_DOUT_CLK should be synchronized to B_CLK. Table 2-9 shows the data width configurations that are supported by LSRAM configured in Dual-port mode. Table 2-9 • Data Width Configurations for LSRAM in Dual-Port Mode Port A Data Width (represented as “x number of bits”) Port B Data Width (represented as “x number of bits”) x1 x1, x2, x4, x8, x16 x2 x1, x2, x4, x8, x16 x4 x1, x2, x4, x8, x16 x8 x1, x2, x4, x8, x16 x16 x1, x2, x4, x8, x16 28 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 2-9 • Data Width Configurations for LSRAM in Dual-Port Mode (continued) Port A Data Width (represented as “x number of bits”) Port B Data Width (represented as “x number of bits”) x9 x9, x18 x18 x9, x18 Two-Port Mode LSRAM configured as two-port SRAM provides a data storage capability of 18 Kbits, with Port A dedicated to read operations and Port B dedicated to write operations (Figure 2-3). In Two-port mode, the maximum data width for the read port (Port A) and the write port (Port B) is x36. A_DIN 18 B_DIN 18 PORT A DATA In A DATA In B Port B Signals Port A Signals DATA Out A DATA Out B PORT B Pipeline Register A Pipeline Register B 18 18 A_DOUT B_DOUT Figure 2-3 • Data Path for Two-Port Mode In Two-port mode, LSRAM can be configured in the following depth x width configurations: • 512 x 36 • 512 x 32 • 1k x 18, 1k x 16 • 2k x 9, 2k x 8 • 4k x 4 • 8k x 2 • 16k x 1 Revision 4 29 LSRAM There is no collision detection or prevention circuit built into LSRAM. Simultaneous read operations from Port A and write operations from Port B for the same address location should be avoided. This situation results in correct values being written into the memory, but garbage values will be read out from the memory. When the read port data width is configured as x36/x32: • Output data pins are borrowed from Port B, with Port A forming the MSB and Port B forming the LSB. • Input data pins are borrowed from Port A, with Port A forming the MSB and Port B forming the LSB. The read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output data appears in the next cycle. The write operation requires one clock cycle. When the read operation is configured with output pipeline registers, the input clock sourcing the pipeline registers has to be synchronized to the LSRAM's clock input. When the read data width is x18 or less, A_DOUT_CLK has to be synchronized to A_CLK. When the read data width is x36/x32, both A_DOUT_CLK and B_DOUT_CLK have to be synchronized to A_CLK. Table 2-10 shows the data width configurations supported by LSRAM configured in Two-port mode. Table 2-10 • Data Width Configurations for LSRAM in Two-Port Mode Read Port – Port A (represented as “x number of bits”) Write Port – Port B (represented as “x number of bits”) x1 x1, x2, x4, x8, x16 x2 x1, x2, x4, x8, x16 x4 x1, x2, x4, x8, x16 x8 x1, x2, x4, x8, x16 x9 x9, x18 x16 x1, x2, x4, x8, x16 x18 x9, x18 x32 x1, x2, x4, x8, x16, x32 x36 x9, x18, x36 Note: In Two-port mode, if the write data width is x36/x32 and read data width is x36/x32, both the bits of A_WEN and B_WEN have to be tied to logic 1 and should not be dynamically changed. Operating Modes Read Operation Flow-Through Read Flow-through mode indicates a non-pipelined read operation where the pipeline registers are bypassed and the data is displayed on the corresponding output in the same clock cycle. During flow-through read operation, the LSRAM can generate glitches on the data output buses. Therefore, Microsemi recommends using LSRAM with pipeline registers to avoid these read glitches. Pipelined Read In a pipelined read operation, the output data is registered at the pipeline registers, so the data is displayed on the corresponding output in the next clock cycle. In Pipeline mode, pipeline clock input and LSRAM's clock input should be synchronized and fed with a single clock source. 30 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Timing Diagram: Flow-Through Read and Pipeline Read • The addresses (A_ADDR, B_ADDR), BLK enables (A_BLK, B_BLK), and read enables (A_WEN, B_WEN = '0') should be set up before the rising edge of the clock (A_CLK, B_CLK). • For non-pipeline read operations, data comes on the output bus (A_DOUT, B_DOUT) after a delay of tCLK2Q (read access time without pipeline register) in the same cycle. • For pipeline read operations, the data is displayed on the output in the next clock cycle. Figure 2-4 shows the timing diagram for a read operation performed on LSRAM. tCY tCH A_CLK B_CLK tADDRSU tADDRHD t BLKSU tBLKHD t RDESU tRDEHD t CL A_ADDR [13:0] B_ADDR [13:0] A_BLK [2:0] B_BLK [2:0] A_WEN B_WEN tCLK2Q A_DOUT [17:0] (Non-Pipeline Read) B_DOUT [17:0] (Non-Pipeline Read) tPLCY A_DOUT_CLK B_DOUT_CLK tPLCLKMPWH tPLCLKMPWL tRDPLESU tRDPLEHD tRDPLESU tRDPLEHD A_DOUT_EN B_DOUT_EN t CLK2Q A_DOUT [17:0] (Pipeline Read) B_DOUT [17:0] (Pipeline Read) Figure 2-4 • Read Operation Timing Waveforms Table 2-11 • Read Operation Timing Parameters Parameters Description tCY Clock period tCH Clock minimum pulse width High tCL Clock minimum pulse width Low tADDRSU Address setup time tADDRHD Address hold time tBLKSU Block select setup time (With pipeline register enabled) Revision 4 31 LSRAM Table 2-11 • Read Operation Timing Parameters (continued) Parameters Description tBLKHD Block select hold time (With pipeline register enabled) tRDESU Read enable setup time (A_WEN, B_WEN =0) tRDEHD Read enable hold time (A_WEN, B_WEN =0) tCLK2Q Read access time with pipeline register Read access time without pipeline register tPLCY Pipelined clock period tPLCLKMPWH Pipelined clock minimum pulse width High tPLCLKMPWHL Pipelined clock minimum pulse width Low tRDPLESU Pipelined read enable setup time (A_DOUT_EN, B_DOUT_EN) tRDPLEHD Pipelined read enable hold time (A_DOUT_EN, B_DOUT_EN) Write Operation Feed-Through Write (write-bypass write) During this write operation, the data written into the memory array is displayed immediately on the corresponding data output for non-pipeline operation. For pipeline operation data output displays in next clock. The feed-through write option is not supported when the LSRAM is configured in Two-port mode. Simple Write In simple write, the data written into the memory array is not displayed on the corresponding data output until it is read out. The data output retains the last read data value. Timing Diagram: Feed-Through Write and Simple Write 32 • The addresses (A_ADDR, B_ADDR), BLK enables (A_BLK, B_BLK), and write enables (A_WEN, B_WEN = '1') should be set up before the rising edge of the clock (A_CLK, B_CLK). • For a feed-through write, the written data is displayed on the output (A_DOUT, B_DOUT) after a delay of tCLK2Q in the same clock cycle. • For a simple write, the written data is displayed on the output only when a read operation is performed on the same address. R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Figure 2-5 shows the timing diagram for a write operation performed on LSRAM. tCY tCH A_CLK B_CLK tADDRSU tCL tADDRHD A_AADR [13:0] B_AADR [13:0] tBLKSU tBLKHD tWESU tWEHD tDSU t DHD A_BLK [2:0] B_BLK [2:0] A_WEN B_WEN A_DIN [17:0] B_DIN [17:0] tCLK2Q A_DOUT [17:0] (Feed Through) B_DOUT [17:0] (Feed Through) Figure 2-5 • Write Operation Timing Waveforms Table 2-12 • Write Operation Timing Parameters Parameters Description tCY Clock period tCH Clock minimum pulse width High tCL Clock minimum pulse width Low tADDRSU Address setup time tADDRHD Address hold time tBLKSU Block select setup time (With pipeline register enabled) tBLKHD Block select hold time (With pipeline register enabled) tWESU Write enable setup time (A_WEN, B_WEN =1) tWEHD Write enable hold time (A_WEN, B_WEN =1) tDSU Data setup time tDHD Data setup time tCLK2Q Read access time with Feed-through write timing Revision 4 33 LSRAM Reset Operation The reset signals (A_ARST_N and B_ARST_N) are asynchronous Active Low signals. For any normal operation of LSRAM, these reset signals should be kept High. To reset the LSRAM, the reset signals must be Low. When reset is asserted (A_ARST_N or B_ARST_N forced Low), the LSRAM behaves as follows during read and write operations: 1. Read operation: If reset is asserted when the read operation is in process, the data output port is forced Low after a certain amount of delay. If the clock is High and the reset signal is asserted and then deasserted in the same High clock phase or Low clock phase, the data output stays Low until the next cycle. The data output changes its state only if a read operation or write operation in Bypass mode is performed on the LSRAM. In a simple write operation, the data output stays Low. 2. Write operation: The corrupted data is written into the memory. Therefore, Microsemi recommends to avoid asserting reset during write operation. Timing Diagram: Asynchronous Reset Operation tCY tCH t CL A_CLK B_CLK A_ARST_N B_ARST_N tR2Q A_DOUT B_DOUT Figure 2-6 • Asynchronous Reset Operation Table 2-13 • Asynchronous Reset Timing Parameters Parameters Description tCY Clock period tCH Clock minimum pulse width High tCL Clock minimum pulse width Low tR2Q Asynchronous reset to output propagation delay 34 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Block Select Operation The block select in LSRAM works like a chip select. When the block select (A_BLK and B_BLK) is High, the LSRAM is active and read and write operations can be performed. If the block select is Low, the LSRAM does not perform any read or write operations. It drives logic 0 on the data output pins until the next read cycle or write operation in Bypass mode. When the pipeline registers are used, the block select effect at the output is delayed by one pipeline clock cycle (the pipeline registers are independent of block select). Figure 2-7 shows the timing diagram for block select inputs for LSRAM. tCY A_CLK B_CLK tBLKMPW tBLKSU tBLKHD A_BLK [2:0] B_BLK [2:0] tBLK2Q A_DOUT [17:0] (Non-Pipeline Mode) B_DOUT [17:0] (Non-Pipeline Mode) t CLK2Q A_DOUT [17:0] (Pipeline Access) B_DOUT [17:0] (Pipeline Access) Figure 2-7 • Block Select Timings Table 2-14 • Block Selection Timing Parameters Parameters Description tCY Clock period tCH Clock minimum pulse width High tCL Clock minimum pulse width Low tBLKSU Block select setup time (with pipeline register enabled) tBLKHD Block select hold time (with pipeline register enabled) tBLKMPW Block select minimum pulse width tBLK2Q Block select to out disable time (when pipeline registers are disabled) tCLK2Q Read access time without pipeline register Revision 4 35 LSRAM Figure 2-6 on page 34 shows the timing diagram for asynchronous reset operation performed on LSRAM. Collision Collision scenarios arise between both ports of the LSRAM when a read operation is requested from one port and a write operation from the other port simultaneously on the same address location, or when a write operation occurs at the same location at the same time from both the ports. Table 2-15 describes the behavior of the LSRAM during the various cases of collisions. Table 2-15 • Collision Operation Description Operation Description Simultaneous read from Port A and Port B at the same Operation is allowed without any restrictions and data is location available on the output ports after the specified time, as described in the read timing diagrams in Figure 2-4 on page 31. Simultaneous read from Port A and write from Port B Not allowed. If the user does this, the new data will be at the same location written, but the output data will be corrupted. Simultaneous read from Port B and write from Port A Not allowed. If the user does this, the new data will be at the same location written, but the output data will be corrupted. Simultaneous write from Port A and Port B at the same Not allowed. If the data to be written is same on both the location ports, then data is successfully written. If the data is different, then the LSRAM cell has an undetermined state. There are no collision prevention or detection techniques available in LSRAM. The last 3 scenarios mentioned in Table 2-15 are not allowed on LSRAM and should be avoided. How to Use LSRAM The following sections describe how to use LSRAM in an application: • Design Flow • LSRAM Use Model Design Flow Libero SoC software provides separate configuration tools for Dual-port mode and Two-port mode. Using these configuration tools, LSRAM blocks can be configured in the required operating modes. These configuration tools generate the required HDL wrapper files for LSRAM with appropriate values assigned to the static signals. The generated LSRAM wrapper HDL files can be used in the design hierarchy by connecting the ports to the rest of the design. LSRAM Dual-Port Mode Figure 2-8 on page 37 shows the ports of the DPSRAM IP macro available in Libero SoC. Refer to the SmartFusion2 Dual-Port Large SRAM Configuration for detailed software configuration information on dual-port LSRAM. 36 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric tcy A_ CLK B_ CLK tblkmpw tblksu tblkhd A_ BLK [2 :0 ] B_ BLK [2 :0 ] tblk 2q A_DOUT [17:0] (non pipeline mode ) B_DOUT [17:0] (non pipeline mode ) tclk 2q A_DOUT [17:0] (pipeline access) B_DOUT [17:0] (pipeline access) Figure 2-8 • Ports of the LSRAM Configured as Dual-Port SRAM - DPSRAM Macro in Libero SoC Table 2-16 • Port Description for the DPSRAM Macro Port Name Direction Description A_CLK, B_CLK Input These signals represent the clock inputs for Port A and Port B. The same clock inputs also act as clock inputs for the output pipeline registers if configured as registers. All inputs must be set up before the rising edge of the clock. The read or write operation begins with the rising edge. A_ADDR, B_ADDR Input These signals represent the address inputs for Port A and Port B. A_BLK, B_BLK Input These signals represent the block-select inputs for Port A and Port B. A_DIN, B_DIN Input These signals represent the data inputs for Port A and Port B. A_WEN, B_WEN Input These signals represent the write enables for Port A and Port B. A_DOUT, B_DOUT Output These signals represent the data outputs for Port A and Port B. A_DOUT_EN, B_DOUT_EN Input These signals represent the Read data register Enable for Port A and Port B A_DOUT_SRST_N, B_DOUT_SRST_N Input These signals represent the Read data register Synchronous reset for Port A and Port B A_DOUT_ARST_N, B_DOUT_ARST_N Input These signals represent the Read data register Asynchronous reset for Port A and Port B Revision 4 37 LSRAM LSRAM Two-Port Mode Figure 2-9 shows the ports of the TPSRAM IP macro available in Libero SoC. Refer to the SmartFusion2 Two-Port Large SRAM Configuration document for detailed software configuration information for twoport LSRAM. Figure 2-9 • Ports of the LSRAM Configured as Two-Port SRAM - TPSRAM Macro in Libero SoC Table 2-17 • Port Description for the TPSRAM Macro Port Name Direction Description WCLK Input This signal represents the clock input for the write port (Port B). All write inputs must be set up before the rising edge of the clock. The write operation begins with the rising edge. RCLK Input This signal represents the clock input for the read port (Port A). The same clock inputs also act as clock inputs for the output pipeline registers if configured as registers. All read inputs must be set up before the rising edge of the clock. The read operation begins with the rising edge. ARST_N Input This signal represents Active Low, asynchronous reset inputs for Port A and Port B. Assertion of this reset during a read operation forces the data output lines to logic '0'. Assertion of these resets during a write operation results in garbage values written into the memory. WADDR Input This signal represents the address input for write Port B. RADDR Input This signal represents the address input for read Port A. WEN Input This signal represents the write enable for write Port B. WD Input This signal represents the data input for write Port B. REN Input This signal represents the read enable for read Port A. RD Output This signal represents the data output for read Port A. RD_EN Input This signal represents the Read data register enable. RD_SRST_N Input This signal represents the Read data register Synchronous reset. 38 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric LSRAM Macro (RAM 1Kx18) Libero SoC can be used to instantiate the LSRAM macro (RAM1Kx18) in the design. When using the RAM1Kx18 macro, care should be taken to provide appropriate values to the static signals to configure the LSRAM correctly before instantiating it in the design. Figure 2-10 shows the LSRAM macro RAM1Kx18 available in Libero SoC. Figure 2-10 • RAM1Kx18 Macro Associated LSRAM IP Cores In addition to LSRAM macros, Libero SoC also has IP cores available to access the LSRAM through AHB and APB slave interfaces through which configuration parameters such as bus (AHB/APB) data width, RAM selection (LSRAM and uSRAM), and depth of the memory can be set. Figure 2-11 and Figure 2-12 on page 40 show CoreAHBLSRAM and CoreAPBLSRAM, available in the Libero SoC catalog. Revision 4 39 LSRAM CoreAHBLSRAM Figure 2-11 shows CoreAHBLSRAM IP (LSRAM with AHB slave Interface), available in Libero SoC. Refer to the CoreAHBLSRAM Handbook for detailed software configuration information for Dual port LSRAM. Figure 2-11 • CoreAHBLSRAM IP in Libero SoC Table 2-18 • Port Description for the CoreAHBLSRAM IP Port Name Direction Description HCLK Input AHB clock. All AHB signals inside the block are clocked on the rising edge. HRESETn Input AHB Reset. The signal is Active Low. Asynchronous assertion and synchronous deassertion. Used to reset AHB registers in the block. S Input/Output AHB slave interface signals include: HSEL: AHBL slave select HADDR: AHBL address HWRITE: AHBL write HREADYIN: AHBL ready input CoreAPBLSRAM Figure 2-12 shows CoreAPBLSRAM IP (LSRAM with APB slave interface), available in Libero SoC. Refer to the CoreAPBLSRAM Handbook for detailed software configuration information. Figure 2-12 • CoreAPBLSRAM IP in Libero SoC 40 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 2-19 • Port Description for the CoreAPBLSRAM IP Port Name Direction Description PCLK Input APB clock. All APB signals inside the block are clocked on the rising edge. PRESETn Input APB Active Low asynchronous reset. S Input/Output APB Slave interface signals include: PSEL: APB slave select PADDR: APB Address PWDATA: APB write data PRDATA: APB read data PENABLE: APB strobe. Indicates the second cycle of an APB transfer. PWRITE: APB write PREADY: APB3 ready signal for future APB3 compliance. Used to extend APB transfer. PSLVERR: APB slave error. Indicates transfer failure. It is tied to Low. CoreFIFO IP Libero SoC IP catalog has a CoreFIFO IP, which can be configured as a soft FIFO for generation of FIFO control logic. Memory configuration can be selected as LSRAM, uSRAM, or external memory as per the design requirements. Refer to the CoreFIFO Handbook for detailed software configuration information. LSRAM Use Model Use Model 1: Two-port SRAM with a Write Data Width of x36 and Read Data Width of x18 LSRAM does not support any two-port configurations with a write port (Port B) data width of x36/x32 and a read port (Port B) data width of x18/x9/x8/x4/x2/x1. If such a configuration is required for the design, two LSRAM blocks must be used to implement these configurations. Following use model explains how to implement a two-port SRAM (using RAM1kx18 macros) with a write data width of x36 and a read data width of x18. The implementation has the following configurations: • Write port: 512 x 36 • Read port: 1024 x 18 • Read and write input clock: Two different clock sources • Pipelined read mode: Disabled Revision 4 41 LSRAM Figure 2-13 shows the two-port SRAM with a write data width of x36 and read data width of x18. RCLK {‘1’} 3 {REN,’1',’1'} {‘0’,RADDR[9:0],‘0’,’0',’0'} 14 {18'b0} {“00”} {‘1’} ARST_N {‘1’} {‘1’} WCLK {WEN,’1',’1'} {‘0’,WADDR[8:0],’0',‘0’,’0',’0'} {WD[26:19], WD[8:0]} {‘1’} 3 14 18 {“11”} {‘1’} {‘0’} {‘1’} {‘1’} A_CLK A_DOUT[17:0] A_ARST_N A_BLK[2:0] A_ADDR[13:0] B_DOUT[17:0] A_DIN[17:0] A_WEN[1:0] BUSY A_DOUT_EN A_DOUT_ARST_N A_DOUT_SRST_N A_DOUT_CLK A_DOUT_LAT A_WIDTH[2:0] A_WMODE A_EN {‘1’} {“100”} {‘0’} {‘1’} B_DOUT_LAT B_WIDTH[2:0] B_WMODE B_EN {‘1’} {18'b0} {“00”} {‘1’} {‘1’} {‘1’} {‘1’} {WD[35:27], WD[17:9]} {“11”} {‘1’} {‘0’} {‘1’} {‘1’} S_LOCK Not Connected LSRAM #1 A_CLK A_DOUT[17:0] A_ARST_N A_BLK[2:0] B_DOUT[17:0] A_ADDR[13:0] A_DIN[17:0] A_WEN[1:0] BUSY A_DOUT_EN A_DOUT_ARST_N A_DOUT_SRST_N A_DOUT_CLK RD[17:9] Not Connected Not Connected B_CLK B_ARST_N B_BLK[2:0] B_ADDR[13:0] B_DIN[17:0] B_WEN[1:0] B_DOUT_EN B_DOUT_ARST_N B_DOUT_SRST_N B_DOUT_CLK {‘1’} {“011”} {‘0’} {‘1’} A_DOUT_LAT A_WIDTH[2:0] A_WMODE A_EN {‘1’} {“100”} {‘0’} {‘1’} B_DOUT_LAT B_WIDTH[2:0] B_WMODE B_EN {‘0’} Not Connected B_CLK B_ARST_N B_BLK[2:0] B_ADDR[13:0] B_DIN[17:0] B_WEN[1:0] B_DOUT_EN B_DOUT_ARST_N B_DOUT_SRST_N B_DOUT_CLK {‘1’} {“011”} {‘0’} {‘1’} {‘0’} RD[8:0] S_LOCK LSRAM #2 Figure 2-13 • Two-Port SRAM With W36 and R18 The above implementation can be configured automatically using two-port LSRAM (TPSRAM) macro available in Libero SoC. Table 2-19 on page 41 shows the TPSRAM data width configurations that require two LSRAM blocks. 42 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 2-20 • Two-Port Configurations Requiring Two LSRAM Blocks Write Data Width Read Data width x36 x18 x32 x16 x36 x9 x32 x8 x32 x4 x32 x2 x32 x1 Revision 4 43 LSRAM List of Changes The following table shows important changes made in this document for each revision. Date Changes Revision 3 (May 2015) Page Removed all instances of and references to M2GL100 devices from Table 2-1 (SAR 62858) 20 Updated Table 2-15 (SAR 59994). 36 Merging the SmartFusion2 and IGLOO2 LSRAM chapter into one. NA Glossary Acronyms LSB Least significant bit LSRAM Large static random access memory MSB Most significant bit uSRAM Micro static random access memory Terminology Flow-through Read A read operation performed with the output not being registered by the output pipeline registers. Pipelined Read A read operation performed with the output being registered by the output pipeline registers. Simple Write A write operation in which the data written does not appear on the SRAM output ports. Feed-through Write (Write-Bypass Write) A write operation in which the data written appears on the SRAM output ports immediately for nonpipeline mode and next clock cycle for pipeline mode. Dual-Port Mode SRAM with two independent ports through which both read and write operation can be done. Two-Port Mode SRAM with two ports, one dedicated to read operations and the other dedicated to write operations. 44 R e visio n 4 3 – Micro SRAM (uSRAM) Introduction The SmartFusion2 SoC and IGLOO2 FPGA fabrics have embedded 1 Kbit micro SRAM (uSRAM) blocks used for storing data. These uSRAMs are arranged in multiple rows within the FPGA fabric can be accessed through the fabric routing architecture. The number of uSRAM blocks available varies among SmartFusion2 and IGLOO2 devices, as shown in Table 3-1 on page 46. For example, in the M2GL050 device there are 72 uSRAM blocks available, spread across three rows inside the fabric. Features The SmartFusion2 and IGLOO2 uSRAM blocks have the following features: • Each uSRAM block stores up to 1 Kbits (1,152 bits) of data and can be configured in any of the following depth × width combinations: 64 × 18, 64 × 16, 128 × 9, 128 × 8, 256 × 4, 512 × 2 and 1,024 × 1. • Each uSRAM has 2 read data ports (Port A and Port B) and 1 write data port (Port C). • Read operations can be performed in both Synchronous and Asynchronous modes. The write operation is always synchronous. • The 2 read ports have address/block select registers for enabling Synchronous mode operation. These registers can also be configured as transparent latches for Asynchronous mode operations. • In Pipelined mode, the 2 read ports have output registers with independent clocks. These Output pipeline registers can also be configured as transparent latches for Asynchronous mode operation. • Due to the availability of separate input address and output pipeline registers, read operations through Port A and Port B in uSRAM can be performed in 6 different modes: – Synchronous read mode without pipeline registers (Synchronous-Asynchronous mode) – Synchronous read mode with pipeline registers (Synchronous-Synchronous mode) – Asynchronous read mode without pipeline registers (Asynchronous-Asynchronous mode) – Asynchronous read mode with pipeline registers (Asynchronous-Synchronous mode) – Synchronous read mode with pipeline registers configured as latches – Asynchronous read mode with pipeline registers configured as latches • Separate synchronous and asynchronous resets are provided for the input address/block select registers. These resets can be used to initialize the read ports. • The output pipeline registers have separate synchronous and asynchronous resets which provide independent control to these registers. • uSRAM can operate up to 400 MHz in Synchronous-Synchronous read mode through Port A and Port B, including a write operation at 400 MHz through Port C. • The two read ports are independent of each other and simultaneous read operations can be performed from both ports at the same address location. • Simultaneous read and write operations at the same location are not allowed. Revision 4 45 Micro SRAM (uSRAM) uSRAM Resource Table Table 3-1 lists uSRAM blocks available for SmartFusion2 and IGLOO2 devices. Table 3-1 • SmartFusion2 and IGLOO2 uSRAM (1Kb Blocks) Resource Table Device Number of uSRAM SmartFusion2/IGLOO2 Rows Number per Row Total M2S005/M2GL005 1 11 11 M2S010/M2GL010 2 11 22 M2S025/M2GL025 2 17 34 M2S050/M2GL050 3 24 72 M2S090/M2GL090 4 28 112 M2S150/M2GL150 6 40 240 Functional Description The following sections provide the detailed description of the following: • Architecture Overview • Port List • Port Description Architecture Overview SmartFusion2 and IGLOO2 uSRAM embedded memory includes the RAM64X18 macro, available in Libero SoC software. Figure 3-1 on page 47 shows a simplified block diagram of the uSRAM memory block with two read data ports, one write data port and pipeline registers at read port. Table 3-2 on page 47 provides the port descriptions. 46 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric A_ADDR[9:0] A_BLK [1:0] A_ADDR_LAT A_ADDR_CLK C_ADDR[9:0] C_WEN A_DOUT_LAT Port C Write Control C_DIN[17:0] A_DOUT[17:0] Port A Read Decode Memory Array 64 x 18 A_DOUT_CLK B_DOUT[17:0] Port B Read Decode B_DOUT_LAT C_CLK B_DOUT_CLK Pipeline Registers B_ADDR[9:0 ] B_BLK [1:0] B_ADDR_LAT B_ADDR_CLK Figure 3-1 • Simplified Functional Block Diagram of uSRAM Port List Table 3-2 • Port List for uSRAM Direction Type* A_ADDR[9:0] Input Dynamic Address input A_BLK[1:0] Input Dynamic Block select A_WIDTH[2:0] Input Static A_DOUT[17:0] Output A_DOUT_ARST_N Port Name Descriptions Polarity Port A – Active High Depth x width mode selection – Dynamic Data output – Input Dynamic Pipeline register asynchronous reset A_DOUT_CLK Input Dynamic Pipeline register clock input A_DOUT_EN Input Dynamic Pipeline register enable Active High A_DOUT_LAT Input Static Pipeline Latch mode input Active High A_DOUT_SRST_N Input Dynamic Pipeline register synchronous reset Active Low A_ADDR_CLK Input Dynamic Address register clock Active Low Rising Rising Note: *Static inputs are defined at design time and are controlled by flash configuration bits. Revision 4 47 Micro SRAM (uSRAM) Table 3-2 • Port List for uSRAM (continued) Direction Type* A_ADDR_EN Input Dynamic A_ADDR_LAT Input A_ADDR_SRST_N A_ADDR_ARST_N Port Name Descriptions Polarity Address register enable Active High Static Address register Latch mode input Active High Input Dynamic Address register synchronous reset Active Low Input Dynamic Address register asynchronous reset Active Low B_ADDR[9:0] Input Dynamic Address input B_BLK[1:0] Input Dynamic Block select B_WIDTH[2:0] Input Static B_DOUT[17:0] Output B_DOUT_ARST_N Port B – Active High Depth x width mode selection – Dynamic Data output – Input Dynamic Pipeline register Asynchronous reset B_DOUT_CLK Input Dynamic Pipeline register clock input B_DOUT_EN Input Dynamic Pipeline register enable Active High B_DOUT_LAT Input Static Pipeline Latch mode input Active High B_DOUT_SRST_N Input Dynamic Pipeline register synchronous reset Active Low B_ADDR_CLK Input Dynamic Address register clock B_ADDR_EN Input Dynamic Address register enable Active High B_ADDR_LAT Input Static Address register Latch mode input Active High B_ADDR_SRST_N Input Dynamic Address register synchronous reset Active Low B_ADDR_ARST_N Input Dynamic Address register asynchronous reset Active Low C_ADDR[9:0] Input Dynamic Address input C_BLK[1:0] Input Dynamic Block select C_WIDTH[2:0] Input Static Output C_CLK C_WEN Active Low Rising Rising Port C – Active High Depth x width mode selection – Dynamic Data output – Input Dynamic Clock input Rising Input Dynamic Write enable A_EN Input Static Port A power-down Low B_EN Input Static Port B power-down Low C_EN Input Static Port C power-down Low SII_LOCK Input Static Lock access to SII High Output Dynamic Busy signal while SII access High C_DIN[17:0] Active High Common Signals Busy Note: *Static inputs are defined at design time and are controlled by flash configuration bits. 48 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Port Description A_WIDTH[2:0], B_WIDTH [2:0], and C_WIDTH [2:0] These signals represent the depth x width mode selections for each port. Table 3-3 shows the depth x width based on ports width selection. Table 3-3 • Width/Depth Mode Selection A_WIDTH / B_WIDTH / C_WIDTH Depth x Width 000 1K x 1 001 512 x 2 010 256 x 4 128 x 9 011 128 x 8 100 101 64 x 18 110 64 x 16 111 A_ADDR[9:0], B_ADDR [9:0], and C_ADDR [9:0] These signals represent the address buses for the three ports (two read and one write). In ×1 mode, 10 bits are used to address the 1,152 independent locations. In wider modes such as ×2 and ×4, fewer address bits are used. The used address bits are the most significant bits (MSB). The unused bits are the least significant bits (LSBs) and they must be grounded. Table 3-4 shows the address bus used and unused bits for depth × width selections. Table 3-4 • Address Bus Used and Unused Bits Depth x Width A_ADDR / B_ADDR / C_ADDR Used Bits Unused Bits (to be grounded) 1K x 1 [9:0] None 512 x 2 [9:1] [0] 256 x 4 [9:2] [1:0] [9:3] [2:0] [9:4] [3:0] 128 x 9 128 x 8 64 x 18 64 x 16 Revision 4 49 Micro SRAM (uSRAM) C_DIN[17:0] This signal represents the data input bus for the write Port C. The used bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded. Table 3-5 shows the data input bus used and unused bits for depth × width selections. Table 3-5 • Data Input Buses Used and Unused Bits Depth x Width C_DIN Used Bits Unused Bits (to be grounded) 1K x 1 [0] [17:1] 512 x 2 [1:0] [17:2] 256 x 4 [3:0] [17:4] 128 x 8 [7:0] [17:8] 128 x 9 [8:0] [17:9] [16:9] [17] [7:0] [8] [17:0] None 64 x 16 64 x 18 A_DOUT[17:0] and B_DOUT[17:0] These signals represent the data output buses for the two ports (Port A and Port B). The used bits for any mode are LSB justified in the data bus and the unused MSB bits must be grounded. Table 3-6 shows the data output bus used and unused bits for different depth x width selections. Table 3-6 • Data Output Buses Used and Unused Bits Depth x Width A_DOUT/B_DOUT Used Bits Unused Bits 1K x 1 [0] [17:1] 512 x 2 [1:0] [17:2] 256 x 4 [3:0] [17:4] 128 x 8 [7:0] [17:8] 128 x 9 [8:0] [17:9] [16:9] [17] [7:0] [8] [17:0] None 64 x 16 64 x 18 50 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric A_BLK[1:0], B_BLK [1:0], and C_BLK [1:0] These signals represent the port select control signal for each port. Table 3-7 shows the operations (Read, write and no operation) based on selection of port select control signals. Table 3-7 • Port Select Control Signals Port Select Signal Value A_BLK[1:0] B_BLK[1:0] C_BLK[1:0] Operation 11 Perform read operation on Port A. 00 - 01 Port A is not selected and its read data will be logic 0. 10 - 11 Perform read operation on Port B. 00 - 01 Port B is not selected and its read data will be logic 0. 10 - 11 Perform write operation on Port C. 00 - 01 Port C is not selected. 10 - C_CLK This signal represents the clock signal for Port C. Ensure all inputs are set up before the first rising clock edge. The write operation starts at the rising edge of this clock signal. C_WEN This signal represents the write enable for Port C. A_ADDR_CLK and B_ADDR_CLK These signals represent the clock inputs for the input address/block select registers for Port A and Port B. In Synchronous read mode, set up the address and block select inputs before the rising edge of these clocks. In Asynchronous mode, tie these clocks to logic 1. A_DOUT_CLK and B_DOUT_CLK These signals represent the clock inputs for the output pipeline registers for Port A and Port B. In Pipelined mode, the output data appears in the next clock cycle. In Latch mode operation, the output data appears in the same clock cycle. When the registers are configured as transparent, tie these inputs to logic 1. A_ADDR_LAT and B_ADDR_LAT These signals represent Latch mode inputs for the input address/block select registers for Port A and Port B. • Logic 0: Register operation • Logic 1: Transparent operation A_DOUT_LAT and B_DOUT_LAT These signals represent Latch mode inputs for the output pipeline registers for Port A and Port B. • Logic 0: Register operation • Logic 1: Latch/Transparent operation Revision 4 51 Micro SRAM (uSRAM) A_ADDR_ARST_N and B_ADDR_ARST_N These signals represent Active Low, asynchronous reset inputs for the input address/block select registers for Port A and Port B. The assertion of these reset signals forces the address and block select input registers to logic 0, which in turn forces the data output to logic 0. When these registers are configured as transparent, tie these inputs to logic 1. A_DOUT_ARST_N and B_DOUT_ARST_N These signals represent Active Low, asynchronous reset inputs for the output pipeline registers for Port A and Port B. Assertion of these reset signals forces the data output to logic 0. When these registers are configured as transparent, tie these inputs to logic 1. A_ADDR_SRST_N and B_ADDR_SRST_N These signals represent Active Low, synchronous reset inputs for the input address/block select registers for Port A and Port B. The assertions of these reset signals forces the address input registers and block select registers to logic 0, which in turn forces the data output to logic 0. When the registers are configured as transparent, these inputs should be tied to logic 1. A_DOUT_SRST_N and B_DOUT_SRST_N These signals represent Active Low, synchronous reset inputs for the output pipeline registers for Port A and Port B. Assertion of these reset signals forces the data output to logic 0. In non-pipelined mode of operation, tie these inputs to logic 1. A_ADDR_EN and B_ADDR_EN These signals represent Active High enable inputs for the input address/block select registers for Port A and Port B. When logic 0 is applied on these inputs, the input registers hold the previous input address. When logic 1 is applied on these inputs, the input registers behave as normal D flip-flops. When the registers are configured as transparent, these inputs should be tied to logic 1. A_DOUT_EN and B_DOUT_EN These signals represent Active High enable inputs for the output pipeline registers for Port A and Port B. When logic 0 is applied on these inputs, the pipeline registers hold the previously read data out. In nonpipelined mode, tie these inputs to logic 1. A_EN, B_EN, and C_EN These are Active Low, power-down configuration bits for each port. SII_LOCK This control signal, when asserted to logic 1, locks the entire uSRAM memory from being accessed by the system controller interface bus (SII). The system controller can access the uSRAM for the following reasons: • Testing the memory • Moving data between uSRAM and eNVM or external memories • Moving data between various uSRAMs • Moving data between uSRAMs and LSRAMs uSRAMs cannot be accessed while the system controller is accessing them. BUSY This signal acts as a status signal when the system controller is accessing a particular uSRAM. Logic 1 on this signal indicates system controller access. This signal can be used to monitor the completion of uSRAM access. 52 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Operating Modes Read Operation uSRAM blocks are read through two ports: Port A and Port B. There are six modes for read operations: • Synchronous read mode without pipeline registers (Synchronous-Asynchronous mode) • Synchronous read mode with pipeline registers (Synchronous-Synchronous mode) • Synchronous read mode with pipeline registers configured as latches • Asynchronous read mode without pipeline registers (Asynchronous-Asynchronous mode) • Asynchronous read mode with pipeline registers (Asynchronous-Synchronous mode) • Asynchronous read mode with pipeline registers configured as latches Synchronous Read Mode Synchronous read mode requires that the input registers for the address and block select inputs are configured in Flip-flop mode (A_ADDR_LAT or B_ADDR_LAT = 0). Similarly, on the output side, the pipeline registers can be configured as registers, latches, or transparent, providing read data as registered, latched, or asynchronous. When the pipeline registers are configured as normal registers, the clock inputs of both the input and output registers should be synchronous to each other and should be fed with a single clock source. If these registers are configured as a transparent latch, the clock inputs should be tied to High. In Latch mode, both the input and output clocks should be in opposite phase. Microsemi recommends configuring the pipeline registers, in either the register or Latch mode during read operation to avoid glitches on the read output data lines. In Synchronous read mode, the address (A_ADDR or B_ADDR) and block-select (A_BLK or B_BLK) inputs must satisfy the setup and hold timings with respect to the input clocks (A_ADDR_CLK or B_ADDR_CLK). Synchronous Read Mode without Pipeline Registers (Synchronous-Asynchronous Read Mode) • The input registers are configured in Synchronous read mode. • The output pipeline registers are configured as transparent. • This mode is achieved by setting A_DOUT_LAT or B_DOUT_LAT = 1, A_DOUT_CLK or B_DOUT_CLK = 1, A_DOUT_ARST_N or B_DOUT_ARST_N = 1, A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1, A_BLK = 1, B_BLK = 1. • Figure 3-2 on page 54 shows the synchronous asynchronous operation with data output behavior when block select inputs are deasserted (any bit forced to logic 0). • The output data is displayed immediately-in the same clock cycle in which the address and block select inputs were registered. • The uSRAM can generate glitches on the output buses when used without the pipeline registers. Revision 4 53 Micro SRAM (uSRAM) Table 3-8 describes the timing parameter values for Synchronous read mode without pipeline registers, with reference to timing waveforms, as shown in Figure 3-2. tCLKMPWH A_ADDR_CLK B_ADDR_CLK tCLKMPWL tCY tADDRSU tADDRHD A_ADDR[9:0] B_ADDR[9:0] A1 A0 tBLKSU tBLKHD tBLKSU tBLKHD A_BLK B_BLK tCLK2Q A_DOUT[17:0] B_DOUT[17:0] tBLK2Q D-1 D0 Figure 3-2 • Timing Waveforms for Synchronous-Asynchronous Read Operation Table 3-8 • Timing Parameters for Synchronous-Asynchronous Read Operation Parameter Description tCY Read clock period tCLKMPWH Read clock minimum pulse width High time tCLKMPWL Read clock minimum pulse width Low time tADDRSU Read address setup time in Synchronous mode tADDRHD Read address hold time in Synchronous mode tBLKSU Read block select setup time (when pipeline registers enabled) tBLKHD Read block select hold time (when pipeline registers enabled) tCLK2Q Read access time without pipeline registers tBLK2Q Read block select to out disable/enable time Synchronous Read Mode with Pipeline Registers (Synchronous-Synchronous Read Mode) 54 • The input registers are configured in Synchronous read mode. • The output pipeline registers are configured as edge-triggered registers (Pipelined mode). • Pipelined mode is achieved by setting A_DOUT_LAT or B_DOUT_LAT = 0, A_DOUT_CLK or B_DOUT_CLK = rising edge clock, A_DOUT_ARST_N or B_DOUT_ARST_N = 1, A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1, A_BLK = 1, B_BLK = 1. • The input register clock and pipeline register clock must be synchronous to each other; hence they should be sourced from the same clock input. • The output data appears on the output bus in the next clock cycle. R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 3-9 describes the timing parameter values for Synchronous read mode with pipeline registers. Refer to Figure 3-3 for timing waveforms. tCLKMPWH A_ADDR_CLK B_ADDR_CLK tCLKMPWL tCY tADDRSU tADDRHD A_ADDR[9:0] B_ADDR[9:0] A1 A0 tBLKSU tBLKHD A2 tBLKSU tBLKHD A_BLK B_BLK tPLCLKMPWH tPLCY tPLCLKMPWL A_DOUT_CLK B_DOUT_CLK tCLK2Q A_DOUT[17:0] B_DOUT[17:0] D-2 tCLK2Q tCLK2Q D0 D-1 Figure 3-3 • Timing Waveforms for Synchronous-Synchronous Read Operation Table 3-9 • Timing Parameters for Synchronous-Synchronous Read Operation Parameter Description tCY Read clock period tCLKMPWH Read clock minimum pulse width High time tCLKMPWL Read clock minimum pulse width Low time tADDRSU Read address setup time in Synchronous mode tADDRHD Read address hold time in Synchronous mode tBLKSU Read block select setup time (when pipeline registers enabled) tBLKHD Read block select hold time (when pipeline registers enabled) tCLK2Q Read access time with pipeline registers tPLCY Read pipeline clock period tPLCLKMPWH Read pipeline clock minimum pulse width High tPLCLKMPWL Read pipeline clock minimum pulse width Low Synchronous Read Mode with Pipeline Registers Configured as Latches • The input registers are configured in Synchronous read mode. • The output pipeline registers are configured as level-sensitive latches with A_DOUT_CLK or B_DOUT_CLK acting as latch enables. • The pipeline registers are configured as latches by setting A_DOUT_LAT or B_DOUT_LAT = 1. • The pipeline latches are enabled by the pipeline register clock (A_DOUT_CLK or B_DOUT_CLK) with opposite phase with respect to the input register clock (A_ADDR_CLK or B_ADDR_CLK). During the low phase of the pipeline clocks, the pipeline latches hold the previous data until the latch inputs become stable. Revision 4 55 Micro SRAM (uSRAM) • In this case, the read access time is related to the negative edge of the address input clock (A_ADDR_CLK or B_ADDR_CLK)-the positive edge of the pipeline clock (A_DOUT_CLK or B_DOUT_CLK). • This mode is used to moderate the effect of glitches that can appear on the uSRAM's data output bus when used without the pipeline registers (when uSRAM is configured in SynchronousAsynchronous read mode). Table 3-10 describes the timing parameter values for Synchronous read mode with Latched mode. Refer to the timing waveforms shown in Figure 3-4. tCLKMPWH A_ADDR_CLK B_ADDR_CLK tCLKMPWL tCY tADDRSU tADDRHD A_ADDR[9:0] B_ADDR[9:0] A1 A0 tBLKSU tBLKHD A2 tBLKSU tBLKHD A_BLK B_BLK A_DOUT_CLK B_DOUT_CLK tCLPL1 tCLK2Q A_DOUT[17:0] B_DOUT[17:0] D-1 D0 Figure 3-4 • Timing Waveforms for Synchronous Latched Read Operation Table 3-10 • Timing Parameters for Synchronous Latched Read Operation Parameter Description tCY Read clock period tCLKMPWH Read clock minimum pulse width High time tCLKMPWL Read clock minimum pulse width Low time tADDRSU Read address setup time in Synchronous mode tADDRHD Read address hold time in Synchronous mode tBLKSU Read block select setup time (when pipeline registers enabled) tBLKHD Read block select hold time (when pipeline registers enabled) tCLK2Q Read access time with pipeline registers in Latch mode tCLPL1 Minimum pipeline clock low phase in order to prevent glitches with pipeline register in Latch mode. Asynchronous Read Mode Asynchronous read mode requires that the input registers for the address and block-select inputs are configured as transparent (A_ADDR_LAT or B_ADDR_LAT = 1, A_ADDR_CLK or B_ADDR_CLK = 1, A_ADDR_EN or B_ADDR_EN = 1, A_ADDR_ARST_N or B_ADDR_ARST_N = 1, A_ADDR_SRST_N or B_ADDR_SRST_N = 1, A_BLK = 1, B_BLK = 1). 56 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Asynchronous Read Mode Without Pipeline Registers (Asynchronous-Asynchronous Mode) • The input registers are configured in Asynchronous read mode. • The output pipeline registers are configured as transparent (non-pipelined operation). • The pipeline registers can be made transparent by setting A_DOUT_LAT or B_DOUT_LAT = 1, A_DOUT_CLK or B_DOUT_CLK = 1, A_DOUT_ARST_N or B_DOUT_ARST_N = 1, A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1. • After the input address is provided, the output data is displayed on the output data bus after a ta2qr delay (Figure 3-5). • The uSRAM can generate glitches on the data output bus when used without the pipeline register. Figure 3-5 shows a timing diagram for Asynchronous-Asynchronous read mode for uSRAM and Table 3-11 lists the description of various timing parameters. A_ADDR[9:0] B_ADDR[9:0] A0 A1 A_BLK B_BLK tBLKMPW tBLK2Q A_DOUT[17:0] B_DOUT[17:0] A2 D-1 tBLK2Q D0 D1 tCLK2Q Figure 3-5 • Timing Waveforms for Read Operations with Asynchronous Inputs Without Pipeline Registers Table 3-11 • Timing Parameters of the Asynchronous Read Mode Without Pipeline Registers Parameter Description tCLK2Q Read access time without pipeline register tBLK2Q Read block select to out disable/enable time tBLKMPW Read block select minimum pulse width Asynchronous Read Mode with Pipeline Registers (Asynchronous-Synchronous Mode) • The input registers are configured in Asynchronous read mode. • The output pipeline registers are configured as registers (Pipelined mode). • Pipelined mode is achieved with A_DOUT_LAT or B_DOUT_LAT = 0, A_DOUT_CLK or B_DOUT_CLK = rising edge clock, A_DOUT_ARST_N or B_DOUT_ARST_N = 1, A_DOUT_SRST_N = 1 or B_DOUT_SRST_N = 1, A_DOUT_EN or B_DOUT_EN = 1, A_BLK = 1, B_BLK = 1. • After the input address is provided, the output data is displayed on the output data bus after the next rising edge of the pipeline register input clock. Revision 4 57 Micro SRAM (uSRAM) Figure 3-6 shows the timing diagrams for Asynchronous-Synchronous read mode for uSRAM. tADDRHD A_ADDR[9:0] B_ADDR[9:0] A0 tBLKSU tBLKSU A_BLK B_BLK A2 A1 tADDRSU tBLKHD tBLKHD tPLCLKMPWL A_DOUT_CLK B_DOUT_CLK tPLCLKMPWH tCLK2Q A_DOUT[17:0] B_DOUT[17:0] D0 tCLK2Q Figure 3-6 • Timing Waveforms for Read Operations with Asynchronous Inputs with Pipeline Registers Table 3-12 lists the timing parameters. Table 3-12 • Timing Parameters of the Asynchronous Read Mode with Pipeline Registers Parameter Description tPLCY Read pipeline clock period tPLCLKMPWH Read pipeline clock minimum pulse width High tPLCLKMPWL Read pipeline clock minimum pulse width Low tADDRSU Read address setup time in Synchronous mode tADDRHD Read address hold time in Synchronous mode tBLKSU Read block select setup time (when pipeline registers enabled) tBLKHD Read block select hold time (when pipeline registers enabled) tCLK2Q Read access time with pipeline register Asynchronous Read Mode with Pipeline Registers Configured as Latches 58 • The input registers are configured in Asynchronous read mode. • The output pipeline registers are configured as level-sensitive latches with A_DOUT_CLK or B_DOUT_CLK acting as latch enables. • The pipeline registers can be configured as latches by setting A_DOUT_LAT or B_DOUT_LAT =1. • After the input address is provided, the output data is displayed on the output data bus when the next high level comes on the latch enable inputs-A_DOUT_CLK or B_DOUT CLK. • This mode is provided to moderate the effect of the glitches which can occur on uSRAM's data output buses when used without the pipeline registers. R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Figure 3-7 shows the timing diagrams for Asynchronous read mode with latched outputs-pipeline registers configured as latches. A_ADDR[9:0] B_ADDR[9:0] A0 tADDRSU tADDRHD tBLKSU tBLKSU A_BLK B_BLK A_DOUT_CLK B_DOUT_CLK A2 A1 tBLKHD tBLKHD tCLPL1 A_DOUT[17:0] B_DOUT[17:0] D0 tCLK2Q tCLK2Q D2 Figure 3-7 • Timing Waveforms for Read Operations with Asynchronous Inputs with Latched Outputs Table 3-13 describes the timing parameters. Table 3-13 • Timing Parameters of the Asynchronous Read Mode with Latched Outputs Parameter Description tCLPL1 Minimum pipeline clock low phase in order to prevent glitches with pipeline register in Latch mode tADDRSU Read address setup time in Synchronous mode tADDRHD Read address hold time in Synchronous mode tBLKSU Read block select setup time (when pipeline registers enabled) tBLKHD Read block select hold time (when pipeline registers enabled) tCLK2Q Read access time with pipeline register Write Operation • Port C is the only port through which a write operation can be performed on uSRAM. • The write operation is purely synchronous and all operations are synchronized to the rising edge of the Port C clock input (C_CLK). • The write inputs-C_ADDR, C_BLK, C_WEN, and C_DIN-have to satisfy the setup and hold timings with respect to the rising edge of the C_CLK input for a successful write operation. • If all the inputs meet the required timing parameters, the input data is written into uSRAM in one clock cycle. Revision 4 59 Micro SRAM (uSRAM) Figure 3-8 shows the timing waveforms for a Port C write operation. tCCLKMPWL tCCLKMPWH tCCY C_CLK tADDRCSU tADDRCHD tADDRCSU tADDRCHD C_ADDR A0 A1 tBLKCSU tBLKCHD C_BLK[1:0] C_WEN C_DIN tADDRCSU tADDRCHD A2 tBLKCSU tBLKCHD tWECSU tWECHD tWECSU tWECHD tDINCSU tDINCHD tDINCSU tDINCHD D1 D0 D0 Data written in SRAM tDINCSU tDINCHD D2 D1 Figure 3-8 • Timing Waveforms for the Write Operation Table 3-14 describes the timing parameters. Table 3-14 • Timing Parameters of the Write Operation Parameter Description tCCY Write clock period tCCLKCMPWH Write clock minimum pulse width High tCCLKCMPWL Write clock minimum pulse width Low tADDRCSU Write address setup time tADDRCHD Write address hold time tBLKCSU Write block setup time tBLKCHD Write block hold time tWECSU Write enable setup time tWECHD Write enable hold time tDINCSU Write input data setup time tDINCHD Write input data hold time Reset Operation The reset signals (A_ADDR_ARST_N, B_ADDR_ARST_N) are asynchronous Active Low signals for the address and block select input registers for Port A and Port B. The assertion of these reset signals forces the address and block select input registers to logic 0, which in turn forces the data output to logic 0. When the registers are configured as transparent, tie these inputs to logic 1. 60 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Figure 3-9 shows the timing waveforms for these asynchronous reset signals. tCLKMPWH A_ADDR_CLK B_ADDR_CLK A_ADDR[9:0] B_ADDR[9:0] tCLKMPWL tCY tADDRSU A0 A2 A1 tADDRHD A_BLK B_BLK A_ADDR_ARST_ N B_ADDR_ARST_N tR2Q A_DOUT[17:0] B_DOUT[17:0] D-1 D0 tCLK2Q Figure 3-9 • Timing Waveforms for Asynchronous Reset Table 3-15 lists the Timing parameters for the asynchronous reset. Table 3-15 • Timing Parameters of the Asynchronous Reset Parameter Description tCY Read clock period tCLKMPWH Read clock minimum pulse width High tCLKMPWL Read clock minimum pulse width Low tADDRSU Read address setup time tADDRHD Read address hold time tR2Q Read asynchronous reset to output propagation delay tCLK2Q Read access time without pipeline register The reset signals (A_ADDR_SRST_N, B_ADDR_SRST_N) are synchronous Active Low signals for the address and block select input registers for Port A and Port B. The assertion of these reset signals forces the address and block select input registers to logic 0, which in turn forces the data output to logic 0. Revision 4 61 Micro SRAM (uSRAM) Figure 3-10 shows the timing waveform for synchronous reset. tCLKMPWL tCLKMPWH A_ADDR_CLK B_ADDR_CLK tCY tSRSTSU tSRSTHD A_ADDR_SRST_N B_ADDR_SRST_N tCLK2Q A_DOUT B_DOUT Figure 3-10 • Timing Waveforms for Synchronous Reset Table 3-16 lists the timing parameters of the synchronous reset. Table 3-16 • Timing Parameters of the Synchronous Reset Parameter Description tCY Read clock period tCLKMPWH Read clock minimum pulse width High tCLKMPWL Read clock minimum pulse width Low tSRSTSU Read synchronous reset setup time tSRSTHD Read synchronous reset hold time tCLK2Q Read synchronous reset to output propagation delay Collision Collision between ports occurs when the read and write operations are requested from two or all three ports at the same time at the same address location. Table 3-17 lists the different scenarios for collision. Table 3-17 • Collision Scenarios Operation Comments Simultaneous read from Port A and read from Port B to Allowed since the read ports are independent of each other. the same address location Both read ports deliver correct read data. Simultaneous read from Port A and write to Port C to Collision occurs. The write operation works correctly but the the same address location read operation from Port A generates ambiguous data output unless the clock cycle is long enough to allow the newly written data to be read. 62 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 3-17 • Collision Scenarios (continued) Operation Comments Simultaneous read from Port B and write to Port C to Collision occurs. The write operation works correctly but the the same address location read operation from Port B generates ambiguous data output unless the clock cycle is long enough to allow the newly written data to be read. Simultaneous read form Port A, read from Port B, and Collision occurs. The write operation works correctly but the write to Port C to the same address location read operation from both the ports generates ambiguous data output unless the clock cycle is long enough to allow the newly written data to be read. There is no collision prevention or detection implemented in the uSRAM architecture, so the designer must take measures to avoid the last three scenarios in designs. How to Use uSRAM The following section describes the Design Flow of uSRAM. Design Flow Libero SoC software provides a tool for configuring uSRAM blocks in the required operating modes. The required HDL wrapper files for uSRAM are generated with appropriate values assigned to the static signals. The generated uSRAM wrapper HDL files can be used in the design hierarchy by connecting the ports to the rest of the design. uSRAM - IP Figure 3-11 shows the ports of the uSRAM IP macro available in Libero SoC. Refer to the SmartFusion2/IGLOO2 Micro SRAM Configuration User Guide for detailed information about software configuration for SRAM. Figure 3-11 • uSRAM IP Macro in Libero SoC Revision 4 63 Micro SRAM (uSRAM) Table 3-18 • Port Description for the uSRAM-IP Macro Port Name Direction A_ADDR[] In A_BLK In Active High Port A block select A_ADDR_CLK In Rising edge Port A clock for A_ADDR A_DOUT_CLK In Rising edge Port A clock for A_DOUT Out - A_DOUT_ARST In Active Low Port A pipeline register asynchronous reset A_DOUT_EN In Active High Port A pipeline register enable A_DOUT_SRST In Active Low Port A pipeline register synchronous reset A_ADDR_EN In Active High Port A address register enable A_ADDR_SRST In Active Low Port A address register synchronous reset A_ADDR_ARST In Active Low Port A address register asynchronous reset B_ADDR[] In - B_BLK In Active High Port B block select B_ADDR_CLK In Rising edge Port B clock for B_ADDR B_DOUT_CLK In Rising edge Port B clock for B_DOUT Out - B_DOUT_ARST In Active Low Port B pipeline register asynchronous reset B_DOUT_EN In Active High Port B pipeline register enable B_DOUT_SRST In Active Low Port B pipeline register synchronous reset B_ADDR_EN In Active High Port B address register enable B_ADDR_SRST In Active Low Port B address register synchronous reset B_ADDR_ARST In Active Low Port B address register asynchronous reset C_ADDR[] In - C_CLK In Rising edge C_DIN[] In - C_WEN In Active High Port C write enable C_BLK In Active High Port C block select A_DOUT[] B_DOUT[] 64 Polarity Description Port A address input Port A data output Port B address input Port B data output Port C address input Port C clock for C_ADDR and C_DIN Port C write data R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric uSRAM Macro (RAM 64X18) The uSRAM macro (RAM64x18) in Libero SoC can be used directly to instantiate the uSRAM in the design. The uSRAM must be configured correctly with the appropriate values provided to the static signals before instantiating it in the design. Figure 3-12 shows the uSRAM macro (RAM64x18) available in Libero SoC. Figure 3-12 • RAM64x18 Macro Associated uSRAM IP Cores CoreAHBLSRAM and CoreAPBLSRAM IP cores In addition to uSRAM macros, Libero SoC also has CoreAHBLSRAM and CoreAPBLSRAM IP cores available to access the uSRAM through AHB and APB slave interfaces. Configuration parameters such as bus (AHB/APB) data width, RAM selection (LSRAM, uSRAM), and depth of the memory can be set as per design requirement. Refer to the CoreAHBLSRAM Handbook for uSRAM with AHB slave interface detailed software configuration information. Refer to the CoreAPBLSRAM Handbook for uSRAM with APB slave interface detailed software configuration information. CoreFIFO IP Libero SoC IP catalog has a CoreFIFO IP, which can be configured as a soft FIFO for generation of FIFO control logic. Memory configuration can be selected as LSRAM, uSRAM or external memory as per the design requirements. Refer to the CoreFIFO Handbook for detailed software configuration information. Revision 4 65 Micro SRAM (uSRAM) List of Changes The following table shows important changes made in this document for each revision. Date Changes Revision 3 (May 2015) Removed all instances of and references to M2GL100 devices from Table 3-1 (SAR 62858). 46 Merge the SmartFusion2 and IGLOO2 Micro SRAM chapter into one. NA Glossary Acronyms LSB Least significant bit LSRAM Large static random access memory MSB Most significant bit uSRAM Micro static random access memory 66 Page R e visio n 4 4 – Mathblocks Introduction The SmartFusion2 SoC and IGLOO2 FPGA devices have embedded mathblocks, which are optimized for digital signal processing (DSP) applications such as finite impulse response (FIR) filters, infinite impulse response (IIR) filters, fast fourier transform (FFT) functions, and encoders that require high data throughput. The SmartFusion2 and IGLOO2 mathblocks have a built-in multiplier and adder, which minimizes the external logic required to implement multiplication, multiply-add, and multiply-accumulate (MACC) functions. Implementation of these arithmetic functions results in efficient resource usage and improved performance for DSP applications. Mathblocks can also be used in conjunction with fabric logic and embedded memories (uSRAM and LSRAM) to implement complex DSP algorithms efficiently. The number of mathblocks varies depending on the size of the device, as shown in Table 4-1. Features Each mathblock has the following features: • High-performance and power optimized multiplications operations • Supports 18 x 18 signed multiplication natively • Supports 17 x 17 unsigned multiplications • Supports dot product: the multiplier computes(A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29 • Built-in addition, subtraction, and accumulation units to combine multiplication results efficiently • Independent third input C with data width 44 bits completely registered. • Supports both registered and unregistered inputs and outputs • Supports signed and unsigned operations • Internal cascade signals (44-bit CDIN and CDOUT) enable cascading of the mathblocks to support larger accumulator, adder, and subtractor without extra logic • Supports loopback capability • Adder support: (A x B) + C or (A x B) + D or (A x B) + C + D • Clock-gated input and output registers for power optimizations • Width of adder and accumulator can be extended by implementing extra adders in the FPGA fabric. Mathblock Resource Table Table 4-1 lists the mathblocks available for SmartFusion2 and IGLOO2 devices. Table 4-1 • SmartFusion2 and IGLOO2 Mathblocks Resource Device SmartFusion2/IGLOO2 M2S005/M2GL005 Number of Mathblocks Rows Number per Row Total 1 11 11 M2S010/M2GL010 2 11 22 M2S025/M2GL025 2 17 34 M2S050/M2GL050 3 24 72 M2S090/M2GL090 3 28 84 M2S150/M2GL150 6 40 240 Revision 4 67 Mathblocks Functional Description This section provides the detailed description of the architecture of Mathblock. Architecture Overview The SmartFusion2 and IGLOO2 devices can have one to three rows of mathblocks in the FPGA fabric, as listed in Table 4-1 on page 67. Mathblocks can be accessed through the FPGA routing architecture and cascaded in a chain, starting from the left-most block to the right-most block. Each mathblock consists of the following: • Multiplier • Adder or Subtractor • I/O and Control Registers Figure 4-1 shows the functional block diagram of the mathblock 68% FQWOUHJ 68%B$/B1 68%B%<3$66 68%B6/B1 68%B6'B1 &/.>@ $>@ '273 68%B$' 68%B(1 LQUHJ $B$567B1>@ $B%<3$66>@ 3B$567B1>@ 3B6567B1>@ $B6567B1>@ $B(1>@ 3B(1>@ &/.>@ %B%<3$66>@ LQUHJ %B$567B1>@ 3B$567B1>@ & %B(1>@ &/.>@ &B$567B1>@ 3B6567B1>@ 3B(1>@ 3B%<3$66>@ &$55<,1 LQUHJ &B%<3$66>@ ' &/.>@ &B6567B1>@ &B(1>@ &/.>@ $56+)7 FQWOUHJ $56+)7B$/B1 $56+)7B6/B1 $56+)7B$' $56+)7B6'B1 29)/B&$55<287B6(/ !! $56+)7B%<3$66 $56+)7B(1 &/.>@ &'6(/ &'6(/B$/B1 FQWOUHJ &'6(/B6/B1 &'6(/B(1 &/.>@ &'6(/B$' &'6(/B6'B1 &'6(/B%<3$66 )'%.6(/ )'%.6(/B$/B1 )'%.6(/B6/B1 )'%.6(/B(1 &/.>@ FQWOUHJ )'%.6(/B$' )'%.6(/B6'B1 )'%.6(/B%<3$66 &',1>@ Figure 4-1 • Functional Block Diagram of the Mathblock 68 &'287>@ %B6567B1>@ &>@ &$55<,1 29)/B&$55<287 3B%<3$66>@ &/.>@ %>@ FQWOUHJ R e visio n 4 RXWUHJ 3>@ SmartFusion2 SoC and IGLOO2 FPGA Fabric Multiplier A SmartFusion2 and IGLOO2 mathblock can be used as a multiplier, which accepts two 18-bit inputs (A and B), and generates a 36-bit output. The mathblock multiplier can be configured in two different operating modes: • Normal Mode • DOTP Mode Normal Mode In Normal mode, the mathblock implements a single 18 x18 signed multiplier. The Mathblock accepts the inputs, A [17:0] and B [17:0], and generates A*B with a 36-bit wide result. Figure 4-2 shows the functional block diagram of the mathblock in Normal mode. Normal Mode A[17:0] SUB 18 36 B[17:0] 18 44 P[43:0] CARRYIN C[43:0] 44 D[43:0] 44 Figure 4-2 • Functional Block Diagram of the Mathblock in Normal Mode DOTP Mode DOTP mode has two independent 9-bit x 9-bit multipliers with adder and the product sum is stored in Upper 36 bits of 44-bit register. In Dot Product (DOTP) mode, the mathblock implements the following equation: (A [8:0] x B [17:9] + A[17:9] x B[8:0]) x 29 EQ 1 DOTP mode can be used to implement 9 x 9 complex multiplications. Revision 4 69 Mathblocks Figure 4-3 shows the functional block diagram of the mathblock in DOTP mode. SUB DOT Product Mode A[17:9] B[8:0] 36 B[17:9] A[8:0] 44 P[43:0] CARRYIN C[43:0] 44 D[43:0] 44 Figure 4-3 • Functional Block Diagram of the Mathblock in DOTP Mode Adder or Subtractor The adder sums the output from the multiplier, C input, CARRYIN, or D input. The final output (P) of the adder is ((A [17:0] x B [17:0]) + C [43:0] + D [43:0] + CARRYIN). The mathblock can be configured as a 2-input or 3-input adder. • As a 2-input adder, the mathblock computes A x B + C or A x B + D. • As a 3-Input adder, the mathblock computes A x B + C + D. If the adder is configured as a subtractor, the adder output is ((C [43:0] + D [43:0] + CARRYIN) – (A[17:0] x B[17:0])). I/O and Control Registers Mathblocks have built-in registers on data inputs (A, B, C), data output (P), and control signals. If required, these registers can be bypassed. All the registers in the mathblock have clock gating capability to reduce power consumption. Mathblocks do not have a pipeline register at the cascade input (CDIN), so pipeline registers can be added from the fabric when multiple mathblocks are cascaded to implement higher bit-width multiplications. C Input The C input port allows the formation of many 3-input mathematical functions, such as 3-input addition or 2-input multiplication with an addition. The CARRYIN signal is the carry input of the adder or accumulator. The C input can also be used as a dynamic input achieving the following functionalities: • 70 Wrapping-around the cascade chain of mathblocks from one row to the next row through the fabric • Rounding of multiplication outputs • Trimming of lower order bits of the final sum or partial sum or the product. R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Cascaded Input, Output, and Selection Higher level DSP functions are supported by cascading individual mathblocks in a row. The two data signals, CDIN [43:0] and CDOUT [43:0], provide the cascading capability with a cascade select input (CDSEL). Table 4-2 on page 71 shows the selection of CDSEL for propagating CDIN to the D input of the adder. To cascade mathblocks, the CDOUT of one block must feed the CDIN of another block. CDOUT to CDIN is a hardwired connection between the blocks within a row. Two different rows can be cascaded using the fabric routing between the two rows. Extra pipeline registers may be needed to compensate for the extra delays added due to the fabric routing, which in turn will increase the latency of the chain. The ability to cascade mathblocks is useful in filter designs. For example, an FIR filter design can use cascading inputs to arrange a series of input data samples and cascading outputs to arrange a series of partial output results. The ability to cascade provides a high-performance and low power implementation of DSP filter functions because the general routing in the fabric is not used. Overflow Output Each mathblock has an overflow signal, OVFL_CARRYOUT. This signal indicates any overflow from the additional operation performed by the adder. This signal is also used to extend the adder data widths from the existing 44 bits using fabric. The overflow signal is also used for the implementation of saturation capabilities. Saturation refers to catching an overflow condition and replacing the output with either the maximum (most positive) or minimum (most negative) value that can be represented. In SmartFusion2 and IGLOO2 mathblocks, this capability is implemented using the adder's output sign bit (MSB [43] bit of the P output) and the overflow signal. Shift Input For multi-precision arithmetic, mathblocks provide a right-wire-shift by 17 which is controlled by the ARSHFT17 input. Thus, a partial product from one mathblock can be shifted to the right and added to the next partial product computed in an adjacent mathblock. Using this technique, mathblocks can be used to build bigger multipliers. Feedback Select Input For accumulation operations, mathblock output needs to loopback to the D input of the adder block. Selection of the D input is controlled by the feedback select (FDBKSEL) input. Table 4-2 lists the selection of FDBKSEL for loopback. Table 4-2 • Truth Table for Propagating Operand D of the Adder or Accumulator CDSEL FDBKSEL ARSHFT17 Operand D 0 0 0 0 0 0 1 0 1 X 0 CDIN[43:0] 1 X 1 {{17{CDIN[43]}}, CDIN[43:18]} 0 1 0 P[43:0] 0 1 1 {{17{P[43]}}, P[43:18]} Mathblock Interface to Fabric Routing Mathblocks can access the fabric routing through interface logic routing clusters. These clusters are composed of 12 flip-flops and 12 4-input (look-up tables) LUTs. When mathblocks are used, these flipflops and LUTs act as an interface to fabric routing. When mathblocks are not used, these flip-flops and LUTs can be utilized as normal flip-flops and LUTs. The interface logic clusters do not have carry chain support. Revision 4 71 Mathblocks How to Use Mathblocks The following sections describe how to use Mathblock in an application: • Design Flow • Mathblock Use Models • Coding Style Examples Design Flow Mathblocks can be used in two ways: through inference or by using the mathblock primitive. Inference is done during the synthesis stage of an RTL design. Alternately, the mathblock primitive is available in the Libero SoC IP catalog as a component that can be used directly in the HDL file or instantiated in SmartDesign. Using a Mathblock Through Inference Synplify Pro can infer mathblocks and can configure them into appropriate modes automatically, if the RTL contains any specific multiply, multiply-accumulate, multiply-add, or multiply-subtract functions. In this case, the synthesis tool takes care of all the signal connections of the mathblock to the rest of the design and provides the correct values for the static signals to configure the appropriate operational mode. The tool ties unused dynamic input signals to ground and provides default values to unused static signals. The synthesis tool maps any multiplication function with input widths of 3 or greater to mathblocks. However, the mapping of multiplication functions with input widths less than 3, which are implemented in FPGA logic by default, can be controlled by the synthesis attribute (syn_multstyle). The tool also has the capability to cascade multiple mathblocks, if the function crosses the limits of a single mathblock. For example, if an RTL function has a 35 x 35 multiplication, the synthesis tool implements this using four mathblocks cascaded in a chain. It also has the capability to place the input and output registers inside the mathblock boundary, provided they are driven by same clock. If the registers have different clocks, the clock that drives the output register has priority, and all registers driven by that clock are placed into the mathblock. If the outputs are unregistered and the inputs are registered with different clocks, the input registers with the larger input have priority and are placed into the mathblock. The synthesis tool supports inference of mathblock components across hierarchical boundaries, which means even if the multipliers, input registers, output registers, and subtracter/adders are present in different hierarchies, they can be placed into the same mathblock. For more information on mathblock inference by Synplify Pro, refer to the Synopsys application note on inferring Microsemi IGLOO2 MACC Blocks. Using the Mathblock Primitive The mathblock primitive available in the Libero SoC IP Catalog is called MACC. Figure 4-4 on page 73 shows the MACC primitive with input/output port and the bit width of each port. The port list and definitions are given in Table 4-3 on page 74. The MACC primitive can be used in designs by SmartDesign for schematic-based design entry or by directly instantiating the MACC wrapper in an HDL file as a component. For the MACC primitive, the inputs and outputs must be connected manually to the design signals. Proper values to the static signals must be provided to ensure that the mathblock is configured in the correct operational mode. For example, to configure the mathblock in DOTP mode, the DOTP signal must be tied to logic 1. Unused active high dynamic signals should be connected to ground, unused active low dynamic signals should be connected to high, and unused static signals should be in default state. 72 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Figure 4-4 • Mathblock Macro Revision 4 73 Mathblocks Table 4-3 • Mathblock Pin Descriptions Pin Name CLK[1:0] Direction Type Polarity Input Dynamic Rising Edge Description Input clocks • CLK[1] is the clock for A[17:9], B[17:9], P[40:18], OVFL, SHFTSEL, CDSEL, FDBKSEL, and SUB registers • CLK[0] is the clock for A[8:0], B[8:0], and P[17:0] In Normal mode, ensure CLK[1] = CLK[0]. Port A (to Multiplier) A[17:0] Input Dynamic A_ARST_N[1:0] Input Dynamic Input Data Low Asynchronous reset • A_ARST_N[1] is for A[17:9] • A_ARST_N[0] is for A[8:0] When not registered, connect A_ARST_N[1:0] to logic 1. In Normal mode, ensure A_ARST_N[1] = A_ARST_N[0]. A_SRST_N[1:0] Input Dynamic Low Synchronous reset • A_SRST_N[1] is for A[17:9] • A_SRST_N[0] is for A[8:0] When not registered, connect A_SRST_N[1:0] to logic 1. In Normal mode, ensure A_SRST_N[1] = A_SRST_N[0]. A_EN[1:0] Input Dynamic High Enable for data registers • A_EN[1] is for A[17:9] • A_EN[0] is for A[8:0] When not registered, connect A_EN[1:0] to logic 1. In Normal mode, ensure A_EN[1] = A_EN[0]. A_BYPASS[1:0] Input Static High Latch input to bypass data registers • A_BYPASS[1] is for A[17:9] • A_BYPASS[0] is for A[8:0] When not registered, connect A_BYPASS [1:0] to logic 1. In Normal mode, ensure A_BYPASS [1] = A_BYPASS [0]. Port B (to Multiplier) B[17:0] Input Dynamic Input Data Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. 74 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 4-3 • Mathblock Pin Descriptions (continued) Pin Name B_ARST_N[1:0] Direction Type Polarity Input Dynamic Low Description Asynchronous reset • B_ARST_N[1] is for B[17:9] • B_ARST_N[0] is for B[8:0] When not registered, connect B_ARST_N [1:0] to logic 1. In Normal mode, ensure B_ARST_N [1] = B_ARST_N [0]. B_SRST_N[1:0] Input Dynamic Low Synchronous reset • B_SRST_N[1] is for B[17:9] • B_SRST_N[0] is for B[8:0] When not registered, connect B_SRST_N [1:0] to logic 1. In Normal mode, ensure B_SRST_N [1] = B_SRST_N [0]. B_EN[1:0] Input Dynamic High Enable for data registers • B_EN[1] is for B[17:9] • B_EN[0] is for B[8:0] When not registered, connect B_EN [1:0] to logic 1. In Normal mode, ensure B_EN [1] = B_EN [0]. B_BYPASS[1:0] Input Static High Latch input to bypass data registers • B_BYPASS[1] is for B[17:9] • B_BYPASS[0] is for B[8:0] When not registered, connect B_BYPASS [1:0] to logic 1. In Normal mode, ensure B_BYPASS [1] = B_BYPASS[0]. Port C (to Adder) C[43:0] Input Dynamic CARRYIN Input Dynamic C_ARST_N[1:0] Input Dynamic Input Data Adder/accumulator's carry input Low Asynchronous reset • C_ARST_N[1] is for C[43:18] • C_ARST_N[0] is for C[17:0] When not registered, connect C_ARST_N[1:0] to logic 1. In Normal mode, ensure C_ARST_N[1] = C_ARST_N[0]. Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. Revision 4 75 Mathblocks Table 4-3 • Mathblock Pin Descriptions (continued) Pin Name C_SRST_N[1:0] Direction Type Polarity Input Dynamic Low Description Synchronous reset • C_SRST_N[1] is for C[43:18] • C_SRST_N[0] is for C[17:0] When not registered, connect C_SRST_N[1:0] to logic 1. In Normal mode, ensure C_SRST_N[1] = C_SRST_N[0]. C_EN[1:0] Input Dynamic High Enable for data registers • C_EN[1] is for C[43:18] • C_EN[0] is for C[17:0] When not registered, connect C_EN[1:0] to logic 1. In Normal mode, ensure C_EN[1] = C_EN[0]. C_BYPASS[1:0] Input Static High Latch input to bypass data registers • C_BYPASS[1] is for C[43:18] • C_BYPASS[0] is for C[17:0] When not registered, connect C_BYPASS[1:0] to logic 1. In Normal mode, ensure C_BYPASS[1] = C_BYPASS[0]. Other Inputs CDIN[43:0] Input Cascade DOTP Input Static Cascaded input for operand D of the adder/accumulator. The entire CDIN will be driven by another mathblock's CDOUT. High Dot product mode When DOTP = 1, mathblock performs (A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29 When DOTP = 0, mathblock performs normal 18 x 18 multiplication operations. SUB Input Dynamic High Subtract operation When SUB = 1, perform 2's complement subtraction to get P = C + D + CARRYIN - (A x B). When SUB = 0, perform 2's complement addition to get P = C + D + CARRYIN + (A x B). SUB_AL_N Input Dynamic Low Asynchronous reset input for SUB input's control register. SUB_SL_N Input Dynamic Low Synchronous reset input for SUB input's control register. SUB_EN Input Dynamic High Enable input for SUB input's control register. Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. 76 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 4-3 • Mathblock Pin Descriptions (continued) Pin Name Direction Type Polarity Description SUB_BYPASS Input Static High Latch input to bypass SUB input's data register. When logic 1, SUB is not registered. SUB_AD Input Static High Asynchronous load data for the SUB input's control register. SUB_SD_N Input Static Low Synchronous load data for the SUB input's control register. ARSHFT17 Input Dynamic High Arithmetic right-shift for operand D. When asserted, a 17-bit arithmetic right-shift is performed on operand D of the adder/accumulator. ARSHFT17_AL_N Input Dynamic Low Asynchronous reset input for ARSHFT17 input's control register. ARSHFT17_SL_N Input Dynamic Low Synchronous reset input for ARSHFT17 input's control register. ARSHFT17_EN Input Dynamic High Enable input for ARSHFT17 input's control register. ARSHFT17_BYPASS Input Static High Latch input to bypass ARSHFT17 input's data register. When logic '1', ARSHFT17 is not registered. ARSHFT17_AD Input Static High Asynchronous load data for the ARSHFT17 input's control register. ARSHFT17_SD_N Input Static Low Synchronous load data for the ARSHFT17 input's control register. CDSEL Input Dynamic High Selects CDIN for operand D of the adder/accumulator input. When CDSEL = 1, CDIN is propagated to the operand D. When CDSEL = 0, either logic 0 or feedback from output P is routed to the operand D depending upon the FDBKSEL. CDSEL_AL_N Input Dynamic Low Asynchronous reset input for CDSEL input's control register. CDSEL_SL_N Input Dynamic Low Synchronous reset input for CDSEL input's control register. CDSEL_EN Input Dynamic High Enable input for CDSEL input's control register. CDSEL_BYPASS Input Static High Latch Input to bypass CDSEL input's data register. When logic 1, CDSEL is not registered. CDSEL_AD Input Static High Asynchronous load data for the CDSEL input's control register. CDSEL_SD_N Input Static Low Synchronous load data for the CDSEL input's control register. Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. Revision 4 77 Mathblocks Table 4-3 • Mathblock Pin Descriptions (continued) Pin Name Direction Type Polarity Description FDBKSEL Input Dynamic High Select the feedback from P for operand D of the adder or accumulator. • When FDBKSEL = 1, propagate the current value of result P register. • Ensure P_BYPASS[1] = 0 and CDSEL = 0. When FDBKSEL = 0, logic 0 is propagated. Ensure CDSEL = 0. FDBKSEL_AL_N Input Dynamic Low Asynchronous reset input for FDBKSEL input's control register. FDBKSEL_SL_N Input Dynamic Low Synchronous reset input for FDBKSEL input's control register. FDBKSEL_EN Input Dynamic High Enable input for FDBKSEL input's control register. FDBKSEL_BYPASS Input Static High Latch input to bypass FDBKSEL input's data register. When logic 1, FDBKSEL is not registered. FDBKSEL_AD Input Static High Asynchronous load data for the FDBKSEL input's control register. FDBKSEL_SD_N Input Static Low Synchronous load data for the FDBKSEL input's control register. Output Port P[43:0] Output Result data out • Normal mode P = C + D + CARRYIN + (A x B) when SUB = 0 P = C + D + CARRYIN - (A x B) when SUB = 1 • DOTP mode P = C + D + CARRYIN + ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) when SUB = 0 P = C + D + CARRYIN - ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) when SUB = 1 Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. 78 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 4-3 • Mathblock Pin Descriptions (continued) Pin Name OVFL_CARRYOUT Direction Type Polarity Output Description Overflow output • Normal mode if C + D + CARRYIN +/- (A x B) > (243 - 1), then OVFL_CARRYOUT = 1 if C + D + CARRYIN +/- (A x B) < - (243), then OVFL_CARRYOUT = 1 else OVFL_CARRYOUT = 0. • DOTP mode if C + D + CARRYIN +/- ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) > (243- 1), then OVFL_CARRYOUT = 1 if C + D + CARRYIN +/- ((A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29) < - (243), then OVFL_CARRYOUT = 1 else OVFL_CARRYOUT = 0. OVFL_CARRYOUT_SEL Input Static High Input to the adder for generating the overflow bit or an external bit, which finally comes as an output on the OVFL_CARRYOUT port. The overflow bit indicates the overflow generated in the addition process. The external bit is generated to extend the adder into the fabric. In this case, P[43], C[43], and D[43] are basically not representing the sign bit. When OVFL_CARRYOUT_SEL = 1, OVFL_CARRYOUT is the external bit for fabric extension. Otherwise, OVFL_CARRYOUT is the overflow output. CDOUT[43:0] P_ARST_N[1:0] Output Input Cascade output of result P. CDOUT is the same as P. It is used to drive the CDIN of another mathblock. Dynamic Low Asynchronous reset input for P and OVFL_CARRYOUT control registers • P_ARST_N [1] is for OVFL_CARRYOUT and P[43:18] • P_ARST_N [0] is for P[17:0] When not registered, connect P_ARST_N [1:0] to logic 1. In Normal mode, ensure P_ARST_N [1] = P_ARST_N [0]. Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. Revision 4 79 Mathblocks Table 4-3 • Mathblock Pin Descriptions (continued) Pin Name P_SRST_N[1:0] Direction Type Polarity Input Dynamic Low Description Synchronous reset input for P and OVFL_CARRYOUT control registers • P_SRST_N [1] is for OVFL_CARRYOUT and P[43:18] • P_SRST_N [0] is for P[17:0] When not registered, connect P_SRST_N [1:0] to logic 1. In Normal mode, ensure P_SRST_N [1] = P_SRST_N [0]. P_EN[1:0] Input Dynamic High Enable input for P and OVFL_CARRYOUT control registers • P_EN[1] is for OVFL_CARRYOUT and P[43:18] • P_EN[0] is for P[17:0] When not registered, connect P_EN[1:0] to logic 1. In Normal mode, ensure P_EN[1] = P_EN[0]. P_BYPASS[1:0] Input Static High Latch input for P and OVFL_CARRYOUT control registers • P_BYPASS[1] is for OVFL_CARRYOUT and P[43:18] • P_BYPASS[0] is for P[17:0] When not registered, connect P_BYPASS[1:0] to logic 1. In Normal mode, ensure P_BYPASS[1] = P_BYPASS[0]. Notes: • The asynchronous reset has priority over the synchronous reset and enable signal of the Input/Output registers. • Asynchronous load input has higher priority than the synchronous load input. 80 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Mathblock Use Models This section describes a few use models for SmartFusion2 and IGLOO2 mathblocks. Use Model 1: Non-Pipelined Implementation of the 35 x 35 Multiplier 35 x 35 multipliers are useful for applications which require more than 18-bit precision. Non-pipelined implementation is typically used for low speed applications. A 35 x 35 multiplier can be constructed using 4 mathblocks in a single row, connected in a cascade. Figure 4-5 shows a typical implementation of a non-pipelined 35 x 35 multiplier. The inputs are assumed to be A [34:0] and B [34:0] with a product of P [69:0]. A H [17:0] = A[34:17] P[69:34] B H [17:0] = B[34:17] >>17 AL [17:0] = {0, A[16:0]} P[33:17] BH [17:0] = B[34:17] AH [17:0] = A[34:17] Unconnected BL [17:0] = {0, B[16:0]} >>17 AL [17:0] = {0, A[16:0]} P[16:0] BL [17:0] = {0, B[16:0]} 0 Figure 4-5 • Non-Pipelined 35 x 35 Multiplier Revision 4 81 Mathblocks Use Model 2: Pipelined Implementation of the 35 x 35 Multiplier The SmartFusion2 and IGLOO2 mathblocks have built-in registers on all input and output ports. To implement high-speed multipliers, extra registers are added to the input or output side of the mathblocks to balance the pipeline latency. These extra registers are implemented in the fabric. Figure 4-6 shows a typical 35 x 35 multiplier implementation with fabric pipeline registers. AH [17:0] = A[34:17] P[69:34] B H [17:0] = B[34:17] >>17 AL [17:0] = {0, A[16:0]} P[33:17] BH [17:0] = B[34:17] AH [17:0] = A[34:17] Unconnected BL [17:0] = {0, B[16:0]} >>17 AL [17:0] = {0, A[16:0]} P[16:0] BL [17:0] = {0, B[16:0]} 0 - Fabric Registers Figure 4-6 • Pipeline 35 x 35 Multiplier 82 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Use Model 3: Implementation of 9-Bit Complex Multiplication Complex multiplication implemented using a mathblock in DOTP mode requires additional 2's complement logic in the fabric for negating the Q input. The DOTP implementation in Figure 4-7 shows the optimized way of implementing the 2's complement with minimal logic in the fabric. For two complex numbers X + jY, P + jQ, the complex multiplication is shown in EQ 2: Multiplication Result = Real part + Imaginary Part = (PX - QY) + j (PY + QX) EQ 2 In EQ 2, real part (PX-QY) requires that ‘-Q’ for the multiplication result. This can be compute using the one‘s complement of Q and add the Y using the c input (since -Q = ~Q+1). Imaginary part = P*Y+Q*X EQ 3 Real part = P*X + (~Q)*Y + Y EQ 4 Figure 4-7 shows the implementation of 9 x 9 complex multiplication using a mathblock configured in DOTP mode. << 9 9 3-Input Adder 44 3-Input Adder 44 PY+ QX (Imaginary Part) 9 AL Y 9 9 BH P Dot Product Mode BL Q AH X 44 C[43:0]= Zeroes Mathblock 1 Q 9 BH 1’s complement Logic 9 BL P AH X Dot Product Mode << 9 9 PX- QY (Real Part) 9 AL Y C[43:19] = Zeroes C[9:0] = Zeroes C[18:10]= Y 44 Mathblock 2 Figure 4-7 • 9-Bit Complex Multiplication Using DOTP Mode Revision 4 83 Mathblocks Use Model 4: Multi-Threading and Multi-Channeling Mathblocks support a multi-threading option where the same mathblock can be used for performing more than one computation by time multiplexing. Time multiplexing can be done easily for designs with low sample rates. The multi-threading capability, if implemented for a chain of mathblocks, is called multi-channeling. Multi-channeling can be used to implement multi-channel FIR filters where the same mathblock chain can be used to process multiple input channels by time multiplexing the mathblock chain. Multi-channel filtering is used in applications such as wireless communications, image processing, and multimedia applications. The mathblock uses its C input for multi-threading and multi-channeling, but fabric registers are also required for implementation. Use Model 5 - Rounding and Trimming Rounding Rounding can be computed by adding a fixed term and a variable term to the input value to be rounded, and then truncating. The fixed term can be feed using the C-Input of the mathblock and the value depends on the number of decimal points required after rounding. The variable term is always a single bit in the least-significant position whose value may be determined from the input value based on the type of rounding. Types of rounding are: • Round to the adjacent even integer: The variable term is determined from the 20 bit of the input value. • Round towards zero: The variable term is determined from the sign bit of the input value. For example, 1.5 rounds to 1 and -1.5 rounds to -1. Table 4-4 lists the examples for 6-bit values including three fraction bits. Table 4-4 • Rounding Examples Input Value Decimal Fixed Binary Term Variable C-Input Term 2.5 010.100 1.5 001.100 -1.5 110.100 -2.5 101.100 0.011 0.011 Round To Even Sum Truncated Sum Round Toward Zero Decimal Variable Term 000.000 010.111 010 0.011 000.001 010.000 010 0.011 000.000 110.111 110 000.001 110.000 110 -2 A[17:0] B[17:0] 2 010 2 000.000 001.111 001 1 -2 000.001 111.000 111 -1 000.001 110.000 110 -2 18 18 Fixed Term 18 C Input Variable Term 1 CARRYIN Figure 4-8 • Rounding Using C-Input and CARRYIN R e visio n 4 Truncated Decimal Sum 000.000 010.111 44 84 Sum P[43:0] 2 SmartFusion2 SoC and IGLOO2 FPGA Fabric Trimming Trimming of the Final Sum: Applications like IIR and FFT often requires the rounding and trimming of the final result (for example, last output of a cascade chain or the final value read from an accumulator). The addition of the rounding terms can be done as shown in the Figure 4-9 and final result can be trimmed in fabric. Variable Term A B A 1 B Fixed Term P Figure 4-9 • Rounding and Trimming of the Final Sum Trimming of Grouped Sums: When computing very large dot products (for example, a large, fully-enumerated FIR) it is good to avoid overflow by breaking the sum into a few groups, trimming the sum for each group, and only then combining the groups' sums into a final result. The rounding of each group's sum can be done as shown in Figure 4-9. The trimming of each group's sum and summation of the final result can be done in the fabric. Trimming can be done between the output of each cascade and the final fabric adder. Trimming of Products: Figure 4-10 shows the implementation of rounding all products towards zero and then trimming the least significant m bits of the product. As long as there are no additive terms other than the products, it is possible to equivalently trim the partial sums instead of the products. Round towards zero can be done using sign bit of the product (A*B) from the sign bits of the incoming factors A and B using an EXOR. A A[17] A B B[17] B C[m-1] C[m-1] C P[43:m] C[43:m] P Figure 4-10 • Rounding and Trimming of the Final Sum Revision 4 85 Mathblocks Coding Style Examples The following code examples illustrate coding styles from which the synthesis tool can infer and implement SmartFusion2 and IGLOO2 Mathblocks. Note: Examples provided are only in Verilog. VHDL examples are provided on request. Example 1: 18 x 18 Signed Multiplication – Non-Registered The following code is for an 18 x 18-bit signed multiplier. The input and output registers are configured in Transparent mode. The synthesis tool maps the code into one mathblock. module sign18x18_mult ( in1, in2, out1 ); input signed [17:0] in1, in2; output signed [40:0] out1; wire signed [40:0] out1; assign out1 = in1 * in2; endmodule Example 2: 18 x 18 Signed Multiplication – Registered The following code is for an 18 x 18 signed multiplier. The inputs and outputs are registered, with a synchronous active low reset signal. The synthesis tool maps the code into one mathblock. module sign18x18_mult_reg ( in1, in2, clock, reset, out1 ); input signed [17:0] in1, in2; input clock; input reset; output signed [40:0] out1; reg signed [40:0] out1; reg signed [17:0] in1_reg, in2_reg; always @ ( posedge clock ) begin if ( ~reset ) begin in1_reg <= 18'b0; in2_reg <= 18'b0; out1 <= 41'b0; end else begin in1_reg <= in1; n2_reg <= in2; out1 <= in1_reg * in2_reg; end end endmodule Example 3: 17 x 17-Bit Unsigned Multiplier with Different Resets The following code is for a 17 x 17-bit unsigned multiplier, which has input and output registers with different asynchronous resets. The synthesis tool maps the code into one SmartFusion2 or IGLOO2 mathblock. module mult_17x17unsign( in1, in2, clock, reset1, reset2, out1 ); input [16:0] in1, in2; input clock, reset1, reset2; output [33:0] out1; reg [33:0] out1; reg [16:0] in1_reg, in2_reg; always @(posedge clock or negedge reset1) begin if (~reset1 ) begin in1_reg <= 17'b0; in2_reg <= 17'b0; end else begin in1_reg <= in1; in2_reg <= in2; 86 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric end end always @(posedge clock or negedge reset2) begin if (~reset2 ) begin out1 <= 34'b0; end else begin out1 <= in1_reg * in2_reg; end end endmodule Example 4: 17 x 17-Bit Unsigned Multiplier with Different Clocks This example shows an unsigned multiplier with inputs and outputs that are registered with different clocks: clock1 and clock2. In this case, the synthesis tool places only the output registers and the multiplier into the SmartFusion2 or IGLOO2 mathblock. The input registers are implemented in FPGA logic outside the mathblock. module mult_17x17unsign ( in1, in2, clock1, clock2, outl ); input [16:0] in1, in2; input clock1,clock2; output [33:0] outl; reg [33:0] outl; reg [16:0] in1_reg, in2_reg; always @ ( posedge clock1 ) begin in1_reg <= in1; in2_reg <= in2; end always @ ( posedge clock2 ) begin outl <= in1_reg * in2_reg; end endmodule Example 5: Multiplier-Adder In the code below. the output of a multiplier is added with another input. Inputs and outputs are registered and have enables and synchronous resets. The synthesis tool maps the code into one SmartFusion2 or IGLOO2 mathblock. module mult_add_v1( in1, in2, in3, clock, reset, en, out1); input [16:0] in1, in2; input [33:0] in3; input clock, reset, en; output [34:0] out1; reg [34:0] out1; reg [16:0] in1_reg, in2_reg; reg [33:0] in3_reg; wire [33:0] mult_out; always @(posedge clock) begin if (~reset) begin in1_reg <= 17'b0; in2_reg <= 17'b0; in3_reg <= 34'b0; end else begin if (en == 1'b1) begin in1_reg <= in1; in2_reg <= in2; Revision 4 87 Mathblocks in3_reg <= in3; end end end always @(posedge clock) begin if (~reset) begin out1 <= 35'b0; end else begin if (en == 1'b1) begin out1 <= {1'b0, mult_out} + {1'b0, in3_reg}; end end end assign mult_out = in1_reg * in2_reg; endmodule Example 6: Multiplier-Subtractor There are two ways to implement multiplier and subtract logic. The synthesis tool places the logic differently, depending on how it is implemented. • Subtract the result of multiplier from an input value (P = Cin – mult_out). The synthesis tool places all logic in the mathblock. • Subtract a value from the result of the multiplier (P = mult_out – Cin). The synthesis tool places only the multiplier in the mathblock. The subtractor is implemented in FPGA logic outside the mathblock. – Unsigned MultSub Example (P = Cin – Mult_out) - Implemented in single mathblock. module mult_sub ( in1, in2, in3, clk, rst, out1 ); input [16:0] in1, in2; input [36:0] in3; input clk; input rst; output [39:0] out1; reg [39:0] out1; reg [16:0] in1_reg, in2_reg; always @ ( posedge clk ) begin if (~rst) begin in1_reg <= 17'b0; in2_reg <= 17'b0; out1 <= 40'b0; end else begin in1_reg <= in1; in2_reg <= in2; out1 <= in3 - (in1_reg * in2_reg); end end endmodule – Unsigned MultSub Example (P = Mult - Cin) - Multiplier is implemented in mathblock and subtractor in FPGA logic module mult_sub_v2 ( in1, in2, in3, clk, rst, out1 ); input [16:0] in1, in2; input [36:0] in3; input clk; input rst; output [39:0] out1; 88 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric reg [39:0] out1; reg [16:0] in1_reg, in2_reg; always @ ( posedge clk ) begin if ( ~rst ) begin in1_reg <= 17'b0; in2_reg <= 17'b0; out1 <= 40'b0; end else begin in1_reg <= in1; in2_reg <= in2; out1 <= (in1_reg * in2_reg) - in3; end end endmodule Example 7: Signed 35 x 35 Multiplication The code below implements a signed 35 x 35 multiplication function. The synthesis tool uses 4 cascaded mathblocks to implement this multiplication function. module sign35x35_mult ( in1, in2, out1); input signed [34:0] in1; input signed [34:0] in2; output signed [69:0] out1; wire signed [69:0] out1; assign out1 = in1 * in2; endmodule Example 8: Signed 35 x 35 Multiplication with Two Pipelined Register Stages The code below implements a signed 35 x 35 multiplication function with two pipelined register stages. The synthesis tool uses four cascaded mathblocks to implement this multiplication function. The synthesis tool first infers pipeline registers at the input, output of the SmartFusion2 or IGLOO2 mathblock and controls pipeline latency by balancing the number of register stages. To balance the stages, the tool adds additional registers at the input or output of the mathblock as required, implemented in the fabric logic. module sign35x35_mult ( in1, in2, clk, rst, out1 ); input signed [34:0] in1, in2; input clk; input rst; output signed [69:0] out1; reg signed [69:0] out1; reg signed [34:0] in1_reg, in2_reg; always @ ( posedge clk or negedge rst) begin if ( ~rst ) begin in1_reg <= 35'b0; in2_reg <= 35'b0; out1 <= 70'b0; end else begin ini_reg <= in1; in2_reg <= in2; out1 <= ini_reg * in2_reg; end end endmodule Revision 4 89 Mathblocks List of Changes The following table shows important changes made in this document for each revision. Date Changes Page Revision 3 (May 2015) Removed M2GL100 devices from Table 4-1 (SAR 62858). 67 Merging the SmartFusion2 and IGLOO2 Math Blocks chapter. NA Revision 2 (March 2014) Updated Figure 4-1 • Functional Block Diagram of the Mathblock and "Coding Style Examples" section (SAR 55075). Glossary Terminology Multi-Channeling Multi-threading done for a chain of mathblocks Multi-Threading Using a mathblock for performing more than one computation by time multiplexing it. Pipelined Operation The mode of operation where the mathblock output is registered at the pipeline registers. 90 R e visio n 4 68, 86 5 – I/Os Introduction SmartFusion2 SoC and IGLOO2 FPGA devices have different types of inputs/outputs (I/Os), such as multi-standard I/Os (MSIO and MSIOD), double-data-rate I/Os (DDRIO), and dedicated I/Os based on functional usage. MSIO, MSIOD, and DDRIO provide programmable I/O features such as drive strength, slew rate, input delay, weak pull-up, and weak pull-down for several voltages. These programmable I/O features are explained in detail in the "I/O Programmable Features" section on page 99. DDRIO is an MSIO optimized for LPDDR/DDR2/DDR3 performance. In SmartFusion2 and IGLOO2 devices, there are two DDR subsystems: the fabric DDR and memory subsystem (MDDR) controllers, which control external DDR memory. DDRIOs can be connected to the respective DDR subsystem PHYs or used directly as user I/Os. For more information on DDR subsystem, refer to the SmartFusion2 and IGLOO2 High Speed Interfaces User Guide. MSIO, MSIOD, and DDRIO can be configured as MSS, HPMS, or fabric I/Os, whereas dedicated I/Os can be used for a single purpose, serializer/deserializer (SERDES), device reset, and clock functions. The MSIO, MSIOD, and DDRIO are configured at power-up through the flash bits used to initialize the fabric register blocks. This is automatically done using the Libero SoC software. Functional Description SmartFusion2 and IGLOO2 I/Os are classified into the following three categories depending on their functional usage: • MSIO, MSIOD, and DDRIO • JTAG I/O • Dedicated I/Os Figure 5-1 on page 92 shows the top-level view of I/O interconnection between the fabric logic and the FDDR. The DDRIOs are shared among the fabric logic and MDDR/FDDR. When the MDDR/FDDR controller is used, the Libero SoC software automatically assigns and configures the controller signals to the respective DDRIOs. The SPIO_SEL signal (as shown in Figure 5-1 on page 92) determines whether the fabric logic or MDDR/FDDR/MSS peripheral is connected to the corresponding I/Os. This selection is set automatically by the Libero SoC software during programming. When the MDDR/FDDR controller is not used, the respective DDRIOs are available to the fabric logic, as shown in Figure 5-1 on page 92. Similarly, when the MSS or HPMS peripheral is used, Libero SoC automatically assigns and configures the MSS or HPMS peripheral’s signals to the MSIOs and the MSIOD.The SPIO_SEL signal (as shown in Figure 5-1 on page 92) determines whether the fabric logic, MSS, or HPMS peripheral is connected to the corresponding I/Os.This selection is set automatically by the Libero SoC software during programming. When the MSS or HPMS peripherals are not used, the respective I/Os are available to the fabric logic, as shown in Figure 5-1 on page 92. For the fabric logic, each I/O port of the design must be individually assigned to I/Os in Libero SoC. Revision 4 91 I/Os IOD User Configures in Libero SoC IOA OE_P Data_out1 DO_P Fabric IOD Fabric Logic DI_P Data_in1 Libero SoC Configures Automatically HPMS Peripheral or MDDR/FDDR Controller + PHY HPMS Peripheral IOD DO_P or MDDR/FDDR DI_P IOD P SPIO_SEL Transmitter and Receiver OE_P DI_P I/P Buffer Disable Control User Configures in Libero SoC O/P Buffer Disable Control OE_N Data_out2 Fabric Logic PAD_P DO_P Fabric IOD Data_in2 DO_N DI_N 1 0 SPIO_SEL Libero SoC Configures Automatically HPMS Peripheral or MDDR/FDDR Controller + PHY HPMS Peripheral IOD DO_N or DI_N MDDR/FDDR IOD Differential OE_N 1 DO_N 0 Transmitter and Receiver PAD_N DI_N Differential N Figure 5-1 • I/O Interconnection MSIO, MSIOD, and DDRIO can be configured as one differential I/O or two single-ended I/Os. Singleended I/Os are composed of two separate I/Os named P and N, as shown in Figure 5-1. The differential I/O is implemented by pairing up P and N. The differential standards are implemented as true differential outputs and not complementary single-ended outputs. An I/O consists of a bidirectional I/O buffer. The I/O is divided into two main sections, as shown in Figure 5-1: • Digital: IOD (fabric and MDDR/FDDR/HPMS peripherals) • Analog: IOA The digital section (IOD) generates output enable (OE), data out (DO), and data in (DIN) signals for both P and N. Refer to the "Fabric Architecture" chapter on page 7 for more details on IOD. As shown in Figure 5-2 on page 94, analog blocks (IOA) together form a differential pair, which supports differential and pseudo differential modes of operation. The differential pair is composed of a true IOA and a complement IOA. The true IOA is called IOP (with positive polarity relative to the DO/DIN data signals of the P cell). The complement IOA is called ION (with negative polarity relative to the DO/DIN data signals of the N cell). The IOA blocks form a ring around the periphery of the device (excluding the SERDES channel edge). 92 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric The top and bottom edge of the IOA order of the device starts with P on the left and N on the right. The left and right edges use N on the top and P on the bottom. There is one IOD for each pair of IOAs. To support different differential standards, SmartFusion2 and IGLOO2 use a pair of regular I/O cells: P and N. These two I/O cells of MSIO, MSIOD, and DDRIO can be configured as separate single-ended I/Os or configured as one differential I/O pair. In differential output mode, the output data signal is driven out on both the P cell and N cell as a differential pair, where the true signal is on pad P and the complement signal is on N pad. The P and N output signals are complementary as required by the DDR1/DDR2/DDR3 standards for the CK and DQS signals. The P and N cells have to be placed next to each other, as a pair, to minimize skew between the two output signals of the differential pair. IOA has transmitter and receiver buffers for the P and N pair as shown in Figure 5-2 on page 94). The transmit and receive buffers support various I/O standards and contain the following modules: • Transmit Buffer • Receive Buffer • Low-Power Exit • On-Die Termination Transmit Buffer Transmit and receive buffers transfer signals between the FPGA fabric and the IOA. They also transfer signals between the MDDR, FDDR, MSS peripherals, HPMS peripherals, and the IOA. The OE_P and OE_N control the direction of I/O buffers, as shown in Figure 5-2 on page 94. When an I/O is operated as a single-ended I/O, OE_P and OE_N individually control the P and N I/O buffers. When an I/O is operated as a differential I/O, OE_P controls both the P and N I/O buffers. The dynamic OE disables or enables the output buffer for all the standards. Receive Buffer The enabling and disabling of the input buffer is controlled automatically by Libero SoC. The I/O receiver can be made to operate in four different modes, as shown in Figure 5-2 on page 94. These modes are selected based on flash configuration bits, which are configured during programming, after power-on. Following are the four modes of operation of the receiver: • True differential • Pseudo-differential • Single-ended • Schmitt trigger In true differential mode, P and N pad inputs are fed to the comparator, whereas in pseudo-differential mode, each pad input is compared to reference with an external reference voltage. Figure 5-2 on page 94 shows the detailed IOA structure. The I/O input can be configured as a schmitt trigger receiver or a single-ended receiver. When schmitt trigger receiver is selected, the input buffer has hysteresis that filters noise at the receiver and prevents double glitching caused by the noisy input edges. Revision 4 93 I/Os Program directly ODT to desired value 44-DDRIO Pairs Connected to MDDR/FDDR DDRIO Calibration Block Reference Resistor Value IOA Fabric or MDDR/FDDR or HPMS Peripherals VCCIO Programmable Pull-up (or) Pull-down (or) Disable both for ‘P’ Programmable Slew rate for ‘P’ driver ODT / Transmitter Impedance Tx P DO_P PAD_P OE_P Single-Ended Receiver P Schmit Psuedo-Differential + True -Differential DIN_P Input Programming Delay DIN_P_delayed + - Voltage Standard Select Programmable Slew rate for ‘N’ driver DO_N 1 0 X_VREF Differential ODT (MSIO and MSIOD only) VCCIO ODT / Transmitter Impedance Tx N PAD_N 1 OE_N 0 Single - ended Receiver N Programmable Pull - up (or ) Pull - down (or) Disable both for ‘N’ Differential Schmit DIN_N Psuedo - Differential DIN_N_delayed Input Programming Delay + - X_VREF Figure 5-2 • IOA Architecture The MSIO and MSIOD in SmartFusion2/IGLOO2 devices support DDR mode. In DDR mode, the new data is present on every transition (or clock edge) of the clock signal. DDR mode doubles the data transfer rate as compared to single data rate (SDR) mode where new data is present on one transition (or clock edge) of the clock signal. Low-power flash devices have DDR circuitry built in to the I/O tiles. I/Os are configured in DDR mode by instantiating the DDR macros (DDR_OUT or DDR_IN) in the RTL design and buffers, as shown in Figure 5-3 on page 95. Refer to the SmartFusion2 and IGLOO2 Datasheet for more information. 94 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Note: DDRIOs are different from the DDR macro (DDR_IN and DDR_OUT). INBUF PAD PAD DDR_IN Y D DataR QR DDR_OUT DR DF Q OUTBUF D PAD DataF QF CLK CLR CLR CLR Figure 5-3 • DDR Support in Low Power Flash Devices Low-Power Exit Low-power exit logic indicates to the system controller that the I/Os have either matched the pre-defined signature bit or have detected activity on the selected I/O after the chip entered low-power mode. For details on signature and activity modes, refer to the "Signature Mode" section on page 111 and "Activity Mode" section on page 111. On-Die Termination On-die termination (ODT) improves the signaling environment by reducing the electrical discontinuities and enables reliable operation at higher signaling rates. For more information on the programmed ODT values for DDRIO, MSIO, and MSIOD, refer to the "I/O Programmable Features" section on page 99. I/O Banks I/Os are grouped on the basis of I/O voltage standards. The grouped I/Os of each voltage standards form an I/O bank. Each I/O bank has dedicated I/O supply and ground voltages; therefore, only I/Os with compatible standards can be assigned to the same I/O voltage bank. Every I/O bank has input and output buffers to support a wide range of standards, each requiring a different VDDI voltage, and where applicable, a different reference voltage (VREF). These voltages are externally supplied and connected to supply pins, which serve banks of I/Os. Note: For I/O pin name and bank assignments for different device packages, refer to the SmartFusion2/IGLOO2 Pin Descriptions document. Revision 4 95 I/Os Supported I/O Standards SmartFusion2/IGLOO2 devices support the different I/O standards, as listed in Table 5-1. These I/O standards can be configured using Libero SoC. Refer to the Libero SoC User Guide for more details. Table 5-1 lists all the I/O standards supported for single-ended and differential I/Os: Table 5-1 • Supported I/O Standards Single-ended Differential MSIO (Max 3.3 V) MSIOD (Max 2.5 V) DDRIO (Max 2.5 V) LVTTL Yes – Yes – – PCI Yes – Yes – – LVPECL (input only) – Yes Yes – – LVDS33 – Yes Yes – – LVCMOS33 Yes – Yes – – LVCMOS25 Yes – Yes Yes Yes LVCMOS18 Yes – Yes Yes Yes LVCMOS15 Yes – Yes Yes Yes LVCMOS12 Yes – Yes Yes Yes SSTL2I Yes Yes Yes Yes Yes (DDR1) SSTL2II Yes Yes Yes – Yes (DDR1) SSTL18I Yes Yes – – Yes (DDR2) SSTL18II Yes Yes – – Yes (DDR2) SSTL15I (only for I/Os used by MDDR/FDDR) Yes Yes – – Yes (DDR3) SSTL15II (only for I/Os used by MDDR/FDDR) Yes Yes – – Yes (DDR3) HSTLI Yes Yes – – Yes HSTLII Yes Yes – – Yes LVDS – Yes Yes Yes – RSDS – Yes Yes Yes – Mini LVDS – Yes Yes Yes – BUSLVDS – Yes Yes Yes (input only) – MLVDS – Yes Yes Yes (input only) – SUBLVDS (output only) – Yes Yes Yes – I/O Standards Note: For I/O pin names and bank assignments for different device packages, refer to the SmartFusion2/IGLOO2 Pin Descriptions document. 96 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Single-Ended Standards Single-ended I/O standards use a push-pull CMOS output stage with a voltage referenced to system ground. The input buffer configuration, output drive, and I/O supply voltage (VCCI) vary among the I/O standards. The advantage of these standards is that a common ground can be used for multiple I/Os. This simplifies board layout and reduces system cost. The reduced slew rate of these I/O standards causes less electromagnetic interference (EMI) on the board. However, these I/Os are not suitable for high frequency (>200 MHz) switching due to noise and higher power consumption. Low Voltage TTL (LVTTL) This is a general purpose standard (EIA/JESD8-B) for 3.3 V applications. It uses an LVTTL input buffer and a push-pull output buffer. The LVTTL output buffer can have up to eight different programmable drive strengths. Low Voltage CMOS (LVCMOS) SmartFusion2 and IGLOO2 devices provide five different kinds of LVCMOS: LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 1.8 V, LVCMOS 1.5 V, and LVCOMS1.2 V. LVCMOS 3.3 V (only in MSIO) is an extension of the LVCMOS standard (JESD8-B compliant) used for general purpose 3.3 V applications. LVCMOS 2.5 V is an extension of the LVCMOS standard (JESD8-5-compliant) used for general purpose 2.5 V applications. LVCMOS 1.8 V is an extension of the LVCMOS standard (JESD8-7-compliant) used for general purpose 1.8 V applications. The LVCMOS 1.5 V is an extension of the LVCMOS standard (JESD8-11-compliant) used for general purpose 1.5 V applications. The VCCI values for these standards are 3.3 V, 2.5 V, 1.8 V, 1.5 V, and 1.2 V, respectively. All these versions use a 3.3 V-tolerant CMOS input buffer and a push-pull output buffer. Similar to LVTTL, the output buffer has up to eight different programmable drive strengths. 3.3 V Peripheral Component Interface (PCI) This standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. With the aid of an external resistor, this I/O standard can be 5 V-compliant. Voltage-Referenced Standards I/Os using these standards are referenced to an external reference voltage (VREF). High-Speed Transceiver Logic (HSTL) Class I These are general purpose, high-speed 1.5 V bus standards (EIA/JESD8-6) for signaling between integrated circuits. The signaling range is 0 V to 1.5 V, and signals can be either single-ended or differential. HSTL requires a differential amplifier input buffer and a push-pull output buffer. These standards are used in the memory bus interface with data switching capability of up to 400 MHz. The other advantages of these standards are low power and fewer EMI concerns. HSTL has four classes, of which SmartFusion2 and IGLOO2 devices support Class I. The reference voltage (VREF) is 0.75 V. Stub Series Terminated Logic 2.5 V (SSTL2) Class I and II These are general purpose 2.5 V memory bus standards (JESD8-9) for driving transmission lines, designed specifically for driving the DDR SDRAM modules used in computer memory. The SSTL2 requires a differential amplifier input buffer and a push-pull output buffer. The reference voltage (VREF) is 1.25 V. Stub Series Terminated Logic 1.8 V (SSTL18) Class I and II These are general purpose 1.8 V memory bus standards (JESD8-15) for driving transmission lines, designed specifically for driving the DDR2 SDRAM modules used in computer memory. SSTL18 requires a differential amplifier input buffer and a push-pull output buffer. The VREF is 0.9 V. Revision 4 97 I/Os Differential Standards These standards require two I/Os per signal (called a signal pair). Logic values are determined by the potential difference between the lines, not with respect to ground. This is why differential drivers and receivers have much better noise immunity than single-ended standards. The differential interface standards offer higher performance and lower power consumption than their single-ended counterparts. Two I/O pins are used for each data transfer channel. Differential standards require resistor termination on both I/Os. Low Voltage Positive Emitter Coupled Logic Low voltage positive emitter coupled logic (LVPECL) requires that one data bit is carried through two signal lines; therefore, two pins are needed per input or output. It also requires external resistor termination. The voltage swing between the two signal lines is approximately 850 mV. When the power supply is +3.3 V, it is commonly referred to as LVPECL. Low Voltage Differential Signal Low voltage differential signal (LVDS) is a differential I/O standard. As with all differential signaling standards, LVDS requires that one data bit is carried through two signal lines, and it has inherent noise immunity over single-ended I/O standards. The voltage swing between two signal lines is approximately 350 mV. The external VREF or board termination voltage (VTT) is not required. LVDS requires the use of two pins per input or output. Reduced Swing Differential Signaling Reduced swing differential signaling (RSDS) is a signaling standard that defines the output characteristics of a transmitter and inputs of a receiver along with the protocol for a chip-to-chip interface between flat-panel timing controllers and column drivers. B-LVDS/M-LVDS Bus LVDS (B-LVDS) refers to bus interface circuits based on LVDS technology. Multipoint LVDS (M-LVDS) specifications extend the LVDS standard to high-performance multipoint bus applications. Multi-drop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. The LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the bus loading. The driver requires series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. The SmartFusion2 and IGLOO2 MSIOD has an internal circuit isolation, and the bus isolation should be taken care of in the design external to the device when using M-LVDS. Mini-LVDS A serial, intra-flat panel solution that serves as an interface between the timing control function and an LCD source driver. Sub-LVDS Sub-LVDS is a differential low-voltage signal that is a subset of the LVDS. It is very similar to LVDS signaling except that sub-LVDS uses a reduced-voltage swing and lower common mode voltage as compared to LVDS. Being similar to LVDS, SmartFusion2 and IGLOO2 devices can support the sub-LVDS signaling as part of the I/O standards. The common mode voltage and differential voltage swing are key differences between Sub-LVDS and LVDS. The maximum differential swing for Sub-LVDS is 200 mV, whereas it is 350 mV for LVDS. For Sub-LVDS, the nominal common mode voltage is 0.9 V compared to LVDS, which is 1.25 V. 98 R e visio n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric I/O Programmable Features SmartFusion2 and IGLOO2 devices support different I/O programmable features for MSIO, MSIOD, and DDRIO user I/Os. Users cannot modify some of these features, if the software rules are locked in the I/O attribute editor. Table 5-2 lists the supported I/O programmable features that can be configured through the I/O attribute editor or pdc file. Table 5-2 • SmartFusion2 and IGLOO2 I/O Features I/O Features MSIO MSIOD DDRIO – – Yes Programmable input delay Yes Yes Yes Programmable weak pull-up/down Yes Yes Yes Programmable Schmitt trigger receiver Yes Yes Yes – Yes – Bus keeping Yes Yes Yes Receiver ODT configuration Yes Yes Yes Driver impedance configuration Yes Yes Yes Hot insertion Yes – – IO state control in low power mode Yes Yes Yes Programmable slew rate control Pre-emphasis Programmable Slew-Rate Control The output buffer has a programmable slew-rate control for high-speed and low-noise performance. A faster slew-rate provides the high-speed transition and slow slew-rate reduces system noise with nominal delay in raising and falling transitions. There are four slew-rate controls configured through the I/O attribute editor or the pdc file for a particular I/O standard of DDRIO. Note: MSIOs and MSIODs do not support programmable slew-rate control. Table 5-3 lists the programmable slew-rate control options that can be set through the I/O attribute editor. Table 5-3 • Programmable Slew Rate Control User I/O DDRIO I/O Standard Slew-Rate Options LVCMOS12 0 Slow LVCMOS15 1 Medium LVCMOS18 2 Medium-Fast LVCMOS25 3 Fast Figure 5-4 shows an example slew-rate using the I/O attribute editor. Figure 5-4 • Programmable Slew-Rate Revision 4 99 I/Os Following is the example script to set slew-rate using io.pdc: set_io signal name \ -pinname A8 \ -fixed yes \ -SLEW MEDIUM_FAST \ -DIRECTION OUTPUT Signal name is the user I\O name where the designer is needed to set slew-rate. Programmable Input Delay Each I/O, when configured as an input, can be programmed with different input delays. The input delay is calculated using: Delay = D + N x 0.1 ns (N ranges from 0 to 63) EQ 1 D is the intrinsic delay or circuit delay of an input without additional delay, when N is 0. The total delay range is between D ns to D + 6.3 ns. There are 64 input delay values, which can be chosen and configured using the I/O attribute editor or the pdc file of Libero SoC for MSIO, MSIOD, and DDRIO. Table 5-5 lists the programmable input delay options available for different I/O standards, and can be set from 0 to 63 through the I/O attribute editor or the pdc file. Figure 5-5 shows an example to set input delay using the I/O attribute editor. Figure 5-5 • Programmable Input Delay Following is the example script to set input delay using io.pdc: set_io signal name -pinname A5 -fixed yes -IN_DELAY 0 -DIRECTION INPUT \ \ \ \ Signal name is the user I/O name that the designer can set for input delay. Note: Input delays can be used for hold time improvement of the input register by increasing input pin to input register delay. 100 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Programmable Weak Pull-Up and Pull-Down All user I/Os can be programmed to optional weak pull-up and pull-down, which are mutually exclusive and weakly hold the output to either VDDI or GND, respectively. Table 5-4 shows the three settings for weak pull-up and pull-down provided by Libero SoC and can be set through the I/O attribute editor or the pdc file. Table 5-4 • Programmable Weak Pull-up and Pull-down Weak Pull-Up/Pull-Down Options None Disable pull-up or pull-down Up Enable pull-up Down Enable pull-down Table 5-5 lists the weak pull-up and pull-down options available for different I/O standards, and can be set as Up, Down, or None through the I/O attribute editor or the pdc file. Figure 5-6 shows an example to set weak pull-up and pull-down using the I/O attribute editor. Figure 5-6 • Programmable Weak Pull-Up and Pull-Down Following is the example script to set weak pull-up and pull-down using io.pdc: set_io signal name -pinname A5 -fixed yes -RES_PULL Up -DIRECTION INPUT \ \ \ \ Signal name is the user I/O name where the designer is required to set weak pull-up and pull-down options. Programmable Schmitt Trigger Receiver The input buffer of an I/O can be configured as a schmitt trigger or single-ended receiver with the support of different I/O standards. To improve noise immunity for signals with slow edge rate, a schmitt trigger feature introduces hysteresis to the input signal. Refer to Table 5-5 for the I/O standards, which support the schmitt trigger option. The schmitt trigger feature can be enabled or disabled by using the I/O attribute editor or the pdc file in Libero SoC, but it is disabled by default. Figure 5-7 shows an example to enable schmitt trigger using the I/O attribute editor. Figure 5-7 • Programmable Schmitt Trigger Receiver Revision 4 101 I/Os Following is the example script to enable schmitt trigger using io.pdc: set_io signal name -pinname A5 \ -fixed yes \ -SCHMITT_TRIGGER On -DIRECTION INPUT \ \ Signal name is the user I/O name that the designer decides on enabling the schmitt trigger feature. Programmable Pre-emphasis The differential swing and output impedance of the driver set the output current limit of a high-speed signal. For high frequency differential signals, slew-rate might not be sufficient to reach the peak before the next edge comes, this produces jitter. With pre-emphasis enabled, the output current is boosted momentarily during transition to increase the slew-rate. MSIOD buffers only support pre-emphasis feature. Pre-emphasis option is NONE by default. The pre-emphasis value can be changed to MIN (dB) or MAX (dB) through the I/O attribute editor or the pdc file. Refer to Table 5-5 for the I/O standards, which support programmable pre-emphasis option. Figure 5-8 shows an example to set pre-emphasis using the I/O attribute editor. Figure 5-8 • Programmable Pre-emphasis Following is the example script to set pre-emphasis using io.pdc set_io signal name -pinname K5 -fixed yes -iostd LVDS -PRE_EMPHASIS MIN -DIRECTION OUTPUT \ \ \ \ \ Signal name is the user I/O name that the designer needs to set for pre-emphasis. Bus Keeper The main function is to weakly hold the signal on an I/O pin at its last driven state, holding it at a valid level with minimal power dissipation. The bus keeper circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended oscillation. Bus Keeper is only available in Flash*Freeze mode (not during normal operation). This feature is activated by setting LAST_VALUE option for the selected I/O pad under I/O state in Flash*Freeze mode column in the I/O attribute editor. Figure 5-9 shows the configuration in I/O Editor. Figure 5-9 • Bus Keeper Configuration in I/O Editor When regular User I/Os (MSIO, MSIOD, DDRIO) are not used, Libero configures the I/O as input buffer disabled, output buffer tristated with weak pull-up. Unused dedicated global I/Os behave similar to unused regular user I/Os. 102 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 5-5 lists the supported I/O programmable features and their support for different standards. Table 5-5 • I/O Programmable Features and Standards Input Delay (off/0-63) I/O Standards Hot-Swap Pre-Emphasis Programmable Slew-Rate Schmitt Trigger Input Resistor Pull MSIO MSIOD DDRIO MSIO MSIOD DDRIO MSIO MSIOD DDRIO MSIO MSIOD DDRIO LVTTL Yes — — Yes — — Yes — — Yes — — PCI Yes — — — — — Yes — — Yes — — LVPECL (Input only) Yes — — Yes — — — — — Yes — — LVDS33 Yes — — Yes — — — — — Yes — — LVCMOS12 Yes Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes LVCMOS15 Yes Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes LVCMOS18 Yes Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes LVCMOS25 Yes Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes LVCMOS33 Yes — — Yes — — Yes — — Yes — — SSTL2I Yes Yes Yes Yes — — — — — Yes Yes Yes SSTL2II Yes — Yes Yes — — — — — Yes — Yes SSTL18I — — Yes — — — — — — — — Yes SSTL18II — — Yes — — — — — — — — Yes SSTL15I (only for I/Os used by MDDR/FDDR) — — Yes — — — — — — — — Yes SSTL15II (only for I/Os used by MDDR/FDDR) — — Yes — — — — — — — — Yes HSTLI — — Yes — — — — — — — — Yes HSTLII — — Yes — — — — — — — — Yes LVDS Yes Yes — Yes Yes — — — — Yes Yes — RSDS Yes Yes — Yes Yes — — — — Yes Yes — Mini LVDS Yes Yes — Yes Yes — — — — Yes Yes — BUSLVDS Yes Yes — Yes — — — — — Yes Yes — MLVDS Yes Yes — Yes — — — — — Yes Yes — R e visi on 4 103 I/Os Receiver ODT Configuration SmartFusion2/IGLOO2 user I/Os support ODT features available on I/O, which is configured as input or bidirectional buffers. The ODT termination provides a good signal integrity, saves board space, and reduces external components on PCB. Receiver ODT Configuration for MSIO and MSIOD Banks Libero SoC has the following settings for receiver ODT configuration. • ODT Static • ODT Impedance ODT Static There are two types of ODT static: ON and OFF. • ON: The termination resistor for impedance matching is enabled in the chip. The value set to ODT impedance is configured as parallel termination for the input or bidirectional buffers. • OFF: The termination resistors for impedance matching are located on the printed circuit board. ODT Impedance When ODT static is ON, the valid ODT impedance values for the input or bidirectional buffers are chosen from the I/O attribute editor. Refer to Table 5-6 for ODT impedance values of different I/O standards. The ODT static and ODT impedance values can be set through the I/O attribute editor or the pdc file for all the different I/O standards. Figure 5-10 shows an example to set ODT static and ODT impedance values using the I/O attribute editor. Figure 5-10 • Receiver ODT Configuration Following is the sample script to set ODT static and ODT impedance values using io.pdc: set_io signal name -iostd SSTL18I -ODT_IMP 75 -ODT_STATIC On -DIRECTION INPUT \ \ \ \ Signal name is the user I/O name that the designer has to set ODT static and impedance values. 104 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 5-6 lists ODT impedance values for MSIO and MSIOD. Table 5-6 • ODT Impedance Values ODT Impedance I/O Standards ODT Static Enabled ODT Static Disabled Single-ended LVCMOS18 LVCMOS15 50, 75, 150 LVCMOS12 Differential External on-board terminations are required as per simulation results LVPECL (differential input only) LVDS RSDS 100 Mini LVDS BUSLVDS (inputs only) MLVDS (inputs only) Note: Due to electromagnetic concerned, ODT is not allowed for 2.5 V or higher I/O standards. Receiver ODT Configuration for DDRIO Banks SmartFusion2/IGLOO2 DDRIOs have an in-built I/O calibration engine for impedance calibration. The I/O calibration engine can be enabled or disabled by using System Builder during MDDR or FDDR configuration. The I/O calibration engine is enabled to achieve the impedance control by calibrating the I/O drivers to an external on-board resistor connected between the DDR_IMP_CALIB and VSS pins. If the I/O calibration engine is disabled, ODT impedance is not supported. In Libero SoC (System Builder Configurator), the DDR Configurator has an option to set the calibration engine ON or OFF for the LPDDR memory only. For DDR2 and DDR3 memories, by default the calibration engine is set to ON internally, and user does not have access to disable it. It is recommended to have the ODT option enabled for higher data rates. Libero SoC has the following settings for receiver ODT configuration: • ODT Static • ODT Impedance • I/O Calibration Engine The ODT static and ODT impedance values can be set through the I/O attribute editor or PDC file. The I/O calibration engine can be set through System Builder during MDDR/FDDR Configurator. ODT Static • ON: The termination resistor for impedance matching is enabled in the chip. The value set to ODT impedance is configured as parallel termination for input or bidirectional buffers. • OFF: The termination resistors for impedance matching are disabled. Changing the ODT impedance value has no effect on the impedance calibration and termination resistors are located on the printed circuit board. ODT Impedance During ODT static ON, the valid ODT impedance values for input or bidirectional buffer are chosen from the I/O attribute editor. Refer Table 5-8 and Table 5-9 for ODT impedance values of different I/O standards. Revision 4 105 I/Os If an I/O is connected to a memory controller, ODT static has no effect and it is overridden by the memory controller. If ODT is not desired, it can be disabled from the memory controller and the option is available in Libero System Builder. I/O Calibration Engine The calibration engine is part of the MDDR/FDDR memory controller IP. The engine calibrates ODT and driver impedance to an external calibration resistor. Calibration occurs during system power up and optionally during DDR refresh. Table 5-7 lists the ODT configuration options for MSIO, MSIOD, and DDRIOs. DDRIO bank may have fabric I/Os muxed with DDR controlled I/Os and can be calibrated for I/O impedance calibration. Calibrate I/Os only during power-up and re-calibrate if fabric I/Os are fully tristated. If designers re-calibrate I/Os during DDR PHY self-refresh mode, the fabric controller I/Os can possibly glitch. There are two possible solutions to avoid glitch on user I/Os. 1. If re-calibration is required for DDR controlled I/Os, designer must not use user I/Os from the same bank for any application. 2. DDR PHY self-refresh mode must not be enabled if the user wants to reuse some of the DDRIOs in a bank for general purpose. Apart from the ODT static and ODT impedance settings, the DDRIOs have an in-built I/O calibration engine to configure ODT. Table 5-7 lists the ODT configuration options for MSIO, MSIOD, and DDRIOs. Table 5-7 • ODT Configuration Options for MSIO, MSIOD, and DDRIOs User I/Os DDRIO DDRIO MDDR/FDDR controller IO calibration engine Enable Disable MSIO - ODT configuration Enable Configure ODT with calibration engine and calibrated to external resistor Disable ODT not available Disable ODT not available - Configure ODT using fixed value through IO attribute editor. MSIOD ODT can be enabled for any I/O in the DDRIO bank, even if the I/O is not associated with DDR controller. To enable ODT, a designer needs the DDR controller in the design with the I/O calibration enabled. All I/Os in the DDRIO bank (including the I/O that is not used by the controller) can be calibrated. When DDR controller is used in a bank, it takes over ODT_STATIC of its own I/Os only. ODT for other I/Os in the same bank can still be controlled using ODT_STATIC option for that particular I/O. Table 5-8 lists the settings available for the designer to configure DDRIO ODT impedance using I/O calibration engine, I/O attribute editor and external on-board resistor. Table 5-8 • DDRIO ODT Configuration- for I/O Connected to Fabric Set Through System Builder1 Memory LPDDR 106 I/O Standards LVCMOS 184 I/O Calibration Engine Set Through I/O Attribute Editor ODT Static ODT Impedance Resistor to be Mounted on PCB On-board Resistor for On-board External Terminations3 I/O Calibration2 - ON- Not supported - - - OFF OFF - - Optional ON ON 50, 75, 150 150 ± 1% Optional R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Table 5-8 • DDRIO ODT Configuration- for I/O Connected to Fabric (continued) Set Through System Builder1 Memory DDR2 DDR3 I/O Standards I/O Calibration Engine SSTL18 ON (by default) SSTL15 User does not have access to disable. Set Through I/O Attribute Editor Resistor to be Mounted on PCB ODT Static ODT Impedance ON 50, 75, 150 150 ± 1% Optional OFF - - Required ON 20, 30, 40, 60, 120 240 ± 1% Optional OFF - - Required OFF OFF - - Required LVCMOS18 OFF OFF - - Required HSTLI OFF OFF - - Required ON ON 50, 75, 150 - Optional LVCMOS18 ON ON 50, 75, 150 - Optional HSTLI ON ON 47.8 - Optional LVCMOS12 On-board Resistor for On-board External I/O Calibration2 Terminations3 LVCMOS15 DDRIO (nonmemory) HSTLII LVCMOS12 LVCMOS15 HSTLII Notes: 1. I/O calibration engine and drive strength can be selected through System Builder during external memory MDDR/FDDR controller configuration. The I/O calibration engine is available only for DDRIOs. 2. Resistor should be mounted between DDR_IMP_CALIB and VSS. 3. Values and location of on-board external terminations are based on the signal integrity analysis. 4. LVCMOS18 is a non-terminated standard and usually does not require on-board external terminations. Table 5-9 • DDRIO ODT Configuration- for I/O Connected to DDR Controller Set Through System Builder Memory LPDDR I/O Standards LVCMOS 18 I/O Calibration Engine Set Through I/O Attribute Editor Local ODT ODT Impedance Resistor to be Mounted on PCB On-board Resistor for On-board External I/O Calibration Terminations OFF ON- Not Supported - - - OFF OFF - - Optional ON ON 50, 75, 150 150 ± 1% Optional Revision 4 107 I/Os Table 5-9 • DDRIO ODT Configuration- for I/O Connected to DDR Controller (continued) Set Through System Builder Memory DDR2 DDR3 I/O Standards SSTL18 SSTL15 I/O Calibration Engine ON (by default) User does not have access to disable. Set Through I/O Attribute Editor Resistor to be Mounted on PCB Local ODT ODT Impedance On-board Resistor for On-board External I/O Calibration Terminations ON 50, 75, 150 150 ± 1% Optional OFF - - Required ON 20, 30, 40, 60, 120 240 ± 1% Optional OFF - - Required Driver Impedance Configuration SmartFusion2/IGLOO2 I/Os support driver impedance configuration only for the output or bidirectional buffers.The driver impedance internal series termination provides a good signal integrity, saves board space, and reduces external components on the PCB. The Libero SoC tool has output drive settings for driver impedance configuration. Table 5-10 shows the options of driver impedance configurations. Table 5-10 • Driver Impedance Configurations User I/Os DDRIO DDRIO MSIO/ MSIOD MDDR/FDDR Controller I/O Calibration Block Driver impedance Enable Configure driver impedance with I/O calibration engine and calibrated to external on-board reference resistor. The target impedance must be set through the I/O attribute editor. Disable Driver impedance disabled. Disable Disable Driver impedance disabled. — — Enable Configure driver impedance using fixed values depending on the drive strength set through the I/O attribute editor. Figure 5-11 shows an example to set output drive using the I/O attribute editor. Figure 5-11 • Output Drive Impedance 108 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Following is the example script to set output drive using io.pdc set_io signal name -pinname A8 -fixed yes -OUT_DRIVE 8 -DIRECTION OUTPUT \ \ \ \ Signal name is the user I/O name for which the designer wants to set driver impedance. Driver Impedance Configuration for MSIO/MSIODs SmartFusion2/IGLOO2 device output or bidirectional buffers have a programmable drive-strength control for certain I/O standards to mitigate the effects of high signal attenuation due to the long transmission line. Table 5-11 lists the programmable drive strengths and these can be set through the I/O attribute editor: Table 5-11 • Driver Impedance Configurations for MSIO/MSIODs I/O Standards Output Drive Strength (mA) MSIO MSIOD 2, 4, 8, 12, 16, 20 — LVCMOS12 2, 4 2, 4 LVCMOS15 2, 4, 6, 8 2, 4, 6 LVCMOS18 2, 4, 6, 8, 10, 12 2, 4, 6, 8, 10 LVCMOS25 2, 4, 6, 8, 12, 16 2, 4, 6, 8, 12 LVCMOS33 2, 4, 8, 12, 16, 20 — LVTTL For other supporting I/O standards, output drive strength is fixed and different for each bank type and the I/O standard combination. For example, PCI standard output drive strength is 20 mA and HSTL is 8 mA. Driver Impedance Configuration for DDRIOs The calibration engine is enabled to achieve the impedance control by calibrating the I/O drivers to an external I/O calibration on-board resistor. If I/O calibration engine is disabled, driver impedance is disabled. In Libero SoC, option is available in the DDR System Builder Configurator to set the calibration engine ON or OFF for the LPDDR memory alone. For DDR2/DDR3 memories, the calibration engine is set to ON internally by default. The output drive strength for DDR2/DDR3 memory interfaces can be selected through System Builder during an external memory MDDR/FDDR controller configuration. Table 5-12 lists the driver impedance configuration for DDRIOs with the DDR controller enabled. Table 5-12 • Driver Impedance Configurations for DDRIOs MDDR/FDDR Controller Enable Memory Type I/O Standards Output Drive Strength (mA) LPDDR LVCMOS18 2, 4, 6, 8, 10, 12, and 16 DDR2 SSTL18 Half/Full DDR3 SSTL15 Half/Full The driver impedance depends on the value of drive strength (mA) set through the I/O attribute editor. The maximum performance is achieved by setting the highest output drive strength of the device. IBIS simulation can show the effects of different drive strengths, termination resistors, and capacitive loads on the system. Revision 4 109 I/Os The DDRIO bank has more I/Os than required for the memory controller. These I/Os can be used for general FPGA I/Os with some caveats. The memory controller calibration engine affects all DDRIO bank I/Os. A re-calibration event results in glitches on these DDRIOs when configured as outputs and also configured as inputs with ODT enabled. DRRIO configured as inputs with ODT OFF does not experience calibration related glitches. Table 5-13 lists the driver impedance configuration for DDRIOs without the DDR controller enabled. Table 5-13 • Driver Impedance Configurations for DDRIOs without DDR Controller Drive Strength Setting Through I/O Attribute Editor (mA) Corresponding Driver Impedance (Ω) LVCMOS25 2, 4, 6, 8, 12,16 75, 60, 50, 33, 25, 20 LVCMOS18 2, 4, 6, 8, 10, 12,16 75, 60, 50, 33, 25, 20 LVCMOS15 2, 4, 6, 8, 10, 12 75, 60, 50, 40 LVCMOS12 2, 4, 6 75, 60, 50, 40 SSTL2I 8.1 42 SSTL2II 16.2 20 SSTL18I 6.5 42 SSTL18II 13.4 20 SSTL15I — 40 SSTL15II — 34 HSTLI 8 47.8 HSTLII 16 25.5 DDRIOs I/O Buffer Structure 9'', 9'', 3DG 2XW%XIIHU 6PDUW)XVLRQ ,*/22 )3*$ 0HPRU\ 9'', 3DG =4 ,Q%XIIHU 3DG ''5B,03B&$/,% Figure 5-12 • Driver Impedance Configurations for MSIO/MSIODs 110 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Internal Clamp Diode System controller keeps the user I/Os in tristate mode during power-up. The user I/Os have internal clamp diodes to protect the device I/Os. All MSIOs are cold separable as the internal clamp diodes are always disabled, except if MSIOs are configured in the PCI I/O standards, which are not cold separable. For more information, refer to AC396: SmartFusion2 and IGLOO2 in Hot Swapping and Cold Sparing Application Note. Low-Power Signature Mode and Activity Mode SmartFusion2 and IGLOO2 devices support Flash*Freeze mode, where several device resources are put into a low-power state using various power management hooks available for each resource. The following two methods can be used for SmartFusion2 and IGLOO2 devices wake-up from Flash*Freeze mode: • Real time counter (RTC) timeout • I/O cell wake-up In the RTC timeout method, the timeout value is set in the RTC before entering Flash*Freeze mode. In the I/O cell wake-up method, any activity on a specified input or matching a user-defined pattern value (signature) on a number of inputs wakes up the device. There are two modes for exiting low-power mode (Flash*Freeze mode): signature mode and activity mode. Each I/O can be configured in Libero SoC to be in either of these modes. Each DDRIO has four options for configuring and controlling low-power exit: • I/O is not designated for low-power exit monitoring • I/O is designated for low-power activity monitoring • I/O is designated for low-power signature, look for 0 • I/O is designated for low-power signature, look for 1 Signature Mode After entering low-power mode, every I/O designated as a signature I/O becomes input-only. All other I/Os are tristated, held by bus hold, or weakly pulled-up or pulled-down. The signature I/O is pre-configured to check the signal (0 or 1) on each pin in the Libero SoC I/O Editor. A group of pins are configured in the I/O Editor to form a signature pattern. In low-power mode when the correct pattern exits on these pins, the device exits low-power mode. Activity Mode In activity mode, the value at I/O pin is latched before the device goes to low-power mode. The I/O is configured for wake-on change input logic 0 or 1 in the Libero SoC I/O Editor. When an I/O activity is detected on the configured pin, the device exits low-power mode. 5 V Input Tolerance and Output Driving Compatibility (only MSIO) 5 V Input Tolerance I/Os can support 5 V input tolerance when LVTTL 3.3 V, LVCMOS 3.3 V, or LVCMOS 2.5 V configurations are used. There are three recommended solutions for achieving 5 V receiver tolerance. All the solutions meet the requirement of limiting the voltage at the input to 3.45 V or less. In fact, the absolute maximum I/O voltage rating is 3.45 V, and any voltage above this can cause long-term gate oxide failure. Solution 1 The board design must ensure that the reflected waveform at the pad does not exceed the limits provided in the recommended operating conditions in the datasheet. Adhering to the recommended operating conditions is a requirement to put in place to ensure long-term reliability of input tolerance. Revision 4 111 I/Os This solution also works for a 3.3 V PCI configuration, but the internal diode must not be used for clamping, and the voltage must be limited by two external resistors. Relying on diode clamping creates an excessive pad DC voltage of 3.3 V + 0.7 V = 4 V. This solution requires two on-board resistors. Here are some examples of possible resistor values based on a simplified simulation model with no line effects and with a 10 Ω transmitter output impedance, where Rtx_out_high = [VCCI – VOH] / IOH and Rtx_out_low = VOL / IOL). EQ 2 Example 1 (high speed, high current): Rtx_out_high = Rtx_out_low = 10 Ω R1 = 36 Ω (±5%), P(r1)min = 0.069 Ω R2 = 82 Ω (±5%), P(r2)min = 0.158 Ω Imax_tx = 5.5 V / (82 × 0.95 + 36 × 0.95 + 10) = 45.04 mA tRISE = tFALL = 0.85 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 4 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Example 2 (low-medium speed, medium current): Rtx_out_high = Rtx_out_low = 10 Ω R1 = 220 Ω (±5%), P(r1)min = 0.018 Ω R2 = 390 Ω (±5%), P(r2)min = 0.032 Ω Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA tRISE = tFALL = 4 ns at C_pad_load = 10 pF (includes up to 25% safety margin) tRISE = tFALL = 20 ns at C_pad_load = 50 pF (includes up to 25% safety margin) Other values of resistors are also allowed, as long as the resistors are sized appropriately to limit the voltage at the receiving end to 2.5 V < Vin(rx) < 3.6 V when the transmitter sends a logic 1. This range of Vin_dc(rx) must be ensured for any combination of the transmitter supply (5 V ± 0.5 V), transmitter output resistance, and board resistor tolerance. 5.5 V 3.3 V Rext1 Rext2 Requires two board resistors LVCMOS 3.3 V I/Os Figure 5-13 • 5 V-Input Tolerance Solution 1 Solution 2 The board design must ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. This is a requirement to ensure long-term reliability. This solution also works for a 3.3 V PCI configuration, but the internal diode must not be used for clamping, and the voltage must be limited by the external resistors and Zener. Adhering to the recommended operating conditions on the diode clamping creates an excessive pad DC voltage of 4 V (3.3 V + 0.7 V = 4 V). 112 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric 5.5 V 3.3 V Rex Zener 3.3 V Requires one board resistors, one Zener 3.3 V diode, LVCMOS 3.3 V I/Os Figure 5-14 • 5 V Input Tolerance Solution 2 Solution 3 The board-level design must ensure that the reflected waveform at the pad does not exceed limits provided in the overshoot and undershoot limits. This is a long-term reliability requirement. Bus switch provides high-speed switching without adding propagation delay or generating additional ground bounce noise. These are ideal for voltage translation interfaces between buses, and in applications that require isolation and protection. Well-implemented bus switch designs maximize the bus speed. This solution also works for a 3.3 V PCI/PCIX configuration, but the internal diode must not be used for clamping, and the voltage must be limited by the bus switch. Adhering to the recommended operating conditions on the diode clamping might create an excessive pad DC voltage of 4 V (3.3 V + 0.7 V = 4 V). Solution 3 requires a bus switch on the board and LVTTL/LVCMOS 3.3 V I/Os. 9'', 9 %XV6ZLWFK ,'746; RUHTXLYDOHQW 6PDUWIXVLRQ ,QSXW3LQ 9 9 2II&KLS 2Q&KLS Figure 5-15 • 5 V Input Tolerance Solution 3 Revision 4 113 I/Os Table 5-14 shows the slew rate control for all the three solutions. Table 5-14 • Slew Rate Control Solutions Board Components Speed high1 Limitations 1 Two resistors Low to 2 Resistor and Zener 3.3 V Medium Limited to transmitter's drive strength 3 Bus switch High N/A Limited to transmitter's drive strength Note: • Speed and current consumption increase as board resistance values decrease. 5 V Output Driving Compatibility SmartFusion2 and IGLOO2 I/Os must be set to 3.3 V LVTTL mode or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there is no external I/O pull-up resistor to 5 V, since this pulls the I/O pad voltage beyond the 3.6 V absolute maximum value and, consequently, cause damage to the I/O. When set to 3.3 V LVTTL mode or 3.3 V LVCMOS mode, the I/Os can directly drive signals into 5 V TTL receivers. In fact, noise margin levels VOL = 0.4 V and VOH = 2.4 V in both 3.3 V LVTTL and 3.3 V LVCMOS modes exceed the VIL = 0.8 V and VIH = 2 V level requirements of 5 V TTL receivers. Therefore, level 1 and level 0 are recognized correctly by 5 V TTL receivers. I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS/HPMS Peripherals DDRIOs with MDDR/FDDR If MDDR/FDDR is selected, Libero SoC automatically connects MDDR/FDDR signals to the DDRIOs. Depending on the memory configuration, the required DDRIOs are used by Libero SoC. The unused DDRIO are available to connect to the FPGA fabric. DDRIOs with Fabric If MDDR/FDDR is not selected, DDRIOs are available to the FPGA fabric. DDRIOs must be manually configured in Libero SoC. MSIOs/MSIODs with MSS or HPMS Peripherals If M S S o r HPMS peripherals are selected, Libero SoC automatically connects M S S o r HPMS peripheral signals to either MSIOs or to the MSIODs. The unused MSIOs or MSIODs are available to connect to the FPGA fabric. MSIOs/MSIODs with Fabric If HPMS peripherals are not selected, MSIOs/MSIODs are available to the FPGA fabric. MSIOs and MSIOD must be manually configured in Libero SoC. JTAG I/O The system controller implements the functionality of a JTAG slave with IEEE 1532 support, which also implies IEEE 1149.1 compliance. JTAG communicates with the system controller using a command register that conveys the JTAG instruction to be executed and a 128-bit data I/O buffer that transfers any associated data. The TAP controller uses 8-bit instructions consistent with previous Microsemi families. The JTAG pin standards are in accordance with MSIO standards. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). The I/O voltage of JTAG interface is set by powering the 114 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric VDDI(JTAG) power pin with the desired I/O voltage. Core voltage must also be powered for the JTAG state machine to operate, even if the device is in bypass mode. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies power supply and board design. If the JTAG interface is not used, with no plan to use it even in the future, the VDDI(JTAG) pin together with the TRSTB pin should be tied to GND. For mandatory bank supplies, refer to AC393: Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Application Note. Table 5-15 • JTAG Pin Description Name Type JTAGSEL Input Description JTAG controller selection Depending on the state of the JTAGSEL pin, an external JTAG controller detects the FPGA fabric TAP/auxiliary TAP. The JTAGSEL pin should be connected to an external pull-up resistor such that the default configuration selects the FPGA fabric TAP. TCK Input • Logic 1: FPGA fabric TAP selected • Logic 0: AUX TAP selected Test clock Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying it off TCK to GND or VDDI(JTAG) through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. To operate at all VDDI(JTAG) voltages, the resistor values mentioned in Table 5-16 are recommended. TDI Input Test data Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pullup resistor on the TDI pin. TDO Output Test data Serial output for JTAG boundary scan, ISP, and UJTAG usage. TDS does not have an internal pull-up/pull-down resistor. Signal drive strength depends on the operating voltage: 3.3 V (16 mA), 2.5 V (16 mA), 1.8 V (12 mA), or 1.5 V (8 mA). TMS – Test mode select The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, and TRSTB). There is an internal weak pull-up resistor on the TMS pin. The signal drive strength depends on the operating voltage: 3.3 V (16 mA), 2.5 V (16 mA), 1.8 V (12 mA), or 1.5 V (8 mA). TRSTB – Boundary scan reset pin. The TRSTB pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin. If JTAG is not used, an external pull-down resistor must be included to ensure the TAP is held in reset mode. The resistor values must be chosen from Table 5-16 and must satisfy the parallel resistance value requirement (multiple devices connected via JTAG chain). The values in Table 5-16 correspond to the resistor recommended when a single device is used. In critical applications, a fault in the JTAG circuit allows the device entering an undesired JTAG state. In such cases, Microsemi recommends tying off TRSTB to GND through a resistor placed close to the FPGA pin. The TRSTB pin also resets the serial wire JTAG debug port (SWJ-DP) circuitry within the Cortex-M3 processor. Revision 4 115 I/Os Table 5-16 • Recommended Tie-Off Values for the TCK and TRST Pins Tie-Off Resistance1, 2 VDDI(JTAG) VDDI(JTAG) at 3.3 V 200 Ω to 1 KΩ VDDI(JTAG) at 2.5 V 200 Ω to 1 KΩ VDDI(JTAG) at 1.8 V 500 Ω to 1 KΩ VDDI(JTAG) at 1.5 V 500 Ω to 1 KΩ Notes: 1. The TCK pin can be pulled up/down. 2. The TRSTB pin can only be pulled down. Dedicated I/O SmartFusion2 and IGLOO2 devices have following dedicated I/Os: • Device Reset I/O • Crystal Oscillator I/O • SERDES I/O Device Reset I/O SmartFusion2 and IGLOO2 devices have a dedicated input reset, which, when asserted, resets the device (chip) as a whole. The device reset feeds the system controller, which generates the system reset for the reset controller to reset the entire device. Figure 5-16 shows the full chip reset flow from device reset. System Controller Reset Controller DEVRST_N Chip-level Resets System Resets Figure 5-16 • Chip Level Resets From Device Reset Asserting device reset causes a SmartFusion2 or IGLOO2 device to exit Flash*Freeze mode; this is very useful in recovering from a situation where the device enters Flash*Freeze mode without the Flash*Freeze exit mechanism being correctly configured in the I/O cells or in the real-time clock (RTC). This can be considered a cold reset, as it resets all parts of the device. For more information on how different reset signals are generated, see in the “Reset Controller” chapter in the SmartFusion2/IGLOO2 High Performance Memory Subsystem User Guide. Port List and I/O Pins Table 5-17 • Device Reset I/O Pin Pin Type I/O DEVRST_N Analog Input 116 Description Device reset is an asynchronous input, and powered by VPP (active low). R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Crystal Oscillator I/O SmartFusion2 and IGLOO2 devices have two dedicated I/O pins (EXTLOSC and XTLOSC) connected to each on-chip crystal oscillator. These I/O pins can be connected to a crystal, (ceramic) resonator, or an RC circuit. Crystal Oscillator I/O Pins Table 5-18 • Crystal Oscillator I/O Pins Pin Type I/O EXTLOSC Analog Input Dedicated pin for a crystal external RC network connection XTLOSC Input Dedicated pin to be used only for crystal connection Analog Description For detailed information on the configuration of these pins and operational modes, refer to SmartFusion2/IGLOO2 Clocking Resources User Guide. SERDES I/O The SERDES I/Os available in SmartFusion2 and IGLOO2 devices are dedicated to high-speed serial communication protocols. The SERDES I/O supports any user-defined high-speed serial protocol implementation in fabric. Supported protocols include PCI Express 2.0, XAUI, serial gigabit media independent interface (SGMII), and serial rapid I/O (SRIO). These protocols access the SERDES lanes through the physical media attachment (PMA) and physical coding sub-layer (PCS) within SERDES interface. For more information, refer to SmartFusion2/IGLOO2 FPGA High Speed Serial Interfaces User Guide. This section describes the SERDES I/O pins, SERDES I/O banks, SERDES I/O standards, and boardlevel design considerations available. SERDES I/O Banks The SERDES I/Os reside in dedicated I/O banks. The number of SERDES I/Os depends on the device size and pin count. For example, the M2GL050 device has two SERDES_IFs (SERDES_IF0 and SERDES_IF1), which reside in two out of ten I/O banks (bank #6 and bank #9). The M2GL010 device, on the other hand, has only one SERDES_IF (SERDES_IF0), which resides in bank #5. For details on I/O bank locations and I/O electrical specifications, refer to SmartFusion2/IGLOO2 FPGA DataSheet. SERDES I/O Pins Each SERDES interface in SmartFusion2 and IGLOO2 devices has four SERDES I/O data lanes or sixteen SERDES I/Os available for accessing the SERDES interface (SERDESIF block). Each data lane has two pairs of differential signals: one for transmit data (TxDP, TxDN) and the other for receive data (RxDP, RxDN). Data Ianes are multiplexed to support different serial protocols and are scalable to various link widths such as x1, x2, and x4. These settings can be configured in the SERDES_IF macro using the Libero SoC software. Each SERDES_IF has two sets of dedicated power, clock, and reference signals. One set for data lanes 0 and 1 and another for data lanes 2 and 3. For SERDES I/O pin names and descriptions, refer to the SmartFusion2/IGLOO2 Pin Descriptions. Revision 4 117 I/Os List of Changes The following table shows important changes made in this document for each revision. Date Changes Page Revision 4 Updated "Supported I/O Standards" section on page 96 (SAR 64101, 73141). 96 (April 2016) Updated "I/O Programmable Features" section on page 99 with ODT, Driver impedance, and other features (SAR 69090, 72477, 68945). 99 Updated Figure 5-2 on page 94 for DDRIO (SAR 68900). 94 Added "Internal Clamp Diode" section section (SAR 64379). 111 Updated "Introduction" section and "Functional Description" section (SAR 52110). 91 Updated Figure 5-1 (SAR 52110). 92 Updated Table 5-1 (SAR 57577,SAR62411, and SAR 57703). 96 Updated Table 5-2 (SAR 60145). 99 Revision 3 (May 2015) Updated "Programmable Slew-Rate Control" section and Table 5-5 (SAR 55824). Revision 2 (March 2014) Updated "Receiver ODT Configuration" section (SAR 61516). 104 Updated "5 V Input Tolerance and Output Driving Compatibility (only MSIO)" section (SAR 62414). 111 Updated "I/O Banks" section 95 Merging the SmartFusion2 and IGLOO2 I/Os chapter. NA Updated the "Receive Buffer" on page 93 for DDR support in low power devices (55545). 93 Added the "Sub-LVDS" on page 98 (59459). 98 Added "Solution 3" on page 113 for 5 V input tolerance section (53747). 113 Updated "Introduction" section, "I/O Banks" section, "Low-Power Signature Mode and Activity Mode" section, Table 5-2, and Table 5-15 (SAR 55075). Revision 1 Updated Figure 5-1 (SAR 50735). (September 2013) Updated Figure 5-4 and Figure 5-5 (SAR 50742). 118 99, 103 91, 95, 111, 99, 115 92 99, 100 Updated "B-LVDS/M-LVDS" section (SAR 50731). 98 Updated "5 V Input Tolerance and Output Driving Compatibility (only MSIO)" section (SAR 50733). 111 Updated "SERDES I/O Pins" section (SAR 50633). 117 R e vi s i o n 4 SmartFusion2 SoC and IGLOO2 FPGA Fabric Glossary Acronyms DDRIO Double data rate input output MDDR Microcontroller subsystem double data rate FDDR Fabric double data rate IOA Input output analog IOD Input output digital LPDDR Low-power double data rate memory ODT On-die termination HPMS High-performance memory subsystem HSTL High-speed transceiver logic SSTL Stub series terminated logic LVDS Bus LVDS ESD Electrostatic discharge protection HSTL High-speed transceiver logic LPE Low power exit LVDS Low-voltage differential signal LVPECL Low-voltage positive emitter coupled logic LVTTL Low voltage transistor transistor logic MLVDS Multipoint LVDS Revision 4 119 I/Os MSIO Multi-standard I/O MVN MultiView Navigator ODT On-die termination RSDS Reduced swing differential signaling SSTL Stub series terminated logic SERDES Serializer/deserializer Terminology Bus Keeper Holds the signal on an I/O pin at its last driven state. Hot Insertion Capability to connect I/O to external circuitry even after power-up. Low-power Exit Logic for the chip to come out from low-power state. 120 R e vi s i o n 4 A – List of Changes The following table shows important changes made in this document for each revision. Date Revision 4 (April 2016) Revision 3 (May 2015) Revision 2 (March 2014) Revision 1 (September 2013) Changed Chapters List of Changes Updated "I/Os" chapter (SAR 69090, 64101, 73141, 72477, 68945, 68900, 64379). "List of Changes" on page 118 Updated "Fabric Architecture" chapter (SAR 62858). "List of Changes" on page 18 Update "LSRAM" chapter (SAR 59994). "List of Changes" on page 44 Updated "Micro SRAM (uSRAM)" chapter (SAR 62858). "List of Changes" on page 66 Updated "Mathblocks" chapter (SAR 62858). "List of Changes" on page 90 Updated "I/Os" chapter (SAR 52110, SAR 55765, SAR 57577, SAR 57703, SAR 60145, SAR 55824, SAR 61516, SAR 62414, SAR 62411, SAR55545, SAR53747, SAR58123, SAR58742, SAR59459, SAR61136, SAR59641). "List of Changes" on page 118 Updated "Fabric Architecture" chapter (SAR 55075). "List of Changes" on page 18 Updated "Mathblocks" chapter (SAR 55075). "List of Changes" on page 90 Updated "I/Os" chapter (SAR 55075). "List of Changes" on page 118 Updated "I/Os" chapter (SAR 50633, SAR 50672, SAR 50731, SAR 50733, SAR 50735, SAR 50742). "List of Changes" on page 118 Revision 4 121 B – Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world, 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues, and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Technical Support For Microsemi SoC Products Support, visit http://www.microsemi.com/products/fpga-soc/designsupport/fpga-soc-support Website You can browse a variety of technical and non-technical information on the SoC home page, at www.microsemi.com/soc. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is [email protected]. Revision 4 122 Product Support My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email ([email protected]) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. ITAR Technical Support For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page. 123 R e vi s i o n 4 Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense and security, aerospace, and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and synchronization devices and precise time solutions; voice processing devices; RF solutions; discrete components; enterprise storage and communications solutions, security technologies, and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees worldwide. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: [email protected] © 2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. 50200445-4/04.16