IGLOO2 FPGAs Up to 150K LEs | DSP | 5G SERDES | PCI Gen2 | XAUI | I/O Density CO LO A B C D CIN _BYP EN NC_SR CLK RST LUT4 OVFL UB ADD_S ] A[17:0 D EN RO D +/- X EN ] C[43:0 SL ] B[17:0 0 17 SHIFT >> 17 ASC SEL_C :0] SN-1[43 More Resources in Low Density Devices Lowest Power Proven Security Exceptional Reliability SN[43: IGLOO2 FPGAs Microsemi IGLOO2 FPGAs Offer More Resources in Low Density Devices With The Lowest Power, Proven Security and Exceptional Reliabilit IGLOO2 FPGAs are ideal for general purpose functions such as Gigabit Ethernet or dual PCI Express control planes, bridging functions, input/output (I/O) expansion and conversion, video/image processing, system management and secure connectivity. Microsemi FPGAs are used by customers in in Communications, Industrial, Medical, Defense, and Aviation markets. Communications Industrial IGLOO2 Advantages More Resources in Low Density Devices • PCIe Gen2 support in 10K LE • High performance memory subsystem • Highest I/O density With Clear Advantages • Lowest Power • Reduce total power by ~20-40% • 70 mW per 5G SERDES • Proven Security • Protection from overbuilding and cloning • Secure boot for FPGA & processors • Exceptional Reliability • SEU immune zero FIT flash FPGA configuration • Reliability safety critical and mission critical systems 1 Defense Automotive IGLOO2 FPGA Architecture IGLOO2 FPGAs offer 5K-150K LEs with a high performance memory subsystem, up to 512KB embedded flash, 2 x 32 KB embedded static random-access memory (SRAM), two direct memory access (DMA) engines and two double data rate (DDR) memory controllers. Architecture highlights include: • 16x 5Gbps SERDES, PCIe, XAUI / XGXS+ Native SERDES • Power as low as 7mW Standby, Typical • Up to 150K LEs, 5Mbit SRAM, 4Mbit eNVM • DPA Hardened, AES256, SHA256, On-Demand NVM Data Integrity Check • Hard 667 mbps DDR2/3 controllers • SEU Protected/Tolerant Memories: eSRAMs, DDR Bridges • Integrated DSP processing blocks High Performance Memory Subsystem Up to 16 Lanes Multi Protocol 5G SERDES PMA Standard Cell / SEU Immune PMA PMA XAUI XGXS SPI eNVM Direct Attach x1,x2,x4 AHB Bus Matrix PCI Express x1,x2,x4 Flash Based / SEU Immune COMM_BLK PMA AXI/AHB, XGMII, Direct 20 Bit Bus System Controller Up to 150K Logic Elements SHA256 ECC NRBG Math Blocks (18x18) Micro SRAM (64x18) Large SRAM (1024x18) 11-240 11-240 10-236 DDR Bridge AXI/AHB 667 Mb/s DDR Controller/PHY AXI/AHB 667 Mb/s DDR Controller/PHY SRAM-PUF Math Blocks (18x18) Micro SRAM (64x18) PDMA HPDMA FIC AES256 eSRAM_1 FIC FPGA Fabric eSRAM_0 Large SRAM (1024x18) Multi-Standard GPIO (1.2 – 3.3 V, LVDS, HSTL/SSTL) AES Advanced Encryption Standard AHB Advanced High-Performance Bus APB Advanced Peripheral Bus SHA Secure Hashing Algorithm AXI Advanced eXtensible Interface XAUI 10 Gbps Attachment Unit Interface DDR Double Data Rate XGMII 10 Gigabit Media Independent Interface ECC Elliptical Curve Cryptography XGXS XGMII Extended Sublayer PCI Express FIC HPMS Fabric Interface Controller High Performance Memory Subsystem DDR3 Controller Secure Flash 2 General Purpose Applications PCIe 1G Control Plane • PCIe Gen2 in 10K LE devices with I/O Expansion GigaBit Ethernet PHY PCIe 10/100 Ethernet PHY SPI SERDES USB SPI Peripherals Security DDR3 DRAM High Performance Memory System SPI Flash I2C GPIO DDR3 DRAM LCD Flash, SRAM FPGA Fabric CPU IGLOO2 FPGA MCU Multi-Axis Motor Control • Deterministic and Secure Multi-axis/High RPM Solutions • Motor Control IP & Development Kit Timing System Control Automation Controller/ Host CPU Inverter Bridge, IGBTs, SiC MOSFETS PWM Timing Host Interface PID Control Loop eNVM, eSRAM Power Supply/ Conversion Sensors: Speed, Torque, Position A/D Conversion Transforms Power Management IGLOO2 FPGA Audio Processing, Storage and Retrieval • I2S to SPI bridge allows multiple audio recordings & playbacks 2 Digital MEMS Microphones IGLOO2 FPGA Timberwolf ZL38051 Audio Processor I2S Interface Conversion, Buffering & Formatter Host Interface Audio Jack 3 SPI Interface SPI Flash General Purpose Applications Bridging & Co-Processing • SERDES to Bridge CPRI, ADC/DAC DFE Co - Processing CPRI CPRI Memory Subsystem ADC/DAC Interfacing JESD204B IGLOO2 FPGA Secure Connectivity • Best–in-class security data communications and anti-tamper • Ultra-low static power for portability IGLOO2 FPGA Receiver Antenna ADC RF Front End Transmitter DAC DDC Baseband Processing Memory Subsystem Crypto Data Processing DCU Board Initialization • PMBus, Instant-on RJ45 / SFP Ethernet PHY SGMII PoE PD69208 SGMII O O O Host Processor I2C SGMII I2C Controller Ethernet Switch RJ45 / SFP Ethernet PHY SGMII PoE PD69208 RJ45 / SFP Ethernet PHY PoE PD69208 To PoE Managers eSPI 5V PoL Supply e SPI Controller PMBus PMBus Interface System Control IGLOO2 FPGA 3.3V PoL Supply 2.5V PoL Supply 1.5V PoL Supply SGMII Clock Management To Status LEDs 4 IGLOO2 FPGA Features High-Performance Memory Subsystem High Performance Memory Subsystem COMM_BLK SPI eNVM AHB Bus Matrix eSRAM_0 eSRAM_1 PDMA FIC HPDMA FIC DDR Bridge AXI/AHB 667 Mb/s DDR Controller/PHY AXI/AHB 667 Mb/s DDR Controller/PHY • 64 KB embedded SRAM (eSRAM) • Up to 512 KB embedded nonvolatile memory (eNVM) • One SPI/COMM_BLK • DDR bridge (2 Port) with 64-Bit AXI interface • Non-blocking, multi-layer AHB bus matrix allowing multi-master scheme supporting 4 masters and 8 slaves • Two AHB/APB interfaces to FPGA fabric (master/slave capable) • Two DMA controllers to offload data transactions -- 8-channel peripheral DMA (PDMA) for data transfer between soft peripherals in fabric and embedded eSRAMs as well as support for memory to memory transfers -- eSRAM and external DDR memory for efficient data movement between embedded real time memories • Up to 16 lanes at up to 5Gbps • Dual based reference clocks with single-lane rate granularity -- Tx and Rx PLLs programmable for each lane -- Reference clock is shared per groups of two lanes • Transmitter features -- Programmable pre/post-emphasis -- Programmable impedance -• --• ---- • High-performance and power optimized multiplications operations • Supports 18x18 signed multiplication natively • Supports 17x17 unsigned multiplications • Supports dot product: the multiplier computes (A[8:0] x B[17:9] + A[17:9] x B[8:0]) x 29 Independent third input C with data width 44-bits completely registered • Supports both registered and unregistered inputs and outputs • Internal cascade signals (44-bit CDIN and CDOUT) enable cascading of the mathblocks to support larger accumulator, adder, and subtractor without extra logic • Supports loopback capability • Adder support: (AxB) + C or (AxB) + D or (AxB) + C + D • Clock-gated input and output registers for power optimizations • A fully permutable 4-input LUT • A dedicated carry chain based on the carry look-ahead technique • A separate flip-flop which can be used independently from the LUT • Clock-gated input and output registers for power optimizations IGLOO2 FPGA SERDES PCI Express Protocol x1, x2, x4 Custom Logic 64-bit AXI/AHB PCS XAUI XGXS 802.3 or Custom Protocol XGMII TXDn 4x20-bit EPCS PMA RXDn ASIC SGMII, SRIO, JESD204x or Custom Protocol FPGA Fabric Up to 150K Logic Elements IGLOO2 Programmable amplitude Receiver features Programmable termination Programmable linear equalization Built-in system debug features PRBS gen/chk Constant patterns Loopbacks IGLOO2 FPGA MathBlocks SUB IGLOO2 Register DOTP A[17:0] Register 36 + B[17:0] C[43:0] CARRYIN +/- Register Register ARSHFT17 Register CDSEL Register FDBKSEL Register Register 44 OVFL_CARRYOUT CDOUT[43:0] Register P[43:0] 44 >>17 OVFL_CARROUT_SEL 0 CDIN[43:0] IGLOO2 FPGA LEs A B C D CIN LUT_BYP EN SYNC_SR CLK RST 5 CO LO LUT4 D EN SL IGLOO2 RO Design Resources Libero SoC Design Software System designers can leverage the easy-to-use Libero® system-on-chip (SoC) software for designing IGLOO2 devices. Libero SoC integrates industry leading synthesis and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis, device debug and push button design flow. SmartDebug and Live Probe are new debug tools available in Libero SoC software that supports probe capabilities in the IGLOO2 architecture and also supports device debug features for memory. IGLOO2 devices have built in probe points that greatly enhance the ability to debug logic elements within the device. The enhanced debug features implemented into the IGLOO2 devices give access to any logic element and enable designers to check the state of inputs and outputs in real time, without any relayout of the design. Live Probe and Active Probe are only available on the SmartFusion2 and IGLOO2 family of products http://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads System-on-Chip IGLOO2 Evaluation Kit Microsemi’s IGLOO2 Evaluation Kit gives designers access to IGLOO2 FPGAs which offer leadership in I/O density, security, reliability and low power into mainstream applications. The IGLOO2 Evaluation Kit supports industry-standard interfaces including Gigabit Ethernet, USB 2.0 OTG, SPI, I2C and UART. The kit can be used with Microsemi’s Libero SoC v11.5 software, which includes a free Libero Gold license and comes preloaded with a demo. The kit can be powered through a 12V power supply or the PCIe connector and includes a FlashPro4 programmer. LEDs RJ45 USBOTG I2C FP4/IAR Header FR4 LPDDR GPIO Header IGLOO2 Tx/Rx/Clk SMA Pairs GbE PHY SPI Flash USBUART 12V from Wall Supply x1 PCIe http://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/igloo2/igloo2-evaluation-kit#overview Intellectual Property Microsemi enhances your design productivity by providing an extensive suite of proven and optimized IP Cores for use with Microsemi FPGAs. Our extensive suite of IP Cores covers all key markets and applications. Our Cores are organized as either Microsemi developed DirectCores or third party developed CompanionCores. Most DirectCores are available for free within our Libero tool suite and include common communications interfaces, peripherals and processing elements. http://www.microsemi.com/products/fpga-soc/design-resources/ip-cores Functionality DirectCore Examples Functionality CompanionCores Examples Connectivity UART,16550, 429, PCI, JESD204B Connectivity CAN, CANFD, PCIE, VME DSP CIC,FFT,FIR,CORDIC, RS DSP FFT, JPEG, RS, DVBMOD Memory Controller FIFO, DDR, QDR, SDR, MemCtrl, MMC Memory Controller SDRAMDDR, Flash, SD Processor 8051, 8051s, ARM7TDMI Processor 80188, 80186, LEON3, 6809 Ethernet MII, RGMII,GMII, SGMII Security Security DES, 3DES, AES, SHA MD5, ARC4, RNG, ZUC, AES, SHA, 802.1ae (MACSec) 6 IGLOO2 FPGA Product Family IGLOO2 Devices Features M2GL005 M2GL010 M2GL025 M2GL050 M2GL060 M2GL090 M2GL150 Maximum Logic Elements (4LUT + DFF) 6,060 12,084 27,696 56,340 56,520 86,184 146,124 Math Blocks (18x18) 11 22 34 72 72 84 240 PLLs and CCCs Logic/DSP 2 6 SPI/HPDMA/PDMA Fabric Interface Controllers (FICs) 1 Data Security 2 1 AES256, SHA256, RNG 2 AES256, SHA256, RNG, ECC, PUF eNVM (K Bytes) 128 LSRAM 18 K Blocks 10 21 31 69 109 236 uSRAM 1 K Blocks 11 21 34 72 112 240 2586 5000 Memory 256 512 eSRAM (K Bytes) 64 Total RAM (K bits) 703 912 DDR Controllers (count × width) High Speed 1104 1826 1×18 SERDES Lanes 0 2×36 1×18 2x36 8 4 16 4 PCIe End Points 0 MSIO (3.3V) 115 MSIOD (2.5V) 28 40 62 40 106 DDRIO (2.5V) 66 70 176 76 176 Total User I/Os 209 Commercial(C),Industrial(I),Military (M) C,I User I/O Grades 8 1 each 1 123 2 157 233 139 267 4 271 377 309 387 292 425 574 C,I,M Note: * Total logic may vary based on utilization of DSP and memories in your design. Please see the IGLOO2 Fabric UG for details. * Feature availablility is package dependent I/Os Per Package Package Options Package Type FCS(G)325 VF(G)256 FCS(G)536 Pitch (mm) 0.5 0.8 0.5 Length x Width (mm) 11x11 14x14 16x16 VF(G)400 FCV(G)484 TQ(G)144 0.5 1.0 1.0 1.0 1.0 19x19 20x20 23x23 27x27 31x31 35x35 0.8 17x17 FG(G)484 FG(G)676 FG(G)896 FC(G)1152 Device I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O Lanes I/O M2GL005 (S) — — 161 — — — 171 — — — 84 — 209 — — — — — — — M2GL010 (S/T/TS) — — 138 2 — — 195 4 — — 84 — 233 4 — — — — — — Lanes M2GL025 (T/TS) 180 2 138 2 — — 207 4 — — — — 267 4 — — — — — — M2GL050 (T/TS) 200 2 — — — — 207 4 — — — — 267 4 — — 377 8 — — M2GL060 (T/TS) 200 2 — — — — 207 4 — — — — 267 4 387 4 — — — — M2GL090 (T/TS) 180 4 — — — — — — — — — — 267 4 425 4 — — — — M2GL150 (T/TS) — — — — 293 4 — — 248 4 — — — — — — — — 574 16 Note: M2GL090 FCS325 is 11x13.5 pkg dim Highlighted devices can migrate vertically in the same package Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information.Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 email: [email protected] www.microsemi.com Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for communications, defense & security, aerospace and industrial markets. Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world’s standard for time; voice processing devices; RF solutions; discrete components; Enterprise Storage and Communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800 employees globally. Learn more at www.microsemi.com. ©2016 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Igloo2-02-16