® RT8910A 10-Channel High Voltage Level Shifter General Description Features The RT8910A provides a 10-Channel level shifter suitable for TFT-LCD row drivers. It level shifts a digital input signal to an output voltage nearly equal to its output supply voltages. The level shifter has 3 supplies : VGH1 and VGH2 are positive supplies and VGL is the negative supply. Fast rising/falling time and low propagation delay makes it suitable for driving TFT-LCD panel. RT8910A is available in a WQFN-28L 4x5 package. Marking Information 08= : Product Code 08=YM DNN YMDNN : Date Code 2.5V to 5V Input Logic Level Range −12V to 38V Output Voltage Range Propagation Delay 55ns 6-Channel (OUT1 to OUT6) Level Shifter with GPM Function for CLK 1-Channel Level Shifter for DISCHARGE 1-Channel (OUT7) Level Shifter for STV 2-Channel (OUT8, OUT9) Level Shifter for ODD and EVEN Separate VGH for DISCHARGE, OUT1 to OUT7 and OUT8, OUT9 Panel DISCHARGE Function Thin 28-Lead WQFN Package RoHS Compliant and Halogen Free Applications IPS TFT-LCD TV Panel Simplified Application Circuit RT8910A FLK1 FLK1 FLK2 FLK2 FLK3 FLK3 DISCHARGE OUT1 CLK1 DCINB OUT2 CLK2 CLK1 IN1 OUT3 CLK3 CLK2 IN2 OUT4 CLK4 CLK3 IN3 OUT5 CLK5 CLK4 IN4 CLK5 IN5 OUT6 CLK6 CLK6 IN6 OUT7 STV VST IN7 OUT8 ODD ODD IN8 OUT9 EVEN EVEN IN9 RE From Voltage Detector VGH1 VGH1 VGH2 VGH2 Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8910A-00 August 2014 DISCHARGE GND VGL VGL is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT8910A Pin Configurations Ordering Information (TOP VIEW) IN5 IN4 IN3 IN2 IN1 FLK3 RT8910A Package Type QW : WQFN-28L 4x5 (W-Type) 28 27 26 25 24 23 Lead Plating System G : Green (Halogen Free and Pb Free) IN6 IN8 IN7 IN9 GND OUT9 OUT8 OUT6 Note : Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. 22 2 21 3 20 4 19 GND 5 6 18 17 7 29 16 15 8 VGL FLK1 DCINB FLK2 DISCHARGE OUT7 OUT5 OUT1 9 10 11 12 13 14 Suitable for use in SnPb or Pb-free soldering processes. OUT4 OUT3 OUT2 RE VGH2 VGH1 1 WQFN-28L 4x5 Functional Pin Description Pin No. 1, 2, 3, 4, 24 to 28 Pin Name IN6, IN8, IN7, IN9, IN1 to IN5 5, GND 29 (Exposed Pad) Pin Function Level Shifter Inputs for Channels 1 to 9. Analog Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. OUT9, OUT8, OUT6, OUT4 to OUT2, OUT1, OUT5, OUT7 Level Shifter Outputs for Channels 9 to 1. 12 RE GPM Shaping Resistor Connection. 13 VGH2 Positive Supply Voltage for Level Shifter Channels 8 and 9. 14 VGH1 Positive Supply Voltage for Level Shifter Channels 1 to 7 and DISCHARGE. 18 DISCHARGE Level Shifter Output for Discharging. 19 FLK2 GPM Timing Clock Input 2. 20 DCINB Panel Discharge Voltage. Connect this pin to GND, if not used. 21 FLK1 GPM Timing Clock Input 1. 22 VGL Negative Supply Voltage for Level Shifter All Channels. 23 FLK3 GPM Timing Clock Input 3. 6, 7, 8, 9 to 11, 15, 16, 17 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS8910A-00 August 2014 RT8910A Function Block Diagram FLK1 FLK2 FLK3 VGH1 DISCHARGE DCINB IN1 OUT1 IN2 OUT2 OUT3 OUT4 OUT5 OUT6 RE IN3 GPM Control IN4 IN5 IN6 OUT7 IN7 GND VGH2 IN8 OUT8 IN9 OUT9 VGL Operation GPM Function OUT1 to OUT6 of the level shifter support GPM function. The GPM is controlled by the three FLK signals from timing controller to modulate the Gate-On voltage. The level shifter output can be modulated from VGH to the RE voltage on the falling edge of the FLK signal if and only if the level shifter input is high. Figure 1 shows the GPM function timing diagram. IN1 IN2 IN3 GPM Control Signal OUT1 OUT1 Starts falling when FLKx = Low and IN1 = IN2 = IN3 = High Figure 1. GPM Function Timing Diagram Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8910A-00 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT8910A Absolute Maximum Ratings (Note 1) VGL to GND -------------------------------------------------------------------------------------------------------- 0.3V to −30V FLKx, INx, DCINB to GND -------------------------------------------------------------------------------------- −0.3V to 6V VGHx to VGL ------------------------------------------------------------------------------------------------------ −0.3V to 45V RE to GND --------------------------------------------------------------------------------------------------------- −0.3V to (VGH1 + 0.3V) OUT1 to OUT7, DISCHARGE to VGL ----------------------------------------------------------------------- −0.3V to (VGH1 + 0.3V) OUT8, OUT9 to VGL --------------------------------------------------------------------------------------------- −0.3V to (VGH2 + 0.3V) Power Dissipation, PD @ TA = 25°C WQFN-28L 4x5 --------------------------------------------------------------------------------------------------- 3.57W Package Thermal Resistance (Note 2) WQFN-28L 4x5, θJA ---------------------------------------------------------------------------------------------- 28°C/W WQFN-28L 4x5, θJC --------------------------------------------------------------------------------------------- 7°C/W Lead Temperature (Soldering, 10 sec.) ---------------------------------------------------------------------- 260°C Junction Temperature -------------------------------------------------------------------------------------------- 150°C Storage Temperature Range ----------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Model) ------------------------------------------------------------------------------------- 2kV MM (Machine Model) -------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4) Junction Temperature Range ----------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ----------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VGHx = 30V, VGL = −6.2V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VGH1, VGH2 Operating Voltage Range 12 -- 38 V VGL Operating Voltage Range 12 -- 2 V -- -- 40 V High Voltage Level Shifter (VGH1, VGH2) VGL Input Voltage Logic-High VIH 1.7 -- -- Logic-Low VIL -- -- 0.4 Input Leakage Current Propagation Delay RE to OUT1 to OUT6 Switch On-Resistance IIL INx = FLKx = DCINB = 0V or 5.5V 1 -- 1 A tPLH OUTx Rising -- 50 -- ns tPHL OUTx Falling -- 50 -- ns -- 65 -- -- -- 100 kHz RDS(ON) Operation Frequency Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 V is a registered trademark of Richtek Technology Corporation. DS8910A-00 August 2014 RT8910A Parameter Symbol Test Conditions Min Typ Max Unit VGH1 Quiescent Current IVGH1 No Load -- 720 -- A VGH2 Quiescent Current IVGH2 No Load -- 120 -- A VGL Quiescent Current IVGL VIN = 0 or 6V, No Load -- 570 -- A -- -- 450 -- -- 120 -- -- 60 -- -- 30 -- -- 300 -- -- 60 -- -- 300 -- -- 150 CLK (OUT1 to OUT6) Channel VST (OUT7) Channel VDD E/O (OUT8, OUT9) Channel DISCHARGE Channel Rising Time tR Falling Time tF Rising Time tR Falling Time tF Rising Time tR Falling Time tF Rising Time tR Falling Time tF CLOAD = 4.7nF (Note5) CLOAD = 0.22nF CLOAD = 1nF CLOAD = 560pF (Note5) (Note5) (Note5) ns ns ns ns Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Level shifter CLOAD condition. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8910A-00 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT8910A Typical Application Circuit RT8910A FLK1 21 FLK2 19 FLK3 23 From Voltage Detector 20 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 VST ODD EVEN VGH1 VGH2 24 FLK1 DISCHARGE 18 FLK2 OUT1 15 CLK1 DCINB OUT2 11 CLK2 IN1 OUT3 10 CLK3 OUT4 9 CLK4 OUT5 16 CLK5 OUT6 8 CLK6 OUT7 17 7 OUT8 6 OUT9 RE 12 STV FLK3 25 IN2 26 IN3 27 IN4 28 IN5 1 IN6 3 IN7 2 IN8 4 IN9 14 13 VGH1 VGH2 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 GND DISCHARGE ODD EVEN 5, 29 (Exposed Pad) VGL 22 VGL is a registered trademark of Richtek Technology Corporation. DS8910A-00 August 2014 RT8910A Typical Operating Characteristics VGH2 Quiescent Current vs. VGH2 Voltage VGH1 Quiescent Current vs. VGH1 Voltage 140 VGH1 = VGH2 + 1V, VGL = −6.2V VGH2 Quiescent Current (μA) VGH1 Quiescent Current (μA) 740 730 720 710 700 690 680 132 124 116 108 100 12 700 VGL Quiescent Current (μA) VGH2 = VGH1 + 1V, VGL = −6.2V 16 20 24 28 32 36 40 12 16 20 24 28 32 36 40 VGH1 Voltage (V) VGH2 Voltage (V) VGL Quiescent Current vs. VGL Voltage Discharge Function when Power On VGH1 = VGH2 = 30V VGH1 = VGH2 = 30V, VGL = −6.2V 650 VGH1 (20V/Div) 600 550 VDCINB (5V/Div) 500 V DISCHARGE (20V/Div) 450 400 -12 -10 -8 -6 -4 Time (50ms/Div) -2 VGL Voltage (V) Level Shift Power On Discharge Function when Power Off VGH1 = VGH2 = 30V, VGL = −6.2V VGH1 = VGH2 = 30V, VGL = −6.2V VGH1 (20V/Div) VGH1 (20V/Div) VDCINB (2V/Div) VDCINB (5V/Div) VIN1 (10V/Div) VOUT1 (50V/Div) V DISCHARGE (20V/Div) Time (100ms/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8910A-00 August 2014 Time (25ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT8910A VGPM Function Level Shift Power Off VGH1 = VGH2 = 30V, VGL = −6.2V VGH1 = VGH2 = 30V, VGL = −6.2V VFLK1 (5V/Div) VGH1 (20V/Div) VDCINB (2V/Div) VOUT1 (50V/Div) VIN1 (10V/Div) VOUT1 (50V/Div) VOUT2 (50V/Div) VOUT3 (50V/Div) Time (50ms/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 Time (5μs/Div) is a registered trademark of Richtek Technology Corporation. DS8910A-00 August 2014 RT8910A The RT8910A is a ten-channel level shifter, which is designed for GIP panel. VGH1 and VGH2 are positive supplies and VGL is the negative supply. DISCHARGE and OUT1 to OUT7 channels are supplied from VGH1 and OUT8 to OUT9 channels are supplied from VGH2. VGH1 and VGH2 can be connected together. DISCHARGE is used for discharge function, OUT1 to 6 are used for clock (CLK1 to CLK6), OUT7 is used for start pulse (VST), and OUT 8 to OUT9 are used for EVEN/ODD function. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : Maximum Power Dissipation (W)1 Applications Information 4 Four-Layer PCB 3 2 1 0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 2. Derating Curve of Maximum Power Dissipation PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-28L 4x5 package, the thermal resistance, θJA, is 28°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : P D(MAX) = (125°C − 25°C) / (28°C/W) = 3.57W for WQFN-28L 4x5 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS8910A-00 August 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT8910A Layout Consideration For best performance of the RT8910A, some recommended layout guidelines are provided just as follows : For good regulation, place the power components as close as possible. IN5 IN4 IN3 IN2 IN1 FLK3 28 27 26 25 24 23 VGL IN6 1 22 VGL IN8 2 21 FLK1 IN7 3 20 DCINB IN9 4 19 FLK2 GND 5 18 DISCHARGE OUT9 6 17 OUT7 OUT8 7 16 OUT5 OUT6 8 15 OUT1 9 10 11 12 13 14 OUT4 OUT3 OUT2 RE VGH2 VGH1 GND For good regulation, place the power components as close as possible. GND GND VGH Figure 3. PCB Layout Guide Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS8910A-00 August 2014 RT8910A Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.900 4.100 0.154 0.161 D2 2.600 2.700 0.102 0.106 E 4.900 5.100 0.193 0.201 E2 3.600 3.700 0.142 0.146 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 28L QFN 4x5 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS8910A-00 August 2014 www.richtek.com 11