ISL97649AIRZ

S
DESIGN
W
E
N
R
DED FO
T PART
OMMEN REPLACEMEN
C
E
R
T
D
NO
MENDE 49AR5566
R E C OM
ISL976
DATASHEET
TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse
Modulator + RESET
ISL97649A
Features
The ISL97649A is an integrated power management IC (PMIC) for
TFT-LCDs used in notebooks, tablet PCs, and monitors. The device
integrates a boost converter for generating AVDD, an LDO for
VLOGIC. VON and VOFF are generated by a charge pump driven by
the switch node of the boost. The ISL97649A also includes a VON
slice circuit, reset function, and a high performance VCOM
amplifier with DCP (Digitally Controlled Potentiometer) that is
used as a VCOM calibrator.
• 2.5V to 5.5V input
• 1.5A, 0.18Ω integrated boost FET
• VON/VOFF supplies generated by charge pumps driven by the
boost switch node
• LDO for VLOGIC channel
• 600/1200kHz selectable switching frequency
• Integrated gate pulse modulator
The AVDD boost converter features a 1.5A/0.18boost FET with
600/1200kHz switching frequency.
• Reset signal generated by supply monitor
• Integrated VCOM amplifier
The logic LDO includes a 350mA FET for driving the low voltage
needed by external digital circuitry.
• DCP
- I2C serial interface, address: 0101000, MSB left
- Wiper position stored in 8-bit nonvolatile memory and
recalled on power-up
- Endurance, 1,000 data changes per bit
The gate pulse modulator can control the gate voltage up to 30V,
and both the rate and slew delay times are selectable.
The supply monitor generates a reset signal when the system is
powered down.
• UVLO, UVP, OVP, OCP, and OTP protection
It provides a programmable VCOM with I2C interface. One VCOM
amplifier is also integrated in the chip. The output of the VCOM is
powered up with the voltage at the last programmed 8-bit
EEPROM setting.
• Pb-free (RoHS compliant)
• 28 Ld 4x5 QFN
Applications
• LCD notebook, tablet, and monitor
Pin Configuration
EN
LX
VIN
FREQ
COMP
SS
ISL97649A
(28 LD 4x5 QFN)
TOP VIEW
28
27
26
25
24
23
FB
1
22
L_IN
PGND
2
21
CD2
CE
3
20
L_OUT
RE
4
19
RESET
VGH
5
18
ADJ
VGHM
6
17
VDIV
VFLK
7
16
NEG
VDPM
8
15 VOUT
June 27, 2013
FN7928.3
1
10
11
12
13
14
SCL
SDA
POS
RSET
GPM_LO
9
AVDD
GND
THERMAL
PAD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL97649A
Application Diagram
VIN
L1 10µH
C1, 2
20µF
LX
C32
0.1µF
AVDD BOOST
CONTROLLER
EN
SS
FREQ SEQUENCER
C25
1µF
VLOGIC
VLOGIC
C24
2.2µF
R18
3.92k
R2 8.06k
FB
COMP
R12 5.5k C20 15nF
D4
C11 C15
0.1µF 1µF
AVDD
C8
47nF
L_OUT
LDO
R17
8.25k
VFLK
ADJ
SCL
SDA
RSET
POS
R9
10k
R6 1k
VGH
GPM
DCP
CE
RE
VGHM
R7
83k
AVDD
VCOM
VOFF
Z1
C16
1µF
SW
C10
47nF
D2
C9
1µF
C17 1nF
C14 100pF
AVDD
OUT
NEG
VDIV
VCOM OP
VOLTAGE
DETECTOR
CD2
RESET
THERMAL PAD
C12
1µF
D3
C28
0.1µF
VGH GPM
R5 100k
R22 22k
GPM_LO
133k
R8
Q1
VON
VDPM
C19
0.47µF
SW
AVDD
PGND
L_IN
LDO VIN
C7
0.1µF
R1
73.2k
VIN
VIN
AVDD
C4, 5, 6
30µF
D1
C18
0.47µF
R14 85k
R26 100k
AVDD
VGH
VIN
OPEN
R15 115k
C26 1nF
RESET
R16
10k
VLOGIC
Submit Document Feedback
2
FN7928.3
June 27, 2013
ISL97649A
Pin Descriptions
PIN#
SYMBOL
DESCRIPTION
1
FB
2
PGND
3
CE
Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time.
4
RE
Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate.
5
VGH
6
VGHM
Gate Pulse Modulator Output for gate driver IC
7
VFLK
Gate Pulse Modulator Control input from TCON
8
VDPM
Gate Pulse Modulator Enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current
source charges the capacitor on VDPM.
9
GPM_LO
10
AVDD
11
SCL
I2C comparable clock input
12
SDA
I2C compatible serial bidirectional data line
13
POS
VCOM Amplifier Non-inverting input
14
RSET
DCP sink current adjustment pin; connect a resistor between this pin and GND to set the resolution of the DCP output voltage.
15
VOUT
VCOM Amplifier output
16
NEG
VCOM Amplifier inverting input
17
VDIV
Voltage detector threshold. Connect to the center of a resistive divider between VIN and GND.
18
ADJ
VLOGIC LDO feedback. Connect to the center of a resistive divider between L_OUT and GND to set VLogic voltage for TCON.
19
RESET
Voltage detector reset output
20
L_OUT
LDO output. Connect at least one 1µF capacitor to GND for stable operation.
21
CD2
Voltage detector rising edge delay. Connect a capacitor between this pin and GND to set the rising edge delay.
22
L_IN
LDO input. Connect a 1µF decoupling capacitor close to this pin.
23
SS
24
COMP
Boost converter compensation pin. Connect a series resistor and capacitor between this pin and GND to optimize transient
response and stability.
25
FREQ
Boost Converter frequency select; pull it to logic high to operate boost at 1.2MHz. Connect this pin to GND to operate boost at
600kHz.
26
VIN
IC input supply. Connect a 0.1µF decoupling capacitor close to this pin.
27
LX
AVDD boost converter switching node
28
EN
AVDD enable pin
AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage.
Power ground
Gate Pulse Modulator High Voltage Input. Place a 0.1µF decoupling capacitor close to the VGH pin.
Gate Pulse Modulator Low Voltage Input; place a 0.47µF decoupling capacitor close to the GPM_LO pin.
DCP and VCOM amplifier high voltage analog supply; place a 0.47µF decoupling capacitor close to the AVDD pin.
Boost Converter Soft-Start. Connect a capacitor between this pin and GND to set the soft-start time.
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL97649AIRZ (Note 1)
PART
MARKING
VIN RANGE
(V)
TEMP RANGE
(°C)
97649 AIRZ
2.5 to 5.5
-40 to +85
PACKAGE
(Pb-free)
28 Ld 4x5 QFN
PKG.
DWG. #
L28.4x5A
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97649A For more information on MSL please see techbrief TB363.
Submit Document Feedback
3
FN7928.3
June 27, 2013
ISL97649A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rectifier Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Linear Regulator (LDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate Pulse Modulator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VGH/VGL Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCOM Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCP Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Communication with ISL97649A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description: Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description: IVP and WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initial VCOM Setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11
11
11
11
11
11
11
12
12
12
12
13
13
14
14
14
14
15
15
17
17
17
17
18
18
18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Submit Document Feedback
4
FN7928.3
June 27, 2013
ISL97649A
Absolute Maximum Ratings
Thermal Information
RE, VGHM, GPM_LO and VGH to GND . . . . . . . . . . . . . . . . . . . . -0.3 to +36V
LX, AVDD, POS, NEG, VOUT to GND. . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V
Voltage Between GND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5V
All Other Pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 1kV
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
28 Ld 4x5 QFN Package (Notes 4, 5). . . . .
38
4.5
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Functional Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Lead Temperature During Soldering . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the
operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
GENERAL
VIN
3.3
5.5
V
VIN Supply Currents when Disabled
VIN < UVLO
390
500
µA
IS
VIN Supply Currents
ENABLE = 3.3V, overdrive AVDD and VGH
0.7
1.0
mA
IEBABLE
ENABLE Pin Current
ENABLE = 0V
IS_DIS
VIN Supply Voltage Range
2.5
0
µA
LOGIC INPUT CHARACTERISTICS - ENABLE, FLK, SCL, SDA, FREQ
VIL
Low Voltage Threshold
VIH
High Voltage Threshold
RIL
Pull-Down Resistor
0.65
1.75
Enable, FLK, FREQ
0.85
V
V
1.25
1.65
M
INTERNAL OSCILLATOR
FOSC
Switching Frequencies
FREQ = low, TA = +25°C
550
600
650
kHz
FREQ = high, TA = +25°C
1100
1200
1300
kHz
AVDD BOOST REGULATOR
DAVDD/
DIOUT
AVDD Load Regulation
50mA < ILOAD < 250mA
0.2
%
DAVDD/
DVIN
AVDD Line Regulation
ILOAD = 150mA, 2.5V < VIN < 5.5V
0.15
%
VFB
Feedback Voltage (VFB)
ILOAD = 100mA, TA = +25°C
IFB
FB Input Bias Current
rDS(ON)
Switch ON-resistance
ILIM
Switch Current Limit
DMAX
Max Duty Cycle
Submit Document Feedback
Freq = 1.2MHz, IAVDD = 100mA
5
0.808
V
100
nA
180
230
m
1.125
1.5
1.875
80
90
%
91
%
TA = +25°C
Freq = 1.2MHz
EFF
0.792
0.8
A
FN7928.3
June 27, 2013
ISL97649A
Electrical Specifications
VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
LDO REGULATOR
DVLDO/
DVIN
Line Regulation
ILDO = 1mA, 3.0V < VIN1 < 5.5V
DVLDO/
DIOUT
Load Regulation
1mA < ILDO < 350mA
VDO
Dropout Voltage
Output drops by 2%, ILDO = 350mA
ILIML
Current Limit
Output drops by 5%
VADJ
ADJ Reference Voltage
ILOAD = 50mA, TA = +25°C
IADJ
ADJ Input Bias Current
1
mV/V
0.2
%
225
330
425
0.792
0.8
300
mV
mA
0.808
V
0.1
µA
33
V
1.30
V
GATE PULSE MODULATOR
VGH
VIH_VDPM
VGH Voltage
7
VDPM Enable Threshold
1.13
IVGH
VGH Input Current
VFLK = 0
VGPM_LO
GPM_LO Voltage
2
IGPM_LO
VGPM_LO Input Current
-2
VCEth1
VCEth2
1.215
125
RE = 100kΩ, VFLK = VIN
µA
27.5
µA
VGH-2
V
0.1
2
µA
CE Threshold Voltage 1
0.6xVIN
0.8xVIN
V
CE Threshold Voltage 2
1.215
V
CE Current
100
µA
RVGHM_PD
VGHM Pull-down Resistance
1.1
k
RONVGH
VGH to VGHM On Resistance
23

VDPM Charge Current
10
µA
ICE
IDPM
SUPPLY MONITOR
VIH_VDIV
VDIV High Threshold
VDIV rising
1.265
1.280
1.295
V
VIL_VDIV
VDIV Low Threshold
VDIV falling
1.21
1.222
1.234
V
VthCD2
CD2 Threshold voltage
1.200
1.217
1.234
ICD2
RIL_RESET
CD2 Charge Current
RESET Pull-Down Resistance
tDELAY_RESET RESET Delay on the Rising Edge
V
10
µA
650

121.7k*
CD
s
VCOM AMPLIFIER RLOAD = 10k, CLOAD = 10pF, Unless Otherwise Stated
IS_com
VOS
IB
VCOM Amplifier Supply Current
0.7
1.08
mA
Offset Voltage
2.5
15
mV
Non-inverting Input Bias Current
0
nA
CMIR
Common Mode Input Voltage Range
0
CMRR
Common-Mode Rejection Ratio
60
75
dB
PSRR
Power Supply Rejection Ratio
70
85
dB
IOUT(source) = 0.1mA
AVDD - 1.39
mV
IOUT(source) = 75mA
AVDD - 1.27
V
IOUT(sink) = 0.1mA
1.2
mV
IOUT(sink) = 75mA
1
V
VOH
VOL
Output Voltage Swing High
Output Voltage Swing Low
Submit Document Feedback
6
AVDD
V
FN7928.3
June 27, 2013
ISL97649A
Electrical Specifications
VIN = ENABLE = 3.3V, AVDD = 8V, VLDO = 2.5V, VON = 24V, VOFF = - 6V. Boldface limits apply over the
operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
ISC
MIN
(Note 6)
TYP
(Note 7)
Pull-up
150
225
mA
Pull-down
150
200
mA
25
V/µs
20
MHz
8
Bits
PARAMETER
Output Short Circuit Current
SR
Slew Rate
BW
Gain Bandwidth
TEST CONDITIONS
-3dB gain point
MAX
(Note 6)
UNITS
DIGITAL CONTROLLED POTENTIOMETER
SETVR
(Note 12)
SET Voltage Resolution
SETDNL
(Note 8, 9,
14)
SET Differential Nonlinearity
TA = +25°C
±1
LSB
SET Zero-Scale Error
SETZSE
(Note 10, 14)
TA = +25°C
±2
LSB
SETFSE
SET Full-Scale Error
(Note 11,14)
TA = +25°C
±8
LSB
IRSET
RSET Current
100
AVDD to SET AVDD to SET Voltage Attenuation
1:20
µA
V/V
FAULT DETECTION THRESHOLD
VUVLO
Undervoltage Lock out Threshold
OVPAVDD
(Note 13)
Boost Overvoltage Protection Off
Threshold to Shutdown IC
TOFF
Thermal Shut-Down all Channels
PVIN rising
2.25
2.33
PVIN falling
2.125
15.0
Temperature rising
2.41
V
2.20
2.27
V
15.5
16.0
V
153
°C
0.45
ms
POWER SEQUENCE TIMING
tssVLOGIC
VLOGIC Soft-start Time
Iss
Boost Soft-start Current
Serial Interface Specifications
SYMBOL
PARAMETER
3
5.5
8
µA
For SCL and SDA Unless Otherwise Noted.
TEST CONDITIONS
MIN
(Note 14)
TYP
(Note 7)
MAX
(Note 14)
UNITS
400
kHz
fSCL
(Note 6)
SCL Frequency
tiN
(Note 6)
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VIN, until
SDA exits the 30% to 70% of VIN window
480
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VIN during
the following START condition
480
ns
tLOW
Clock LOW Time
Measured at the 30% of VIN crossing
480
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VIN crossing
400
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
crossing 70% of VIN
480
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VIN to
SCL falling edge crossing 70% of VIN
400
ns
Submit Document Feedback
7
FN7928.3
June 27, 2013
ISL97649A
Serial Interface Specifications
SYMBOL
For SCL and SDA Unless Otherwise Noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 14)
TYP
(Note 7)
MAX
(Note 14)
UNITS
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70% of VIN
window, to SCL rising edge crossing 30% of
VIN
40
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VIN to
SDA entering the 30% to 70% of VIN window
0
ns
tSU:STO
STOP Condition Set-up Time
From SCL rising edge crossing 70% of VIN, to
SDA rising edge crossing 30% of VIN
400
ns
tHD:STO
STOP Condition Hold Time for Read, or
Volatile Only Write
From SDA rising edge to SCL falling edge;
both crossing 70% of VIN
400
ns
CSCL
Capacitive on SCL
5
pF
CSDA
Capacitive on SDA
5
pF
Non-Volatile Write Cycle Time
25
ms
tWp
EEPROM Endurance
TA= +25°C
1
kCyc
EEPROM Retention
TA = +25°C
88
kHrs
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Typical values are for TA = +25°C and VIN = 3.3V.
8. LSB = I V255 - V1I / 254. V255 and V1 are the measured voltages for the DCP register set to FF hex and 01 hex respectively.
9. DNL = I Vi+1 - Vi I / LSB-1, i   1 255 
10. ZS error = (V1 -VMIN) / LSB. VMIN = (VAVDD*R2) * [1-254*R1/(255*20*RSET)]/ (R1+R2).
11. FS error = (V255 - VMAX) / LSB. VMAX= (VAVDD*R2) * [1-0*R1/(255*20*RSET)]/ (R1+R2).
12. Established by design. Not a parametric spec.
13. Boost will stop switching as soon as boost output reaches OVP threshold.
14. Compliance to limits is assured by characterization and design.
Submit Document Feedback
8
FN7928.3
June 27, 2013
ISL97649A
Typical Performance Curves
92
0.00
88
fOSC = 600kHz
86
LOAD REGULATION (%)
EFFICIENCY (%)
90
fOSC = 1.2MHz
84
82
80
78
76
fOSC = 600kHz
-0.01
-0.02
fOSC = 1.2MHz
-0.03
VIN = 3.3V, VOUT = 8.06V
0.0
50
100
150
200
250
300
VIN = 3.3V, VOUT = 8.06V
350
-0.04
50
100
IAVDD (mA)
150
200
250
IAVDD (mA)
FIGURE 1. AVDD EFFICIENCY vs IAVDD
FIGURE 2. AVDD LOAD REGULATION vs IAVDD
L = 10µH, COUT = 40µF, CCOMP = 15nF, RCOMP = 5.5k
0.14
0.12
AVDD (V)
0.10
0.08
0.06
IAVDD = 150mA
0.04
0.02
0.00
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
FIGURE 3. AVDD LINE REGULATION vs VIN
CE = 1pF, RE = 100k
VGHM
FIGURE 5. GPM CIRCUIT WAVEFORM
Submit Document Feedback
9
5.5
FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE
VGHM
CE = 100pF, RE = 100k
FIGURE 6. GPM CIRCUIT WAVEFORM
FN7928.3
June 27, 2013
ISL97649A
Typical Performance Curves (Continued)
CE = 10pF, RE = 50k
CE = 10pF, RE = 150k
VGHM
VGHM
FIGURE 7. GPM CIRCUIT WAVEFORM
FIGURE 8. GPM CIRCUIT WAVEFORM
VGHM
FIGURE 9. VGHM FOLLOWS VGH WHEN THE SYSTEM POWERS OFF
FIGURE 10. VCOM RISING SLEW RATE
2.4854
0.000
LOAD REGULATION (%)
2.4852
2.4850
VLDO (V)
2.4848
2.4846
2.4844
ILDO = 1mA
2.4842
2.4840
2.4838
2.4836
3.0
3.5
4.0
4.5
VLDO_IN (V)
FIGURE 11. LDO LINE REGULATION vs VIN
Submit Document Feedback
10
5.0
5.5
-0.005
-0.010
-0.015
VLDO = 2.5V
-0.020
-0.025
-0.030
0
50
100
150
200
250
300
350
ILDO (mA)
FIGURE 12. LDO LOAD REGULATION vs ILDO
FN7928.3
June 27, 2013
ISL97649A
Applications Information
This restricts the maximum output current (average) based on
Equation 3:
Enable Control
With VIN > UVLO, only the Logic output channel is activated. All
other functions in ISL97649A are shut down when the enable pin
is pulled down. When the voltage at the enable pin reaches H
threshold, the whole chip turns on.
Frequency Selection
The ISL97649A switching frequency can be user selected to
operate at either constant 600kHz or 1.2MHz. Lower switching
frequency can save power dissipation at very light load
conditions. Also, low switching frequency more easily leads to
discontinuous conduction mode, while higher switching
frequency allows for smaller external components, such as
inductor and output capacitors, etc. Higher switching frequency
will get higher efficiency within some loading range depending
on VIN, VOUT, and external components, as shown in Figure 1.
Connecting the FREQ pin to GND sets the PWM switching
frequency to 600kHz, or connecting FREQ pin to VIN for 1.2MHz.
Soft-Start
The soft-start is provided by an internal current source to charge
the external soft-start capacitor. The ISL97649A ramps up the
current limit from 0A up to the full value, as the voltage at the SS
pin ramps from 0V to 0.8V. Hence, the soft-start time is 3.2ms
when the soft-start capacitor is 22nF, 6.8ms for 47nF and
14.5ms for 100nF.
Operation
The boost converter is a current mode PWM converter operating
at either 600kHz or 1.2MHz. It can operate in both discontinuous
conduction mode (DCM) at light load and continuous conduction
mode (CCM). In continuous conduction mode, current flows
continuously in the inductor during the entire switching cycle in
steady state operation. The voltage conversion ratio in
continuous current mode is given by Equation 1:
V Boost
1
------------------- = ------------V IN
1–D
(EQ. 3)
where IL is the peak-to-peak inductor ripple current, and is set
by Equation 4:
V IN D
I L = ---------  ---L
fs
(EQ. 4)
where fS is the switching frequency (600kHz or 1.2MHz).
Capacitor
An input capacitor is used to suppress the voltage ripple injected
into the boost converter. The ceramic capacitor with a
capacitance larger than 10µF is recommended. The voltage
rating of the input capacitor should be larger than the maximum
input voltage. Some input capacitors are recommended in
Table 1.
TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
MFG
PART NUMBER
10µF/6.3V
0603
TDK
C1608X5R0J106M
10µF/16V
1206
TDK
C3216X7R1C106M
10µF/10V
0805
Murata
GRM21BR61A106K
22µF/10V
1210
Murata
GRB32ER61A226K
Inductor
The boost inductor is a critical part that influences the output
voltage ripple, transient response, and efficiency. Values of
3.3µH to 10µH are used to match the internal slope
compensation. The inductor must be able to handle the following
average and peak currents shown in Equation 5:
IO
I LAVG = ------------1–D
(EQ. 5)
I L
I LPK = I LAVG + -------2
(EQ. 1)
Some inductors are recommended in Table 2 for different design
considerations.
where D is the duty cycle of the switching MOSFET.
The boost regulator uses a summing amplifier architecture
consisting of gm stages for voltage feedback, current feedback
and slope compensation. A comparator looks at the peak
inductor current cycle-by-cycle and terminates the PWM cycle if
the current limit is reached.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current drawn by
the resistor network should be limited to maintain the overall
converter efficiency. The maximum value of the resistor network
is limited by the feedback input bias current and the potential for
noise being coupled into the feedback pin. A resistor network in
the order of 60kΩ is recommended. The boost converter output
voltage is determined by Equation 2:
R1 + R2
V Boost = ---------------------  V FB
R2
(EQ. 2)
The current through the MOSFET is limited to 1.5APEAK.
Submit Document Feedback
I L
V IN
I OMAX =  I LMT – --------  --------
2  VO
11
Rectifier Diode
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of their
fast recovery time and low forward voltage. The reverse voltage
rating of this diode should be higher than the maximum output
voltage. The rectifier diode must meet the output current and
peak inductor current requirements. Table 3 shows some
recommendations for boost converter diode.
TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION
INDUCTOR
10µH/
4Apeak
DIMENSIONS
(mm)
MFG
PART
NUMBER
8.3x8.3x4.5 Sumida CDR8D43-100NC
6.8µH/
5.0x5.0x2.0
1.8Apeak
TDK
NOTE
Efficiency
Optimization
PLF5020T-6R8M1R8
FN7928.3
June 27, 2013
ISL97649A
TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION
INDUCTOR
10µH/
2.2Apeak
DIMENSIONS
(mm)
6.6x7.3x1.2
PART
NUMBER
MFG
Cyntec PCME061B-100MS
NOTE
PCB
space/profile
optimization
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION
DIODE
VR/IAVG RATING
PMEG2010ER
20V/1A
SOD123W NXP
MSS1P2U
20V/1A
MicroSMP VISHAY
PACKAGE
MFG
Output Capacitor
The output capacitor supplies the load directly and reduces the
ripple voltage at the output. Output ripple voltage consists of two
components:
1. The voltage drop due to the inductor ripple current flowing
through the ESR of the output capacitor.
2. Charging and discharging of the output capacitor.
IO
V O – V IN
1
V RIPPLE = I LPK  ESR + ------------------------  ----------------  ---f
V
C
O
OUT
The efficiency of the LDO depends on the difference between
input voltage and output voltage (Equation 7) by assuming LDO
quiescent current is much lower than LDO output current:
 V LDO_IN 
  %  =  ------------------------------  100%
 V LDO_OUT
(EQ. 7)
The less difference between input and output voltage, the higher
efficiency it is.
Ceramic capacitors are recommended for the LDO input and
output capacitors. Intersil recommends an output capacitor
within the 1µF to 4.7µF range and a maximum feedback resistor
impedance of 20kΩ. Larger capacitors help to reduce noise and
deviation during transient load change. Some capacitors are
recommended in Table 5.
TABLE 5. LDO OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
MFG
PART NUMBER
1µF/10V
0603
TDK
C1608X7R1A105K
1µF/6.3V
0603
MURATA
GRM188R70J105K
2.2µF/6.3V
0603
TDK
C1608X7R0J225K
(EQ. 6)
s
For low ESR ceramic capacitors, the output ripple is dominated
by the charging and discharging of the output capacitor. The
voltage rating of the output capacitor should be greater than the
maximum output voltage.
Supply Monitor Circuit
The Supply Monitor circuit monitors the voltage on VDIV, and sets
open-drain output RESET low when VDIV is below 1.28V (rising)
or 1.22V (falling).
Note: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
COUT in Equation 6 assumes the effective value of the capacitor
at a particular voltage and not the manufacturer’s stated value,
measured at 0V.
There is a delay on the rising edge, controlled by a capacitor on
CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from
0V to 1.217V by a 10µA current source. Once CD2 exceeds
1.217V, RESET will go tri-state. When VDIV falls below 1.22V,
RESET will become low with a 650Ω pull-down resistance. The
delay time is controlled by Equation 8:
Table 4 shows some selections of output capacitors.
t delay = 121.7k  CD2
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
SIZE
MFG
PART NUMBER
10µF/25V
1210
TDK
C3225X7R1E106M
10µF/25V
1210
Murata
GRM32DR61E106K
(EQ. 8)
For example, the delay time is 12.17ms if the CD2 = 100nF.
Figure 13 shows the Supply Monitor Circuit timing diagram.
Compensation
The boost converter of ISL97649A can be compensated by an RC
network connected from the COMP pin to ground. 15nF and 5.5k
RC network is used in the demo board. The larger value resistor
and lower value capacitor can lower the transient overshoot,
however, at the expense of the stability of the loop.
1.28V
VDIV
1.22V
1.217V
CD2
Linear Regulator (LDO)
The ISL97649A includes an LDO with adjustable output. It can
supply current up to 350mA. The output voltage is adjusted by
connection of the ADJ pin.
RESET
RESET DELAY TIME IS
CONTROLLED BY CD2
CAPACITOR
FIGURE 13. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM
Submit Document Feedback
12
FN7928.3
June 27, 2013
ISL97649A
VIN
UVLO
THRESHOLD
0
VGH
RESET
VDPM
1.215V
VFLK
VGH
VGHM IS FORCED
VGH_M is forced to
TO VGH WHEN VIN
VGH
FALLS
TOwhen
UVLORESET
AND
Slope
goes to low AND
SLOPEisIScontrolled
VGH>3V
CONTROLLED
BY
RE
VGH>3V
by RE
Power on DELAY
delay time
Delay
POWER-ON
TIME
DELAYtime
TIMEisIScontrolled
is
controlled
by
CONTROLLED BY CDPM
by
CE
CONTROLLED
BY CE
CDPM
VGHM
GPM_LO
FIGURE 14. GATE PULSE MODULATOR TIMING DIAGRAM
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, GPM_LO and VGH.
Voltage selection is provided by digital inputs VDPM (enable) and
VFLK (control). High to low delay and slew control is provided by
external components on pins CE and RE, respectively.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When the input voltage exceeds UVLO threshold,
VDPM starts to drive an external capacitor. Once VDPM exceeds
1.215V, the GPM circuit is enabled, and the output VGHM is
determined by VFLK, RESET signal and VGH voltage. If RESET
signal is high and VFLK is high, VGHM is pulled to VGH. When
VFLK goes low, there is a delay controlled by capacitor CE,
following which, VGHM is driven to GPM_LO, with a slew rate
controlled by resistor RE. Note that GPM_LO is used only as a
reference voltage for an amplifier, and thus does not have to
source or sink a significant DC current.
Low to high transition is determined primarily by the switch
resistance and the external capacitive load. High to low transition
is more complex. Take the case where the block is already
enabled (VDPM is H). When VFLK is H, if CE is not externally
pulled above threshold voltage 1, pin CE is pulled low. On the
falling edge of VFLK, a current is passed into pin CE to charge the
external capacitor up to threshold voltage 2, providing a delay
which is adjustable by varying the capacitor on CE. Once this
threshold is reached, the output starts to be pulled down from
VGH to GPM_LO. The maximum slew current is equal to 500/(RE
+ 40k), and the dv/dt slew rate is Isl/CLOAD, where CLOAD is the
load capacitance applied to VGHM. The slew rate reduces as
VGHM approaches GPM_LO.
If CE is always pulled up to a voltage above threshold 1, zero
delay mode is selected; thus, there will be no delay from FLK
falling to the point where VGHM starts to fall. Slew down currents
will be identical to the previous case.
3V, VGHM will not be actively driven until VIN is driven. Figure 14
shows the VGHM voltage based on VIN, VGH and RESET.
VGH/VGL Charge Pump
To provide VGH and VGL rails for the application, two external
charge pumps driven by AVDD and the boost switching node can
be used to generate the desired VGH and VGL, as shown in the
“Application Diagram” on page 2.
The number of charge pump stages can be calculated using
Equations 9 and 10.
VGL_headroom = N AVDD – 2 N Vd – VGL  0
VGH_headroom =  N + 1  AVDD – 2 N Vd – VGH  0
(EQ. 9)
(EQ. 10)
Where N is the number of charge pump stages and Vd is the
forward voltage drop of one Schottky diode used in the charge
pump. Vd varies with forward current and ambient temperature,
so it should be the maximum value in the diode datasheet
according to max forward current and lowest temperature in the
application condition.
Once the number of the charge pump stages is determined, the
maximum current that the charge pump can deliver can be
calculated using Equations 11 and 12:
VGL = N  – AVDD + 2 Vd + I VGL   Freq C_fly  
(EQ. 11)
VGH = AVDD + N  AVDD – 2 Vd – I VGH   Freq C_fly   (EQ. 12)
Where Freq is the switching frequency of the AVDD boost, C_fly is
the flying capacitance (C8, C10, C11 in the application diagram).
IVGL and IVGH are the loadings of VGL and VGH. The relationships
between minimum flying capacitance and VGL and VGH loadings
are shown in Figures 15 and 16. The flying capacitance must be
higher than the minimum value shown in Figures 15 and 16 for a
certain loading on VGL and VGH.
At power-down, when VIN falls to UVLO, VGHM will be tied to VGH
until the VGH voltage falls to 3V. Once the VGH voltage falls below
Submit Document Feedback
13
FN7928.3
June 27, 2013
ISL97649A
140
DCP Memory Description
VGL = -6V, SINGLE STAGE CHARGE PUMP
The ISL97649A contains one non-volatile byte known as the
Initial Value Register (IVR). It is accessed by the I2C interface
operations with Address 00h. The IVR contains the value that is
loaded into the Volatile Wiper Register (WR) at power-up.
120
C_FLY (nF)
100
The volatile WR and the non-volatile IVR of a DCP are accessed
with the same address.
FREQ = 600kHz
80
FREQ = 1.2MHz
40
The Access Control Register (ACR) determines which word at
address 00h is accessed (IVR or WR). The volatile ACR must be
set as follows:
20
When the ACR is all zeroes, which is the default at power-up:
60
0
0
20
40
60
80
100
• A read operation to address 0 outputs the value of the
non-volatile IVR.
• A write operation to address 0 writes the identical values to the
WR and IVR of the DCP.
IVGL (mA)
FIGURE 15. FLYING CAPACITANCE vs VGL LOADING
• When the ACR is 80h:
- A read operation to address 0 outputs the value of the
volatile WR.
- A write operation to address 0 only writes to the
volatile WR.
It is not possible to write to an IVR without writing the same value
to its WR.
700
VGH = 22V, TWO-STAGE CHARGEPUMP
600
C_FLY (nF)
500
400
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be written
to address 2.
FREQ = 600kHz
FREQ = 1.2MHz
300
TABLE 6. MEMORY MAP
200
100
0
0
20
40
60
80
100
IVGH (mA)
FIGURE 16. FLYING CAPACITANCE vs VGH LOADING
VCOM Amplifier
The VCOM amplifier is designed to control the voltage on the back
plane of an LCD display. This plane is capacitively coupled to the
pixel drive voltage, which alternately cycles positive and negative at
the line rate for the display. Thus, the amplifier must be capable of
sourcing and sinking pulses of current, which can occasionally be
quite large (in the range of 100mA for typical applications).
The ISL97649A VCOM amplifier's output current is limited to
225mA typical. This limit level, which is roughly the same for
sourcing and sinking, is included to maintain reliable operation
of the part. It does not necessarily prevent a large temperature
rise if the current is maintained. (In this case, the whole chip may
be shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than this
limit, the reservoir capacitor will provide the excess and the
amplifier will top the reservoir capacitor back up once the pulse
has stopped. This will happen in the µs time scale in practical
systems and for pulses 2 or 3 times the current limit; the VCOM
voltage will have settled again before the next line is processed.
Submit Document Feedback
14
ADDRESS
NON-VOLATILE
VOLATILE
2
-
ACR
1
0
Reserved
IVR
WR
WR: Wiper Register, IVR: Initial value Register.
I2C Serial Interface
The ISL97649A supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data on to the bus as
a transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the DCP of the ISL97649A operates as a slave device
in all applications. The fall and rise time of SDA and SCL signal
should be in the range listed in Table 8. Capacitive load on I2C
bus is also specified in Table 8.
All communication over the I2C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 17). On
power-up of the ISL97649A, the SDA pin is in the input mode.
FN7928.3
June 27, 2013
ISL97649A
All I2C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
DCP continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition is met (see Figure 17). A START condition is ignored
during the power-up sequence and during internal non-volatile
write cycles.
All I2C interface must be terminated by a STOP condition, which
is a LOW to HIGH transition of SDA while SCL is high (see
Figure 17). A STOP condition at the end of a read operation, or at
the end of a write operation to volatile bytes only places the
device in its standby mode. A STOP condition during a write
operation to a non-volatile write byte, initiates an internal
non-volatile write cycle. The device enters its standby state when
the internal non-volatile write cycle is completed.
Register (WR) or to the Access Control Register respectively, at
the falling edge of the SCL pulse that loads the last bit (LSB) of
the Data Byte. If the Address Byte is 0, and the Access Control
Register is all zeros (default), then the STOP condition initiates
the internal write cycle to non-volatile memory.
TABLE 8. I2C INTERFACE SPECIFICATION
PARAMETER
MIN
TYP
MAX
UNITS
SDA and SCL Rise Time
1000
ns
SDA and SCL Fall Time
300
ns
I2C Bus Capacitive Load
400
pF
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (see
Figure 18).
The ISL97649A DCP responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and once
again after successful receipt of an Address Byte. The ISL97649A
also respond with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven MSBs.
The LSB is in the Read/Write bit. Its value is "1" for a Read
operation, and "0" for a Write operation (see Table 7).
TABLE 7. IDENTIFICATION BYTE FORMAT
0
1
0
1
(MSB)
0
0
0
R/W
(LSB)
Write Operation
A write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition (see Figure 19). After each of the three bytes, the
ISL97649A responds with an ACK. At this time, if the Data Byte is
to be written only to volatile registers, the device enters its
standby state. If the Data Byte is to be written also to non-volatile
memory, the ISL97649A begins its internal write cycle to
non-volatile memory. During the internal non-volatile write cycle,
the device ignores transitions at the SDA and SCL pins and the
SDA output is at high impedance state. When the internal
non-volatile write cycle is completed, the ISL97649A enters its
standby state. The byte at address 02h determines if the Data
Byte is to be written to volatile and/or non-volatile memory.
Data Protection
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile and
non-volatile registers. During a Write sequence, the Data Byte is
loaded into an internal shift register as it is received. If the
Address Byte is 0 or 2, the Data Byte is transferred to the Wiper
Submit Document Feedback
15
FN7928.3
June 27, 2013
ISL97649A
SCL
SDA
START
DATA
STABLE
DATA
CHANGE
DATA
STABLE
STOP
FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
SIGNALS FROM
THE MASTER
SIGNAL AT SDA
S
T
A
R
T
WRITE
IDENTIFICATION
BYTE
0 1 0 1 0 0 0
SIGNALS FROM
THE ISL97649A
ADDRESS
BYTE
S
T
O
P
DATA
BYTE
0 0 0 0 0 0 X 0
0
A
C
K
A
C
K
A
C
K
FIGURE 19. BYTE WRITE SEQUENCE
SIGNALS
FROM THE
MASTER
S
T
A
R
T
SIGNAL AT SDA
IDENTIFICATION
BYTE WITH
R/W = 0
0 1 0 1 0 0 0 0
A
C
K
SIGNALS FROM
THE SLAVE
ADDRESS
BYTE
S
T
A IDENTIFICATION
R
BYTE WITH
T
R/W = 1
0 0 0 0 0 0 X 0
0 1 0 1 0 0 0
A
C
K
S
T
O
P
A
C
K
1
A
C
K
A
C
K
FIRST READ
DATA BYTE
LAST READ
DATA BYTE
FIGURE 20. READ SEQUENCE
Submit Document Feedback
16
FN7928.3
June 27, 2013
ISL97649A
Read Operation
Register Description: Access Control
A read operation consists of a three-byte instruction followed by
one or more Data Bytes (see Figure 20). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to "0", an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to "1". After each of the three bytes, the ISL97649A responds
with an ACK; then the ISL97649A transmits the Data Byte. The
master then terminates the read operation (issuing a STOP
condition) following the last bit of the Data Byte (see Figure 18).
The Access Control Register (ACR) is volatile and is at address
02h. It is 8 bits, and only the MSB is significant; all other bits
should be zero (0). The ACR controls which word is accessed at
register 00h as follows:
• 00h = Nonvolatile IVR
• 80h = Volatile WR
All other bits of the ACR should be written 0 or 1. Power-up
default for this address is 00h.
The byte at address 02h determines if the Data Bytes being read
are from volatile or non-volatile memory.
Register Description: IVP and WR
The output of the DCP is controlled directly by the WR. Writes and
reads can be made directly to this register to control and monitor
without any non-volatile memory changes. This is done by setting
address 02h to data 80h, then writing the data.
Communication with ISL97649A
There are three register addresses in the ISL97649A, of which
two can be used. Address 00h and address 02h are used to
control the device. Address 01h is reserved and should not be
used. Address 00h contains the non-volatile Initial Value Register
(IVR), and the volatile Wiper Register (WR). Address 02h contains
only a volatile word and is used as a pointer to either the IVR or
WR.
The non-volatile IVR stores the power-up value of the DCP output.
On power -up, the contents of the IVR are transferred to the WR.
To write to the IVR, first address 02h is set to data 00h and then
the data is written. Writing a new value to the IVR register will set
Writing a new value to the IVR
Write to ACR first
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
D0
D7
D6
D5
D4
D3
D2
D1
A
Then, write to IVR
0
1
0
Note that the WR will also reflect this new value since both registers get writen at the same time
D0:LSB, D7:MSB
Writing a new value to WR only
Write to ACR first
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
D0
D7
D6
D5
D4
D3
D2
D1
A
0
0
0
0
0
0
0
0
A
1
0
0
0
0
0
0
0
A
Then, write to WR
0
1
0
Note that the IVR value will NOT change
D0:LSB, D7:MSB
Reading from IVR
Write to the ACR first
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
1
0
0
0
1
A
D0
D7
D6
D5
D4
D3
D2
D1
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
1
0
0
0
1
A
D0
D7
D6
D5
D4
D3
D2
D1
Then set the IVR address
0
1
0
Read from the IVR
0
1
0
Example 2
Reading from the WR
Write to the ACR first
0
1
0
Then set the WR address
0
1
0
Read from the WR
0
1
0
Submit Document Feedback
17
FN7928.3
June 27, 2013
ISL97649A
Initial VCOM Setting
Layout Recommendation
A 256-step resolution is provided under digital control, which
adjusts the sink current of the output. The output is connected to
an external voltage divider, so that the device will have the
capability to reduce the voltage on the output by increasing the
output sink current. The equations that control the output are
given in the following. The initial setting value is at 128. The WR
value is set back to 128 if any error occurs during I2C read or
write communication. When writing to the EEPROM, VGH needs
to be higher than 12V when AVDD is 8V. Outside these
conditions, writing operations may be not successful. The
minimum resistor value of RSET is determined by the following
equations:
The device's performance, including efficiency, output noise,
transient response and control loop stability, is affected by the
PCB layout. PCB layout is critical, especially at high switching
frequency.
RSET  V_AVDD   20x100A 
(EQ. 13)
V AVDD
255 – Setting
IOUT = -------------------------------------  ----------------------------20  RSET 
256
(EQ. 14)
R L  V AVDD
RU
255 – Setting
VOUT = --------------------------------   1 – -------------------------------------  -----------------------------
 RU + RL  
20  RSET 
256
(EQ. 15)
where RL, RU and RSET in Equation 15 correspond to R7, R8 and
R9 in the Application Diagram on page 2.
Start-up Sequence
When VIN rising exceeds UVLO, it takes 120µs to read the
settings stored in the chip in order to activate the chip correctly.
After all the settings are written in the registers, VLOGIC starts up
with a 0.5ms soft-start time. When both VLOGIC is in regulation
and EN is high, the boost converter starts up. The Gate Pulse
modulator output VGHM is held low until VDPM is charged to
1.215V. The detailed power on sequence is shown in Figure 21.
Following are some general guidelines for layout:
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
2. Place VDC and VREF bypass capacitors close to the pins.
3. Loops with large AC amplitudes and fast slew rate should be
made as small as possible.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from the LX
node as possible.
5. The power ground (PGND) should be connected at the
ISL97649A exposed die plate area.
6. The exposed die plate, on the underside of the package,
should be soldered to an equivalent area of metal on the PCB.
This contact area should have multiple via connections to the
back of the PCB as well as connections to intermediate PCB
layers, if available to maximize thermal dissipation away from
the IC.
7. To minimize the thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track and
ground plane area connected to the exposed die plate should
be maximized and spread out as far as possible from the IC.
The bottom and top PCB areas especially should be
maximized to allow thermal dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
A demo board is available to illustrate the proper layout
implementation.
Submit Document Feedback
18
FN7928.3
June 27, 2013
ISL97649A
EN
UVLO
UVLO
VIN
tSS_VLOGIC
PANEL NORMAL OPERATION
VLOGIC
AVDD
tSS_AVDD CONTROLLED BY VSS
VOFF
VON
VCOM
1.280V
1.222V
1.217V
VDIV
CD2
1.215V
RESET
VDPM
GPM ENABLED WHEN BOTH
1) EN = HIGH AND
2) VDPM > 1.215V
VGHM
VGHM OUTPUT TIED TO VGH WHEN VIN FALLS TO UVLO
FIGURE 21. ISL97649A POWER ON/OFF SEQUENCE
Submit Document Feedback
19
FN7928.3
June 27, 2013
ISL97649A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
CHANGE
June 11, 2013
FN7928.3
Made correction to Equation 10 on page 13
From: VGH_headroom = (N + 1)*AVDD - N*Vd - VGH > 0
To: VGH_headroom = (N + 1)*AVDD - 2*N*Vd - VGH > 0
October 2, 2012
FN7928.2
Removed retired evaluation board ISL97649AIRTZ-EVALZ from “Ordering Information” on page 3.
Corrected Figure 2 title on page 9 from “IAVDD LOAD REGULATION vs IAVDD” to “AVDD LOAD REGULATION
vs IAVDD”.
Corrected Figure 3 title on page 9 from “IAVDD LINE REGULATION vs VIN” to “AVDD LINE REGULATION vs
VIN”.
Corrected Y axis of Figure 11 on page 10 from "VILDO" to “VLDO”.
Added "“VGH/VGL Charge Pump” on page 13.
Added Figures 15 and 16 to page 14.
Corrected Equation 14 on page 18.
Corrected Equation 15 on page 18.
June 19, 2012
FN7928.1
Page 1, "Features"
Changed “1.5A Integrated Boost for Up to 15V AVDD"
To: "1.5A, 0.18Ω integrated Boost FET"
May 23, 2012
Revised Equation 13 on page 18 from:
RSET  V_AVDD  100A
to:
RSET  V_AVDD   20x100A 
April 5, 2012
Changed pin 13, POS description in “Pin Descriptions” on page 3 from "VCOM Positive Amplifier Noninverting input" to "VCOM Amplifier Non-inverting input"
Changed pin 16, NEG description in “Pin Descriptions” on page 3 from "VCOM Negative Amplifier Noninverting input" to "VCOM Amplifier inverting input"
“Absolute Maximum Ratings” on page 5. Changed:
LX, AVDD, POS, OUT to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V
to:
LX, AVDD, POS, NEG, VOUT to GND . . . . . . . . . . . . . . . . . . -0.3 to +18V
December 5, 2011
FN7928.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
Submit Document Feedback
20
FN7928.3
June 27, 2013
ISL97649A
Package Outline Drawing
L28.4x5A
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 06/08
2.50
4.00
B
22
5.00
PIN #1 INDEX AREA
28
23
6
PIN 1
INDEX AREA
(4X)
6
24X 0.50
A
1
3.50
Exp. DAP
3.50
0.10 M C A B
4
28X 0.25
0.15
8
15
9
14
SIDE VIEW
TOP VIEW
2.50
Exp. DAP
28X 0.400
BOTTOM VIEW
SEE DETAIL "X"
( 3.80 )
0.10 C
Max 0.90
( 2.50)
C
SEATING PLANE
0.08 C
SIDE VIEW
( 4.80 )
( 24X 0.50)
( 3.50 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
(28X .250)
DETAIL "X"
( 28 X 0.60)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6.
Submit Document Feedback
21
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7928.3
June 27, 2013