TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET ISL97649B Features The ISL97649B is an integrated power management IC (PMIC) for TFT-LCDs used in notebooks, tablet PCs, and monitors. The device integrates a boost converter for generating AVDD. VON and VOFF are generated by a charge pump driven by the switching node of the boost. The ISL97649B also includes a VON slice circuit, reset function, and a high performance VCOM amplifier with DCP (Digitally Controlled Potentiometer) that is used as a VCOM calibrator. • 2.5V to 5.5V Input • 1.5A Integrated Boost for Up to 15V AVDD • VON /VOFF Supplies Generated by Charge Pumps Driven by Boost Switch Node • 600/1200kHz Selectable Switching Frequency • Integrated Gate Pulse Modulator • Reset Signal Generated by Supply Monitor The AVDD boost converter features a 1.5A /0.18Ω boost FET with 600/1200kHz switching frequency. The gate pulse modulator can control gate voltage up to 30V, and both the rate and slew delay time are selectable. The supply monitor generates a reset signal when the system is powered down. • Integrated VCOM Amplifier • DCP - I2C Serial Interface, address:100111, MSB Left - Wiper Position Stored in 8-bit Nonvolatile Memory and Recalled on Power-up - Endurance, 1,000 Data Changes Per Bit • UVLO, UVP, OVP, OCP, and OTP Protection The ISL97649B provides a programmable VCOM with I2C interface. One VCOM amplifier is also integrated in the chip. The output of VCOM is power-up with voltage at the last programmed 8-bit EEPROM setting. • Pb-Free (RoHS Compliant) • 28 Ld 4X5 QFN Applications • LCD Notebook, Tablet, and Monitor Pin Configuration EN LX VIN FREQ COMP SS ISL97649B (28 LD 4X5 QFN) TOP VIEW 28 27 26 25 24 23 FB 1 22 NC PGND 2 21 CD2 CE 3 20 NC RE 4 19 RESET VGH 5 18 NC VGHM 6 17 VDIV VFLK 7 16 NEG VDPM 8 15 VOUT December 5, 2011 FN7927.0 1 10 11 12 13 14 SCL SDA POS RSET GPM_LO 9 AVDD GND THERMAL PAD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL97649B Application Diagram VIN L1 10µH C1,2 20µF VIN VIN C7 0.1µF AVDD SW LX C32 0.1µF AVDD C4,5,6 30µF D1 R1 73.2k AVDD BOOST CONTROLLER EN SS FREQ SEQUENCER PGND R2 8.06k FB COMP R12 5.5k C20 15nF D4 C11 0.1µF C15 1µF Q1 R6 1k VOFF Z1 C16 1µF SW AVDD C8 47nF C10 47nF VON VFLK D2 C9 1µF C12 1µF D3 VGH VDPM SCL SDA RSET POS R9 10k 133k R8 AVDD C19 0.47µF VCOM GPM DCP CE C17 1nF C14 100pF C28 0.1µF RE VGHM VGH GPM R5 100k R22 22k GPM_LO R7 83k AVDD OUT NEG VDIV VCOM OP VOLTAGE DETECTOR CD2 RESET THERMAL PAD C18 0.47µF R14 85k R26 100k AVDD VGH Vin OPEN R15 115k C26 1nF RESET R16 10k VLOGIC Pin Descriptions PIN# SYMBOL DESCRIPTION 1 FB 2 PGND 3 CE Gate Pulse Modulator delay control. Connect a capacitor between this pin and GND to set the delay time. 4 RE Gate Pulse Modulator slew control. Connect a resistor between this pin and GND to set the falling slew rate. 5 VGH 6 VGHM Gate Pulse Modulator output for gate drive IC. 7 VFLK Gate Pulse Modulator control input from TCON. 8 VDPM Gate Pulse Modulator enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is enabled. A current source charges the capacitor on VDPM. 9 GPM_LO 10 AVDD 11 SCL AVDD boost converter feedback. Connect to the center of a voltage divider between AVDD and GND to set the AVDD voltage. Power ground Gate Pulse Modulator high voltage input. Place a 0.1µF decoupling capacitor close to VGH pin. Gate Pulse Modulator low voltage input. Place a 0.47µF decoupling capacitor close to GPM_LO pin. DCP and VCOM amplifier high voltage analog supply. Place a 0.47µF decoupling capacitor close to AVDD pin. I2C compatible clock input 2 FN7927.0 December 5, 2011 ISL97649B Pin Descriptions PIN# (Continued) SYMBOL DESCRIPTION 12 SDA I2C compatible serial bidirectional data line 13 POS VCOM positive amplifier non-inverting input 14 RSET DCP sink current adjustment pin. Connect a resistor between this pin and GND to set the resolution of DCP output voltage. 15 VOUT VCOM amplifier output 16 NEG VCOM negative amplifier non-inverting input 17 VDIV Voltage detector threshold. Connect to the center of a resistive divider between VIN and GND. 18 NC 19 RESET 20 NC Not connected 21 CD2 Voltage detector rising edge delay. Connect a capacitor between this pin and GND to set the rising edge delay. 22 NC Not connected 23 SS Boost converter soft-start. Connect a capacitor between this pin and GND to set the soft-start time. 24 COMP Boost converter compensation pin. Connect a series resistor and capacitor between this pin and GND to optimize transient response and stability. 25 FREQ Boost converter frequency select. Pull to logic high to operate boost at 1.2MHz. Connect this pin to GND to operate boost at 600kHz. 26 VIN IC input supply. Connect a 0.1µF decoupling capacitor close to this pin. 27 LX AVDD boost converter switching node 28 EN AVDD enable pin Not connected Voltage detector reset output Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING VIN RANGE (V) TEMP RANGE (°C) ISL97649BIRZ 97649 BIRZ 2.5 to 5.5 -40 to +85 ISL97649BIRTZ-EVALZ Evaluation Board PACKAGE (Pb-free) 28 Ld 4x5 QFN PKG. DWG. # L28.4x5A NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97649B. For more information on MSL please see Tech Brief TB363. 3 FN7927.0 December 5, 2011 ISL97649B Absolute Maximum Ratings Thermal Information RE, VGHM, GPM_LO, and VGH to GND . . . . . . . . . . . . . . . . . . . -0.3 to +36V LX, AVDD, POS, OUT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18V Voltage Between GND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5V All Other Pins to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . . . 1kV Thermal Resistance θJA (°C/W) θJC (°C/W) 4 x 5 QFN Package (Notes 4, 5) . . . . . . . . . 38 4.5 Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Functional Junction Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +150°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Lead Temperature during Soldering. . . . . . . . . . . . . . . . . . . . . . . . . +260°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications temperature range, -40°C to +85°C. SYMBOL VIN = ENABLE = 3.3V, AVDD = 8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 7) MAX (Note 6) UNITS 2.5 3.3 5.5 V GENERAL VIN IS_DIS VIN Supply Voltage Range VIN Supply Currents when Disabled VIN<UVLO 390 500 µA IS VIN Supply Currents ENABLE = 3.3V, overdrive AVDD and VGH 0.7 1.0 mA IENABLE ENABLE Pin Current ENABLE = 0V 0 µA LOGIC INPUT CHARACTERISTICS - ENABLE, FLK, SCL, SDA, FREQ VIL Low Voltage Threshold VIH High Voltage Threshold RIL Pull-Down Resistor 0.65 V 1.75 V Enable, FLK, FREQ 0.85 1.25 1.65 MΩ FREQ = low, TA = 25°C 550 600 650 kHz FREQ = high, TA = 25°C 1100 1200 1300 kHz INTERNAL OSCILLATOR FOSC Switching Frequencies AVDD BOOST REGULATOR ΔAVDD/ ΔIOUT AVDD Load Regulation 50mA < ILOAD < 250mA 0.2 % ΔAVDD/ ΔVIN AVDD Line Regulation ILOAD = 150mA, 2.5V < VIN < 5.5V 0.15 % VFB Feedback Voltage (VFB) ILOAD = 100mA, TA = +25°C IFB FB Input Bias Current rDS(ON) Switch ON-resistance ILIM Switch Current Limit DMAX Max Duty Cycle Freq = 1.2MHz, IAVDD = 100mA 4 0.8 0.808 100 nA 180 230 mΩ 1.125 1.5 1.875 A 80 90 % 91 % TA = +25°C Freq = 1.2MHz EFF 0.792 V FN7927.0 December 5, 2011 ISL97649B Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 7) MAX (Note 6) UNITS 33 V 1.30 V GATE PULSE MODULATOR VGH VIH_VDPM IVGH VGH Voltage 7 VDPM Enable Threshold VGH Input Current 1.13 1.215 VFLK = 0 125 µA RE = 100kΩ, VFLK = VIN 27.5 µA VGPM_LO GPM_LO Voltage 2 IGPM_LO VGPM_LO Input Current -2 VCEth1 VCEth2 VGH-2 V 0.1 2 µA CE Threshold Voltage 1 0.6xVIN 0.8xVIN V CE Threshold Voltage 2 1.215 V CE Current 100 µA RVGHM_PD VGHM Pull-down Resistance 1.1 kΩ RONVGH VGH to VGHM On Resistance 23 Ω VDPM Charge Current 10 µA ICE IDPM SUPPLY MONITOR VIH_VDIV VDIV High Threshold VDIV rising 1.265 1.280 1.295 V VIL_VDIV VDIV Low Threshold VDIV falling 1.21 1.222 1.234 V VthCD2 CD2 Threshold Voltage 1.200 1.217 1.234 V ICD2 RIL_RESET CD2 Charge Current 10 µA RESET Pull-down Resistance 650 Ω 121.7k* CD s tDELAY_RESET RESET Delay on Rising Edge VCOM AMPLIFIER: RLOAD = 10k, CLOAD = 10pF, UNLESS OTHERWISE STATED IS_com VOS IB VCOM Amplifier Supply Current 0.7 1.08 mA Offset Voltage 2.5 15 mV Noninverting Input Bias Current 0 nA CMIR Common Mode Input Voltage Range 0 CMRR Common-mode Rejection Ratio 60 75 dB PSRR Power Supply Rejection Ratio 70 85 dB IOUT(source) = 0.1mA AVDD 1.39 mV IOUT(source) = 75mA AVDD 1.27 V IOUT(sink) = 0.1mA 1.2 mV IOUT(sink) = 75mA 1 V VOH VOL ISC Output Voltage Swing High Output Voltage Swing Low Output Short Circuit Current SR Slew Rate BW Gain Bandwidth V Pull up 150 225 mA Pull down 150 200 mA 25 V/µs 20 MHz -3dB gain point 5 AVDD FN7927.0 December 5, 2011 ISL97649B Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP (Note 7) MAX (Note 6) UNITS DIGITAL CONTROLLED POTENTIOMETER SETVR SET Voltage Resolution (Note 12) SETDNL SET Differential Nonlinearity (Notes 8, 9, 14) TA = +25°C - - ±1 LSB SETZSE SET Zero-Scale Error (Note 10,14) TA = +25°C - - ±2 LSB SETFSE SET Full-Scale Error (Note 11,14) TA = +25°C - - ±8 LSB 100 µA IRSET AVDD to SET 8 Bits RSET Current - AVDD to SET Voltage Attenuation - 1:20 - V/V PVIN rising 2.25 2.33 2.41 V PVIN falling 2.125 2.20 2.27 V 15.0 15.5 16.0 V FAULT DETECTION THRESHOLD VUVLO OVPAVDD TOFF Undervoltage Lock-out Threshold Boost Overvoltage Protection Off Threshold to Shut Down IC (Note 13) Thermal Shut-Down all channels Temperature rising 153 °C POWER SEQUENCE TIMING ISS Boost Soft-start Current Serial Interface Specifications 3 5.5 8 µA For SCL and SDA, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. SYMBOL fSCL PARAMETER TEST CONDITIONS MIN (Note 14) TYP (Note 7) SCL Frequency (Note 6) MAX (Note 14) UNITS 400 kHz tiN Pulse Width Suppression Time at SDA and SCL Inputs (Note 6) Any pulse narrower than the max spec is suppressed. 50 ns tAA SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing 30% of VIN, until SDA exits the 30% to 70% of VIN window. 480 ns tBUF Time the Bus Must be Free Before the Start of a New Transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VIN during the following START condition. 480 ns tLOW Clock LOW Time Measured at 30% of VIN crossing. 480 ns tHIGH Clock HIGH Time Measured at 70% of VIN crossing. 400 ns tSU:STA START Condition Set-up Time SCL rising edge to SDA falling edge, both crossing 70% of VIN. 480 ns tHD:STA START Condition Hold Time From SDA falling edge crossing 30% of VIN to SCL falling edge crossing 70% of VIN. 400 ns tSU:DAT Input Data Set-up Time From SDA exiting 30% to 70% of VIN window to SCL rising edge crossing 30% of VIN. 40 ns tHD:DAT Input Data Hold Time From SCL rising edge crossing 70% of VIN to SDA entering 30% to 70% of VIN window. 0 ns tSU:STO STOP Condition Set-up Time From SCL rising edge crossing 70% of VIN to SDA rising edge crossing 30% of VIN. 400 ns tHD:STO STOP Condition Hold Time for Read, or Volatile Only Write From SDA rising edge to SCL falling edge, both crossing 70% of VIN. 400 ns CSCL Capacitive on SCL 5 6 pF FN7927.0 December 5, 2011 ISL97649B Serial Interface Specifications For SCL and SDA, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL CSDA tWp PARAMETER TEST CONDITIONS MIN (Note 14) TYP (Note 7) MAX (Note 14) UNITS Capacitive on SDA 5 pF Non-Volatile Write Cycle Time 25 ms EEPROM Endurance TA= +25°C 1 kCyc EEPROM Retention TA = +25°C 88 kHrs NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Typical values are for TA = +25°C and VIN = 3.3V. 8. LSB = I V255 - V1 I / 254. V255 and V1 are the measured voltages for the DCP register set to FF hex and 01 hex, respectively. 9. DNL = I Vi+1 - Vi I / LSB-1, i ∈ [ 1, 255 ] 10. ZS error = (V1- VMAX)/LSB. VMAX = (VAVDD * R2) * [1-2 * R1/(256 * 20 * RSET)]/(R1 + R2) 11. FS error = (V255 - VMIN)/LSB. VMIN = (VAVDD * R2) * [1-256 * R1/(256 * 20 * RSET)]/(R1 + R2) 12. Established by design. Not a parametric spec. 13. Boost will stop switching as soon as boost output reaches OVP threshold. 14. Compliance to limits is assured by characterization and design. 7 FN7927.0 December 5, 2011 ISL97649B Typical Performance Curves 92 90 fOSC = 600kHz LOAD REGULATION (%) EFFICIENCY (%) 0.00 fOSC = 1.2MHz 88 86 84 82 80 VIN = 3.3V 78 VOUT = 8.06V 76 0 50 100 150 200 250 300 350 -0.01 -0.02 fOSC = 600kHz fOSC = 1.2MHz -0.03 VIN = 3.3V -0.04 50 VOUT = 8.06V 100 IAVDD (mA) 150 200 250 IAVDD (mA) FIGURE 1. AVDD EFFICIENCY vs IAVDD FIGURE 2. AVDD LOAD REGULATION vs IAVDD 0.14 IAVDD = 150mA 0.12 AVDD (V) 0.10 0.08 0.06 0.04 0.02 0.00 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VIN (V) FIGURE 3. AVDD LINE REGULATION vs VIN VGHM FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE VGHM FIGURE 5. GPM CIRCUIT WAVEFORM 8 FIGURE 6. GPM CIRCUIT WAVEFORM FN7927.0 December 5, 2011 ISL97649B Typical Performance Curves (Continued) VGHM VGHM FIGURE 7. GPM CIRCUIT WAVEFORM FIGURE 8. GPM CIRCUIT WAVEFORM VGHM FIGURE 9. VGHM FOLLOWS VGH WHEN THE SYSTEM POWERS OFF 9 FIGURE 10. VCOM RISING SLEW RATE FN7927.0 December 5, 2011 ISL97649B Applications Information The current through the MOSFET is limited to 1.5APEAK. This restricts the maximum output current (average) based on Equation 3: Enable Control With VIN > UVLO, all functions in ISL97649B are shut down when the Enable pin is pulling down. When the voltage at the Enable pin reaches H threshold, the whole ISL97649B is on. Frequency Selection The ISL97649B switching frequency can be user selected to operate at either a constant 600kHz or 1.2MHz. Lower switching frequency can save power dissipation when the boost load is very low and the device is operating in deep discontinuous mode. Higher switching frequency can allow the use of smaller external components like inductors and output capacitors. Higher switching frequency will get higher efficiency within some loading ranges, depending on VIN, VOUT, and external components, as shown in Figure 1. Connecting the FREQ pin to GND sets the PWM switching frequency to 600kHz. Connecting the FREQ pin to VIN sets the PWM switching frequency to 1.2MHz. ΔI L V IN I OMAX = ⎛ I LMT – --------⎞ × -------⎝ ⎠ 2 VO (EQ. 3) where ΔIL is peak-to-peak inductor ripple current, which is set by Equation 4: V IN D ΔI L = -------- × ---L fs (EQ. 4) where fS is the switching frequency (600kHz or 1.2MHz). Capacitor An input capacitor is used to suppress the voltage ripple injected into the boost converter. A ceramic capacitor with capacitance larger than 10µF is recommended. The voltage rating of the input capacitor should be larger than the maximum input voltage. Table 1 shows some recommended input capacitors. TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATIONS Soft-Start CAPACITOR SIZE MFG PART NUMBER Soft-start is provided by an internal current source to charge the external soft-start capacitor. The ISL97649B ramps up the current limit from 0A to full value as voltage at the SS pin ramps from 0 to 0.8V. Hence, the soft-start time is 3.2ms when the softstart capacitor is 22nF and is 6.8ms for 47nF and 14.5ms for 100nF. 10µF/6.3V 0603 TDK C1608X5R0J106M 10µF/16V 1206 TDK C3216X7R1C106M 10µF/10V 0805 Murata GRM21BR61A106K 22µF/10V 1210 Murata GRB32ER61A226K Operation Inductor The boost converter is a current mode PWM converter operating at either 600kHz or 1.2MHz. It can operate in both discontinuous conduction mode (DCM) at light load and in continuous conduction mode (CCM). In continuous conduction current mode, current flows continuously in the inductor during the entire switching cycle in steady-state operation. The voltage conversion ratio in continuous current mode is given by Equation 1: The boost inductor is a critical part that influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH are used to match the internal slope compensation. The inductor must be able to handle the average and peak currents shown in Equation 5: V Boost 1 ----------------- = ------------1–D V IN ΔI L I LPK = I LAVG + -------2 (EQ. 1) where D is the duty cycle of the switching MOSFET. The boost regulator uses a summing amplifier architecture consisting of gm stages for voltage feedback, current feedback, and slope compensation. A comparator looks at the peak inductor current, cycle by cycle, and terminates the PWM cycle if the current limit is reached. An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network on the order of 60kΩ is recommended. The boost converter output voltage is determined by Equation 2: R1 + R2 V Boost = -------------------- × V FB R2 (EQ. 2) 10 IO I LAVG = ------------1–D (EQ. 5) Table 2 shows some recommended inductors for different design considerations. TABLE 2. BOOST INDUCTOR RECOMMENDATIONS INDUCTOR 10µH/ 4Apeak DIMENSIONS (mm) MFG PART NUMBER DESIGN CONSIDERATION 8.3x8.3x4.5 Sumida CDR8D43- Efficiency 100NC optimization 6.8µH/ 1.8Apeak 5.0x5.0x2.0 PLF5020T6R8M1R8 10µH/ 2.2Apeak 6.6x7.3x1.2 TDK Cyntec PCME061B- PCB space /profile 100MS optimization Rectifier Diode A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The reverse voltage rating of this diode should be higher than the maximum output FN7927.0 December 5, 2011 ISL97649B voltage. The rectifier diode must meet the output current and peak inductor current requirements. Table 3 shows some recommendations for boost converter diode. For example, delay time is 12.17ms if CD2 = 100nF. Figure 11 shows the supply monitor circuit timing diagram. TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATIONS DIODE VR/IAVG RATING PACKAGE MFG PMEG2010ER 20V/1A SOD123W NXP MSS1P2U 20V/1A MicroSMP VISHAY 1.28V VDIV 1.22V 1.217V Output Capacitor CD2 The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components (Equation 6): 1. Voltage drop due to inductor ripple current flowing through the ESR of output capacitor. 2. Charging and discharging of output capacitor. IO V O – V IN 1 V RIPPLE = I LPK × ESR + --------------------- × ------------- × ---f C V O OUT s NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in Equation 6 assumes the effective value of the capacitor at a particular voltage and not the manufacturer’s stated value, measured at 0V. Table 4 shows some recommendations for output capacitors. TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATIONS CAPACITOR SIZE MFG PART NUMBER 10µF/25V 1210 TDK C3225X7R1E106M 10µF/25V 1210 Murata GRM32DR61E106K Compensation The boost converter of ISL97649B can be compensated by an RC network connected from the COMP pin to ground. A 15nF and 5.5k RC network is used in the ISL97649BIRTZ-EVALZ evaluation board. The larger-value resistor and lower-value capacitor can lower the transient overshoot, but at the expense of loop stability. Supply Monitor Circuit The supply monitor circuit monitors the voltage on VDIV and sets the open-drain output RESET low when VDIV is below 1.28V (rising) or 1.22V (falling). There is a delay on the rising edge, controlled by a capacitor on CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from 0V to 1.217V by a 10µA current source. When CD2 exceeds 1.217V, RESET goes tri-state. When VDIV falls below 1.22V, RESET becomes low, with a 650Ω pull-down resistance. Delay time is controlled as shown in Equation 7: (EQ. 7) 11 RESET DELAY TIME IS CONTROLLED BY CD2 CAPACITOR FIGURE 11. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM (EQ. 6) For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. t delay = 121.7k × CD2 RESET Gate Pulse Modulator Circuit The gate pulse modulator circuit functions as a three-way multiplexer, switching VGHM between ground, GPM_LO, and VGH. Voltage selection is provided by digital inputs VDPM (enable) and VFLK (control). High-to-low delay and slew control are provided by external components on pins CE and RE, respectively. When VDPM is LOW, the block is disabled, and VGHM is grounded. When the input voltage exceeds UVLO threshold, VDPM starts to drive an external capacitor. When VDPM exceeds 1.215V, the GPM circuit is enabled, and the output VGHM is determined by VFLK, RESET signal, and VGH voltage. If RESET signal is high and VFLK is high, VGHM is pulled to VGH. When VFLK goes low, there is a delay controlled by capacitor CE, following which VGHM is driven to GPM_LO, with a slew rate controlled by resistor RE. Note that GPM_LO is used only as a reference voltage for an amplifier, and thus does not have to source or sink a significant DC current. Low-to-high transition is determined primarily by the switch resistance and the external capacitive load. High-to-low transition is more complex. Consider a case in which the block is already enabled (VDPM is H). When VFLK is H, if CE is not externally pulled above threshold voltage 1, Pin CE is pulled low. On the falling edge of VFLK, a current is passed into Pin CE to charge the external capacitor up to threshold voltage 2, providing a delay that is adjustable by varying the capacitor on CE. Once this threshold is reached, the output starts to be pulled down from VGH to GPM_LO. The maximum slew current is equal to 500/(RE + 40k), and the dv/dt slew rate is Isl/CLOAD, where CLOAD is the load capacitance applied to VGHM. The slew rate reduces as VGHM approaches GPM_LO. If CE is always pulled up to a voltage above threshold 1, zero delay mode is selected; thus, there will be no delay from FLK falling to the point where VGHM starts to fall. Slew down currents will be identical to the previous case. At power-down, when VIN falls to UVLO, VGHM is tied to VGH until the VGH voltage falls to 3V. Once the VGH voltage falls below 3V, VGHM is not actively driven until VIN is driven. Figure 12 shows the VGHM voltage based on VIN, VGH, and RESET. FN7927.0 December 5, 2011 ISL97649B VIN UVLO THRESHOLD 0 VGH RESET VDPM 1.215V VFLK VGH VGHM VGHM IS FORCED is forced to TO VGH WHEN VIN VGH FALLS TOwhen UVLORESET AND Slope goes SLOPEisIScontrolled VGH >3Vto low AND CONTROLLED BY RE VGH>3V by RE Power on DELAY delay time Delay POWER-ON TIME DELAYtime TIMEisIScontrolled is controlled by CONTROLLED BY CDPM by CE CONTROLLED BY CE CDPM GPM_LO FIGURE 12. GATE PULSE MODULATOR TIMING DIAGRAM VCOM Amplifier The VCOM amplifier is designed to control the voltage on the back plane of an LCD display. This plate is capacitively coupled to the pixel drive voltage, which alternately cycles positive and negative at the line rate for the display. Thus, the amplifier must be capable of sourcing and sinking pulses of current, which can occasionally be quite large (in the range of 100mA for typical applications). The ISL97649B VCOM amplifier output current is limited to 225mA typical. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case, the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen in the µs time scale in practical systems and for pulses 2 or 3 times the current limit, the VCOM voltage will have settled again before the next line is processed. A VDD REGISTER VALUE 19R 255 AVDD 20 254 253 VDCP 252 R 251 2 1 0 FIGURE 13. SIMPLIFIED SCHEMATIC OF DIGITALLY CONTROLLED POTENTIOMETER (DCP) DCP (Digitally Controlled Potentiometer) Current Sink Figure 13 shows the relationship between the register value and the resistor string of the DCP. Note that the register value of zero actually selects the first step of the resistor string. The output voltage of DCP is given by Equation 8: Figure 14 shows the schematic of the POS pin current sink. The circuit is made up of amplifier A1, transistor Q1, and resistor RSET, which form a voltage controlled current source. RegisterValue + 1 A VDD V DCP = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞ ⎝ ⎠ ⎝ 20 ⎠ 256 12 (EQ. 8) FN7927.0 December 5, 2011 ISL97649B AVDD AVDD R1 POS VOUT VDCP Q1 A1 controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the DCP of the ISL97649B operates as a slave device in all applications. The fall and rise times of the SDA and SCL signals should be in the range listed in Table 5. Capacitive load on I2C bus is also specified in Table 5. All communication over the I2C interface is conducted by sending the MSB of each byte of data first. R2 VSAT RSET VSET = (IOUT)*(RSET) = VDCP TABLE 5. I2C INTERFACE SPECIFICATIONS PARAMETER RSET IOUT FIGURE 14. CURRENT SINK CIRCUIT The external RSET resistor sets the full-scale sink current that determines the lowest output voltage of the external voltage divider, R1 and R2. IOUT is calculated as shown by Equation 9: V DCP RegisterValue + 1 A VDD 1 I OUT = ------------- = ⎛ ---------------------------------------------------⎞ ⎛ --------------⎞ ⎛ -------------⎞ ⎝ ⎠ ⎝ 20 ⎠ ⎝ R ⎠ R SET 256 SET (EQ. 9) The maximum value of IOUT can be calculated by substituting the maximum register value of 255 into Equation 9, resulting in Equation 10: A VDD I OUT ( MAX ) = -------------------20R SET (EQ. 10) Equation 9 can also be used to calculate the unit sink current step size by removing the Register Value term from it, as shown in Equation 11. A VDD I STEP = ---------------------------------------------( 256 ) ( 20 ) ( R SET ) (EQ. 11) The voltage difference between the POS and RSET pins, which are the drain and source, respectively, of the output transistor, should be greater than the minimum saturation voltage for the IOUT(MAX) being used. This difference keeps the output transistor in its saturation region. The maximum voltage on the RSET pin is AVDD/20, and this voltage is added to the minimum voltage difference between the VOUT and RSET pins to calculate the minimum VOUT voltage, as shown in Equation 12. A VDD V OUT ( MIN ) ≥ -------------- + MinimumSaturationVoltage 20 (EQ. 12) Output Voltage The output voltage, VOUT, can be calculated with Equation 13: R L ⋅ V AVDD RU RegisterValue + 1 V OUT = ---------------------------- ⋅ ⎛ 1 – --------------------------------------------------- × ---------------------------⎞ ( RU + RL ) ⎝ 20 ( RSET )⎠ 256 (EQ. 13) where RL, RU and RSET in Equation 11 correspond to R7, R8 and R9 in the Application Diagram on page 2. I2C Serial Interface The ISL97649B supports a bidirectional, bus-oriented protocol. The protocol defines any device that sends data on to the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master, and the device being 13 MIN TYP MAX UNITS SDA and SCL Rise Time 1000 ns SDA and SCL Fall Time 300 ns I2C Bus Capacitive Load 400 pF Programming Supply Voltage To program EEPROM bits, VGH must be higher than 12V when AVDD is 8V. Outside these conditions, writing operations may not be successful. Protocol Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (Figure 15). On power-up of the ISL97649B, the SDA pin is in input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The DCP continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (Figure 15). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is high (Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only, places the device in standby mode. A STOP condition during a write operation to a non-volatile write byte initiates an internal non-volatile write cycle. The device enters standby mode when the internal non-volatile write cycle is completed. An Acknowledge (ACK) is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge receipt of the eight bits of data (Figure 16). The ISL97649B DCP responds with an ACK after recognizing a START condition followed by a valid identification byte (Byte 1). If a master-receiver is involved in a transfer, it must signal the end of data transmission to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The ISL97649B releases the dataline to allow the master to generate a STOP condition. FN7927.0 December 5, 2011 ISL97649B SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 SDA OUTPUT FROM TRANSMITTER 9 HIGH IMPEDANCE HIGH IMPEDANCE SDA OUTPUT FROM RECEIVER START ACK FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER A valid identification byte (Byte 1) contains 100111 as the six MSBs. The 7th bit could be either 0 or 1 in the read operation, while it is the data LSB (D0) in the write operation. The LSB is in the read/write bit. Its value is 1 for a read operation and 0 for a write operation (Figures 17 and 18). Read Operation A read operation consists of one instruction byte followed by one data byte (Figure 17). The master initiates a START and the identification byte with the R/W bit set to 1; the ISL97649B responds with an ACK; and then the ISL97649B transmits the data byte. The master terminates the read operation (issues a STOP condition) following the last bit of the data byte (Figure 17). Write Operation A write operation requires a START condition followed by a valid identification byte, a data byte, and a STOP condition (Figure 18). After each of the two bytes, the ISL97649B responds with an ACK. If the data byte is also to be written to non-volatile memory, the ISL97649B begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output 14 is at high impedance state. When the internal non-volatile write cycle is completed, the ISL97649B enters its standby state. The LSB in Byte 2 determines whether the data byte is to be written to volatile and/or non-volatile memory. Data Protection A STOP condition also acts as a protection of non-volatile memory. A valid identification byte, a data byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a write sequence, the data byte is loaded into an internal shift register as it is received. If Byte 2 LSB is 1, the data byte is transferred to the register only. If Byte 2 LSB is 0, then the STOP condition initiates the internal write cycle to non-volatile memory. ISL97649B Programming Figure 17 shows the serial data format for reading the register. Figure 18 shows the serial data format for writing the register. The ISL97649B uses a 6-bit I2C address, which is 100111xx. The complete read and write protocol is shown in Figures 17 and 18. FN7927.0 December 5, 2011 ISL97649B I2C Read and Write Format FIGURE 17. I2C READ FORMAT ISL24 201 I 2 C rite ISL97649B I2CWWrite B yte 1 By te 2 D ata L SB 6 b it Ad d res s S tar t MSB 1 R/ W AC K LSB 0 0 1 1 1 D0 0 D a ta P rog ra m M SB A D7 A CK Sto p LSB D6 D5 R /W = 0 = W rite R/ W = 1 = R ead D4 D3 D2 D1 P A W he n R /W = 0 P = 0 = EE P ROM P r og ram m in g P = 1 = Reg ister W rite FIGURE 18. I2C WRITE FORMAT 15 FN7927.0 December 5, 2011 ISL97649B Start-up Sequence When VIN rising exceeds UVLO, it takes 120µs to read the settings stored in the chip in order to activate the chip correctly. When VIN is above UVLO and EN is high, the boost converter starts up. The gate pulse modulator output VGHM is held low until VDPM is charged to 1.215V. The detailed power-on sequence is shown in Figure 19. EN UVLO UVLO VIN PANEL NORMAL OPERATION AVDD T SS_AVDD CONTROLLED BY V SS VOFF VON VCOM 1.280V 1.222V 1.217V VDIV CD2 1.215V RESET VDPM GPM ENABLED WHEN BOTH 1) EN = HIGH AND 2) VDPM >1.215V VGHM VGHM OUTPUT TIED TO VGH WHEN VIN FALLS TO UVLO FIGURE 19. ISL97649B DETAILED POWER-ON/POWER-OFF SEQUENCE 16 FN7927.0 December 5, 2011 ISL97649B Layout Recommendations The device's performance, including efficiency, output noise, transient response and control loop stability, is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. Some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VDC and VREF bypass capacitors close to the pins. 3. Reduce the loop with large AC amplitudes and fast slew rate. 4. The feedback network should sense the output voltage directly from the point of load and should be as far away from the LX node as possible. 17 5. The power ground (PGND) and signal ground (SGND) pins should be connected at the ISL97649B exposed die plate area. 6. The exposed die plate, on the underside of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. Minimize feedback input track lengths to avoid switching noise pick-up. The ISL97649BIRTZ-EVALZ evaluation board is available to illustrate the proper layout implementation. FN7927.0 December 5, 2011 ISL97649B Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION December 5, 2011 FN7927.0 CHANGE Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL97649B To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7927.0 December 5, 2011 ISL97649B Package Outline Drawing L28.4x5A 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 06/08 2.50 4.00 B 22 5.00 PIN #1 INDEX AREA 28 23 6 PIN 1 INDEX AREA (4X) 6 24X 0.50 A 1 3.50 Exp. DAP 3.50 0.10 M C A B 4 28X 0.25 0.15 8 15 9 14 SIDE VIEW TOP VIEW 2.50 Exp. DAP 28X 0.400 BOTTOM VIEW SEE DETAIL "X" ( 3.80 ) 0.10 C Max 0.90 ( 2.50) C SEATING PLANE 0.08 C SIDE VIEW ( 4.80 ) ( 24X 0.50) ( 3.50 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. (28X .250) DETAIL "X" ( 28 X 0.60) TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. 19 The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN7927.0 December 5, 2011