SPI42N03S2L-13 SPP42N03S2L-13 OptiMOS® Power-Transistor SPB42N03S2L-13 Product Summary Features • N-channel • Enhancement mode V DS 30 V R DS(on),max 12.9 mΩ ID 42 A • Logic level • Excellent gate charge x R DS(on) product (FOM) • Superior thermal resistance • 175 °C operating temperature P-TO262-3-1 P-TO263-3-2 P-TO220-3-1 • Avalanche rated • dv /dt rated Type Package Ordering Code Marking SPP42N03S2L-13 P-TO220-3-1 Q67042-S4034 2N03L13 SPB42N03S2L-13 P-TO263-3-2 Q67042-S4035 2N03L13 SPI42N03S2L-13 P-TO262-3-1 Q67042-S4104 2N03L13 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Continuous drain current1) ID Value T C=25 °C 42 T C=100 °C 42 Unit A Pulsed drain current I D,pulse T C=25 °C 248 Avalanche energy, single pulse E AS I D=42 A, R GS=25 Ω 110 mJ Repetitive avalanche energy E AR limited by T jmax 2) 8 mJ Reverse diode dv /dt dv /dt I D=42 A, V DS=24 V, di /dt =200 A/µs, T j,max=175 °C 6 kV/µs Gate source voltage V GS Power dissipation P tot Operating and storage temperature T j, T stg T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 2.0 ±20 V 83 W -55 ... 175 °C 55/175/56 page 1 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Parameter SPB42N03S2L-13 Values Symbol Conditions Unit min. typ. max. - 1.2 1.8 minimal footprint - - 62 6 cm2 cooling area3) - - 40 Thermal characteristics Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=37 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=30 V, V GS=0 V, T j=25 °C - 0.01 1 V DS=30 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 1 100 nA Drain-source on-state resistance4) R DS(on) V GS=4.5 V, I D=21 A - 14.9 19.9 mΩ V GS=4.5 V, I D=21 A, SMD version - 14.5 19.6 V GS=10 V, I D=21 A - 10.3 12.9 V GS=10 V, I D=21 A, SMD version - 9.9 12.6 - 1 - Ω 21 42 - S Gate resistance RG Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=42 A 1) Current is limited by bondwire; with an R thJC=1.8 K/W the chip is able to carry 64 A at 25°C, for detailed information see app.-note ANPS071E at www.infineon.com/optimos. 2) Defined by design. Not subject to production test. 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 4) Diagrams are related to straight lead versions. Rev. 2.0 page 2 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Parameter SPB42N03S2L-13 Values Symbol Conditions Unit min. typ. max. - 850 1130 - 330 440 Dynamic characteristics Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 90 130 Turn-on delay time t d(on) - 6.5 9.8 Rise time tr - 12 18 Turn-off delay time t d(off) - 24 36 Fall time tf - 14.5 21.8 Gate to source charge Q gs - 2.7 3.6 Gate to drain charge Q gd - 7.9 11.9 Gate charge total Qg - 22.9 30.5 Gate plateau voltage V plateau - 3.5 - V - - 42 A - - 248 - 0.95 1.25 V - 24 31 ns - 18 23 nC V GS=0 V, V DS=25 V, f =1 MHz V DD=15 V, V GS=10 V, I D=21 A, R G=7.8 Ω pF ns Gate Charge Characteristics V DD=24 V, I D=21 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current IS Diode pulse current I S,pulse Diode forward voltage V SD Reverse recovery time t rr T C=25 °C V GS=0 V, I F=42 A, T j=25 °C V R=15 V, I F=I S, di F/dt =100 A/µs Reverse recovery charge Rev. 2.0 Q rr page 3 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 1 Power dissipation 2 Drain current P tot=f(T C) I D=f(T C); V GS≥10 V 90 SPB42N03S2L-13 50 80 40 70 60 I D [A] P tot [W] 30 50 40 20 30 20 10 10 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 1000 10 100 1 1 µs limited by on-state resistance 100 0.5 10 µs I D [A] 102 101 0.2 Z thJC [K/W] 103 200 0.1 10-1 100 µs 0.05 0.1 0.02 0.01 101 100 10 1 ms 1 0.1 1 -1 10 Rev. 2.0 10 0 10 100 1 V DS [V] 10 10-2 0.01 10-3 0.001 2 10 page 4 single pulse 0 0 -6 10 0 -5 10 0 -4 10 0 -3 10 t p [s] 0 -2 10 1 -1 10 100 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 SPB42N03S2L-13 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 40 120 3V 5.5 V 10 V 4V 3.5 V 5V 6V 100 30 80 R DS(on) [mΩ] I D [A] 4.5 V 60 4V 20 4.5 V 5V 5.5 V 40 6V 10 V 10 3.5 V 20 3V 0 0 0 1 2 3 4 0 5 10 20 V DS [V] 30 40 50 60 I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 60 100 90 50 80 70 40 g fs [S] I D [A] 60 50 30 40 20 30 20 10 175 °C 25 °C 10 0 0 0 1 2 3 4 5 V GS [V] Rev. 2.0 0 20 40 60 80 I D [A] page 5 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 SPB42N03S2L-13 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=21 A; V GS=10 V V GS(th)=f(T j); V GS=V DS parameter: I D 30 2.5 25 2 800 µA 15 1.5 V GS(th) [V] R DS(on) [mΩ] 20 98 % 37 µA 1 typ 10 0.5 5 0 0 -60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 10000 104 1000 25°C 98% Ciss 1000 103 175°C 98% 100 25 °C 175 °C I F [A] C [pF] Coss Crss 100 102 10 10 1 0 5 10 15 20 25 30 V DS [V] Rev. 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V SD [V] page 6 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 13 Avalanche characteristics 14 Typ. gate charge E AS=f(Tj) V GS=f(Q gate); I D=21 A pulsed parameter: ID=42A, VDD=25V, RGS=25Ω parameter: V DD SPB42N03S2L-13 16 120 6V 14 24 V 100 12 80 V GS [V] E AS [mJ] 10 60 8 6 40 4 20 2 0 0 25 50 75 100 125 150 0 175 4 T j [°C] 8 12 16 20 24 28 32 36 Q gate [nC] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=1 mA 35 V GS 34 Qg 33 V BR(DSS) [V] 32 31 V g s(th) 30 29 Q g (th) 28 Q sw Q gs 27 -60 -20 20 60 100 140 Q gate Q gd 180 T j [°C] Rev. 2.0 page 7 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 SPB42N03S2L-13 Package Outline P-TO263-3-2: Outline Footprint Packaging P-TO262-3-1: Outline Dimensions in mm Rev. 2.0 page 8 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 SPB42N03S2L-13 Package Outline P-TO220-3-1: Outline Packaging Dimensions in mm Rev. 2.0 page 9 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 SPB42N03S2L-13 Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Straße 53 D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide (see address list). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Further information Please note that the part number is BSPP42N03S2L-13, BSPB42N03S2L-13 and BSPI42N0ß3S2L, for simplicity the device is refered to by the term SPP42N03S2L-13, SPB42N03S2L-13, SPI42N03S2L-13 throughout this documentation. Rev. 2.0 page 10 2004-06-04