Data Sheet, Rev. 1.1, October 2008 TLE42694 Low Dropout Fixed Voltage Regulator Automotive Power Low Dropout Fixed Voltage Regulator 1 TLE42694 Overview Features • • • • • • • • • • • • • • • • • Output Voltage 5 V ± 2% Ouput Current up to 150 mA Very Low Current Consumption Early Warning Power-on and Undervoltage Reset with Programmable Delay Time Reset Low Down to VQ = 1 V Adjustable Reset Threshold Very Low Dropout Voltage Output Current Limitation Reverse Polarity Protection Overtemperature Protection Suitable for Use in Automotive Electronics Wide Temperature Range from -40 °C up to 150 °C Input Voltage Range from -42 V to 45 V Integrated Pull-Up Resistors at Logic Outputs Green Product (RoHS compliant) AEC Qualified PG-DSO-8 Description The TLE 42694 is a monolithic integrated low dropout voltage PG-DSO-14 regulator, especially designed for automotive applications. An input voltage up to 45 V is regulated to an output voltage of 5.0 V. The component is able to drive loads up to 150 mA. It is short-circuit proof by the implemented output current limitation and has an integrated overtemperature shutdown. A reset signal is generated for an output voltage VQ,rt of typically 4.65 V. This threshold can be decreased by an external resistor divider. The power-on reset delay time can be programmed by the external delay capacitor. The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be monitored, an under-voltage condition is indicated by setting the comparator’s output to low. The reset and sense output are internally connected to the output Q via a pull-up resistor. If these PG-SSOP-14 exposed pad integrated resistors are not desired, the TLE42794 can be used instead of the TLE42694. Type Package Marking TLE42694G PG-DSO-8 42694G TLE42694GM PG-DSO-14 42694GM TLE42694E PG-SSOP-14 exposed pad 42694E Data Sheet 2 Rev. 1.1, 2008-10-07 TLE42694 Overview Dimensioning Information on External Components The input capacitor CI is recommended for compensation of line influences. The output capacitor CQ is necessary for the stability of the control loop. Circuit Description The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any oversaturation of the power element. The component also has a number of internal circuits for protection against: • • • Overload Overtemperature Reverse polarity Data Sheet 3 Rev. 1.1, 2008-10-07 TLE42694 Block Diagram 2 Block Diagram Ι Q Error Amplifier 20 kΩ 20 kΩ Current and Saturation Control Reference Trimming D RO & Reference SO RADJ SI GND Figure 1 Data Sheet AEB01669 Block Diagram 4 Rev. 1.1, 2008-10-07 TLE42694 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-DSO-8 PG-DSO-8 Ι SΙ RADJ D 1 2 3 4 8 7 6 5 Q SO RO GND AEP01668 Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions PG-DSO-8 Table 1 Pin Symbol Function 1 I Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended 2 SI Sense Input connect the voltage to be monitored; connect to Q if the sense comparator is not needed 3 RADJ Reset Threshold Adjust connect an external voltage divider to adjust reset threshold; connect to GND for using internal threshold 4 D Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed 5 GND Ground 6 RO Reset Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the reset function is not needed 7 SO Sense Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the sense comparator is not needed 8 Q Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in “Functional Range” on Page 9 Data Sheet 5 Rev. 1.1, 2008-10-07 TLE42694 Pin Configuration 3.3 Pin Assignment PG-DSO-14 PG-DSO-14 RADJ D GND GND GND GND RO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SI Ι GND GND GND Q SO AEP02248 Figure 3 Pin Configuration (top view) 3.4 Pin Definitions and Functions PG-DSO-14 Table 2 Pin Symbol Function 1 RADJ Reset Threshold Adjust connect an external voltage divider to adjust reset threshold; connect to GND for using internal threshold 2 D Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed 3, 4, 5, 6 GND Ground all pins must be connected to GND 7 RO Reset Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the reset function is not needed 8 SO Sense Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the sense comparator is not needed 9 Q Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table “Functional Range” on Page 9 10, 11, 12 GND Ground all pins must be connected to GND 13 I Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended 14 SI Sense Input connect the voltage to be monitored; connect to Q if the sense comparator is not needed Data Sheet 6 Rev. 1.1, 2008-10-07 TLE42694 Pin Configuration 3.5 Pin Assignment PG-SSOP-14 exposed pad 5$'QF ' *1' QF QF 52 6, , QF 4 QF QF 62 3LQ&RQILJB6623YVG Figure 4 Pin Configuration (top view) 3.6 Pin Definitions and Functions PG-SSOP-14 exposed pad Table 3 Pin Symbol Function 1 RADJ Reset Threshold Adjust connect an external voltage divider to adjust reset threshold; connect to GND for using internal threshold 2, 5, 6 n.c. not connected 3 D Reset Delay Timing connect a ceramic capacitor to GND for adjusting the reset delay time; leave open if the reset function is not needed 4 GND Ground all pins must be connected to GND 7 RO Reset Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the reset function is not needed 8 SO Sense Output open collector output; internally linked to the output via a 20kΩ pull-up resistor; leave open if the sense comparator is not needed 9, 10, 12 n.c. not connected 11 Q Output block to GND with a capacitor close to the IC terminals, respecting the values given for its capacitance CQ and ESR in the table “Functional Range” on Page 7 13 I Input for compensating line influences, a capacitor to GND close to the IC terminals is recommended 14 SI Sense Input connect the voltage to be monitored; connect to Q if the sense comparator is not needed Data Sheet 7 Rev. 1.1, 2008-10-07 TLE42694 General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Absolute Maximum Ratings 1) -40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. -40 45 V – VQ, VRO, VSO, VD -0.3 7 V – VRADJ IRADJ -0.3 7 V – -10 10 mA – Tj Tstg -40 150 °C – -50 150 °C – Voltage -2 2 kV – Voltage -1 1 kV – Input, Sense Input 4.1.1 VI, VSI Voltage Output, Reset Output, Sense Output, Reset Delay 4.1.2 Voltage Reset Threshold 4.1.3 Voltage 4.1.4 Current Temperature 4.1.5 Junction Temperature 4.1.6 Storage Temperature ESD Susceptibility 4.1.7 4.1.8 Human Body Model (HBM)2) Charged Device Model (CDM) 3) 1) not subject to production test, specified by design 2) ESD HBM Test according to AEC-Q100-002 - JESD22-A114 3) ESD CDM Test according to ESDA ESD-STM5.3.1 Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Integrated protection functions are designed to prevent IC destruction under fault conditions. Fault conditions are considered as outside normal operating range. Protections functions are not designed for continuous repetitive operation. Data Sheet 8 Rev. 1.1, 2008-10-07 TLE42694 General Product Characteristics 4.2 Pos. Functional Range Parameter 4.2.1 Input Voltage 4.2.2 Output Capacitor’s Requirements for Stability 4.2.3 Junction Temperature Symbol VI CQ ESR(CQ) Tj Limit Values Unit Conditions Min. Max. 5.5 45 V – 10 – µF –1) – 3 Ω –2) -40 150 °C – 1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30% 2) relevant ESR value at f = 10 kHz Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. Data Sheet 9 Rev. 1.1, 2008-10-07 TLE42694 General Product Characteristics 4.3 Pos. Thermal Resistance Parameter Symbol Limit Value Min. Typ. Unit Conditions Max. TLE42694G (PG-DSO-8) 4.3.4 Junction to Soldering Point1) RthJSP RthJA – 80 – K/W measured to pin 5 – 113 – K/W 2) 4.3.6 – 170 – K/W Footprint only3) 4.3.7 – 142 – K/W 300mm2 heatsink area on PCB3) 4.3.8 – 136 – K/W 600mm2 heatsink area on PCB3) 4.3.5 Junction to Ambient 1) TLE42694GM (PG-DSO-14) 4.3.9 Junction to Soldering Point1) RthJSP – 27 – K/W measured to group of pins 3, 4, 5, 10, 11, 12 4.3.10 Junction to Ambient1) RthJA – 63 – K/W 2) 4.3.11 – 104 – K/W Footprint only3) 4.3.12 – 73 – K/W 300mm2 heatsink area on PCB3) 4.3.13 – 65 – K/W 600mm2 heatsink area on PCB3) – 10 – K/W measured to pin 5 – 47 – 4.3.16 – 145 – K/W Footprint only3) 4.3.17 – 63 – K/W 300mm2 heatsink area on PCB3) 4.3.18 – 53 – K/W 600mm2 heatsink area on PCB3) TLE42694E (PG-SSOP-14 exposed pad) 4.3.14 4.3.15 Junction to Soldering Point1) Junction to Ambient 1) RthJSP RthJA 2) 1) not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product (Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu). Data Sheet 10 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics 5 Block Description and Electrical Characteristics 5.1 Voltage Regulator The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional Range” on Page 9 have to be maintained. For details see also the typical performance graph “Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 14. As the output capacitor also has to buffer load steps it should be sized according to the application’s needs. An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the component’s terminals. A protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events. These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown in case of overtemperature. In order to avoid excessive power dissipation that could never be handled by the pass element and the package, the maximum output current is decreased at input voltages above VI = 22 V. The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime. The TLE 42694 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC, increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal protection circuit is not operating during reverse polarity conditions. Supply II I Q IQ Regulated Output Voltage Saturation Control Current Limitation CQ CI Temperature Shutdown Blo c k Di a gram _Vol tag eReg ul a to r.v s d Figure 5 Data Sheet LOAD Bandgap Reference GND Voltage Regulator 11 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Electrical Characteristics Voltage Regulator VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 5.1.1 Output Voltage VQ 4.9 5.0 5.1 V 100 µA < IQ < 100 mA 6 V < VI < 18 V 5.1.2 Output Current Limitation 150 5.1.3 Load Regulation steady-state IQ,max ∆VQ,load 200 500 mA -15 – mV VQ = 4.8V IQ = 5 mA to -30 100 mA VI = 6 V 5.1.4 Line Regulation steady-state ∆VQ,line – 10 40 mV 5.1.5 Dropout Voltage1) Vdr – 250 500 mV VI = 6 V to 32 V IQ = 5 mA IQ = 100 mA Vdr = VI - VQ 5.1.6 Overtemperature Shutdown Threshold Tj,sd 151 – 200 °C Tj increasing2) 5.1.7 Overtemperature Shutdown Threshold Hysteresis Tj,sdh – 15 – °C Tj decreasing2) 5.1.8 Power Supply Ripple Rejection2) PSRR – 70 – dB fripple = 100 Hz Vripple = 0.5 Vpp 1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V 2) not subject to production test, specified by design Data Sheet 12 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Typical Performance Characteristics Voltage Regulator Output Voltage VQ versus Junction Temperature Tj Output Current IQ versus Input Voltage VI 01_VQ_TJ.VSD 5,2 02_IQ_VI.VSD 300 V Q = 4.8 V I Q = 5 mA V I = 13.5 V 5,1 I Q,max [mA] 4,9 V Q [V] 5 4,8 200 150 100 T j = 150 °C 50 4,7 0 4,6 -40 0 40 80 120 0 160 10 Power Supply Ripple Rejection PSRR versus ripple frequency fr 4 70 3,5 T j = 25 °C I Q = 10 mA C Q = 10 µF ceramic ∆V Q,line [mV] PSRR [dB] 40 40 30 04_DVQ_DVI.VSD 4,5 80 50 30 Line Regulation ∆VQ,line versus Input Voltage Change ∆VI 03_PSRR_FR.VSD 90 20 V I [V] T j [°C] 60 T j = -40 °C T j = 25 °C 250 T j = 150 °C I Q = 5 mA 3 T j = 25 °C 2,5 2 1,5 20 1 10 0 0,01 T j = -40 °C 0,5 0,1 1 10 100 1000 0 0 f [kHz] 10 20 30 40 V I [V] Data Sheet 13 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Typical Performance Characteristics Voltage Regulator Load Regulation ∆VQ,load versus Output Current Change ∆IQ Output Capacitor Series Resistor ESR(CQ) versus Output Current IQ 05_DVQ_DIQ.VSD 0 06_ESR_IQ.VSD 100 VI = 13.5 V C Q = 10 µF V I = 13.5 V Unstable Region 10 -4 -6 -8 T j = -40 °C T j = 25 °C -10 T j = 150 °C ESR(C Q ) [Ω ] ∆VQ,load [mV] -2 1 Stable Region 0,1 -12 0,01 -14 0 20 40 60 80 0 100 50 100 150 IQ [mA] I Q [mA] Dropout Voltage Vdr versus Output Current IQ Dropout Voltage Vdr versus Junction Temperature Tj 07_VDR_IQ.VSD 300 08_VDR_TJ.VSD 300 I Q = 100 mA 250 T j = 25 °C 200 200 T j = -40 °C V DR [mV] V DR [mV] 250 T j = 150 °C 150 150 100 100 50 50 I Q = 25 mA I Q = 5 mA I Q = 100 µA 0 0 0 20 40 60 80 100 -40 I Q [mA] Data Sheet 0 40 80 120 160 T j [°C] 14 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics 5.2 Current Consumption Electrical Characteristics Current Consumption VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. – 210 280 Unit Conditions 5.2.1 Current Consumption Iq = II - IQ Iq µA 5.2.2 – 240 300 µA 5.2.3 5.2.4 – – 0.7 3.5 1 8 mA mA IQ = 100 µA Tj = 25 °C IQ = 100 µA Tj ≤ 85 °C IQ = 10 mA IQ = 50 mA Data Sheet 15 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Typical Performance Characteristics Current Consumption Current Consumption Iq versus Output Current IQ (IQ low) Current Consumption Iq versus Output Current IQ 09_IQ_IQ_IQLOW.VSD 1,6 V I = 13.5 V T j = 25 °C 1,4 V I = 13.5 V T j = 25 °C 10 8 1 I q [mA] I q [mA] 1,2 10_IQ_IQ.VSD 12 0,8 0,6 6 4 0,4 2 0,2 0 0 0 5 10 15 20 25 0 I Q [mA] 20 40 60 80 100 120 I Q [mA] Current Consumption Iq versus Input Voltage VI 11_IQ_VI.VSD 6 5 I q [mA] 4 R LOAD = 100 Ω 3 2 1 R LOAD = 50 k Ω 0 0 10 20 30 40 V I [V] Data Sheet 16 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics 5.3 Reset Function The reset function provides several features: Output Undervoltage Reset: An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used to reset a microcontroller during low supply voltage. Power-On Reset Delay Time: The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from “low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D charged by the delay capacitor charge current ID,ch starting from VD = 0 V. If the application needs a power-on reset delay time trd different from the value given in Item 5.3.8, the delay capacitor’s value can be derived from the specified values in Item 5.3.8 and the desired power-on delay time: t rd, new C D = ---------------- × 100nF t rd with • • • CD: capacitance of the delay capacitor to be chosen trd,new: desired power-on reset delay time trd: power-on reset delay time specified in this datasheet For a precise calculation also take the delay capacitor’s tolerance into consideration. Reset Reaction Time: The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes: t rr = t rd, int + t rr, d with • • • trr: reset reaction time trr,int: internal reset reaction time trr,d: reset discharge Optional Reset Output Pull-Up Resistor RRO,ext: The Reset Output RO is an open collector output with an integrated pull-up resistor. To improve the EMC behaviour of the component, an external pull-up resistor to the output VQ can be added. In Table “Electrical Characteristics Reset Function” on Page 21 a minimum value for the external resistor RRO,ext is given. Data Sheet 17 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Reset Adjust Function The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting an external voltage divider (RADJ1, RADJ2) at pin RADJ. For selecting the default threshold connect pin RADJ to GND. When dimensioning the voltage divider, take into consideration that there will be an additional current constantly flowing through the resistors. With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows: R ADJ, 1 + R ADJ, 2 V RT, new = ------------------------------------------ × V RADJ, th R ADJ, 2 with • • • VRT,new: the desired new reset switching threshold RADJ1, RADJ2: resistors of the external voltage divider VRADJ,th: reset adjust switching threshold given in Table “Electrical Characteristics Reset Function” on Page 21 Data Sheet 18 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics I Q RRO Int. Supply Control CQ RO ID,ch RRO,ext Reset I RO VDST VRADJ,th VDD optional Supply OR RADJ,1 MicroController RADJ I RADJ GND optional ID,dch D BlockDiagram_ResetAdjust.vsd RADJ,2 GND CD Figure 6 Data Sheet Block Diagram Reset Function 19 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics VI t t < trr,total VQ VRT 1V t t rd VD V DU V DRL t VRO V RO,low t rd trr,total trd t rr,total t rd t rr,total 1V t Thermal Shutdown Figure 7 Data Sheet Input Voltage Dip Undervoltage Spike at output Overload T i mi n g Di a g ra m_ Re se t . vs Timing Diagram Reset 20 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Electrical Characteristics Reset Function VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 4.5 4.65 4.8 V VQ decreasing Output Undervoltage Reset 5.3.1 Default Output Undervoltage Reset VRT Switching Thresholds Output Undervoltage Reset Threshold Adjustment 5.3.2 Reset Adjust Switching Threshold VRADJ,th 1.26 1.35 1.44 V 3.5 V ≤ VQ < 5 V 5.3.3 Reset Adjustment Range1) VRT,range 3.50 – 4.65 V – Reset Output RO 5.3.4 Reset Output Low Voltage VRO,low – 0.1 0.4 V 1 V ≤ VQ ≤ VRT no external RRO,ext 5.3.5 Reset Output Internal Pull-Up Resistor to VQ RRO 10 20 40 kΩ – 5.3.6 Optional Reset Output External Pull-up Resistor to VQ RRO,ext 20 – – kΩ 1 V ≤ VQ ≤ VRT ; VRO ≤ 0.4 V VD trd VDU – – 5 V – 17 28 39 ms CD = 100 nF – 1.8 – V – Reset Delay Timing 5.3.7 Delay Pin Output Voltage 5.3.8 Power On Reset Delay Time 5.3.9 Upper Delay Switching Threshold 5.3.10 Lower Delay Switching Threshold VDL – 0.45 – V – 5.3.11 Delay Capacitor Charge Current ID,ch – 6.5 – µA VD = 1 V 5.3.12 Delay Capacitor Reset Discharge Current ID,dch – 70 – mA VD = 1 V 5.3.13 Delay Capacitor Discharge Time trr,d – 1.9 3 µs Calculated Value: trr,d = CD*(VDU VDL)/ ID,dch CD = 100 nF 5.3.14 Internal Reset Reaction Time – 3 7 µs CD = 0 nF 2) 5.3.15 Reset Reaction Time trr,int trr,total – 4.9 10 µs Calculated Value: trr,total = trr,int + trr,d CD = 100 nF 1) VRT is scaled linearly, in case the Reset Switching Threshold is modified 2) parameter not subject to production test; specified by design Data Sheet 21 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Typical Performance Characteristics Power On Reset Delay Time trd versus Junction Temperature Tj Power On Reset Delay Time trd versus Capacitance CD 12_TRD_TJ.VSD 35 13_trd_CD.vsd 70 T j = 25 °C 30 60 25 50 20 40 t r d [m s] t rd [ms] C D = 100 nF 15 30 10 20 5 10 0 -40 0 40 80 120 0 160 0 T j [°C] Data Sheet 50 100 150 200 250 C D [nF] 22 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics 5.4 Early Warning Function The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be monitored, an undervoltage condition is indicated by setting the comparator’s output to low. Sense Input Voltage VSI, High VSI, Low t Sense Output High Low t AED03049 Figure 8 Sense Timing Diagram Electrical Characteristics Early Warning Function VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions 1.38 V – 1.22 1.28 V – 20 90 160 mV – -1 -0.1 1 µA – Min. Typ. Max. 1.24 1.31 1.16 Sense Comparator Input 5.4.1 Sense Threshold High 5.4.2 Sense Threshold Low 5.4.3 Sense Switching Hysteresis 5.4.4 Sense Input Current Data Sheet VSI,high VSI,low VSI,hy ISI 23 Rev. 1.1, 2008-10-07 TLE42694 Block Description and Electrical Characteristics Electrical Characteristics Early Warning Function VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Min. Typ. Max. Unit Conditions VSI < VSI,low VI > 5.5 V Sense Comparator Output 5.4.5 Sense Output Low Voltage VSO,low – 0.1 0.4 V 5.4.6 Sense Output Internal Pull-Up Resistor to VQ RSO,int 10 20 40 kΩ – 5.4.7 Optional Sense Output External Pull-up Resistor to VQ RSO,ext 20 – – kΩ VI > 5.5 V VSO ≤ 0.4 V no external RSO,ext Data Sheet 24 Rev. 1.1, 2008-10-07 TLE42694 Package Outlines 6 Package Outlines 0.1 2) 0.41+0.1 -0.06 0.2 8 5 1 4 5 -0.2 1) M B 0.19 +0.06 C 8 MAX. 1.27 4 -0.21) 1.75 MAX. 0.175 ±0.07 (1.45) 0.35 x 45˚ 0.64 ±0.25 6 ±0.2 A B 8x 0.2 M C 8x A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01181 Figure 9 PG-DSO-8 You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 25 Dimensions in mm Rev. 1.1, 2008-10-07 TLE42694 Package Outlines 1.75 MAX. C 1) 4 -0.2 B 1.27 0.64 ±0.25 0.1 2) 0.41+0.10 -0.06 6±0.2 0.2 M A B 14x 14 0.2 M C 8 1 7 1) 8.75 -0.2 8˚MAX. 0.19 +0.06 0.175 ±0.07 (1.47) 0.35 x 45˚ A Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Lead width can be 0.61 max. in dambar area GPS01230 Figure 10 Data Sheet PG-DSO-14 26 Rev. 1.1, 2008-10-07 TLE42694 Package Outlines 0.19 +0.06 0.08 C 0.15 M C A-B D 14x 0.64 ±0.25 1 8 1 7 0.2 M D 8x Bottom View 3 ±0.2 A 14 6 ±0.2 D Exposed Diepad B 0.1 C A-B 2x 14 7 8 2.65 ±0.2 0.25 ±0.05 2) 0.1 C D 8˚ MAX. C 0.65 3.9 ±0.11) 1.7 MAX. Stand Off (1.45) 0 ... 0.1 0.35 x 45˚ 4.9 ±0.11) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion PG-SSOP-14-1,-2,-3-PO V02 Figure 11 PG-SSOP-14 exposed pad Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 27 Dimensions in mm Rev. 1.1, 2008-10-07 TLE42694 Revision History 7 Revision History Revision Date Changes 1.1 2008-10-07 package version TLE42694E in PG-SSOP-14 exposed pad and all related information added In “Overview” on Page 2 package graphic for PG-SSOP-14 exposed pad and product name “TLE42694E” added In Chapter 3 “Pin Assignment PG-SSOP-14 exposed pad” on Page 7 and “Pin Definitions and Functions PG-SSOP-14 exposed pad” on Page 7 added In “Thermal Resistance” on Page 10 values for TLE42694E added In “Package Outlines” on Page 25 outlines for TLE4269E added 1.0 Data Sheet 2008-08-25 initial version data sheet 28 Rev. 1.1, 2008-10-07 Edition 2008-10-07 Published by Infineon Technologies AG 81726 Munich, Germany © 2008 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. 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