Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers AD7172-2 Data Sheet FEATURES GENERAL DESCRIPTION Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V Split supply with AVDD1 and AVSS at ±2.5 V or ±1.65 V ADC current: 1.5 mA Temperature range: −40°C to +105°C 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) Serial port interface (SPI), QSPI-, MICROWIRE-, and DSPcompatible The AD7172-2 is an intelligent, low noise, low power, multiplexed, Σ-Δ analog-to-digital converter (ADC) with 2- or 4-channel (fully differential/single-ended) inputs for low bandwidth signals. The AD7172-2 has a maximum channel scan rate of 6.21 kSPS (161 µs) for fully settled data. The output data rates range from 1.25 SPS to 31.25 kSPS. The AD7172-2 integrates key analog and digital signal conditioning blocks to allow users to configure an individual setup for each analog input channel in use via the SPI. Integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. The precision 2.5 V low drift (2 ppm/°C) band gap internal reference (with an output reference buffer) adds embedded functionality to reduce the external component count. The digital filter allows simultaneous 50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The user can switch between different filter options according to the demands of each channel in the application, with further digital processing functions such as offset and gain calibration registers, which are also configurable on a per channel basis. General-purpose inputs/outputs (GPIOs) control external multiplexers synchronous to the ADC conversion timing. APPLICATIONS Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography The specified operating temperature range is −40°C to +105°C. The AD7172-2 is in a 24-lead TSSOP package. Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function only. FUNCTIONAL BLOCK DIAGRAM AVDD1 CROSSPOINT MULTIPLEXER AIN0 REF– REF+ REFOUT AVDD2 REGCAPA AVDD1 AVSS 1.8V LDO BUFFERED PRECISION REFERENCE RAIL-TO-RAIL REFERENCE INPUT BUFFERS AVDD IOVDD REGCAPD INT REF AIN1 DIGITAL FILTER Σ-Δ ADC AIN2 1.8V LDO CS SERIAL INTERFACE AND CONTROL SCLK DIN DOUT/RDY AIN4 AVSS RAIL-TO-RAIL ANALOG INPUT BUFFERS GPIO AND MUX I/O CONTROL SYNC/ERROR XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY AD7172-2 TEMPERATURE SENSOR AVSS GPIO0 GPIO1 XTAL1 XTAL2/CLKIO DGND 12672-001 AIN3 Figure 1. Rev. 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Technical Support www.analog.com AD7172-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 CRC Calculation......................................................................... 42 Applications ....................................................................................... 1 Integrated Functions ...................................................................... 44 General Description ......................................................................... 1 General-Purpose Input/Output................................................ 44 Functional Block Diagram .............................................................. 1 External Multiplexer Control ................................................... 44 Revision History ............................................................................... 3 Delay ............................................................................................ 44 Specifications..................................................................................... 4 16-Bit/24-Bit Conversions......................................................... 44 Timing Characteristics ................................................................ 7 DOUT_RESET ........................................................................... 44 Timing Diagrams.......................................................................... 8 Synchronization .......................................................................... 44 Absolute Maximum Ratings ............................................................ 9 Error Flags ................................................................................... 45 Thermal Resistance ...................................................................... 9 DATA_STAT ............................................................................... 45 ESD Caution .................................................................................. 9 IOSTRENGTH ........................................................................... 46 Pin Configuration and Function Descriptions ........................... 10 Internal Temperature Sensor .................................................... 46 Typical Performance Characteristics ........................................... 12 Grounding and Layout .................................................................. 47 Noise Performance and Resolution .............................................. 19 Register Summary .......................................................................... 48 Getting Started ................................................................................ 20 Register Details ............................................................................... 49 Power Supplies ............................................................................ 21 Communications Register......................................................... 49 Digital Communication............................................................. 21 Status Register ............................................................................. 50 AD7172-2 Reset .......................................................................... 22 ADC Mode Register ................................................................... 51 Configuration Overview ........................................................... 22 Interface Mode Register ............................................................ 52 Circuit Description ......................................................................... 27 Register Check ............................................................................ 53 Buffered Analog Input ............................................................... 27 Data Register ............................................................................... 53 Crosspoint Multiplexer .............................................................. 27 GPIO Configuration Register ................................................... 54 AD7172-2 Reference .................................................................. 28 ID Register................................................................................... 55 Buffered Reference Input ........................................................... 29 Channel Register 0 ..................................................................... 55 Clock Source ............................................................................... 29 Channel Register 1 to Channel Register 3 .............................. 56 Digital Filters ................................................................................... 30 Setup Configuration Register 0 ................................................ 57 Sinc5 + Sinc1 Filter..................................................................... 30 Sinc3 Filter ................................................................................... 30 Setup Configuration Register 1 to Setup Configuration Register 3 ..................................................................................... 57 Single Cycle Settling ................................................................... 31 Filter Configuration Register 0 ................................................. 58 Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 34 Filter Configuration Register 1 to Filter Configuration Register 3 ..................................................................................... 59 Operating Modes ............................................................................ 37 Continuous Conversion Mode ................................................. 37 Continuous Read Mode ............................................................. 38 Single Conversion Mode ........................................................... 39 Standby and Power-Down Modes ............................................ 40 Calibration ................................................................................... 40 Digital Interface .............................................................................. 41 Offset Register 0 ......................................................................... 59 Offset Register 1 to Offset Register 3....................................... 59 Gain Register 0............................................................................ 59 Gain Register 1 to Gain Register 3 ........................................... 59 Outline Dimensions ....................................................................... 60 Ordering Guide .......................................................................... 60 Checksum Protection................................................................. 41 Rev. A | Page 2 of 60 Data Sheet AD7172-2 REVISION HISTORY 3/16—Rev. 0 to Rev. A Changes to Figure 1........................................................................... 1 Change to Figure 17, Figure 18, and Figure 19 ...........................14 Changes to Figure 20 and Figure 21 .............................................14 Changes to Figure 40 and Figure 41 .............................................18 Changes to Power Supplies Section ..............................................20 Changes to Buffered Analog Input Section .................................27 Changes to Figure 65 Caption, Figure 66 Caption, and Figure 67 Caption ............................................................................35 Changes to Figure 69 Caption .......................................................36 Changes to Delay Section ...............................................................44 10/14—Revision 0: Initial Version Rev. A | Page 3 of 60 AD7172-2 Data Sheet SPECIFICATIONS AVDD1 = 3.0 V to 5.5 V, AVDD2 = IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, MCLK = internal master clock = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted. Table 1. Parameter ADC SPEED AND PERFORMANCE Output Data Rate (ODR) No Missing Codes 1 Resolution Noise ACCURACY Integral Nonlinearity (INL) Offset Error 2 Offset Drift Gain Error2 Gain Drift REJECTION Power Supply Rejection Common-Mode Rejection At DC At 50 Hz, 60 Hz1 Normal Mode Rejection1 ANALOG INPUTS Differential Input Range Absolute Voltage Limits1 Input Buffers Disabled Input Buffers Enabled Analog Input Current Input Buffers Disabled Input Current Input Current Drift Input Buffers Enabled Input Current Input Current Drift Crosstalk INTERNAL REFERENCE Output Voltage Initial Accuracy 3 Temperature Coefficient1 0°C to 105°C −40°C to +105°C Reference Load Current, ILOAD Power Supply Rejection Load Regulation Voltage Noise Voltage Noise Density Turn On Settling Time Short-Circuit Current, ISC Test Conditions/Comments Min Excluding sinc3 filter ≥ 15 kSPS See Table 6 and Table 7 See Table 6 and Table 7 Typ 1.25 24 ±2 ±40 ±65 ±5 ±0.2 Internal short Internal short AVDD1 = 5 V AVDD1, AVDD2, VIN = 1 V VIN = 0.1 V Max Unit 31,250 SPS Bits ±5 ppm of FSR µV nV/°C ppm of FSR ppm/°C ±45 ±0.5 98 20 Hz output data rate (postfilter), 50 Hz ± 1 Hz and 60 Hz ± 1 Hz 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (postfilter) External clock, 20 SPS ODR (postfilter) 95 120 71 85 VREF = (REF+) − (REF−) dB dB 90 90 dB dB ±VREF V AVSS − 0.05 AVSS External clock Internal clock (±2.5% clock) 1 kHz input 100 nF external capacitor to AVSS REFOUT, with respect to AVSS REFOUT, TA = 25°C AVDD1 + 0.05 AVDD1 µA/V pA/V/°C nA/V/°C ±5 ±0.1 −120 nA nA/°C dB 2.5 −0.12 +0.12 −10 Rev. A | Page 4 of 60 V V ±6 ±75 ±0.5 ±2 ±3 AVDD1, AVDD2 (line regulation) ∆VOUT/∆ILOAD eN, 0.1 Hz to 10 Hz, 2.5 V reference eN, 1 kHz, 2.5 V reference 100 nF REFOUT capacitor dB 90 50 4.5 215 200 25 ±5 ±10 +10 V % of V ppm/°C ppm/°C mA dB ppm/mA µV rms nV/√Hz µs mA Data Sheet Parameter EXTERNAL REFERENCE INPUTS Differential Input Range Absolute Voltage Limits1 Input Buffers Disabled Input Buffers Enabled REFIN Input Current Input Buffers Disabled Input Current Input Current Drift Input Buffers Enabled Input Current Input Current Drift Normal Mode Rejection1 Common-Mode Rejection TEMPERATURE SENSOR Accuracy Sensitivity BURNOUT CURRENTS Source/Sink Current GPIO (GPIO0, GPIO1) Input Mode Leakage Current1 Floating State Output Capacitance Output High Voltage, VOH1 Output Low Voltage, VOL1 Input High Voltage, VIH1 Input Low Voltage, VIL1 CLOCK Internal Clock Frequency Accuracy Duty Cycle Output Low Voltage, VOL Output High Voltage, VOH Crystal Frequency Startup Time External Clock (CLKIO) Duty Cycle1 LOGIC INPUTS Input High Voltage, VINH1 Input Low Voltage, VINL1 Hysteresis1 AD7172-2 Test Conditions/Comments Min Typ Max Unit VREF = (REF+) − (REF−) 1 2.5 AVDD1 V AVDD1 + 0.05 AVDD1 V V AVSS − 0.05 AVSS ±9 ±100 ±0.75 µA/V pA/V/°C nA/V/°C ±100 ±0.25 nA nA/°C 95 dB After user calibration at 25°C ±2 477 °C µV/K Analog input buffers must be enabled With respect to AVSS ±10 µA External clock Internal clock See the Rejection parameter −10 +10 5 ISOURCE = 200 µA ISINK = 800 µA pF AVSS + 4 AVSS + 0.4 AVSS + 3 AVSS + 0.7 2 −2.5% +2.5% 50 0.4 0.8 × IOVDD 14 30 2 V ≤ IOVDD < 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V 2 V ≤ IOVDD < 2.3 V 2.3 V ≤ IOVDD ≤ 5.5 V IOVDD ≥ 2.7 V IOVDD < 2.7 V 16 10 2 50 16.384 Leakage Currents Rev. A | Page 5 of 60 V V V V MHz % % V V 2.048 70 MHz µs MHz % 0.35 × IOVDD 0.7 0.25 0.2 +10 V V V V V V µA 0.65 × IOVDD 0.7 × IOVDD 0.08 0.04 −10 µA AD7172-2 Parameter LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH1 Output Low Voltage, VOL1 Leakage Current Output Capacitance SYSTEM CALIBRATION1 Full-Scale (FS) Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS Power Supply Voltage AVDD1 to AVSS AVDD2 to AVSS AVSS to DGND IOVDD to DGND IOVDD to AVSS POWER SUPPLY CURRENTS 4 Full Operating Mode AVDD1 Current AVDD1 = 5 V Typical, 5.5 V Maximum AVDD1 = 3.3 V Typical, 3.6 V Maximum1 AVDD2 Current IOVDD Current Standby Mode Standby (LDO On) Power-Down Mode Data Sheet Test Conditions/Comments Min IOVDD ≥ 4.5 V, ISOURCE = 1 mA 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA IOVDD < 2.7 V, ISOURCE = 200 µA IOVDD ≥ 4.5 V, ISINK = 2 mA 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA IOVDD < 2.7 V, ISINK = 400 µA Floating state Floating state 0.8 × IOVDD 0.8 × IOVDD 0.8 × IOVDD Typ Max 0.4 0.4 0.4 +10 −10 10 Unit V V V V V V µA pF 1.05 × FS V 2.1 × FS V V 5.5 5.5 0 5.5 6.35 V V V V V 0.23 0.27 mA 0.4 0.48 mA 1.9 2.35 mA 0.38 0.15 0.19 mA mA 0.33 0.39 mA −1.05 × FS 0.8 × FS 3.0 2 −2.75 2 For AVSS < DGND All outputs unloaded, digital inputs connected to IOVDD or DGND AIN± and REF± buffers disabled; external reference AIN± and REF± buffers disabled; internal reference AIN± and REF± buffers enabled; internal reference Each buffer: AIN± and REF± AIN± and REF± buffers disabled; external reference AIN± and REF± buffers disabled; internal reference AIN± and REF± buffers enabled; internal reference Each buffer: AIN± and REF± External reference Internal reference External clock Internal clock External crystal 1.65 2.1 mA 0.33 1 1.3 0.33 0.61 0.98 1.1 1.45 0.5 0.82 mA mA mA mA mA mA Reference off, total current consumption Reference on, total current consumption Full power-down, LDO, REF± 32 420 1 Rev. A | Page 6 of 60 10 µA µA µA Data Sheet AD7172-2 Parameter POWER DISSIPATION4 Full Operating Mode Test Conditions/Comments Min Unbuffered, external clock and reference; AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V Unbuffered, external clock and reference; all supplies = 5 V Unbuffered, external clock and reference; all supplies = 5.5 V Fully buffered, internal clock and reference (note that REFOUT has no load); AVDD1 = 3.3 V, AVDD2 = 2 V, IOVDD = 2 V Fully buffered, internal clock and reference (note that REFOUT has no load); all supplies = 5 V Fully buffered, internal clock and reference (note that REFOUT has no load); all supplies = 5.5 V Reference off, all supplies = 5 V Reference on, all supplies = 5 V Full power-down, all supplies = 5 V Full power-down, all supplies = 5.5 V Standby Mode Power-Down Mode Typ Max Unit 3.16 mW 7.8 mW 10.3 mW 9.27 mW 19.1 mW 25.4 mW 55 µW mW µW µW 160 2.1 5 This specification is not production tested but is supported by characterization data at initial product release. Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration reduces the gain error to the order of the noise for the programmed output data rate. 3 This specification includes moisture sensitivity level (MSL) preconditioning effects. 4 These specifications are with no load on the REFOUT and digital output pins. 1 2 TIMING CHARACTERISTICS IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted. Table 2. Parameter SCLK t3 t4 READ OPERATION t1 t2 3 t5 t6 t7 5 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX Unit Test Conditions/Comments 1, 2 25 25 ns min ns min SCLK high pulse width SCLK low pulse width 0 15 40 0 12.5 25 2.5 20 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V SCLK active edge to data valid delay 4 IOVDD = 4.75 V to 5.5 V IOVDD = 2 V to 3.6 V Bus relinquish time after CS inactive edge SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high/low 0 8 8 5 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time Sample tested during initial release to ensure compliance. See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 1 2 Rev. A | Page 7 of 60 Data Sheet AD7172-2 TIMING DIAGRAMS CS (I) t6 t1 MSB DOUT/RDY (O) t5 LSB t7 t2 t3 12672-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 2. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) DIN (I) t10 MSB LSB I = INPUT, O = OUTPUT Figure 3. Write Cycle Timing Diagram Rev. A | Page 8 of 60 12672-004 t9 Data Sheet AD7172-2 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for a device soldered on a JEDEC test board for surface-mount packages. Parameter AVDD1, AVDD2 to AVSS AVDD1 to DGND IOVDD to DGND IOVDD to AVSS AVSS to DGND Analog Input Voltage to AVSS Reference Input Voltage to AVSS Digital Input Voltage to DGND Digital Output Voltage to DGND Analog Input/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Soldering, Reflow Temperature ESD Rating (HBM) Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +7.5 V −3.25 V to +0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to AVDD1 + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V 10 mA −40°C to +105°C −65°C to +150°C 150°C 260°C 4 kV Table 4. Thermal Resistance Package Type 24-Lead TSSOP 1-Layer JEDEC Board 2-Layer JEDEC Board ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 9 of 60 θJA Unit 149 81 °C/W °C/W AD7172-2 Data Sheet AIN4 1 24 AIN3 REF– 2 23 AIN2 REF+ 3 22 AIN1 REFOUT 4 21 AIN0 REGCAPA 5 20 GPIO1 19 GPIO0 18 REGCAPD AVSS 6 AD7172-2 TOP VIEW (Not to Scale) AVDD1 7 AVDD2 8 17 DGND XTAL1 9 16 IOVDD XTAL2/CLKIO 10 15 SYNC/ERROR DOUT/RDY 11 14 CS DIN 12 13 SCLK 12672-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 Mnemonic AIN4 REF− REF+ Type 1 AI AI AI 4 5 6 7 8 9 10 REFOUT REGCAPA AVSS AVDD1 AVDD2 XTAL1 XTAL2/CLKIO AO AO P P P AI AI/ DI/O 11 DOUT/RDY DO 12 DIN DI 13 SCLK DI 14 CS DI Description Analog Input 4. Analog Input 4 is selectable through the crosspoint multiplexer. Reference Input Negative Terminal. REF− can span from AVSS to AVDD1 − 1 V. Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+ can span from AVSS + 1 V to AVDD1.The device functions with a reference magnitude from 1 V to AVDD1. Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Analog LDO Regulator Output. Decouple this pin to AVSS using a 1 µF and a 0.1 µF capacitor. Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V. Analog Supply Voltage 1. This voltage is 3.3 V or 5 V ± 10% with respect to AVSS. Analog Supply Voltage 2. This voltage ranges from 2 V to 5.5 V with respect to AVSS. Input 1 for Crystal. Input 2 for Crystal/Clock Input or Output. Based on the CLOCKSEL bits in the ADCMODE register. The following four options are available for selecting the MCLK source: Internal oscillator: no output. Internal oscillator: output to XTAL2/CLKIO. Operates at IOVDD logic level. External clock: input to XTAL2/CLKIO. Input must be at IOVDD logic level. External crystal: connected between XTAL1 and XTAL2/CLKIO. Serial Data Output/Data Ready Output. DOUT/RDY is a dual purpose pin. This pin functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. The data-word/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the DOUT/RDY output is three-stated. When CS is low, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register address (RA) bits of the communications register identifying the appropriate register. Data is clocked in on the rising edge of SCLK. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt triggered input, making the interface suitable for opto-isolated applications. Chip Select Input. This is an active low logic input selects the ADC. CS can select the ADC in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to operate in 3wire mode with the SCLK, DIN, and DOUT pins interfacing with the device. When CS is high, the DOUT/RDY output is three-stated. Rev. A | Page 10 of 60 Data Sheet AD7172-2 Pin No. 15 Mnemonic SYNC/ERROR Type 1 DI/O 16 IOVDD P 17 18 DGND REGCAPD P AO 19 20 21 22 23 24 GPIO0 GPIO1 AIN0 AIN1 AIN2 AIN3 DI/O DI/O AI AI AI AI 1 Description Synchronization Input/Error Input/Output. This pin can be switched between a logic input and a logic output in the GPIOCON register. When synchronization input (SYNC) is enabled, this pin allows synchronization of the digital filters and analog modulators when using multiple AD7172-2 devices. For more information, see the Synchronization section. When the synchronization input is disabled, this pin can be used in one of the following three modes: Active low error input mode: this mode sets the ADC_ERROR bit in the status register. Active low, open-drain error output mode: the status register error bits are mapped to the ERROR output. The SYNC/ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. General-purpose output mode: the status of the pin is controlled by the ERR_DAT bit in the GPIOCON register. The pin is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the GPIOx pins. The pin has an active pull-up in this case. Digital Input/Output Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V. IOVDD is independent of AVDD2. For example, IOVDD can be operated at 3 V when AVDD2 equals 5 V, or vice versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V. Digital Ground. Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND using a 1 µF and a 0.1 µF capacitor. General-Purpose Input/Output 0. The pin is referenced between the AVDD1 and AVSS levels. General-Purpose Input/Output 1. The pin is referenced between the AVDD1 and AVSS levels. Analog Input 0. Analog Input 0 is selectable through the crosspoint multiplexer. Analog Input 1. Analog Input1 is selectable through the crosspoint multiplexer. Analog Input 2. Analog Input 2 is selectable through the crosspoint multiplexer. Analog Input 3. Analog Input 3 is selectable through the crosspoint multiplexer. AI is analog input, AO is analog output, DI/O is bidirectional digital input/output, DO is digital output, DI is digital input, and P is power supply. Rev. A | Page 11 of 60 AD7172-2 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 5 V, AVDD2 = 5 V, IOVDD = 3.3 V, TA = 25°C, unless otherwise noted. 1200 8388492 8388490 1000 800 OCCURENCE 8388486 8388484 400 8388482 200 8388480 0 200 400 600 800 1000 SAMPLE NUMBER 0 12672-205 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 ADC CODE Figure 5. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 1.25 SPS) Figure 8. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 1.25 SPS) 140 8388510 8388505 120 8388500 100 OCCURENCE 8388495 ADC CODE 600 12672-208 ADC CODE 8388488 8388490 8388485 8388480 8388475 80 60 40 8388470 8388505 ADC CODE Figure 9. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 2.6 kSPS) 100 8388530 90 8388520 80 8388510 70 8388490 8388480 60 50 40 8388470 30 8388460 20 8388450 10 0 100 200 300 400 500 600 700 800 900 OCCURENCE 1000 0 ADC CODE Figure 7. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 31.25 kSPS) Figure 10. Histogram (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 31.25 kSPS) Rev. A | Page 12 of 60 12672-210 8388500 8388446 8388449 8388452 8388455 8388458 8388461 8388464 8388467 8388470 8388473 8388476 8388479 8388482 8388485 8388488 8388491 8388494 8388497 8388500 8388503 8388506 8388509 8388512 8388515 8388518 8388521 8388524 8388527 8388530 8388533 OCCURENCE 8388540 12672-207 ADC CODE Figure 6. Noise (Analog Input Buffers Disabled, VREF = 5 V, Output Data Rate = 2.6 kSPS) 8388440 12672-209 8388503 8388501 8388499 8388497 8388495 8388493 8388491 8388489 OCCURENCE 0 8388487 1000 8388485 900 8388483 800 8388481 700 8388479 600 8388477 500 8388475 400 8388473 300 8388471 200 8388469 100 8388467 0 12672-206 8388460 8388465 20 8388465 Data Sheet AD7172-2 8388495 1200 8388493 1000 800 OCCURENCE 8388489 8388487 400 8388485 200 400 600 800 1000 SAMPLE NUMBER 0 12672-211 0 Figure 14. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 1.25 SPS) 8388520 120 8388510 100 8388500 80 OCCURENCE 8388490 8388480 60 40 8388470 20 100 200 300 400 500 600 700 800 900 1000 OCCURENCE 0 12672-212 0 ADC CODE Figure 12. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 2.6 kSPS) 12672-215 ADC CODE 8388482 8388484 8388486 8388488 8388490 8388492 8388494 ADC CODE Figure 11. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 1.25 SPS) 8388460 12672-214 200 8388483 8388481 600 8388462 8388464 8388466 8388468 8388470 8388472 8388474 8388476 8388478 8388480 8388482 8388484 8388486 8388488 8388490 8388492 8388494 8388496 8388498 8388500 8388502 8388504 8388506 8388508 8388510 8388512 8388514 8388516 ADC CODE 8388491 Figure 15. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 2.6 kSPS) 8388560 120 8388540 100 80 OCCURENCE 8388500 8388480 8388460 60 40 8388440 8388542 ADC CODE Figure 13. Noise (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 31.25 kSPS) Figure 16. Histogram (Analog Input Buffers Enabled, VREF = 5 V, Output Data Rate = 31.25 kSPS) Rev. A | Page 13 of 60 12672-216 8388534 8388526 0 8388518 1000 8388510 900 8388502 800 8388494 700 8388486 600 8388478 500 OCCURENCE 8388470 400 8388462 300 8388454 200 8388446 100 8388438 0 8388430 8388400 8388422 20 8388420 12672-213 ADC CODE 8388520 AD7172-2 Data Sheet 20 –60 ANALOG INPUT BUFFERS OFF ANALOG INPUT BUFFERS ON 18 –70 16 –80 –90 PSRR (dB) 12 10 8 –100 –110 FREQUENCY (MHz) 100 1k 10k 100k 1M 10M 100M Figure 20. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency 0 6 –20 INTERNAL 2.5V REFERENCE, ANALOG INPUT BUFFERS OFF INTERNAL 2.5V REFERENCE, ANALOG INPUT BUFFERS ON EXTERNAL 2.5V REFERENCE, ANALOG INPUT BUFFERS OFF EXT-CRYSTAL BUFFERS OFF EXT-CRYSTAL BUFFERS ON EXT CLK BUFFERS OFF EXT CLK BUFFERS ON 4 –40 2 INL (ppm/FS) CMRR (dB) 10 VIN FREQUENCY (Hz) Figure 17. Noise vs. External Master Clock Frequency, Analog Input Buffers On and Off –60 –80 0 –2 –100 –4 –140 –6 –5 1 10 100 1k 10k 100k 1M 12672-224 –120 VIN FREQUENCY (Hz) EXTERNAL 2.5V REFERENCE, ANALOG INPUT BUFFERS ON EXTERNAL 5V REFERENCE, ANALOG INPUT BUFFERS OFF EXTERNAL 5V REFERENCE, ANALOG INPUT BUFFERS ON –4 –3 –2 –1 0 1 2 3 4 5 VIN (V) Figure 21. Integral Nonlinearity (INL) vs. VIN (Differential Input) Figure 18. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, Output Data Rate = 31.25 kSPS) 35 0 –20 30 –40 25 OCCURENCE –60 CMRR (dB) 1 12672-218 1801000 1601000 1401000 1001000 1201000 –150 801000 0 601000 –140 401000 2 201000 –130 1000 4 12672-226 –120 6 12672-227 NOISE (V rms) 14 –80 –100 –120 20 15 10 –140 20 30 40 50 VIN FREQUENCY (Hz) 60 70 0 12672-225 –180 10 Figure 19. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency (VIN = 0.1 V, 10 Hz to 70 Hz, Output Data Rate = 20 SPS, Enhanced Filter) 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 INL (ppm) 12672-228 5 –160 Figure 22. INL Distribution Histogram (Differential Input, Analog Input Buffers Enabled, VREF = 2.5 V External, 100 Units) Rev. A | Page 14 of 60 Data Sheet AD7172-2 40 5.0 AIN BUFFERS ON AIN BUFFERS OFF 4.5 35 4.0 30 INL (ppm) OCCURENCE 3.5 25 20 15 3.0 2.5 2.0 1.5 10 1.0 5 INL (ppm) 0 –40 –30 –20 –10 0 Figure 23. INL Distribution Histogram (Differential Input, Analog Input Buffers Disabled, VREF = 2.5 V External, 100 Units) 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 12672-232 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 12672-229 0 0.5 Figure 26. INL vs. Temperature (Differential Input, VREF = 2.5 V External) 35 50 45 30 40 25 OCCURENCE OCCURENCE 35 30 25 20 15 20 15 10 10 5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 INL (ppm) 0 12672-230 0 Figure 24. INL Distribution Histogram (Analog Input Buffers Enabled, Differential Input, VREF = 5 V External, 100 Units) 1.996 1.997 1.998 1.999 2.00 2.001 2.002 2.003 FREQUENCY (MHz) 12672-233 5 Figure 27. Internal Oscillator Frequency Distribution Histogram (100 Units) 40 2.01 35 2.00 FREQUENCY (Hz) OCCURENCE 30 25 20 15 1.99 1.98 1.97 10 1.96 0 0.2 0.4 0.6 0.8 INL (ppm) 1.0 1.2 1.4 Figure 25. INL Distribution Histogram (Analog Input Buffers Disabled, Differential Input, VREF = 5 V External, 100 Units) Rev. A | Page 15 of 60 1.95 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 28. Internal Oscillator Frequency vs. Temperature | 12672-234 0 12672-231 5 AD7172-2 Data Sheet 25 0.0015 0.0010 20 OCCURENCE 0 –0.0005 15 10 TEMPERATURE (°C) 0 –8 –7 –6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6 12672-238 10 20 30 40 50 60 70 80 90 100 12672-235 –0.0015 –40 –30 –20 –10 0 5 6 12672-239 5 –0.0010 0.5 12672-240 ERROR (V) 0.0005 GAIN ERROR (ppm of FSR) Figure 29. Absolute Reference Error vs. Temperature Figure 32. Gain Error Distribution Histogram (Analog Input Buffers Enabled, 100 Units) 30 25 25 20 OCCURENCE OCCURENCE 20 15 10 10 5 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 OFFSET (µV) 12672-236 5 0 15 0 –7 30 10 25 OCCURENCE 12 8 6 –3 –2 –1 0 1 2 3 4 20 15 4 10 2 5 12672-237 OCCURENCE 35 OFFSET DRIFT (nV/°C) –4 Figure 33. Gain Error Distribution Histogram (Analog Input Buffers Disabled, 100 Units) 14 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 –5 GAIN ERROR (ppm of FSR) Figure 30. Offset Error Distribution Histogram (Internal Short, 100 Units) 0 –6 Figure 31. Offset Error Drift Distribution Histogram (Internal Short, 100 Units) 0 –0.2 –0.1 0 0.1 0.2 0.3 0.4 GAIN DRIFT (ppm/°C) Figure 34. Gain Drift Distribution Histogram (Analog Input Buffers Enabled, 100 Units) Rev. A | Page 16 of 60 Data Sheet AD7172-2 30 700 25 500 CURRENT (µA) 15 10 400 300 200 5 100 0 0.05 0.10 0.15 0.20 0.25 GAIN DRIFT (ppm/°C) 0 –40 –30 –20 –10 0 12672-241 –0.05 TEMPERATURE (°C) Figure 37. Current Consumption vs. Temperature (Standby Mode) Figure 35. Gain Drift Distribution Histogram (Analog Input Buffers Disabled, 100 Units) 7 18 ALL BUFFERS ENABLED ALL BUFFERS DISABLED 6 10 20 30 40 50 60 70 80 90 100 12672-243 OCCURENCE 20 0 REFERENCE ENABLED REFERENCE DISABLED 600 16 14 OCCURENCE 12 4 3 10 8 6 2 4 1 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 0 –2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 TEMPERATURE DELTA (°C) Figure 38. Temperature Sensor Distribution Histogram (Uncalibrated, 100 Units) Figure 36. Current Consumption vs. Temperature (Continuous Conversion Mode) Rev. A | Page 17 of 60 1.2 12672-244 2 12672-242 CURRENT (mA) 5 AD7172-2 Data Sheet 45 15 40 10 35 CURRENT (nA) 30 OCCURENCE AIN+ = AVDD1 – 0.2 V AIN– = AVSS + 0.2 V AIN+ = AVDD1 AIN– = AVSS 25 20 15 5 0 –5 10 9.5 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 CURRENT (µA) 12672-245 0 Figure 39. Burnout Current Distribution Histogram (100 Units) 10 –5 12672-246 –10 –5.00 –4.62 –4.29 –3.96 –3.63 –3.30 –2.97 –2.64 –2.31 –1.98 –1.65 –1.32 –990.00m –660.00m –330.00m 0 330.00m 660.00m 990.00m 1.32 1.65 1.98 2.31 2.64 2.97 3.30 3.63 3.96 4.29 4.62 5.00 INPUT CURRENT (nA) 0 INPUT VOLTAGE (V) 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) Figure 41. Analog Input Current vs. Temperature –40°C, AIN– –40°C, AIN+ +25°C, AIN– +25°C, AIN+ +85°C, AIN– +85°C, AIN+ +105°C, AIN– +105°C, AIN– 5 –15 –40 –30 –20 –10 0 Figure 40. Analog Input Current vs. Input Voltage (VCM = 2.5 V) Rev. A | Page 18 of 60 12672-247 –10 5 Data Sheet AD7172-2 NOISE PERFORMANCE AND RESOLUTION Table 6 and Table 7 show the rms noise, peak-to-peak noise, effective resolution, and the noise free (peak-to-peak) resolution of the AD7172-2 for various output data rates and filters. The numbers given are for the bipolar input range with an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the peak-to-peak resolution is calculated based on the peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. Table 6. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using Sinc5 + Sinc1 Filter (Default) 1 Output Data Rate (SPS) Input Buffers Disabled 31,250 15,625 10,417 1007 59.52 49.68 16.63 1.25 Input Buffers Enabled 31,250 15,625 10,417 1007 59.52 49.68 16.63 1.25 1 RMS Noise (µV rms) Effective Resolution (Bits) Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits) 8.2 7.0 6.0 2.2 0.48 0.47 0.25 0.088 20.2 20.4 20.7 22.2 24 24 24 24 66 52 45 15 3.2 3.1 1.6 0.32 17.2 17.5 17.8 19.3 21.6 21.6 22.6 24 9.5 8.2 7.1 2.6 0.62 0.53 0.32 0.089 20 20.2 20.4 21.9 24 24 24 24 74 63 53 16 3.6 3.3 1.7 0.35 17 17.3 17.5 19.3 21.4 21.5 22.2 24 Selected rates only, 1000 samples. Table 7. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate Using Sinc3 Filter 1 Output Data Rate (SPS) Input Buffers Disabled 31,250 15,625 10,417 1008 59.98 50 16.67 1.25 Input Buffers Enabled 31,250 15,625 10,417 1008 59.98 50 16.67 1.25 1 RMS Noise (µV rms) Effective Resolution (Bits) Peak-to-Peak Noise (µV p-p) Peak-to-Peak Resolution (Bits) 211 27.2 7.9 1.6 0.38 0.35 0.21 0.054 15.5 18.5 20.3 22.6 24 24 24 24 1600 205 57 11 2.5 2.3 1.1 0.27 12.5 15.6 17.4 19.8 21.9 22 23.1 24 212 27.7 8.5 1.8 0.45 0.44 0.24 0.073 15.5 18.5 20.2 22.4 24 24 24 24 1600 210 63 13 2.8 2.5 1.2 0.29 12.5 15.5 17.3 19.6 21.8 22 23 24 Selected rates only, 1000 samples. Rev. A | Page 19 of 60 AD7172-2 Data Sheet GETTING STARTED The AD7172-2 includes a precision, 2.5 V, low drift (±2 ppm/°C) band gap internal reference. This reference can be used for the ADC conversions, reducing the external component count. Alternatively, the reference can be output to the REFOUT pin to be used as a low noise biasing voltage for external circuitry. An example of this is using the REFOUT signal to set the input common mode for an external amplifier. The AD7172-2 offers the user a fast settling, high resolution, multiplexed ADC with high levels of configurability, including the following features: • • • Two fully differential or four single-ended analog inputs. A crosspoint multiplexer selects any analog input combination as the input signals to be converted, routing them to the modulator positive or negative input. True rail-to-rail buffered analog and reference inputs. Fully differential input or single-ended input relative to any analog input. Per channel configurability—up to four different setups can be defined. A separate setup can be mapped to each of the channels. Each setup allows the user to configure whether the buffers are enabled or disabled, gain and offset correction, filter type, output data rate, and reference source selection (internal or external). The AD7172-2 includes two separate linear regulator blocks for both the analog and digital circuitry. The analog LDO regulator regulates the AVDD2 supply to 1.8 V, supplying the ADC core. The user can tie the AVDD1 and AVDD2 supplies together for easiest connection. If there is already a clean analog supply rail in the system in the range of 2 V (minimum) to 5.5 V (maximum), the user can also choose to connect this supply to the AVDD2 input, allowing lower power dissipation. GENERAL-PURPOSE I/O 0 AND GENERAL-PURPOSE I/O 1 OUTPUT HIGH = AVDDx GPIO1 GPIO0 OUTPUT LOW = AVSS 16MHz 21 AIN0 22 AIN1 19 20 GPIO0 GPIO1 CX2 CX1 OPTIONAL EXTERNAL CRYSTAL CIRCUITRY CAPACITORS XTAL1 9 XTAL2/CLKIO 10 DOUT/RDY 11 DOUT/RDY DIN DIN 12 23 SCLK SCLK 13 AIN2 CS CS 14 24 AIN3 1 AIN4 SYNC/ERROR 15 SYNC/ERROR AD7172-2 VIN 2 4.7µF 0.1µF 1 3 TP NC VIN REGCAPD 18 0.1µF TP 5 8 1µF AVDD1 AVDD1 7 VOUT 6 TRIM 0.1µF DGND 17 NC 7 GND IOVDD IOVDD 16 ADR445BRZ 4 CLKIN OPTIONAL EXTERNAL CLOCK INPUT 3 0.1µF 4.7µF 2.5V REFERENCE OUTPUT 0.1µF REF+ 0.1µF 0.1µF AVDD2 AVDD2 8 2 REF– 4 REFOUT 0.1µF REGCAPA 5 0.1µF AVSS 1µF 6 0.1µF Figure 42. Typical Connection Diagram Rev. A | Page 20 of 60 12672-051 • • Data Sheet AD7172-2 The ADM660 and ADP7182 generate a clean negative rail for AVSS in the bipolar configuration to provide optimal converter performance. 5V INPUT • • POWER SUPPLIES The AD7172-2 has three independent power supply pins: AVDD1, AVDD2, and IOVDD. AVDD1 powers the crosspoint multiplexer and integrated analog and reference input buffers. AVDD1 is referenced to AVSS, and AVDD1 − AVSS = 3.3 V or 5 V. AVDD1 and AVSS can be a single 3.3 V or 5 V supply or a ±1.65 V or ±2.5 V split supply. The split supply operation allows true bipolar inputs. When using split supplies, consider the absolute maximum ratings (see the Absolute Maximum Ratings section). AVDD2 powers the internal 1.8 V analog LDO regulator. This regulator powers the ADC core. AVDD2 is referenced to AVSS, and AVDD2 to AVSS can range from 5.5 V (maximum) to 2 V (minimum). IOVDD powers the internal 1.8 V digital LDO regulator. This regulator powers the digital logic of the ADC. IOVDD sets the voltage levels for the SPI interface of the ADC. IOVDD is referenced to DGND, and IOVDD to DGND can vary from 5.5 V (maximum) to 2 V (minimum). There is no specific requirement for a power supply sequence on the AD7172-2. When all power supplies are stable, a device reset is required; see the AD7172-2 Reset section for details on how to reset the device. Recommended Linear Regulators 12V INPUT ADP7118 5V: AVDD1 ADP7118 3.3V: AVDD2/IOVDD LDO LDO 12672-100 The ADP7118 provides positive supply rails to the AD7172-2, creating either a single 5 V, 3.3 V, or dual AVDD1/IOVDD, depending on the required supply configuration. The ADP7118 can operate from input voltages up to 20 V. ADP7118 +3.3V: IOVDD ADM660 LDO –5V ADP7182 –2.5V: AVSS LDO Figure 44. Bipolar AD7172-2 Supply Rails Table 8. Recommended Power Management Devices Product ADP7118 ADP7182 ADM660 Description 20 V, 200 mA, low noise, CMOS LDO regulator −28 V, −200 mA, low noise, linear regulator CMOS switched-capacitor voltage converter DIGITAL COMMUNICATION The AD7172-2 has a 3- or 4-wire SPI interface that is compatible with QSPI™, MICROWIRE, and DSPs. The interface operates in SPI Mode 3 and can be operated with CS tied low. In SPI Mode 3, the SCLK idles high, the falling edge of SCLK is the drive edge, and the rising edge of SCLK is the sample edge. This means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. DRIVE EDGE SAMPLE EDGE 12672-052 • Fast scanning of analog input channels using the internal multiplexer Fast scanning of analog input channels using an external multiplexer with automatic control from the GPIOs High resolution at lower speeds in either channel scanning or ADC per channel applications Single ADC per channel: the fast low latency output allows further application specific filtering in an external microcontroller, DSP, or field programmable gate array (FPGA) +2.5V: AVDD1/AVDD2 LDO LDO The AD7172-2 can be used across a wide variety of applications, providing high resolution and accuracy. A sample of these scenarios is as follows: • ADP7118 12672-101 The linear regulator for the digital IOVDD supply regulates the input voltage applied at the IOVDD pin to 1.8 V for the internal digital filtering. The serial interface signals always operate from the IOVDD supply seen at the pin; if 3.3 V is applied to the IOVDD pin, the interface logic inputs and outputs operate at this level. Figure 45. SPI Mode 3 SCLK Edges Accessing the ADC Register Map The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. On power-up or after a reset, the digital interface defaults to a state where it is expecting a write to the communications register; therefore, all communication begins by writing to the communications register. The data written to the communications register determines which register is being accessed and if the next operation is a read or write. The register address bits (RA, Bits[5:0] in Register 0x00) determine the specific register to which the read or write operation applies. When the read or write operation to the selected register is complete, the interface returns to the default state, where it expects a write operation to the communications register. Figure 46 and Figure 47 illustrate writing to and reading from a register by first writing the 8-bit command to the communications register, followed by the data for that register. Figure 43. Single Supply Linear Regulator Rev. A | Page 21 of 60 AD7172-2 Data Sheet 8-BIT COMMAND 8 BITS, 16 BITS, OR 24 BITS OF DATA CONFIGURATION OVERVIEW After power-on or reset, the AD7172-2 default configuration is as follows: CS • CMD DIN DATA • 12672-053 SCLK Figure 46. Writing to a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DIN Is Dependent on the Register Selected) 8-BIT COMMAND • 8 BITS, 16 BITS, 24 BITS, OR 32 BITS OUTPUT • CS DOUT/RDY SCLK Note that only a few of the register setting options are shown; this list is just an example. For full register information, see the Register Details section. CMD Figure 48 shows an overview of the suggested flow for changing the ADC configuration, divided into the following three blocks: DATA 12672-054 DIN • Channel configuration: CH0 is enabled, AIN0 is selected as the positive input, and AIN1 is selected as the negative input. Setup 0 is selected. Setup configuration: The internal reference and the analog input buffers are disabled. The reference input buffers are also disabled. An external reference on the REF± pins is selected. Filter configuration: The sinc5 + sinc1 filter is selected and the maximum output data rate of 31.25 kSPS is selected. ADC mode: Continuous conversion mode and the internal oscillator are enabled. Interface mode: CRC and data + status output are disabled. Figure 47. Reading from a Register (8-Bit Command with Register Address Followed by Data of 8, 16, or 24 Bits; Data Length on DOUT/RDY Is Dependent on the Register Selected) Reading the ID register is the recommended method for verifying correct communication with the device. The ID register is a read only register and contains the value 0x00DX for the AD7172-2. The communications register and the ID register details are described in Table 9 and Table 10. AD7172-2 RESET After a power-up cycle and when the power supplies are stable, a device reset is required. In situations where interface synchronization is lost, a device reset is also required. A write operation of at least 64 serial clock cycles with DIN high returns the ADC to the default state by resetting the entire device, including the register contents. Alternatively, if CS is being used with the digital interface, returning CS high sets the digital interface to the default state and halts any serial interface operation. • • • Channel configuration (see Box A in Figure 48) Setup configuration (see Box B in Figure 48) ADC mode and interface mode configuration (see Box C in Figure 48) Channel Configuration The AD7172-2 has four independent channels and four independent setups. The user can select any of the analog input pairs on any channel, as well as any of the four setups for any channel, giving the user full flexibility in the channel configuration. This also allows per channel configuration when using differential inputs and single-ended inputs because each channel can have a dedicated setup. Channel Registers The channel registers select which of the five analog input pins (AIN0 to AIN4) are used as either the positive analog input (AIN+) or the negative analog input (AIN−) for that channel. This register also contains a channel enable/disable bit and the setup selection bits, which select which of the four available setups to use for this channel. When the AD7172-2 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from Channel 0 to Channel 3. If a channel is disabled, it is skipped by the sequencer. Details of the channel register for Channel 0 are shown in Table 11. Rev. A | Page 22 of 60 AD7172-2 A CHANNEL CONFIGURATION SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL SELECT ONE OF 4 SETUPS FOR ADC CHANNEL B SETUP CONFIGURATION 4 POSSIBLE ADC SETUPS SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE C ADC MODE AND INTERFACE MODE CONFIGURATION SELECT ADC OPERATING MODE, CLOCK SOURCE, ENABLE CRC, DATA + STATUS, AND MORE 12672-044 Data Sheet Figure 48. Suggested ADC Configuration Flow Table 9. Communications Register Reg. 0x00 Name COMMS Bits [7:0] Bit 7 WEN Bit 6 R/W Bit 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset 0x00 RW W Bit 2 Bit 1 Bit 0 Reset 0x00DX RW R RA Table 10. ID Register Reg. 0x07 Name ID Bits [15:8] [7:0] Bit 4 Bit 3 ID[15:8] ID[7:0] Table 11. Channel 0 Register Reg. 0x10 Name CH0 Bits [15:8] [7:0] Bit 7 CH_EN0 Bit 6 Bit 5 Bit 4 Reserved SETUP_SEL0 AINPOS0[2:0] Bit 3 Rev. A | Page 23 of 60 Bit 2 Reserved AINNEG0 Bit 1 Bit 0 AINPOS0[4:3] Reset 0x8001 RW RW AD7172-2 Data Sheet ADC Setups Setup Configuration Registers The AD7172-2 has four independent setups. Each setup consists of the following four registers: The setup configuration registers allow the user to select the output coding of the ADC by selecting between bipolar mode and unipolar mode. In bipolar mode, the ADC accepts negative differential input voltages, and the output coding is offset binary. In unipolar mode, the ADC accepts only positive differential voltages, and the coding is straight binary. In either case, the input voltage must be within the AVDD1/AVSS supply voltages. The user can select the reference source using these registers. Three options are available: an internal 2.5 V reference, an external reference connected between the REF+ and REF− pins, or AVDD1 − AVSS. The analog input and reference input buffers can also be enabled or disabled using these registers. • • • • Setup configuration register Filter configuration register Gain register Offset register For example, Setup 0 consists of Setup Configuration Register 0, Filter Configuration Register 0, Gain Register 0, and Offset Register 0. Figure 49 shows the grouping of these registers. The setup is selectable from the channel registers (see the Channel Configuration section), which allows each channel to be assigned to one of four separate setups. Table 12 through Table 15 show the four registers that are associated with Setup 0. This structure is repeated for Setup 1 to Setup 3. Filter Configuration Registers The filter configuration registers select which digital filter is used at the output of the ADC modulator. The order of the filter and the output data rate is selected by setting the bits in these registers. For more information, see the Digital Filters section. FILTER CONFIG REGISTERS SETUP CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz AND 60Hz 12672-045 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL Figure 49. ADC Setup Register Grouping Table 12. Setup Configuration Register 0 Reg. 0x20 Name Bits Bit 7 Bit 6 SETUPCON0 [15:8] Reserved [7:0] BURNOUT_EN0 Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− 0x1000 REF_SEL0 Reserved RW RW Table 13. Filter Configuration Register 0 Reg. 0x28 Name FILTCON0 Bits Bit 7 [15:8] SINC3_MAP0 [7:0] Reserved Bit 6 Bit 5 Bit 4 Reserved ORDER0 Bit 3 Bit 2 ENHFILTEN0 ODR0 Bit 1 Bit 0 ENHFILT0 Reset 0x0500 RW RW Table 14. Gain Register 0 Reg. 0x38 Name GAIN0 Bits [23:0] Bits[23:0] GAIN0[23:0] Reset RW 0x5XXXX0 RW Bits[23:0] OFFSET0[23:0] Reset RW 0x800000 RW Table 15. Offset Register 0 Reg. 0x30 Name OFFSET0 Bits [23:0] Rev. A | Page 24 of 60 Data Sheet AD7172-2 Gain Registers ADC Mode and Interface Mode Configuration The gain registers are 24-bit registers that hold the gain calibration coefficient for the ADC. The gain registers are read/write registers. These registers are configured at power-on with factory calibrated coefficients. Therefore, every device has different default coefficients. The default value is automatically overwritten if the user initiates a system full-scale calibration or writes to a gain register. For more information on calibration, see the Operating Modes section. The ADC mode register and the interface mode register configure the core peripherals for use by the AD7172-2 and the mode for the digital interface. ADC Mode Register The ADC mode register primarily sets the conversion mode of the ADC to either continuous or single conversion. The user can also select the standby and power-down modes, as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference enable bits. The reference select bits are contained in the setup configuration registers (see the ADC Setups section for more information). The details of this register are shown in Table 16. Offset Registers The offset registers hold the offset calibration coefficient for the ADC. The power-on reset value of the offset registers is 0x800000. The offset registers are 24-bit read/write registers. The power-on reset value is automatically overwritten if the user initiates an internal or system zero-scale calibration or if the user writes to an offset register. Interface Mode Register The interface mode register configures the digital interface operation. This register allows the user to control data-word length, CRC enable, data plus status read, and continuous read mode. The details of this register are shown in Table 17. For more information, see the Digital Interface section. Table 16. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 HIDE_DELAY Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0x0000 RW RW Reset 0x0000 RW RW Table 17. Interface Mode Register Reg. 0x02 Name IFMODE Bits [15:8] [7:0] Bit 7 CONTREAD Bit 6 Reserved DATA_STAT Bit 5 REG_CHECK Bit 4 ALT_SYNC Reserved Bit 3 Bit 2 Bit 1 IOSTRENGTH Reserved CRC_EN Reserved Rev. A | Page 25 of 60 Bit 0 DOUT_RESET WL16 AD7172-2 Data Sheet Understanding Configuration Flexibility The most straightforward implementation of the AD7172-2 is to use two differential inputs with adjacent analog inputs and run both of them with the same setup, gain correction, and offset correction register. In this case, the user selects the following differential inputs: AIN0/AIN1 and AIN2/AIN3. In Figure 50, the registers shown in black font must be programmed for such a configuration. The registers that are shown in gray font are redundant in this configuration. Programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. An alternative way to implement these two fully differential inputs is to take advantage of the four available setups. Motivation for doing this includes having a different speed/noise requirement on each of the differential inputs, or there may be a specific offset or gain correction for each channel. Figure 51 shows how each of the differential inputs can use a separate setup, allowing full flexibility in the configuration of each channel. CHANNEL REGISTERS SETUP CONFIG REGISTERS Figure 52 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. In this example, one differential input and two single-ended inputs are required. The single-ended inputs are the AIN2/AIN4 and AIN3/AIN4 combinations. The differential input pair is AIN0/ AIN1 and uses Setup 0. The two single-ended input pairs are set up as diagnostics; therefore, they use a separate setup from the differential input but share a setup between them, Setup 1. Given that two setups are selected, SETUPCON0 and SETUPCON1 are programmed as required, and FILTCON0 and FILTCON1 are programmed as desired. Optional gain and offset correction can be employed on a per setup basis by programming GAIN0 and GAIN1 and OFFSET0 and OFFSET1. In the example shown in Figure 52, the CH0 to CH2 registers are used. Setting the MSB in each of these registers, the CH_EN0 to CH_EN2 bits enable the three combinations via the crosspoint mux. When the AD7172-2 converts, the sequencer transitions in ascending sequential order from CH0 to CH1 to CH2 before looping back to CH0 to repeat the sequence. FILTER CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS AIN0 CH0 0x10 SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 AIN1 CH1 0x11 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 AIN2 CH2 0x12 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 AIN3 CH3 0x13 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SELECT ANALOG INPUT PAIRS ENABLE THE CHANNEL SELECT SETUP 0 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC5 + SINC1 SINC3 SINC3 MAP 12672-046 AIN4 ENHANCED 50Hz AND 60Hz Figure 50. Two Fully Differential Inputs, Both Using a Single Setup (SETUPCON0; FILTCON0; GAIN0; OFFSET0) CHANNEL REGISTERS FILTER CONFIG REGISTERS SETUP CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS AIN0 CH0 0x10 SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 AIN1 CH1 0x11 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 AIN2 CH2 0x12 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 AIN3 CH3 0x13 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SINC5 + SINC1 SINC3 SINC3 MAP GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) 12672-047 SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL AIN4 ENHANCED 50Hz AND 60Hz Figure 51. Two Fully Differential Inputs with a Setup per Channel FILTER CONFIG REGISTERS SETUP CONFIG REGISTERS GAIN REGISTERS* OFFSET REGISTERS AIN0 CH0 0x10 SETUPCON0 0x20 FILTCON0 0x28 GAIN0 0x38 OFFSET0 0x30 AIN1 CH1 0x11 SETUPCON1 0x21 FILTCON1 0x29 GAIN1 0x39 OFFSET1 0x31 AIN2 CH2 0x12 SETUPCON2 0x22 FILTCON2 0x2A GAIN2 0x3A OFFSET2 0x32 AIN3 CH3 0x13 SETUPCON3 0x23 FILTCON3 0x2B GAIN3 0x3B OFFSET3 0x33 AIN4 SELECT ANALOG INPUT PARTS ENABLE THE CHANNEL SELECT SETUP SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS GAIN CORRECTION OFFSET CORRECTION OPTIONALLY OPTIONALLY PROGRAMMED PROGRAMMED PER SETUP AS REQUIRED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz AND 60Hz Figure 52. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups Rev. A | Page 26 of 60 12672-048 CHANNEL REGISTERS AD7172-2 Data Sheet CIRCUIT DESCRIPTION AVDD1 BUFFERED ANALOG INPUT The AD7172-2 has true rail-to-rail, integrated, precision unity gain buffers on both ADC analog inputs. The buffers provide high input impedance with only 5 nA typical input current, allowing high impedance sources connect directly to the analog inputs. The buffers fully drive the internal ADC switch capacitor sampling network, simplifying the analog front-end circuit requirements while consuming a very efficient 0.38 mA typical per buffer. Each analog input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. The 1/f noise profile of the ADC and buffer combined is shown in Figure 53. 0 AIN0 AVSS AVDD1 +IN AIN1 Ø1 CS1 AVSS Ø2 AVDD1 Ø2 AIN2 CS2 AVSS –IN AVDD1 Ø1 AIN3 AVSS AVDD1 AIN4 –100 12672-056 AMPLITUDE (dB) –50 AVSS Figure 54. Simplified Analog Input Circuit –150 The CS1 and CS2 capacitors have a magnitude in the order of a number of picofarads each. This capacitance is the combination of both the sampling capacitance and the parasitic capacitance. –200 1 10 100 1k 10k FREQUENCY (Hz) 12672-255 Fully Differential Inputs –250 0.1 Figure 53. Shorted Input FFT (Analog Input Buffers Enabled) The analog input buffers do not suffer from linearity degradation when operating at the rails, unlike many discrete amplifiers. When operating at or close to the AVDD1 and AVSS supply rails, there is an increase in input current. This increase is most notable at higher temperatures. Figure 40 and Figure 41 show the input current for various conditions. With the analog input buffers disabled, the average input current to the AD7172-2 changes linearly with the differential input voltage at a rate of 6 µA/V. CROSSPOINT MULTIPLEXER There are five analog input pins: AIN0, AIN1, AIN2, AIN3, and AIN4. Each of these pins connects to the internal crosspoint multiplexer. The crosspoint multiplexer enables any of these inputs to be configured as an input pair, either single-ended or fully differential. The AD7172-2 can have up to four active channels. When more than one channel is enabled, the channels are automatically sequenced in order from the lowest enabled channel number to the highest enabled channel number. The output of the multiplexer is connected to the input of the integrated true rail-to-rail buffers. These buffers can be bypassed and the multiplexer output can directly connect to the switched-capacitor input of the ADC. The simplified analog input circuit is shown in Figure 54. Because the AIN0 to AIN4 analog inputs are connected to a crosspoint multiplexer, any combination of signals can create an analog input pair. This allows the user to select two fully differential inputs or four single-ended inputs. If two fully differential input paths are connected to the AD7172-2, using AIN0/AIN1 as one differential input pair and AIN2/AIN3 as the second differential input pair is recommended. This is due to the relative locations of these pins to each other. Decouple all analog inputs to AVSS. Single-Ended Inputs The user can also choose to measure four different single-ended analog inputs. In this case, each of the analog inputs is converted as the difference between the single-ended input to be measured and a set analog input common pin. Because there is a crosspoint multiplexer, the user can set any of the analog inputs as the common pin. An example of such a scenario is to connect the AIN4 pin to AVSS or to the REFOUT voltage (that is, AVSS + 2.5 V) and select this input when configuring the crosspoint multiplexer. When using the AD7172-2 with single-ended inputs, the INL specification is degraded. Rev. A | Page 27 of 60 AD7172-2 Data Sheet AD7172-2 REFERENCE The REF− pin is connected directly to the AVSS potential. On power-up of the AD7172-2, the internal reference is disabled by default. The external reference is used by default instead of the internal reference. When an external reference is used instead of the internal reference to supply the AD7172-2, attention must be paid to the output of the REFOUT pin. If the internal reference is not being used elsewhere in the application, ensure that the REFOUT pin is not hardwired to AVSS because this draws a large current on power-up. The internal reference is controlled by the REF_EN bit (Bit 15) in the ADC mode register, which is shown in Table 19. The AD7172-2 offers the user the option of either supplying an external reference to the REF+ and REF− pins of the device or allowing the use of the internal 2.5 V, low noise, low drift reference. Select the reference source to be used by the analog input by setting the REF_SELx bits (Bits[5:4]) in the setup configuration registers appropriately. The structure of the Setup Configuration 0 register is shown in Table 18. The AD7172-2 defaults on power-up to use the external reference inputs, REF+ and REF−. External Reference The AD7172-2 has a fully differential reference input applied through the REF+ and REF− pins. Standard low noise, low drift voltage references, such as the ADR445, ADR444, and ADR441, are recommended for use. Apply the external reference to the AD7172-2 reference pins as shown in Figure 55. Decouple the output of any external reference to AVSS. As shown in Figure 55, the ADR445 output is decoupled with a 0.1 µF capacitor at the output for stability purposes. The output is then connected to a 4.7 µF capacitor, which acts as a reservoir for any dynamic charge required by the ADC, and followed by a 0.1 µF decoupling capacitor at the REF+ input. This capacitor is placed as close as possible to the REF+ and REF− pins. Internal Reference The AD7172-2 includes a low noise, low drift voltage reference. The internal reference has a 2.5 V output. The internal reference is output on the REFOUT pin after the REF_EN bit in the ADC mode register is set and is decoupled to AVSS with a 0.1 µF capacitor. The AD7172-2 internal reference is disabled by default on power-up. The REFOUT signal is buffered before being output to the pin. The signal can be used externally in the circuit as a common-mode source for external amplifier configurations. AD7172-2 3V TO 18V ADR4412 0.1µF 1 0.1µF 5V VREF 1 1 3 REF+ 2 REF– 0.1µF 4.7µF 1 1 1ALL DECOUPLING IS TO AVSS. 2ANY OF THE ADR44x FAMILY OF 12672-159 REFERENCES CAN BE USED. THE ADR441 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY NEEDED FOR AVDD1 TO POWER THE REFERENCE VIN. Figure 55. External Reference (ADR441) Connected to AD7172-2 Reference Pins Table 18. Setup Configuration 0 Register Reg. 0x20 Name SETUPCON0 Bits [15:8] [7:0] Bit 7 Bit 6 Reserved BURNOUT_EN0 Reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BI_UNIPOLAR0 REFBUF0+ REFBUF0− AINBUF0+ AINBUF0− REF_SEL0 Reserved Reset RW 0x1000 RW Table 19. ADC Mode Register Reg. 0x01 Name ADCMODE Bits [15:8] [7:0] Bit 7 REF_EN Reserved Bit 6 HIDE_DELAY Bit 5 SING_CYC Mode Bit 4 Bit 3 Reserved Rev. A | Page 28 of 60 Bit 2 CLOCKSEL Bit 1 Bit 0 Delay Reserved Reset 0x0000 RW RW Data Sheet AD7172-2 BUFFERED REFERENCE INPUT External Crystal The AD7172-2 has true rail-to-rail, integrated, precision unitygain buffers on both ADC reference inputs. The buffers provide the benefit of providing high input impedance and allowing high impedance external sources to be directly connected to the reference inputs. The integrated reference buffers can fully drive the internal reference switch capacitor sampling network, simplifying the reference circuit requirements while consuming a very efficient 0.38 mA typical per buffer. Each reference input buffer amplifier is fully chopped, meaning that it minimizes the offset error drift and 1/f noise of the buffer. When using an external reference, such as the ADR445, ADR444, or ADR441, these buffers are not required because these references, with proper decoupling, can drive the reference inputs directly. If higher precision, lower jitter clock sources are required, the AD7172-2 can use an external crystal to generate the master clock. The crystal is connected to the XTAL1 and XTAL2/CLKIO pins. A recommended crystal for use is the FA-20H, a 16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom that is available in a surfacemount package. As shown in Figure 56, insert two capacitors from the traces connecting the crystal to the XTAL1 and XTAL2/ CLKIO pins. These capacitors allow circuit tuning. Connect these capacitors to the DGND pin. The value for these capacitors depends on the length and capacitance of the trace connections between the crystal and the XTAL1 and XTAL2/CLKIO pins. Therefore, the values of these capacitors differ depending on the printed circuit board (PCB) layout and the crystal employed. CLOCK SOURCE AD7172-2 CX1 The AD7172-2 uses a nominal master clock of 2 MHz. The AD7172-2 can source the sampling clock from one of three sources: • XTAL2/CLKIO 10 CX2 Internal oscillator External crystal (use a 16 MHz crystal, automatically divided internally to set the 2 MHz clock) External clock source 1 1DECOUPLE TO DGND. 12672-160 • • 1 XTAL1 9 Figure 56. External Crystal Connections All output data rates listed in the data sheet relate to a master clock rate of 2 MHz. Using a lower clock frequency from, for instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates for rejection of 50 Hz and 60 Hz, use a 2 MHz clock. The source of the master clock is selected by setting the CLOCKSEL bits (Bits[3:2]) in the ADC mode register as shown in Table 19. The default operation on power-up and reset of the AD7172-2 is to operate with the internal oscillator. It is possible to fine tune the output data rate and filter notch at low output data rates using the SINC3_MAPx bit (Bit 7 of the FILTCONx registers). See the Sinc3 Filter section for more information. Internal Oscillator The internal oscillator runs at 16 MHz, is internally divided down to 2 MHz for the modulator, and can be used as the ADC master clock. The internal oscillator is the default clock source for the AD7172-2 and is specified with an accuracy of ±2.5%. There is an option to allow the internal clock oscillator to be output on the XTAL2/CLKIO pin. The clock output is driven to the IOVDD logic level. Use of this option can affect the dc performance of the AD7172-2 due to the disturbance introduced by the output driver. The extent to which the performance is affected depends on the IOVDD voltage supply. Higher IOVDD voltages create a wider logic output swing from the driver and affect performance to a greater extent. This effect is further exaggerated if the IOSTRENGTH bit is set at higher IOVDD levels (see Table 29 for more information). The external crystal circuitry can be sensitive to the SCLK edges, depending on SCLK frequency, IOVDD voltage, crystal circuitry layout, and the crystal used. During crystal startup, any disturbances caused by the SLCK edges can cause double edges on the crystal input, resulting in invalid conversions until the crystal voltage has reached a high enough level such that any interference from the SCLK edges is insufficient to cause double clocking. This double clocking can be avoided by ensuring that the crystal circuitry has reached a sufficient voltage level after startup before applying any SCLK. Due to the nature of the crystal circuitry, it is recommended that empirical testing of the circuit be performed under the required conditions, with the final PCB layout and crystal, to ensure correct operation. External Clock The AD7172-2 can also use an externally supplied clock. In systems where this is desirable, the external clock is routed to the XTAL2/CLKIO pin. In this configuration, the XTAL2/ CLKIO pin accepts the externally sourced clock and routes it to the modulator. The logic level of this clock input is defined by the voltage applied to the IOVDD pin. Rev. A | Page 29 of 60 AD7172-2 Data Sheet DIGITAL FILTERS SINC3 FILTER The AD7172-2 has three flexible filter options to allow optimization of noise, settling time, and rejection: The sinc3 filter achieves the best single-channel noise performance at lower rates and is, therefore, most suitable for single-channel applications. The sinc3 filter always has a settling time equal to Sinc5 + sinc1 filter Sinc3 filter Enhanced 50 Hz and 60 Hz rejection filters SINC1 Figure 59 shows the frequency domain filter response for the sinc3 filter. The sinc3 filter has good roll-off over frequency and has wide notches for good notch frequency rejection. 50Hz AND 60Hz POSTFILTER SINC3 0 –10 –20 Figure 57. Digital Filter Block Diagram The filter and output data rate are configured by setting the appropriate bits in the filter configuration register for the selected setup. Each channel can use a different setup and, therefore, a different filter and output data rate. See the Register Details section for more information. FILTER GAIN (dB) –30 –80 –100 The sinc5 + sinc1 filter is targeted at multiplexed applications and achieves single cycle settling at output data rates of 2.6 kSPS and less. The sinc5 block output is fixed at the maximum rate of 31.25 kSPS, and the sinc1 block output data rate can be varied to control the final ADC output data rate. Figure 58 shows the frequency domain response of the sinc5 + sinc1 filter at a 50 SPS output data rate. The sinc5 + sinc1 filter has a slow roll-off over frequency and narrow notches. 0 –20 FILTER GAIN (dB) –60 –70 –90 SINC5 + SINC1 FILTER –40 –110 –120 0 50 100 150 FREQUENCY (Hz) Figure 59. Sinc3 Filter Response The output data rates with the accompanying settling time and rms noise for the sinc3 filter are shown in Table 22 and Table 23. It is possible to fine tune the output data rate for the sinc3 filter by setting the SINC3_MAPx bit in the filter configuration registers. If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter. All other options are eliminated. The data rate when on a single channel can be calculated using the following equation: Output Data Rate = –60 f MOD 32 × FILTCONx[14:0] where: fMOD is the modulator rate (MCLK/2) and is equal to 1 MHz. FILTCONx[14:0] are the contents on the filter configuration registers excluding the MSB. –80 0 50 100 150 FREQUENCY (Hz) 12672-059 –100 –120 –40 –50 12672-060 SINC5 tSETTLE = 3/Output Data Rate 12672-058 • • • Figure 58. Sinc5 + Sinc1 Filter Response at 50 SPS ODR For example, an output data rate of 50 SPS can be achieved with SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a value of 625. The output data rates with the accompanying settling time and rms noise for the sinc5 + sinc1 filter are shown in Table 20 and Table 21. Rev. A | Page 30 of 60 Data Sheet AD7172-2 The AD7172-2 can be configured by setting the SING_CYC bit in the ADC mode register so that only fully settled data is output, thus effectively putting the ADC into a single cycle settling mode. This mode achieves single cycle settling by reducing the output data rate to be equal to the settling time of the ADC for the selected output data rate. This bit has no effect with the sinc5 + sinc1 filter at output data rates of 2.6 kSPS and less. Figure 61 shows the same step on the analog input but with single cycle settling enabled. The analog input requires at least a single cycle for the output to be fully settled. The output data rate, as indicated by the RDY signal, is now reduced to equal the settling time of the filter at the selected output data rate. ANALOG INPUT FULLY SETTLED ADC OUTPUT Figure 60 shows a step on the analog input with single cycle settling mode disabled and the sinc3 filter selected. The analog input requires at least three cycles after the step change for the output to reach the final settled value. 12672-062 SINGLE CYCLE SETTLING tSETTLE Figure 61. Step Input with Single Cycle Settling ANALOG INPUT ADC OUTPUT 12672-061 FULLY SETTLED 1/ODR Figure 60. Step Input Without Single Cycle Settling Table 20. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Disabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 31,250 15,625 10,417 5208 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 6211 5181 4444 3115 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Settling Time1 161 µs 193 µs 225 µs 321 µs 385 µs 993 µs 1.99 ms 2.63 ms 4.99 ms 9.99 ms 16.8 ms 20.13 ms 49.98 ms 60.13 ms 100 ms 200 ms 400 ms 800 ms Notch Frequency (Hz) 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 Noise (µV rms) 8.2 7.0 6.0 4.5 3.9 2.2 1.5 1.3 0.88 0.64 0.48 0.47 0.27 0.25 0.2 0.14 0.091 0.088 Effective Resolution with 5 V Reference (Bits) 20.2 20.4 20.7 21.1 21.3 22.2 22.6 22.9 23.3 23.8 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 66 52 45 33 29 15 10 9.1 6.1 4.2 3.2 3.1 1.7 1.6 1.1 0.75 0.32 0.32 Peak-to-Peak Resolution with 5 V Reference (Bits) 17.2 17.5 17.8 18.2 18.4 19.3 19.9 20.1 20.6 21.2 21.6 21.6 22.4 22.6 23.1 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 31 of 60 AD7172-2 Data Sheet Table 21. Output Data Rate, Settling Time, and Noise Using the Sinc5 + Sinc1 Filter with Input Buffers Enabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 31,250 15,625 10,417 5208 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 6211 5181 4444 3115 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Settling Time1 161 µs 193 µs 225 µs 321 µs 385 µs 993 µs 1.99 ms 2.63 ms 4.99 ms 9.99 ms 16.8 ms 20.13 ms 49.98 ms 60.13 ms 100 ms 200 ms 400 ms 800 ms Notch Frequency (Hz) 31,250 15,625 10,417 5208 3906 1157 539 401 206 102 59.98 50 20 16.67 10 5 2.5 1.25 Noise (µV rms) 9.5 8.2 7.1 5.3 4.7 2.6 1.8 1.6 1.1 0.75 0.62 0.53 0.32 0.32 0.25 0.18 0.11 0.089 Effective Resolution with 5 V Reference (Bits) 20 20.2 20.4 20.9 21 21.9 22.4 22.6 23.1 23.6 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 74 63 53 39 29 16 12 11 7.5 5.1 3.6 3.3 1.8 1.7 1.2 0.83 0.35 0.35 Peak-to-Peak Resolution with 5 V Reference (Bits) 17 17.3 17.5 18 18.4 19.3 19.7 19.8 20.3 21 21.4 21.5 22.4 22.5 23 23.5 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 32 of 60 Data Sheet AD7172-2 Table 22. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Disabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 31,250 15,625 10,417 5,208 2,604 1,008 504 400.6 200.3 100.2 59.98 50 20.01 16.67 10 5 2.5 1.25 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 10,309 5,181 3,460 1,733 867.3 335.9 167.98 133.5 66.67 33.39 19.99 16.67 6.67 5.56 3.33 1.67 0.83 0.42 Settling Time1 97 µs 193 µs 289 µs 577 µs 1.15 ms 2.98 ms 5.95 ms 7.49 ms 14.98 ms 29.95 ms 50.02 ms 60 ms 149.95 ms 180 ms 300 ms 600 ms 1.2 sec 2.4 sec Notch Frequency (Hz) 31,250 15,625 10,417 5,208 2,604 1,008 504 400.6 200.3 100.2 59.98 50 20.01 16.67 10 5 2.5 1.25 Noise (µV rms) 211 27.2 7.9 3.7 2.5 1.6 1.1 0.99 0.68 0.47 0.38 0.35 0.21 0.21 0.18 0.18 0.16 0.054 Effective Resolution with 5 V Reference (Bits) 15.5 18.5 20.3 21.4 21.9 22.6 23.1 23.3 23.7 24 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 1600 205 57 27 17 11 7.5 6.7 4.6 3.1 2.5 2.3 1.2 1.1 0.83 0.56 0.41 0.27 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.5 15.6 17.4 18.5 19.2 19.8 20.3 20.5 21 21.6 21.9 22 23 23.1 23.5 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Table 23. Output Data Rate, Settling Time, and Noise Using the Sinc3 Filter with Input Buffers Enabled Default Output Data Rate (SPS); SING_CYC = 0 and Single Channel Enabled 1 31,250 15,625 10,417 5,208 2,604 1,008 504 400.6 200.3 100.2 59.98 50 20.01 16.67 10 5 2.5 1.25 1 2 Output Data Rate (SPS/Channel); SING_CYC = 1 or with Multiple Channels Enabled1 10,309 5,181 3,460 1,733 867.3 335.9 167.98 133.5 66.67 33.39 19.99 16.67 6.67 5.56 3.33 1.67 0.83 0.42 Settling Time1 97 µs 193 µs 289 µs 577 µs 1.15 ms 2.98 ms 5.95 ms 7.49 ms 14.98 ms 29.95 ms 50.02 ms 60 ms 149.95 ms 180 ms 300 ms 600 ms 1.2 sec 2.4 sec Notch Frequency (Hz) 31,250 15,625 10,417 5,208 2,604 1,008 504 400.6 200.3 100.2 59.98 50 20.01 16.67 10 5 2.5 1.25 Noise (µV rms) 212 27.7 8.5 4.3 3.0 1.8 1.3 1.2 0.82 0.57 0.45 0.44 0.26 0.24 0.19 0.12 0.098 0.073 Effective Resolution with 5 V Reference (Bits) 15.5 18.5 20.2 21.2 21.7 22.4 22.9 23 23.5 24 24 24 24 24 24 24 24 24 Noise (µV p-p) 2 1600 210 63 28 20 13 8.9 8.2 5.6 3.8 2.8 2.5 1.3 1.2 0.91 0.62 0.45 0.29 Peak-to-Peak Resolution with 5 V Reference (Bits) 12.5 15.5 17.3 18.4 19 19.6 20.1 20.2 20.8 21.3 21.8 22 22.9 23 23.4 24 24 24 The settling time is rounded to the nearest microsecond. This is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time. 1000 samples. Rev. A | Page 33 of 60 AD7172-2 Data Sheet ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS The enhanced filters provide rejection of 50 Hz and 60 Hz simultaneously and allow the user to trade off settling time and rejection. These filters can operate up to 27.27 SPS or can reject up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference. These filters are realized operated by postfiltering the output of the sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must be selected when using the enhanced filters to achieve the specified settling time and noise performance. Table 24 shows the output data rates with the accompanying settling time, rejection, and rms noise. Figure 62 to Figure 69 show the frequency domain plots of the responses from the enhanced filters. Table 24. Enhanced Filters Output Data Rate, Noise, Settling Time, and Rejection Using the Enhanced Filters Output Data Rate (SPS) 27.27 25 20 16.667 1 Settling Time (ms) 36.67 40.0 50.0 60.0 Simultaneous Rejection of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB) 1 47 62 85 90 Noise (µV rms) 0.45 0.44 0.41 0.417 Master clock = 2.00 MHz. Rev. A | Page 34 of 60 Peak-to-Peak Resolution (Bits) 21.4 21.4 21.7 21.7 Comments See Figure 62 and Figure 65 See Figure 63 and Figure 66 See Figure 64 and Figure 67 See Figure 68 and Figure 69 AD7172-2 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –70 –50 –60 –70 –80 –80 –90 –90 100 200 300 400 500 600 FREQUENCY (Hz) –100 40 Figure 62. 27.27 SPS ODR, 36.67 ms Settling Time –10 –20 –20 –30 –30 FILTER GAIN (dB) –10 –40 –50 –60 –70 –70 –90 500 600 FREQUENCY (Hz) –100 40 12672-065 400 –10 –20 –20 –30 –30 FILTER GAIN (dB) –10 –40 –50 –60 –70 500 FREQUENCY (Hz) 70 –70 –90 400 65 –60 –80 300 60 –50 –90 200 55 –40 –80 100 50 Figure 66. 25 SPS ODR, 40 ms Settling Time (40 – 70 Hz) 0 600 12672-067 FILTER GAIN (dB) Figure 63. 25 SPS ODR, 40 ms Settling Time 0 45 FREQUENCY (Hz) 0 –100 70 –60 –80 300 65 –50 –90 200 60 –40 –80 100 55 Figure 65. 27.27 SPS ODR, 36.67 ms Settling Time (40 – 70 Hz) 0 0 50 FREQUENCY (Hz) 0 –100 45 12672-066 0 Figure 64. 20 SPS ODR, 50 ms Settling Time –100 40 45 50 55 60 65 FREQUENCY (Hz) Figure 67. 20 SPS ODR, 50 ms Settling Time (40 – 70 Hz) Rev. A | Page 35 of 60 70 12672-068 –100 FILTER GAIN (dB) –40 12672-064 FILTER GAIN (dB) 0 12672-063 FILTER GAIN (dB) Data Sheet Data Sheet 0 –10 –10 –20 –20 –30 –30 –40 –50 –60 –70 –40 –50 –60 –70 –80 –80 –90 –90 –100 0 100 200 300 400 500 FREQUENCY (Hz) 600 Figure 68. 16.667 SPS ODR, 60 ms Settling Time –100 40 45 50 55 60 65 70 FREQUENCY (Hz) Figure 69. 16.667 SPS ODR, 60 ms Settling Time (40 – 70 Hz) Rev. A | Page 36 of 60 12672-070 FILTER GAIN (dB) 0 12672-069 FILTER GAIN (dB) AD7172-2 Data Sheet AD7172-2 OPERATING MODES The AD7172-2 has a number of operating modes that can be set from the ADC mode register and interface mode register (see Table 28 and Table 29). These modes are as follows and are described in the following sections: The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion; otherwise, the new conversion word is lost. • • • • • • When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all the channels have been converted, the sequence starts again with the first channel. The channels are converted in order from the lowest enabled channel to the highest enabled channel. The data register is updated as soon as each conversion is available. The RDY output pulses low each time a conversion is available. The user can then read the conversion while the ADC converts the next enabled channel. Continuous conversion mode Continuous read mode Single conversion mode Standby mode Power-down mode Calibration modes (three) CONTINUOUS CONVERSION MODE Continuous conversion is the default power-up mode. The AD7172-2 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the RDY output also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, the DOUT/RDY pin goes high. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. The status register indicates the channel to which the conversion corresponds. CS DOUT/RDY 0x44 0x44 DATA DATA 12672-071 DIN SCLK Figure 70. Continuous Conversion Mode Rev. A | Page 37 of 60 AD7172-2 Data Sheet CONTINUOUS READ MODE To enable continuous read mode, set the CONTREAD bit in the interface mode register. When this bit is set, the only serial interface operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register command (0x44) while the RDY output is low. Alternatively, apply a software reset, that is, 64 SCLKs with CS = 0 and DIN = 1. This resets the ADC and all register contents. These are the only commands that the interface recognizes after it is placed in continuous read mode. Hold DIN low in continuous read mode until an instruction is to be written to the device. In continuous read mode, it is not required to write to the communications register before reading ADC data; apply only the required number of SCLKs after the RDY output goes low to indicate the end of a conversion. When the conversion is read, the RDY output returns high until the next conversion is available. In this mode, the data can be read only once. The user must also ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion or if insufficient serial clocks are applied to the AD7172-2 to read the data-word, the serial output register is reset shortly before the next conversion is complete, and the new conversion is placed in the output serial register. The ADC must be configured for continuous conversion mode to use continuous read mode. If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if the DATA_STAT bit is set in the interface mode register. The status register indicates the channel to which the conversion corresponds. CS DOUT/RDY 0x02 0x0080 DATA DATA DATA 12672-072 DIN SCLK Figure 71. Continuous Read Mode Rev. A | Page 38 of 60 Data Sheet AD7172-2 SINGLE CONVERSION MODE In single conversion mode, the AD7172-2 performs a single conversion and is placed in standby mode after the conversion is complete. The RDY output goes low to indicate the completion of a conversion. When the data-word has been read from the data register, the RDY output goes high. The data register can be read several times, if required, even when the RDY output has gone high. If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, the RDY output goes high and remains high until a valid conversion is available and CS is low. When the conversion is available, the RDY output goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. When the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to standby mode. If the DATA_STAT bit in the interface mode register is set to 1, the contents of the status register, along with the conversion, are output each time the data register is read. The two LSBs of the status register indicate the channel to which the conversion corresponds. CS DIN 0x01 0x8010 0x44 DATA 12672-073 DOUT/RDY SCLK Figure 72. Single Conversion Mode Rev. A | Page 39 of 60 AD7172-2 Data Sheet STANDBY AND POWER-DOWN MODES In standby mode, most blocks are powered down. The LDO regulators remain active so that the registers maintain their contents. The internal reference remains active if enabled, and the crystal oscillator remains active if selected. To power down the reference in standby mode, set the REF_EN bit in the ADC mode register to 0. To power down the clock in standby mode, set the CLOCKSEL bits in the ADC mode register to 00 (internal oscillator). In power-down mode, all blocks are powered down, including the LDO regulators. All registers lose their contents, and the GPIO outputs are placed in three-state. To prevent accidental entry to power-down mode, the ADC must first be placed in standby mode. Exiting power-down mode requires 64 SCLKs with CS = 0 and DIN = 1, that is, a serial interface reset. A delay of 500 µs is recommended before issuing a subsequent serial interface command to allow the LDO regulator to power up. CALIBRATION The AD7172-2 allows a two-point calibration to be performed to eliminate any offset and gain errors. Three calibration modes eliminate these offset and gain errors on a per setup basis: • • • Internal zero-scale calibration mode System zero-scale calibration mode System full-scale calibration mode There is no internal full-scale calibration mode because this is calibrated in the factory at the time of production. Only one channel can be active during calibration. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The default value of the offset register is 0x800000, and the nominal value of the gain register is 0x555555. The calibration range of the ADC gain is from 0.4 × VREF to 1.05 × VREF. The following equations show the calculations that are used. In unipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: 0.75 × V IN Gain Data = × 2 23 − (Offset − 0 x 800000) × ×2 V REF 0 x 400000 In bipolar mode, the ideal relationship—that is, not taking into account the ADC gain error and offset error—is as follows: To start a calibration, write the relevant value to the mode bits (Bits[6:4]) in the ADC mode register. The DOUT/RDY pin and the RDY bit (Bit 7) in the status register go high when the calibration initiates. When the calibration is complete, the contents of the corresponding offset or gain register are updated, the RDY bit in the status register is reset, the RDY output pin returns low (if CS is low), and the AD7172-2 reverts to standby mode. During an internal offset calibration, the selected positive analog input pin is disconnected, and both modulator inputs are connected internally to the selected negative analog input pin. Therefore, it is necessary to ensure that the voltage on the selected negative analog input pin does not exceed the allowed limits and is free from excessive noise and interference. However, for system calibrations, the system zero-scale (offset) and system full-scale (gain) voltages must be applied to the ADC pins before initiating the calibration modes. As a result, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. An offset calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the RDY output to determine the end of a calibration via a polling sequence or an interrupt-driven routine. All calibrations require a time equal to the settling time of the selected filter and output data rate to be completed. An internal offset calibration, system zero-scale calibration, and system full-scale calibration can be performed at any output data rate. Using lower output data rates results in better calibration accuracy and is accurate for all output data rates. A new offset calibration is required for a given channel if the reference source for that channel is changed. The offset error is typically ±40 µV, and an offset calibration reduces the offset error to the order of the noise. The gain error is factory calibrated at ambient temperature. Following this calibration, the gain error is typically ±35 ppm of FSR. The AD7172-2 provides the user with access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write calibration coefficients. A read or write of the offset and gain registers can be performed at any time except during an internal or self calibration. 0.75 × VIN Gain + 0 x 800000 × 2 23 – (Offset – 0 x 800000 ) × Data = 0 x 400000 V REF Rev. A | Page 40 of 60 Data Sheet AD7172-2 DIGITAL INTERFACE Figure 2 and Figure 3 show timing diagrams for interfacing to the AD7172-2 using CS to decode the device. Figure 2 shows the timing for a read operation from the AD7172-2, and Figure 3 shows the timing for a write operation to the AD7172-2. It is possible to read from the data register several times even though the RDY output returns high after the first read operation. However, ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY pins communicate with the AD7172-2. The end of the conversion can also be monitored using the RDY bit in the status register. The AD7172-2 can be reset by writing 64 SCLKs with CS = 0 and DIN = 1. A reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, allow a period of 500 µs before addressing the serial interface. CHECKSUM PROTECTION The AD7172-2 has a checksum mode that can improve interface robustness. Using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. If an error occurs during a register write, the CRC_ERROR bit is set in the status register. However, to ensure that the register write was successful, read back the register and verify the checksum. x8 + x2 + x + 1 During read operations, the user can select between this polynomial and a simpler exclusive or (XOR) function. The XOR function requires less time to process on the host microcontroller than the polynomial-based checksum. The CRC_EN bits in the interface mode register enable and disable the checksum and allow the user to select between the polynomial check and the simple XOR check. The checksum is appended to the end of each read and write transaction. The checksum calculation for the write transaction is calculated using the 8-bit command word and the 8-bit to 24-bit data. For a read transaction, the checksum is calculated using the command word and the 8-bit to 32-bit data output. Figure 73 and Figure 74 show SPI write and read transactions, respectively. 8-BIT COMMAND UP TO 24-BIT INPUT 8-BIT CRC CS DATA CRC CS DIN SCLK 12672-074 The DOUT/RDY pin also functions as a data ready signal, with the output going low if CS is low when a new data-word is available in the data register. The RDY output is reset high when a read operation from the data register is complete. The RDY output also goes high before updating the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. Take care to avoid reading from the data register when the RDY output is about to go low. The best method to ensure that no data read occurs is to always monitor the RDY output; start reading the data register as soon as the RDY output goes low; and ensure a sufficient SCLK rate, such that the read is completed before the next conversion result. CS selects a device. CS can decode the AD7172-2 in systems where several components are connected to the serial bus. For CRC checksum calculations during a write operation, the following polynomial is always used: Figure 73. SPI Write Transaction with CRC 8-BIT COMMAND UP TO 32-BIT OUTPUT 8-BIT CRC DATA CRC CS DIN DOUT/ RDY CMD SCLK 12672-075 The programmable functions of the AD7172-2 are controlled via the SPI. The serial interface of the AD7172-2 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN input transfers data into the on-chip registers, and the DOUT output accesses data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN input or on DOUT output) occur with respect to the SCLK signal. Figure 74. SPI Read Transaction with CRC If checksum protection is enabled when continuous read mode is active, an implied read data command of 0x44 before every data transmission must be accounted for when calculating the checksum value. This implied read data command ensures a nonzero checksum value even if the ADC data equals 0x000000. Rev. A | Page 41 of 60 AD7172-2 Data Sheet CRC CALCULATION Polynomial The checksum, which is eight bits wide, is generated using the polynomial x8 + x2 + x + 1 To generate the checksum, the data is left shifted by eight bits to create a number ending in eight Logic 0s. The polynomial is aligned so that the MSB is adjacent to the leftmost Logic 1 of the data. An XOR function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that the MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure is repeated. This process repeats until the original data is reduced to a value less than the polynomial. This is the 8-bit checksum. Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) An example of generating the 8-bit checksum using the polynomial based checksum is as follows: Initial value 011001010100001100100001 x +x +x+1 8 2 01100101010000110010000100000000 left shifted eight bits = polynomial 100000111 100100100000110010000100000000 100000111 XOR result polynomial 100011000110010000100000000 100000111 XOR result polynomial 11111110010000100000000 100000111 XOR result polynomial value 1111101110000100000000 100000111 XOR result polynomial value 111100000000100000000 100000111 XOR result polynomial value 11100111000100000000 100000111 XOR result polynomial value 1100100100100000000 100000111 XOR result polynomial value 100101010100000000 100000111 XOR result polynomial value 101101100000000 100000111 1101011000000 100000111 101010110000 100000111 1010001000 100000111 10000110 XOR result polynomial value XOR result polynomial value XOR result polynomial value XOR result polynomial value checksum = 0x86 Rev. A | Page 42 of 60 Data Sheet AD7172-2 XOR Calculation The checksum, which is 8 bits wide, is generated by splitting the data into bytes and then performing an XOR of the bytes. Example of an XOR Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data) Using the previous example, divide into three bytes: 0x65, 0x43, and 0x21 01100101 0x65 01000011 0x43 00100110 XOR result 00100001 0x21 00000111 CRC Rev. A | Page 43 of 60 AD7172-2 Data Sheet INTEGRATED FUNCTIONS The AD7172-2 has integrated functions that improve the usefulness of a number of applications as well as serve diagnostic purposes in safety conscious applications. GENERAL-PURPOSE INPUT/OUTPUT The AD7172-2 has two general-purpose digital input/output pins: GPIO0 and GPIO1. They are enabled using the IP_EN0/ IP_EN1 bits or the OP_EN0/OP_EN1 bits in the GPIOCON register. When the GPIO0 or GPIO1 pin is enabled as an input, the logic level at the pin is contained in the GP_DATA0 or GP_DATA1 bit, respectively. When the GPIO0 or GPIO1 pin is enabled as an output, the GP_ DATA0 or GP_DATA1 bits, respectively, determine the logic level output at the pin. The logic levels for these pins are referenced to AVDD1 and AVSS; therefore, outputs have an amplitude of 5 V or 3.3 V. The SYNC/ERROR pin can also be used as a general-purpose output. When the ERR_EN bits in the GPIOCON register are set to 11, the SYNC/ERRORA pin operates as a general-purpose output. In this configuration, the ERR_DAT bit in the GPIOCON register determines the logic level output at the pin. The logic level for the pin is referenced to IOVDD and DGND. The GPIO0 pin, GPIO1 pin, and SYNC/ERROR pin, when set as general-purpose outputs, have an active pull-up. EXTERNAL MULTIPLEXER CONTROL If an external multiplexer increases the channel count, the multiplexer logic pins can be controlled via the AD7172-2 GPIOx pins. With the MUX_IO bit (Bit 12 in the GPIOCON register), the GPIOx timing is controlled by the ADC; therefore, the channel change is synchronized with the ADC, eliminating any need for external synchronization. DELAY It is possible to insert a programmable delay before the AD7172-2 begins to take samples. This delay allows an external amplifier or multiplexer to settle and can also alleviate the specification requirements for the external amplifier or multiplexer. Eight programmable settings, ranging from 0 µs to 8 ms, can be set using the delay bits in the ADC mode register (Register 0x01, Bits[10:8]). If a delay greater than 0 µs is selected and the HIDE_DELAY bit in the ADC mode register is set to 0, this delay is added to the conversion time, regardless of selected output data rate. When using the sinc5 + sinc1 filter, it is possible to hide this delay so the output data rate remains the same as the output data rate without the delay enabled. If the HIDE_DELAY bit is set to 1 and the selected delay is less than half of the conversion time, the delay can be absorbed by reducing the number of averages the digital filter performs, which keeps the conversion time the same but can affect the noise performance. The effect on the noise performance depends on the delay time compared to the conversion time. It is possible to absorb the delay only for output data rates less than 2.6 kSPS with the exception of the following four rates, which cannot absorb any delay: 381 SPS, 59.52 SPS, 49.68 SPS, and 16.66 SPS. 16-BIT/24-BIT CONVERSIONS By default, the AD7172-2 generates 24-bit conversions. However, the width of the conversions can be reduced to 16 bits. Setting the WL16 bit in the interface mode register to 1 rounds all data conversions to 16 bits. Clearing this bit sets the width of the data conversions to 24 bits. DOUT_RESET The serial interface uses a shared DOUT/RDY pin. By default, this pin outputs the RDY signal. During a data read, this pin outputs the data from the register being read. After the read is complete, the pin reverts to outputting the RDY signal after a short fixed period of time (t7). However, this time may be too short for some microcontrollers and can be extended until the CS pin is brought high by setting the DOUT_RESET bit in the interface mode register to 1. This setting means CS must frame each read operation and compete the serial interface transaction. SYNCHRONIZATION Normal Synchronization When the SYNC_EN bit in the GPIOCON register is set to 1, the SYNC/ERROR pin functions as a synchronization input. The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the device. This feature allows the user to start to gather samples of the analog input from a known point, the rising edge of the SYNC input. The SYNC input must be low for at least one master clock cycle to ensure that synchronization occurs. If multiple AD7172-2 devices are operated from a common master clock, they can be synchronized so the analog inputs aresampled simultaneously. This synchronization is typically completed after each AD7172-2 device has performed each respective calibration or has calibration coefficients loaded into the calibration registers. A falling edge on the SYNC input resets the digital filter and the analog modulator and places the AD7172-2 into a consistent known state. While the SYNC input is low, the AD7172-2 is maintained in this known state. On the SYNC input rising edge, the modulator and filter are taken out of this reset state, and on the next master clock edge, the device starts to gather input samples again. Rev. A | Page 44 of 60 Data Sheet AD7172-2 The device is taken out of reset on the master clock falling edge following the SYNC input low to high transition. Therefore, when multiple devices are being synchronized, take the SYNC Ainput high on the master clock rising edge to ensure that all devices are released on the master clock falling edge. If the SYNC input is not taken high in sufficient time, a difference of one master clock cycle between the devices is possible, that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. CRC_ERROR If the CRC value that accompanies a write operation does not correspond with the information sent, the CRC_ERROR flag is set. The flag is reset when the status register is explicitly read. REG_ERROR The SYNC input can also be used as a start conversion command for a single channel when in normal synchronization mode. In this mode, the rising edge of SYNC input starts a conversion, and the falling edge of the RDY output indicates when the conversion is complete. The settling time of the filter is required for each data register update. After the conversion is complete, bring the SYNC input low in preparation for the next conversion start signal. The REG_ERROR flag is used in conjunction with the REG_CHECK bit in the interface mode register. When the REG_CHECK bit is set, the AD7172-2 monitors the values in the on-chip registers. If a bit changes, the REG_ERROR bit is set to 1. Therefore, for writes to the on-chip registers, set the REG_CHECK bit to 0. When the registers have been updated, the REG_CHECK bit can be set to 1. The AD7172-2 calculates a checksum of the on-chip registers. If one of the register values has changed, the REG_ERROR bit is set to 1. If an error is flagged, the REG_CHECK bit must be set to 0 to clear the REG_ERROR bit in the status register. The register check function does not monitor the data register, status register, or interface mode register. Alternate Synchronization ERROR Input/Output In alternate synchronization mode, the SYNC input operates as a start conversion command when several channels of the AD7172-2 are enabled. Setting the ALT_SYNC bit in the interface mode register to 1 enables an alternate synchronization scheme. When the SYNC input is taken low, the ADC completes the conversion on the current channel, selects the next channel in the sequence, and then waits until the SYNC input is taken high to start the conversion. The RDY output goes low when the conversion is complete on the current channel, and the data register is updated with the corresponding conversion. Therefore, the SYNC input does not interfere with the sampling on the currently selected channel but allows the user to control the instant at which the conversion begins on the next channel in the sequence. When the SYNC_EN bit in the GPIOCON register is set to 0, the SYNC/ERROR pin functions as an error input/output pin or a general-purpose output pin. The ERR_EN bits in the GPIOCON register determine the function of the pin. Alternate synchronization mode can be used only when several channels are enabled. It is not recommended to use this mode when a single channel is enabled. ERROR FLAGS The status register contains three error bits (ADC_ERROR, CRC_ERROR, and REG_ERROR) that flag errors with the ADC conversion, errors with the CRC check, and errors caused by changes in the registers, respectively. In addition, the ERROR output can indicate that an error has occurred. ADC_ERROR The ADC_ERROR bit in the status register flags any errors that occur during the conversion process. The flag is set when an overrange or underrange result is output from the ADC. The ADC also outputs all 0s or all 1s when an undervoltage or overvoltage occurs. This flag is reset only when the overvoltage or undervoltage condition is removed. This flag is not reset by a read of the data register. When the ERR_EN bits are set to 10, the SYNC/ERROR pin functions as an open-drain error output, ERROR. The three error bits in the status register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are OR’ed, inverted, and mapped to the ERROR output. Therefore, the ERROR output indicates that an error has occurred. The status register must be read to identify the error source. When the ERR_EN bits are set to 01, the SYNC/ERROR pin functions as an error input, ERROR. The error output of another component can be connected to the AD7172-2 ERROR input so that the AD7172-2 indicates when an error occurs on either itself or the external component. The value on the ERROR input is inverted and OR’ed with the errors from the ADC conversion, and the result is indicated via the ADC_ERROR bit in the status register. The value of the ERROR input is reflected in the ERR_DAT bit in the GPIO configuration register. The ERROR input/output is disabled when the ERR_EN bits are set to 00. When the ERR_EN bits are set to 11, the SYNC/ERROR pin operates as a general-purpose output. DATA_STAT The contents of the status register can be appended to each conversion on the AD7172-2 using the DATA_STAT bit in the IFMODE register. This function is useful if several channels are enabled. Each time a conversion is output, the contents of the status register are appended. The two LSBs of the status register indicate to which channel the conversion corresponds. In addition, the user can determine if any errors are being flagged by the error bits. Rev. A | Page 45 of 60 AD7172-2 Data Sheet IOSTRENGTH The serial interface can operate with a power supply as low as 2 V. However, at this low voltage, the DOUT/RDY pin may not have sufficient drive strength if there is moderate parasitic capacitance on the board or if the SCLK frequency is high. The IOSTRENGTH bit in the interface mode register increases the drive strength of the DOUT/RDY pin. INTERNAL TEMPERATURE SENSOR The AD7172-2 has an integrated temperature sensor. The temperature sensor can be used as a guide for the ambient temperature at which the device is operating. This can be used for diagnostic purposes or as an indicator of when the application circuit must rerun a calibration routine to take into account a shift in operating temperature. The temperature sensor is selected using the crosspoint multiplexer and is selected in the same way as an analog input channel. The temperature sensor requires that the analog input buffers be enabled on both analog inputs. If the buffers are not enabled, selecting the temperature sensor as an input forces the buffers to be enabled during the conversion. To use the temperature sensor, the first step is to calibrate the device in a known temperature (25°C) and take a conversion as a reference point. The temperature sensor has a nominal sensitivity of 477 µV/K; the difference in this ideal slope and the slope measured can calibrate the temperature sensor. The temperature sensor is specified with a ±2°C typical accuracy after calibration at 25°C. The temperature can be calculated as follows: Rev. A | Page 46 of 60 Conversion Result Temperature ( °C ) = 477 μV – 273.15 Data Sheet AD7172-2 GROUNDING AND LAYOUT The analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common-mode voltages. The high common-mode rejection of the device removes common-mode noise on these inputs. The analog and digital supplies to the AD7172-2 are independent and connected to separate pins to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. possible to provide low impedance paths and reduce glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This technique reduces the effects of feedthrough on the board. A microstrip technique is by far the best but is not always possible with a double-sided board. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7172-2 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7172-2 is high and the noise levels from the converter are so low, take care with regard to grounding and layout. Good decoupling is important when using high resolution ADCs. The AD7172-2 has three power supply pins: AVDD1, AVDD2, and IOVDD. The AVDD1 and AVDD2 pins are referenced to AVSS, and the IOVDD pin is referenced to DGND. Decouple AVDD1 and AVDD2 with a 10 µF capacitor in parallel with a 0.1 µF capacitor to AVSS on each pin. Place the 0.1 µF capacitor as close as possible to the device on each supply, ideally right up against the device. Decouple IOVDD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to DGND. Decouple all analog inputs to AVSS. If an external reference is used, decouple the REF+ and REF− pins to AVSS. The PCB that houses the ADC must be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it results in the best shielding. In any layout, the user must consider the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the paths the currents took to reach their destinations. Avoid running digital lines under the device because this couples noise onto the die. Allow the analog ground plane to run under the AD7172-2 to prevent noise coupling. The power supply lines to the AD7172-2 must use as wide a trace as The AD7172-2 also has two on-board LDO regulators, one that regulates the AVDD2 supply and one that regulates the IOVDD supply. For the REGCAPA pin, use 1 µF and 0.1 µF capacitors to AVSS. Similarly, for the REGCAPD pin, use 1 µF and 0.1 µF capacitors to DGND. If using the AD7172-2 for split supply operation, a separate plane must be used for AVSS. Rev. A | Page 47 of 60 AD7172-2 Data Sheet REGISTER SUMMARY Table 25. Register Summary Reg. Name Bits Bit 7 COMMS [7:0] WEN Bit 6 R/W Bit 5 0x00 0x00 STATUS [7:0] RDY ADC_ERROR CRC_ERROR 0x01 ADCMODE [15:8] [7:0] REF_EN RESERVED HIDE_DELAY SING_CYC MODE CONTREAD REGCHECK [15:8] [7:0] [23:16] DATA [15:8] [7:0] [23:16] REGISTER_CHECK[15:8] REGISTER_CHECK[7:0] DATA[23:16] [15:8] [7:0] DATA[15:8] DATA[7:0] 0x02 0x03 0x04 0x06 IFMODE GPIOCON 0x07 ID 0x10 CH0 [15:8] [7:0] [15:8] [7:0] [15:8] Bit 3 RESERVED DATA_STAT REG_ERROR MUX_IO IP_EN0 IP_EN1 RESERVED SETUP_SEL0 CH2 0x13 CH3 0x20 SETUPCON0 BURNOUT_EN0 SETUPCON1 [7:0] [15:8] RESERVED RESERVED REF_SEL0 BI_UNIPOLAR1 [7:0] [15:8] [7:0] BURNOUT_EN1 RESERVED RESERVED RESERVED REF_SEL1 BI_UNIPOLAR2 REF_SEL2 0x22 0x23 0x28 0x29 0x2A 0x2B 0x30 0x31 0x32 0x33 0x38 0x39 0x3A 0x3B SETUPCON2 SETUPCON3 FILTCON0 FILTCON1 FILTCON2 FILTCON3 OFFSET0 OFFSET1 OFFSET2 OFFSET3 GAIN0 GAIN1 GAIN2 GAIN3 [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] [23:0] BURNOUT_EN2 BURNOUT_EN3 SINC3_MAP0 RESERVED SINC3_MAP1 RESERVED SINC3_MAP2 RESERVED SINC3_MAP3 RESERVED RESERVED RESERVED CLOCKSEL DELAY RESERVED OP_EN0 RESERVED RESERVED AINNEG0 RESERVED AINNEG1 RESERVED AINNEG2 RESERVED AINNEG3 REFBUF0+ REFBUF0− SETUP_SEL1 SETUP_SEL2 SETUP_SEL3 BI_UNIPOLAR0 REFBUF1+ REFBUF2+ BI_UNIPOLAR3 REFBUF3+ REF_SEL3 RESERVED ENHFILTEN0 ORDER0 RESERVED ENHFILTEN1 RESERVED ENHFILTEN2 RESERVED ENHFILTEN3 ORDER1 ORDER2 ORDER3 OFFSET0[23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] GAIN0[23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] Rev. A | Page 48 of 60 Reset RW 0x00 W 0x80 R 0x0000 RW DOUT_RESET 0x0000 WL16 0x000000 RW R 0x000000 R 0x0800 RW 0x00DX R AINPOS0[4:3] 0x8001 RW AINPOS1[4:3] 0x0001 RW AINPOS2[4:3] 0x0001 RW AINPOS3[4:3] 0x0001 RW ERR_EN GP_DATA1 RESERVED 0x12 0x21 AINPOS0[2:0] RESERVED AINPOS1[2:0] RESERVED AINPOS2[2:0] RESERVED AINPOS3[2:0] RESERVED CHANNEL SYNC_EN OP_EN1 ID[15:8] ID[7:0] CH1 CH_EN3 Bit 0 RESERVED ALT_SYNC IOSTRENGTH RESERVED CRC_EN REGISTER_CHECK[23:16] REG_CHECK 0x11 CH_EN2 Bit 1 RESERVED [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] CH_EN1 Bit 2 RA RESERVED RESERVED CH_EN0 Bit 4 ERR_DAT GP_DATA0 AINBUF0+ AINBUF0− 0x1000 RW RESERVED REFBUF1− AINBUF1+ AINBUF1− 0x1000 RW AINBUF2− 0x1000 RW AINBUF3− 0x1000 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x0500 RW 0x800000 0x800000 0x800000 0x800000 0x5XXXX0 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW RW RW RW RW RESERVED REFBUF2− AINBUF2+ RESERVED REFBUF3− AINBUF3+ RESERVED ENHFILT0 ODR0 ENHFILT1 ODR1 ENHFILT2 ODR2 ENHFILT3 ODR3 Data Sheet AD7172-2 REGISTER DETAILS COMMUNICATIONS REGISTER Address: 0x00, Reset: 0x00, Name: COMMS All access to the on-chip registers must start with a write to the communications register. This write determines what register is accessed next and whether that operation is a write or a read. Table 26. Bit Descriptions for COMMS Bits 7 Bit Name WEN 6 R/W Settings 0 1 [5:0] RA 000000 000001 000010 000011 000100 000110 000111 010000 010001 010010 010011 100000 100001 100010 100011 101000 101001 101010 101011 110000 110001 110010 110011 111000 111001 111010 111011 Description This bit must be low to begin communications with the ADC. Reset 0x0 Access W This bit determines if the command is a read or write operation. Write command Read command The register address bits determine which register is to be read from or written to as part of the current communication. Status register ADC mode register Interface mode register Register check register Data register GPIO configuration register ID register Channel Register 0 Channel Register 1 Channel Register 2 Channel Register 3 Setup Configuration Register 0 Setup Configuration Register 1 Setup Configuration Register 2 Setup Configuration Register 3 Filter Configuration Register 0 Filter Configuration Register 1 Filter Configuration Register 2 Filter Configuration Register 3 Offset Register 0 Offset Register 1 Offset Register 2 Offset Register 3 Gain Register 0 Gain Register 1 Gain Register 2 Gain Register 3 0x0 W 0x00 W Rev. A | Page 49 of 60 AD7172-2 Data Sheet STATUS REGISTER Address: 0x00, Reset: 0x80, Name: STATUS The status register is an 8-bit register that contains ADC and serial interface status information. It can optionally be appended to the data register by setting the DATA_STAT bit in the interface mode register. Table 27. Bit Descriptions for STATUS Bits 7 Bit Name RDY Settings 0 1 6 ADC_ERROR 0 1 5 CRC_ERROR 0 1 4 REG_ERROR 0 1 [3:2] [1:0] RESERVED CHANNEL 00 01 10 11 Description The status of RDY is output to the DOUT/RDY pin whenever CS is low and a register is not being read. This bit goes low when the ADC has written a new result to the data register. In ADC calibration modes, this bit goes low when the ADC has written the calibration result. RDY is brought high automatically by a read of the data register. New data result available Awaiting new data result This bit by default indicates if an ADC overrange or underrange has occurred. The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000 for underrange errors. This bit is updated when the ADC result is written and is cleared at the next update after removing the overrange or underrange condition. No error Error This bit indicates if a CRC error has taken place during a register write. For register reads, the host microcontroller determines if a CRC error has occurred. This bit is cleared by a read of this register. No error CRC error This bit indicates if the content of one of the internal registers has changed from the value calculated when the register integrity check was activated. The check is activated by setting the REG_CHECK bit in the interface mode register. This bit is cleared by clearing the REG_CHECK bit. No error Error These bits are reserved. These bits indicate which channel was active for the ADC conversion whose result is currently in the data register. This channel may be different from the channel currently being converted. The mapping is a direct map from the channel register; therefore, Channel 0 results in 0x0 and Channel 3 results in 0x3. Channel 0 Channel 1 Channel 2 Channel 3 Rev. A | Page 50 of 60 Reset 0x1 Access R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R Data Sheet AD7172-2 ADC MODE REGISTER Address: 0x01, Reset: 0x0000, Name: ADCMODE The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets the filter and the ARDYA bits and starts a new conversion or calibration. Table 28. Bit Descriptions for ADCMODE Bits 15 Bit Name REF_EN Settings 0 1 14 HIDE_DELAY 0 1 13 SING_CYC 0 1 [12:11] [10:8] RESERVED DELAY 000 001 010 011 100 101 110 111 7 [6:4] RESERVED MODE 000 001 010 011 100 110 111 [3:2] CLOCKSEL 00 01 10 11 [1:0] RESERVED Description This bit enables the internal reference and outputs a buffered 2.5 V to the REFOUT pin. Disabled Enabled If a programmable delay is set using the DELAY bits, this bit allows the delay to be hidden by absorbing the delay into the conversion time for selected data rates with the sinc5 + sinc1 filter. See the Delay section for more information. Enabled Disabled This bit can be used when only a single channel is active to set the ADC to only output at the settled filter data rate. Disabled Enabled These bits are reserved; set these bits to 0. These bits allow a programmable delay to be added after a channel switch to allow settling of external circuitry before the ADC starts processing the input. 0 µs 32 µs 128 µs 320 µs 800 µs 1.6 ms 4 ms 8 ms This bit is reserved; set this bit to 0. These bits control the operating mode of the ADC. See the Operating Modes section for more information. Continuous conversion mode Single conversion mode Standby mode Power-down mode Internal offset calibration System offset calibration System gain calibration This bit selects the ADC clock source. Selecting internal oscillator also enables the internal oscillator. Internal oscillator Internal oscillator output on the XTAL2/CLKIO pin External clock input on the XTAL2/CLKIO pin External crystal on the XTAL1 and XTAL2/CLKIO pins These bits are reserved; set these bits to 0. Rev. A | Page 51 of 60 Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 0x0 R RW 0x0 0x0 R RW 0x0 RW 0x0 R AD7172-2 Data Sheet INTERFACE MODE REGISTER Address: 0x02, Reset: 0x0000, Name: IFMODE The interface mode register configures various serial interface options. Table 29. Bit Descriptions for IFMODE Bits [15:13] 12 Bit Name RESERVED ALT_SYNC Settings 0 1 11 IOSTRENGTH 0 1 [10:9] 8 RESERVED DOUT_RESET 0 1 7 CONTREAD 0 1 6 DATA_STAT 0 1 5 REG_CHECK 0 1 4 [3:2] RESERVED CRC_EN 00 01 10 1 RESERVED Description These bits are reserved; set these bits to 0. This bit enables a different behavior of the SYNC/ERROR pin to allow the use of SYNC/ERROR as a control for conversions when cycling channels (see the description of the SYNC_EN bit in the GPIO Configuration Register section for details). Disabled Enabled This bit controls the drive strength of the DOUT/RDY pin. Set this bit when reading from the serial interface at high speed with a low IOVDD supply and moderate capacitance. Disabled (default) Enabled These bits are reserved; set these bits to 0. See the DOUT_RESET section for more information. Disabled Enabled This bit enables a continuous read of the ADC data register. The ADC must be configured in continuous conversion mode to use continuous read. For more details, see the Operating Modes section. Disabled Enabled This enables the status register to be appended to the data register when read so that the channel and status information are transmitted with the data. This is the only way to ensure that the channel bits read from the status register correspond to the data in the data register. Disabled Enabled This bit enables a register integrity checker, which can monitor any change in the value of the user registers. To use this feature, configure all other registers as desired, with this bit cleared. Then write to this register to set the REG_CHECK bit to 1. If the contents of any of the registers change, the REG_ERROR bit is set in the status register. To clear the error, set the REG_CHECK bit to 0. Neither the interface mode register nor the ADC data or status registers are included in the registers that are checked. If a register must have a new value written, this bit must first be cleared; otherwise, an error is flagged when the new register contents are written. Disabled Enabled This bit is reserved; set this bit to 0. These bits enable CRC protection of register reads/writes. CRC increases the number of bytes in a serial interface transfer by one. See the CRC Calculation section for more details. Disabled XOR checksum enabled for register read transactions; register writes still use CRC with these bits set CRC checksum enabled for read and write transactions This bit is reserved; set this bit to 0. Rev. A | Page 52 of 60 Reset 0x0 0x0 Access R RW 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW 0x0 RW 0x0 0x00 R RW 0x0 R Data Sheet Bits 0 Bit Name WL16 AD7172-2 Settings 0 1 Description This bit changes the ADC data register to 16 bits. The ADC is not reset by a write to the interface mode register; therefore, the ADC result is not rounded to the correct word length immediately after writing to this bit. The first new ADC result is correct. 24-bit data 16-bit data Reset 0x0 Access RW REGISTER CHECK Address: 0x03, Reset: 0x000000, Name: REGCHECK The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit in the interface mode register must be set for this register to operate; otherwise, the register reads 0. Table 30. Bit Descriptions for REGCHECK Bits [23:0] Bit Name REGISTER_CHECK Settings Description This register contains the 24-bit checksum of user registers when the REG_CHECK bit is set in the interface mode register. Reset 0x000000 Access R DATA REGISTER Address: 0x04, Reset: 0x000000, Name: DATA The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the BI_UNIPOLARx bit in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high if they are low. The ADC result can be read multiple times; however, because the RDY output has been brought high, it is not possible to know if another ADC result is imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data register. Table 31. Bit Descriptions for DATA Bits [23:0] Bit Name DATA Settings Description This register contains the ADC conversion result. If the DATA_STAT bit is set in the interface mode register, the status register is appended to this register when read, making this a 32-bit register. If the WL16 bit is set in the interface mode register, this register is reduced to 16 bits. Rev. A | Page 53 of 60 Reset 0x000000 Access R AD7172-2 Data Sheet GPIO CONFIGURATION REGISTER Address: 0x06, Reset: 0x0800, Name: GPIOCON The GPIO configuration register controls the general-purpose input/output pins of the ADC. Table 32. Bit Descriptions for GPIOCON Bits [15:13] 12 Bit Name RESERVED MUX_IO 11 SYNC_EN Settings 0 1 [10:9] ERR_EN 00 01 10 11 8 ERR_DAT [7:6] 5 RESERVED IP_EN1 0 1 4 IP_EN0 0 1 3 OP_EN1 0 1 2 OP_EN0 0 1 1 0 GP_DATA1 GP_DATA0 Description These bits are reserved; set these bits to 0. This bit allows the ADC to control an external multiplexer, using GPIO0/GPIO1 in sync with the internal channel sequencing. The analog input pins used for a channel can still be selected on a per channel basis. Therefore, it is possible to have a 4-channel multiplexer in front of AIN0/AIN1 and another in front of AIN2/AIN3, giving a total of eight differential channels with the AD7172-2. However, only four channels at a time can be automatically sequenced. A delay can be inserted after switching an external multiplexer (see the delay bits in the ADC Mode Register section). This bit enables the SYNC/ERROR pin as a sync input. When the pin is low, this bit holds the ADC and filter in reset until the SYNC/ERROR pin goes high. An alternative operation of the SYNC/ERROR pin is available when the ALT_SYNC bit in the interface mode register is set. This mode only works when multiple channels are enabled. In this case, a low on the SYNC/ERROR pin does not immediately reset the filter/ modulator. Instead, if the SYNC/ERROR pin is low when the channel is due to be switched, the modulator and filter are prevented from starting a new conversion. Bringing SYNC/ERROR high begins the next conversion. This alternative sync mode allows SYNC/ERROR to be used while cycling through channels. Disabled. Enabled. These bits enable the SYNC/ERROR pin as an error input/output. Disabled. SYNC/ERROR is an error input. The (inverted) readback state is OR'ed with other error sources and is available in the ADC_ERROR bit in the status register. The SYNC/ ERROR pin state can also be read from the ERR_DAT bit in this register. SYNC/ERROR is an open-drain error output. The status register error bits are OR'ed, inverted, and mapped to the SYNC/ERROR pin. The SYNC/ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error on any device can be observed. SYNC/ERROR is a general-purpose output. The status of the pin is controlled by the ERR_DAT bit in this register. This output is referenced between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the general-purpose input/output pins. The SYNC/ERROR pin has an active pull-up in this case. Reset 0x0 0x0 Access R RW 0x1 RW 0x0 RW This bit determines the logic level at the SYNC/ERROR pin if the pin is enabled as a general-purpose output. This bit reflects the readback status of the pin if the pin is enabled as an input. These bits are reserved; set these bits to 0. This bit turns GPIO1 into an input. Inputs are referenced to AVDD1 or AVSS. Disabled. Enabled. This bit turns GPIO0 into an input. Inputs are referenced to AVDD1 or AVSS. Disabled. Enabled. This bit turns GPIO1 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled. Enabled. This bit turns GPIO0 into an output. Outputs are referenced between AVDD1 and AVSS. Disabled. Enabled. This bit is the readback or write data for GPIO1. This bit is the readback or write data for GPIO0. 0x0 RW 0x0 0x0 R RW 0x0 RW 0x0 RW 0x0 RW 0x0 0x0 RW RW Rev. A | Page 54 of 60 Data Sheet AD7172-2 ID REGISTER Address: 0x07, Reset: 0x00DX, Name: ID The ID register returns a 16-bit ID. For the AD7172-2, this ID is 0x00DX. Table 33. Bit Descriptions for ID Bits [15:0] Bit Name ID Settings 0x00DX Description The ID register returns a 16-bit ID code that is specific to the ADC. AD7172-2 Reset 0x00DX Access R CHANNEL REGISTER 0 Address: 0x10, Reset: 0x8001, Name: CH0 The channel registers are 16-bit registers that select which channels are currently active, which inputs are selected for each channel, and which setup configures the ADC for that channel. Table 34. Bit Descriptions for CH0 Bits 15 Bit Name CH_EN0 Settings 0 1 14 [13:12] RESERVED SETUP_SEL0 00 01 10 11 [11:10] [9:5] RESERVED AINPOS0 00000 00001 00010 00011 00100 10001 10010 10011 10100 10101 10110 Description This bit enables Channel 0. If more than one channel is enabled, the ADC automatically sequences between them. Disabled Enabled (default) This bit is reserved; set this bit to 0. These bits identify which of the four setups configure the ADC for this channel. A setup comprises a set of four registers: setup configuration register, filter configuration register, offset register, and gain register. All channels can use the same setup, in which case the same 2-bit value must be written to these bits on all active channels, or up to four channels can be configured differently. Setup 0 Setup 1 Setup 2 Setup 3 These bits are reserved; set these bits to 0. These bits select which input is connected to the positive input of the ADC for this channel. AIN0 (default) AIN1 AIN2 AIN3 AIN4 Temperature sensor+ Temperature sensor− ((AVDD1 − AVSS)/5)+ (analog input buffers must be enabled) ((AVDD1 − AVSS)/5)− (analog input buffers must be enabled) REF+ REF− Rev. A | Page 55 of 60 Reset 0x1 Access RW 0x0 0x0 R RW 0x0 0x0 R RW AD7172-2 Bits [4:0] Data Sheet Bit Name AINNEG0 Settings 00000 00001 00010 00011 00100 10001 10010 10011 10100 10101 10110 Description These bits select which input is connected to the negative input of the ADC for this channel. AIN0 AIN1 (default) AIN2 AIN3 AIN4 Temperature sensor+ Temperature sensor− ((AVDD1 − AVSS)/5)+ ((AVDD1 − AVSS)/5)− REF+ REF− Reset 0x1 Access RW CHANNEL REGISTER 1 TO CHANNEL REGISTER 3 Address: 0x11, 0x12, 0x13, Reset: 0x0001, Name: CH1 to CH3 The remaining three channel registers share the same layout as Channel Register 0. Table 35. CH1 to CH3 Register Map Reg. 0x11 Name CH1 Bits [15:8] [7:0] Bit 7 CH_EN1 Bit 6 RESERVED AINPOS1[2:0] 0x12 CH2 [15:8] [7:0] CH_EN2 RESERVED AINPOS2[2:0] 0x13 CH3 [15:8] CH_EN3 [7:0] RESERVED Bit 5 Bit 4 SETUP_SEL1 Bit 3 Bit 2 RESERVED AINNEG1 Bit 1 Bit 0 AINPOS1[4:3] Reset 0x0001 RW RW SETUP_SEL2 RESERVED AINNEG2 AINPOS2[4:3] 0x0001 RW SETUP_SEL3 RESERVED AINPOS3[4:3] 0x0001 RW AINPOS3[2:0] AINNEG3 Rev. A | Page 56 of 60 Data Sheet AD7172-2 SETUP CONFIGURATION REGISTER 0 Address: 0x20, Reset: 0x1000, Name: SETUPCON0 The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC. Table 36. Bit Descriptions for SETUPCON0 Bits [15:13] 12 Bit Name RESERVED BI_UNIPOLAR0 Settings 0 1 11 REFBUF0+ 0 1 10 REFBUF0− 0 1 9 AINBUF0+ 0 1 8 AINBUF0− 0 1 7 BURNOUT_EN0 6 [5:4] RESERVED REF_SEL0 00 10 11 [3:0] RESERVED Description These bits are reserved; set these bits to 0. This bit sets the output coding of the ADC for Setup 0. Unipolar coded output Bipolar coded output (offset binary) This bit enables or disables the REF+ input buffer. REF+ buffer disabled REF+ buffer enabled This bit enables or disables the REF− input buffer. REF− buffer disabled REF− buffer enabled This bit enables or disables the AIN+ input buffer. AIN+ buffer disabled AIN+ buffer enabled This bit enables or disables the AIN− input buffer. AIN− buffer disabled AIN− buffer enabled This bit enables a 10 µA current source on the positive analog input selected and a 10 µA current sink on the negative analog input selected. The burnout currents are useful in diagnosis of an open wire, whereby the ADC result goes to full scale. Enabling the burnout currents during measurement results in an offset voltage on the ADC. The best strategy for diagnosing an open wire is turning on the burnout currents at intervals, before or after precision measurements. These bits are reserved; set these bits to 0. These bits allow you to select the reference source for ADC conversion on Setup 0. External reference. Internal 2.5 V reference. The REF_EN bit must also be enabled in the ADC mode register. AVDD1 − AVSS. This can be used to as a diagnostic to validate other reference values. These bits are reserved; set these bits to 0. Reset 0x0 0x1 Access R RW 0x0 RW 0x0 RW 0x0 RW 0x0 RW 0x00 R 0x00 0x0 R RW 0x0 R SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 3 Address: 0x21, 0x22, 0x23, Reset: 0x1000, Name: SETUPCON1 to SETUPCON3 The remaining three setup configuration registers share the same layout as Setup Configuration Register 0. Table 37. SETUPCON1 to SETUPCON3 Register Map Reg. 0x21 Name SETUPCON1 0x22 SETUPCON2 0x23 SETUPCON3 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 7 BURNOUT_EN1 BURNOUT_EN2 BURNOUT_EN3 Bit 6 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Bit 5 Bit 4 BI_UNIPOLAR1 REF_SEL1 BI_UNIPOLAR2 REF_SEL2 BI_UNIPOLAR3 REF_SEL3 Rev. A | Page 57 of 60 Bit 3 REFBUF1+ REFBUF2+ REFBUF3+ Bit 2 Bit 1 REFBUF1− AINBUF1+ RESERVED REFBUF2− AINBUF2+ RESERVED REFBUF3− AINBUF3+ RESERVED Bit 0 AINBUF1− Reset 0x1000 RW RW AINBUF2− 0x1000 RW AINBUF3− 0x1000 RW AD7172-2 Data Sheet FILTER CONFIGURATION REGISTER 0 Address: 0x28, Reset: 0x0500, Name: FILTCON0 The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets any active ADC conversion and restarts converting at the first channel in the sequence. Table 38. Bit Descriptions for FILTCON0 Bits 15 Bit Name SINC3_MAP0 [14:12] 11 RESERVED ENHFILTEN0 Settings 0 1 [10:8] ENHFILT0 010 011 101 110 7 [6:5] RESERVED ORDER0 00 11 [4:0] ODR0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 Description If this bit is set, the mapping of the filter register changes to directly program the decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This allows fine tuning of the output data rate and filter notch for rejection of specific frequencies. The data rate when on a single channel equals fMOD/(32 × FILTCON0[14:0]). These bits are reserved; set these bits to 0. This bit enables various postfilters for enhanced 50 Hz and 60 Hz rejection for Setup 0. The ORDER0 bits must be set to 00 to select the sinc5 + sinc1 filter for this bit to work. Disabled Enabled These bits select between various postfilters for enhanced 50 Hz and 60 Hz rejection for Setup 0. 27 SPS, 47 dB rejection, 36.7 ms settling 21.25 SPS, 62 dB rejection, 40 ms settling 20 SPS, 86 dB rejection, 50 ms settling 16.67 SPS, 92 dB rejection, 60 ms settling This bit is reserved; set this bit to 0. These bits control the order of the digital filter that processes the modulator data for Setup 0. Sinc5 + sinc1 (default) Sinc3 These bits control the output data rate of the ADC and, therefore, the settling time and noise for Setup 0. Rates shown are for the sinc5 + sinc1 filter. See Table 20 to Table 23. 31,250 31,250 31,250 31,250 31,250 31,250 15,625 10,417 5208 2597 1007 503.8 381 200.3 100.2 59.52 49.68 20.01 16.63 10 5 2.5 1.25 Rev. A | Page 58 of 60 Reset 0x0 Access RW 0x0 0x0 R RW 0x5 RW 0x0 0x0 R RW 0x0 RW Data Sheet AD7172-2 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 3 Address: 0x29, 0x2A, 0x2B, Reset: 0x0500, Name: FILTCON1 to FILTCON3 The remaining three filter configuration registers share the same layout as Filter Configuration Register 0. Table 39. FILTCON1 to FILTCON3 Register Map Reg. Name Bits Bit 7 0x29 FILTCON1 [15:8] [7:0] SINC3_MAP1 RESERVED RESERVED ORDER1 ENHFILTEN1 [15:8] [7:0] SINC3_MAP2 RESERVED RESERVED ORDER2 ENHFILTEN2 [15:8] SINC3_MAP3 RESERVED ENHFILTEN3 [7:0] RESERVED 0x2A 0x2B FILTCON2 FILTCON3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Reset RW ENHFILT1 Bit 0 0x0500 RW ENHFILT2 0x0500 RW ENHFILT3 0x0500 RW ODR1 ODR2 ORDER3 ODR3 OFFSET REGISTER 0 Address: 0x30, Reset: 0x800000, Name: OFFSET0 The offset (zero-scale) registers are 24-bit registers that compensate for any offset error in the ADC or in the system. Table 40. Bit Descriptions for OFFSET0 Bits [23:0] Bit Name OFFSET0 Settings Description Offset calibration coefficient for Setup 0. Reset 0x800000 Access RW OFFSET REGISTER 1 TO OFFSET REGISTER 3 Address: 0x31, 0x 32, 0x33, Reset: 0x800000, Name: OFFSET1 to OFFSET3 The remaining three offset registers share the same layout as Offset Register 0. Table 41. OFFSET1 to OFFSET3 Register Map Reg. 0x31 0x32 0x33 Name OFFSET1 OFFSET2 OFFSET3 Bits [23:0] [23:0] [23:0] OFFSET1[23:0] OFFSET2[23:0] OFFSET3[23:0] Reset 0x800000 0x800000 0x800000 RW RW RW RW GAIN REGISTER 0 Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0 The gain (full-scale) registers are 24-bit registers that compensate for any gain error in the ADC or in the system. Table 42. Bit Descriptions for GAIN0 Bits [23:0] Bit Name GAIN0 Settings Description Gain calibration coefficient for Setup 0. Reset 0x5XXXX0 Access RW GAIN REGISTER 1 TO GAIN REGISTER 3 Address: 0x39, 0x3A, 0x3B, Reset: 0x5XXXX0, Name: GAIN1 to GAIN3 The remaining three gain registers share the same layout as Gain Register 0. Table 43. GAIN1 to GAIN3 Register Map Reg. 0x39 0x3A 0x3B Name GAIN1 GAIN2 GAIN3 Bits [23:0] [23:0] [23:0] GAIN1[23:0] GAIN2[23:0] GAIN3[23:0] Rev. A | Page 59 of 60 Reset 0x5XXXX0 0x5XXXX0 0x5XXXX0 RW RW RW RW AD7172-2 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 75. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Models1 AD7172-2BRUZ AD7172-2BRUZ-RL AD7172-2BRUZ-RL7 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] 24-Lead Thin Shrink Small Outline Package [TSSOP] Z = RoHS Compliant Part. ©2014–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12672-0-3/16(A) Rev. A | Page 60 of 60 Package Option RU-24 RU-24 RU-24