GSM Receiver Circuit PMB 2401 Preliminary Data Bipolar IC Features ● Heterodyne receiver with demodulator ● Down mixing from 900 MHz receiver band to the base ● ● ● ● ● ● ● ● ● ● ● ● band Demodulation and generation of I/Q-baseband components Low mixer noise 10 dB (SSB) Input high intercept point + 2 dB Integrated 0˚ and 90˚ phase shifter 82 dB AGC-range On-chip second LO-oscillator with external tuning circuit Two differential operational amplifiers Low power consumption due to highly flexible powerdown capability Wide input frequency range up to 1 GHz Wide IF-range from 35 MHz to 100 MHz P-DSO-28 package and P-DSO-28-4 shrink package Temperature range – 25 ˚C to 85 ˚C P-DSO-28 P-DSO-28-4 Applications ● Digital mobile cellular systems as GSM, DAMPS, JDC ● Various demodulation schemes, such as PM, PSK, FSK, QAM, QPSK, GMSK ● Space and power saving optimizations of existing discrete demodulator circuits Type Version Ordering Code Package PMB 2401T V 2.1 Q67000-A6061 P-DSO-28 (SMD) PMB 2401T V 2.1 Q67006-A6061 P-DSO-28 (SMD, Tape + Reel) PMB 2401S V 2.1 Q67000-A6062 P-DSO-28-4 (Shrink, SMD) PMB 2401S V 2.1 Q67006-A6062 P-DSO-28-4 (Shrink, SMD, Tape + Reel) Semiconductor Group 1 01.94 PMB 2401 Functional Description The PMB 2401 is a single-chip single-conversion heterodyn PM-receiver with phase shifting circuitry for the I/Q-phase baseband demodulation on chip. It also includes the second local oscillator, a gain controlled second IF-amplifier, two differential operational amplifiers for baseband filtering purposes and power down circuitry. The PMB 2401 is designed for digital mobile telephones according to the GSM-standard and other digital systems. Pin Configuration (top view) Semiconductor Group 2 PMB 2401 Pin Definitions and Functions Pin No. Symbol Function 1 SOI Non-inverting in-phase signal output 2 SOQ Non-inverting quadratur signal output 3 INQ Inverting op. amp. signal output (Q) 4 OUTQ Non-inverting op. amp. signal output (Q) 5 OUTQ Inverting op. amp. signal output (Q) 6 INQ Non-inverting op. amp. signal input (Q) 7 SOQ Inverting quadratur signal output 8 LO2E External capacitors for oscillator 9 LO2B VCO-tuning circuit 10 GND Ground 11 IFI Inverting IF input 12 IFI Non-inverting IF input 13 GC Gain control input 14 LO2O VCO-signal output 15 MO Inverted output of first mixer 16 MO Non-inverted output of first mixer 17 VS Supply voltage 18 SI Non-inverted signal input of first mixer 19 SI Inverted signal input of first mixer 20 PD1 Power-down input 1 21 LO1 Non-inverting input for first local oscillator 22 LO1 Inverting input for first local oscillator 23 PD2 Power-down input 2 24 SOI Inverting in-phase signal output 25 INI Non-inverting op. amp. signal input (I) 26 OUTI Inverting op. amp. signal output (I) 27 OUTI Non-inverting op. amp. signal output (I) 28 INI Inverting op. amp. signal input (I) Semiconductor Group 3 PMB 2401 Block Diagram Semiconductor Group 4 PMB 2401 Circuit Description The input signal SI/SI and the amplified first local oscillator signal LO1/LO1 are mixed down to an intermediate frequency (IF). The open collector output of the mixer generates a differential current at pins MO/MO which is filtered by an external resonant circuit. The resulting voltage drives an external SAW-filter. The second local oscillator signal LO2 is generated in an on chip VCO and is fed to two dividers, which generate orthogonal signals at a quarter of VCO-frequency. The internal LO-signal is fed to an additionally divider, whose output signal LO2O is fed to the RF-signal of PLL-synthesizer. The filtered IF-signal reenters the chip at the IFI/IFI input, where it is amplified and demodulated to the final baseband output frequency with each of the orthogonal signals. The resulting in-phase and quadrature signals pass through differential output drivers and appear at SOI/SOI and SOQ/SOQ outputs, respectively. The amplification of the IF-signal before the second mixer stage is performed by a gain-controlled amplifier, the gain being determined by the voltage at the gain control input GC. Two differential operational amplifiers with the input signals INI/INI (INQ/INQ) and the output signals OUTI/OUTI (OUTQ/OUTQ) can be used as active filters. Differential signals and symmetrical circuitry are used throughout, except at the signal output. Bias drivers generate internal temperature- and supply voltage-compensated reference voltages required by various circuit blocks. Switching the power down inputs PD1 and PD2 from high to low (see table) sets the circuit from its normal operating mode into a mode with reduced supply current. PD1 PD2 RF-Part IF-Part VCO/Divders L L OFF OFF ON L H OFF ON ON H L ON OFF ON H H ON ON ON Semiconductor Group 5 PMB 2401 Internal Input / Output Circuits Semiconductor Group 6 PMB 2401 Electrical Characteristics Absolute Maximum Ratings The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. TA = – 25 ˚C to 85 ˚C Parameter Symbol Limit Values min. max. Unit Remarks Supply voltage VS – 0.5 7 V Input/output voltage (any except open collector) VIO – 0.5 – 0.5 VS + 0.5 V V VS ≤ 7 V VS ≤ 7 V Open collector output voltage (MO/MO) VOC – 0.5 – 0.5 VS + 2.5 7.5 V V VS ≥ 5 V VS ≥ 5 V Differential input voltage (any differential input) VI –3 3 V Junction temperature Tj 125 ˚C Storage temperature Tstg 125 ˚C Thermal resistance (junction to ambient) Rth JA 55 K/W K/W – 55 7.5 The pins 15, 16, 18, 19 have no additional internal ESD protection circuitry Semiconductor Group 7 P-DSO-28 P-DSO-28-4 PMB 2401 Operational Range Within the operational range the IC operates as described in the circuit description. The AC/DCcharacteristics limits are not guaranteed. VS = 4.5 V to 5.5 V; TA = – 25 ˚C to 85 ˚C; refer to test circuit 1. Parameter Symbol Limit Values min. Unit max. SI/SI input level PSI – 11 dBm SI/SI input frequency fSI 1000 MHz LO1/LO1 input level PLO1 3 dBm LO1/LO1 input frequency fLO1 1100 MHz Intermediate frequency fIF 100 MHz IFI/IFI input level PIFI – 24 dBm IFI/IFI input frequency fIFI 35 100 MHz LO2 input level PLO2 – 20 0 dBm LO2 input frequency fLO2 140 400 MHz VCO frequency range fVCO 120 250 MHz LO2O output level PLO2O 120 180 mVpp LO2O output frequency fLO2O 15 50 MHz SOI/SOI, SOQ/SOQ output Bandwidth BSO 0 0.8 MHz GC input voltage VGC 0 2 V L-PD1/PD2 voltage VPDL 0 1 V H-PD1/PD2 voltage VPDH 4 VS V – 11 35 Note: Power levels are referred to resistance of 50 Ω Semiconductor Group 8 Remarks VCO external with ext. capacitors – 3 dB roll off PMB 2401 AC/DC Characteristics AC/DC-characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are the median of the production. VS = 4.75 to 5.25 V; TA = 25 ˚C; Parameter Supply current Symbol IS Limit Values Unit Test Condition Test Circuit PD1 = L PD1 = L PD1 = H PD1 = H 1 min. typ. max. 3.1 12 11.5 20 5.5 15.5 15 24.5 6.8 19 18.5 30 mA mA mA mA PD2 = L PD2 = H PD2 = L PD2 = L First Mixer Signal Input SI/SI Input resistance RSI 17 25 33 Ω Input inductance LSI 3.5 5 6.5 nH In series to RSI 2a Max. input level PSI – 13 – 11 dBm 1 dB compr. at MO/MO 1 Input intercept Point PIPI 0 2 3 dBm GMO = 14 dB 1 Blocking level PB – 16 – 14 – 12 dBm 3 dB attenuation of wanted Signal at MO 1 Input interference level at f = fint Pint – 38 dBm – 98 dBm interference at f = (fint ± fLO1) X2 at MO 3 Input frequency fSI Noise figure NSI NSI 7.5 9.5 8 10 2a 960 MHz 1 9.5 11.5 dB dB DSB-noise, fC = 900 MHz SSB-noise, fC = 900 MHz including optimum noise matching 1 Output of First Mixer MO/MO (open collector) 11.2 7 16 10 20.8 13 kΩ kΩ fMO = 45 MHz fMO = 71 MHz 2c 2c Output capacitance CMO 0.7 1 1.3 pF parallel to RMO 2c Total output current IMO + MO 3.5 5 6.5 mA 1 13 14 dB 1 100 MHz 1 Output resistance RMO RMO Power gain from Signal input GMO Intermediate frequency fIF Semiconductor Group 35 9 PMB 2401 AC/DC Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition Test Circuit max. Input of First Mixer Local Oscillator LO1/LO1 Input resistance RLO1 490 700 910 Ω fLO1 = 900 MHz 2a Input capacitance CLO1 0.7 1 1.3 pF parallel to RLO1 2a Input level PLO1 VLO1 – 11 178 3 890 dBm mVpp see diagram 1 1 1 Input frequency fLO1 1100 MHz 1 Isolation of First Mixer From SI to MO ASI – MO 30 dB fSI = 945 MHz; fLO1 = 900 MHz 1 SI to LO1 ASI – LO1 60 dB fSI = 945 MHz; fLO1 = 900 MHz 1 LO1 to MO ALO1 – MO 50 dB fSI = 945 MHz; fLO1 = 900 MHz 1 LO1 to SI ALO1 – SI 60 dB fSI = 945 MHz; fLO1 = 900 MHz 1 MO to SI AMO – SI 50 dB fSI = 945 MHz; fLO1 = 900 MHz 1 MO to LO1 AMO – LO1 65 dB fSI = 945 MHz; fLO1 = 900 MHz 1 IF Input IFI/IFI Input resistance RIFI 63 90 117 Ω Input capacitance CIFI 0.35 0.5 0.65 pF parallel to RIFI 2a Max. input level PIFI VIFI – 17 89 dBm mVpp VGC = 2 V, 1 dB compr. at 1 1 Input intercept point PIPI see diagram 5 Input frequency fSI 35 Noise figure NSI 10 11 2a SO; see diagram 4 1 100 MHz 14 dB 1 SSB-noise 1 fLO2 = 180 MHz fLO2 = 360 MHz 2b 2b Input for Second Local Oscillator LO2 (VCO external) Input resistance RLO2 Semiconductor Group 1.9 1.3 2.4 1.8 3.1 2.3 10 kΩ kΩ PMB 2401 AC/DC Characteristics (cont’d) Parameter Symbol Limit Values Unit min. typ. max. 1 1.3 pF Input capacitance CLO2 0.7 Input level PLO2 VLO2 – 20 63 0 630 dBm mVpp Input frequency fLO2 140 400 MHz 250 MHz Test Condition Test Circuit 2b into 50 Ω 1.1 1.1 1.1 Voltage Controlled Oscillator VCO (LO2) fVCO 120 RLO2O 0.9 1.2 1.5 kΩ Output capacitance CLO2O 0.7 1 1.3 pF Output level VLO2O 150 120 160 140 Output frequency fLO2O 15 VCO-frequency with ext. capacitors 1.2 IF ≤ 75 MHz IF ≥ 75 MHz 1 1 VCO Output LO2O Output resistance mVpp mVpp 50 MHz 1 Signal Outputs SOI/SOI, SOQ/SOQ RSO 175 250 325 Ω Output capacitance CSO 0.7 1 1.3 pF Output resistance SO frequency roll off fSO DC output level VSO Diff. output offset voltage VSO/SO Voltage gain from IF to I/Q-output GSO 800 2.0 70 – 12 74 –8 kHz see diagram 6 2.5 V 1 28 mV between I/I or Q/Q 1 78 –4 dB dB VGC = 0 V VGC = 2 V 1 2 V 1 µA 0 V ≤ VGC ≤ 2 V 1 dB/V FGC = dGSO/dVGC 1 see diagram 2 + 3 Gain Control Input GC GC-input voltage VGC GC-input current – IGC Gain control factor FGC 0 40 1 see diagram 3 Semiconductor Group 11 PMB 2401 AC/DC Characteristics (cont’d) Parameter Symbol Limit Values min. typ. Unit Test Condition max. Test Circuit Power-Down Inputs PD1, PD2 L-PD input voltage VPDL L-PD input current IPD1L IPD2L H-PD input voltage VPDH H-PD input current 0 4 IPDH 1 V 0.1 0.2 µA µA VS V 10 µA 1 0 ≤ VPD1, 2L ≤ 1 V 1 1 4 ≤ VPD1, 2L ≤ VS 1 Differential Operational Amplifier (open loop) Slew rate SR 4.6 V/µs 1 Gain Bandwidth Prod. GBW 12 MHz 1 Voltage gain AVo 55 dB 1 Phase margin ϕR 60 degr. 1 Gain margin AR 14 dB 1 Common mode Rejection Ratio CMRR 58 dB 1 Offset voltage VOFF 1 mV 1 Output voltage VOUT Semiconductor Group 0.8 VS –1 V 12 1 PMB 2401 *1) *2) *3) *4) Test Circuit 1 Semiconductor Group 13 Balun 1:2 “NEOSID” 00553110 Balun 1:1 “NEOSID” 00553100 Transformer Kit “Vogt”1 5171100002 Cul 0.008 Tuned for resonance PMB 2401 Test Circuit 1.1 Test Circuit 1.2 Semiconductor Group 14 PMB 2401 Test Circuit 2a Test Circuit 2b Test Circuit 2c Semiconductor Group 15 PMB 2401 The S-parameters are tested at the indicated frequency and the equivalent parallel or series circuit is calculated on this base. Test Point Test Circuit Test Frequency / MHz Pin x Pin y LO1-input impedance 2a 900 21 22 SI-input impedance 2a 900 18 19 IFI-input impedance 2a 45 … 90 11 12 LO2-input impedance 2b 180, 360 9 – MO-output impedance 2c 45, 71 15 16 Semiconductor Group 16 PMB 2401 Test Circuit 3 f W = wanted input signal from received channel fint = unwanted interfering signal within band : fint = fLO – fIF / 2 fLO = local oscillator signal fIFW = wanted IF signal from received channel = fLO – fW fIFi t = unwanted IF / 2 signal from interfering channel: fIFint = fLO – fint fIF2in = unwanted harmonic signal of fIF2in : fIF2in = 2 × fIFint Semiconductor Group 17 PMB 2401 Application Circuit Semiconductor Group 18 PMB 2401 Diagram 1 First Mixer Gain versus LO-Level PLO1 PSI = – 40 dBm, fMO = 45 MHz Diagram 2 Gain Control Characteristic Output Level PSO versus input Level PIFI Diagram 3 Gain Control Characteristic Voltage Gain GSO versus GC-Voltage VGC Diagram 4 Gain Control Characteristic Max. Input Level PIFI versus GC-Voltage VGC: (1 dB Compression at SO) Semiconductor Group 19 PMB 2401 Diagram 5 Gain–Control Characteristic Input Intercept Point PIPI versus GC-Voltage VGC Semiconductor Group Diagram 6 Frequency Transfer Characteristic of Outputs SOI / SOQ 20 PMB 2401 Diagram 7 Worst-Case Signal Levels without Blocking Level Semiconductor Group 21 PMB 2401 Diagram 8 Worst-Case Signal Levels with Blocking Level Semiconductor Group 22 PMB 2401 Package Outlines GPS05123 Plastic-Package, P-DSO-28 (SMD) (Dual-Small-Outlines) GPS05389 Plastic-Package, P-DSO-28-4 (Shrink) (SMD) (Dual-Small-Outlines) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 23 23 Dimensions in mm