UT54ACS193E Synchronous 4-Bit Up-Down Dual Clock Counter July 2013 www.aeroflex.com/Logic Datasheet FEATURES The device is characterized over full HiRel temperature range of -55oC to +125oC. Look-ahead circuitry enhances cascaded counters Fully synchronous in count modes Parallel asynchronous load for modulo-N count lengths Asynchronous clear m CRH CMOS process - Latchup immune High speed Low power consumption Wide power supply operating range of 3.0V to 5.5V Available QML Q or V processes 16-lead flatpack UT54ACS193E - SMD 5962-96566 PINOUT 16-Lead Flatpack TopView DESCRIPTION The UT54ACS193E is a synchronous 4-bit, reversible up-down binary counter. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed. Synchronous operation eliminates the output counting spikes normally associated with asynchronous counters. B 1 16 VDD QB 2 15 A QA 3 14 CLR DOWN UP 4 5 13 12 BO CO QC 6 11 LOAD QD VSS 7 8 10 9 C D FUNCTION TABLE The outputs of the four flip-flops are triggered on a low-to-highlevel transition of either count input (Up or Down). The direction of the counting is determined by which count input is pulsed while the other count input is high. The counter is fully programmable. The outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The outputs will change to agree with the data inputs independently of the count pulses. Asynchronous loading allows the counter to be used as moduloN divider by simply modifying the count length with the preset inputs. A clear input has been provided that forces all outputs to the low level when a high level is applied. The clear function is independent of the count and the load inputs. The counter is designed for efficient cascading without the need for external circuitry. The borrow output (BO) produces a lowlevel pulse while the count is zero and the down input is low. Similarly, the carry output (CO) produces a low-level pulse while the count is maximum and the up input is low. 1 FUNCTION CLOCK UP CLOCK DOWN CLR LOAD Count Up H L H Count Down H L H Reset X X H X Load Preset Input X X L L LOGIC SYMBOL (14) CLR (5) UP DOWN LOAD A (4) (11) (15) (1) B (10) C (9) D CTRDIV 16 CT=0 1CT=15 2+ G1 1G2 C3 2CT=0 (1) 3D (2) (4) (8) (12) (13) (3) (2) CO BO QA QB (6) QC (7) QD Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 LOGIC DIAGRAM (13) (12) A BO CO (15) DOWN (4) SQ C RQ UP (5) (3) Q A B (1) SQ C RQ C (2) Q B (10) SQ C RQ D (9) CLR (14) SQ C RQ LOAD (11) 3 (6) Q (7) Q C D OPERATIONAL ENVIRONMENT 1 PARAMETER LIMIT UNITS Total Dose 1.0E6 rads(Si) SEU Threshold 2 108 MeV-cm2/mg SEL Threshold 120 MeV-cm2/mg Neutron Fluence 1.0E14 n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage -0.3 to 7.0 V VI/O Voltage any pin -0.3 to VDD +0.3 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C TLS Lead temperature (soldering 5 seconds) +300 C JC Thermal resistance junction to case 15 C/W II DC input current 10 mA PD2 Maximum package power dissipation 3.3 W permitted @ Tc = +125oC Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Per MIL-STD-883, method 1012.1, Section 3.4.1, PD = (Tj(max) - Tc(max) ) / jc RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 3.0 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to +125 C 4 DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS193E7 ( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C) SYMBOL DESCRIPTION CONDITION VIL Low-level input voltage 1 VDD from 3.0V to 5.5V VIH High-level input voltage 1 VDD from 3.0V to 5.5V IIN Input leakage current VIN = VDD or VSS Low-level output voltage 3 IOL = 100A VOL MIN MAX UNIT 0.3 VDD V 0.7 VDD -1 V 1 A 0.25 V VDD from 3.0V to 5.5V VOH High-level output voltage 3 IOH = -100A VDD -0.25 V VDD from 3.0V to 5.5V IOS1 Short-circuit output current 2 ,4 VO = VDD and VSS -200 200 mA -100 100 mA VDD from 4.5V to 5.5V IOS2 Short-circuit output current 2 ,4 VO = VDD and VSS VDD from 3.0V to 3.6V IOL1 Low level output current9 VIN = VDD or VSS (sink) VOL = 0.4V 8 mA 6 mA -8 mA -6 mA VDD from 4.5V to 5.5V IOL2 Low level output current9 VIN = VDD or VSS (sink) VOL = 0.4V VDD from 3.0V to 3.6V IOH1 High level output current9 VIN = VDD or VSS (source) VOH = VDD-0.4V VDD from 4.5V to 5.5V IOH2 High level output current9 VIN = VDD or VSS (source) VOH = VDD-0.4V VDD from 3.0V to 3.6V Ptotal1 Power dissipation 8, 9 CL = 50pF 1.4 mW/ MHz 0.6 mW/ MHz 10 A VDD = 4.5V to 5.5V Ptotal2 Power dissipation 8, 9 CL = 50pF VDD = 3.0V to 3.6V IDDQ Quiescent Supply Current VIN = VDD or VSS VDD from 3.0V to 5.5V 5 CIN Input capacitance 5 = 1MHz 15 pF 15 pF VDD = 0V COUT Output capacitance 5 = 1MHz VDD = 0V Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rs maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019. 8. Power dissipation specified per switching output. 9. Guaranteed by characterization, but not tested. 6 AC ELECTRICAL CHARACTERISTICS FOR UT54ACS193E2 (VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C) SYMBOL tPLH1 tPHL1 tPLH2 tPHL2 tPLH3 tPHL3 tPLH4 tPHL4 tPLH5 tPHL5 tPHL6 fMAX3 tSU1 tSU2 PARAMETER UP to Qn UP to Qn UP to CO UP to CO DOWN to BO DOWN to BO DOWN to Qn DOWN to Qn LOAD to Qn LOAD to Qn CLR to Qn Maximum clock frequency CONDITION VDD CL = 50pF 3.0V to 3.6V CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF CL = 50pF LOAD inactive setup time before UP or DOWN CL = 50pF CLR inactive setup time before UP or DOWN CL = 50pF 7 MINIMUM MAXIMUM UNIT 3 25 ns 4.5V to 5.5V 3 15 3.0V to 3.6V 4 27 4.5V to 5.5V 3 16 3.0V to 3.6V 2 17 4.5V to 5.5V 2 10 3.0V to 3.6V 2 20 4.5V to 5.5V 2 11 3.0V to 3.6V 2 17 4.5V to 5.5V 2 10 3.0V to 3.6V 2 20 4.5V to 5.5V 2 11 3.0V to 3.6V 3 27 4.5V to 5.5V 3 15 3.0V to 3.6V 4 27 4.5V to 5.5V 3 16 3.0V to 3.6V 4 27 4.5V to 5.5V 3 16 3.0V to 3.6V 4 26 4.5V to 5.5V 3 16 3.0V to 3.6V 4 25 4.5V to 5.5V 3 15 3.0V to 3.6V 80 4.5V to 5.5V 120 3.0V to 3.6V 1 4.5V to 5.5V 1 3.0V to 3.6V 1 4.5V to 5.5V 1 ns ns ns ns ns ns ns ns ns ns MHz ns ns tSU3 tH1 tH2 tH3 tW A, B, C, D setup time before LOAD CL = 50pF UP high hold time after DOWN CL = 50pF DOWN high hold time after UP A, B, C, D hold time after LOAD Minimum pulse width UP high or low DOWN high or low LOAD low CLR high CL = 50pF CL = 50pF CL = 50pF 3.0V to 3.6V 4 4.5V to 5.5V 3 3.0V to 3.6V 5 4.5V to 5.5V 3 3.0V to 3.6V 6 4.5V to 5.5V 4 3.0V to 3.6V 0 4.5V to 5.5V 0 3.0V to 3.6V 8 4.5V to 5.5V 6 Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2. 3. Maximum clock frequency fMAX is the max rate at which the device will count up or down at the given voltage. However, the user must wait the appropriate UP-to-Qn or Down-to-Qn propagation delay time in order to observe the current counter value. 8 ns ns ns ns ns Packaging Figure 1. 16-Lead Flatpack 9 Ordering Information: UT54ACS193E: SMD 5962 * ***** ** * * * Lead Finish: (Notes 1 to 2) A = Solder C = Gold X = Optional Package Type: X = 16-lead ceramic bottom-brazed dual-in-line Flatpack Class Designator: Q = QML Class Q V = QML Class V Device Type: 02 = 1 rad(Si)/sec 03 = 50 to 300 rads(Si)/sec Drawing Number: 96566 = UT54ACS193E Total Dose: (Note 3 and 4) R = 1E5 rads(Si) F = 3E5 rads(Si) G = 5E5 rads(Si) H = 1E6 rads(Si) Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory. 4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A. 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