Standard Products UT54ACS299E CMOS 8-bit Universal Shift/Storage Register with Three-State Outputs Datasheet July 2, 2013 www.aeroflex.com/Logic LOGIC SYMBOL FEATURES MR Common parallel I/O for reduced pin count Additional serial inputs and outputs for expansion Three-state outputs for bus-oriented applications Operate with outputs enabled or at high impedance Four operating modes: shift left, shift right, load and store Can be cascaded for n-bit word lengths (9) OE1 R (2) & OE2 (3) S0 (1) S1 (19) CP (12) 0.6m Commercial RadHardTM CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune DS0 (11) SRG8 3EN13 0 1 M 0 3 C4/1 (8) 1, 4D (7) 3, 4D I01 (13) 3, 4D I00 /2 5, 13 - SEU Onset LET: 95 MeV-cm2/mg (4.5V) and 48MeV-cm2/mg (3.0V) Applications: - Stacked or push-down registers - Buffer storage - Accumulator registers Output source/sink 24mA Available QML Q or V processes Standard Microcircuit Drawing 5962-06238 Package: - 20-lead flatpack Z5 6, 13 I02 Q0 Z6 (6) I03 (14) (5) I04 I05 (15) I06 (4) I07 (16) DS7 (18) 3, 4D 12, 13 Z12 (17) 2, 4D Q7 PIN DESCRIPTION DESCRIPTION Pin Names The UT54ACS299E 8-bit shift/storage register is built using Aeroflex’s Commercial RadHardTM epitaxial CMOS technology and is ideal for space applications. The UT54ACS299E is an 8-bit universal shift/storage register featuring multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two output enable (OE1, OE2) inputs can be used to choose the mode of operation listed in the function table. Additional outputs are provided for flip flops Q0, Q7 to allow easy serial cascading. A separate active low master reset (MR) is used to reset the register, overriding the select and CP inputs. All flip-flops are brought out through three-state buffers to separate I/O pins that also serve as data inputs in the parallel load mode. All other state changes are initiated by the rising edge of the clock. CP Clock Pulse Input DS0 Serial Data Input for Right Shift DS7 Serial Data Input for Left Shift S0, S1 MR OE1, OE2 1 Description Mode Select Inputs Asynchronous Master Reset Three-State Output Enable Inputs IO0-IO7 Parallel Data Inputs or Three-State Parallel Outputs Q0, Q7 Serial Outputs FUNCTION TABLE INPUTS OPERATION MR S1 S0 CP OE1 OE2 L X L X L L Q0=Q7=Low, Async Reset L L X X L L Q0=Q7=Low, Async Reset L H H X X X Q0=Q7=Low, I/O = Hiz, Async Reset H H H X X Parallel Load; IOn > Qn H L H L L Shift Right; DS0 > Q0,Q0 > Q1, etc. H L L L Shift Left; DS7 > Q7, Q7 > Q6, etc. H L L X L L Hold PINOUTS 20-Lead Flatpack Top View S0 1 20 VDD OE1 2 19 S1 OE2 3 18 IO6 IO4 4 5 17 16 DS7 Q7 IO2 6 15 IO0 7 14 IO3 Q0 MR VSS 8 9 10 13 12 11 IO1 CP DS0 2 IO7 IO5 LOGIC DIAGRAM DS7 Q7 CP D Q IO7 CD CP D Q IO6 CD CP D Q IO5 CD CP D Q IO4 CD CP D Q IO3 CD CP D Q I02 CD CP D Q IO1 CD CP D Q IO0 CD Q0 S0 S1 DS0 CP 3 MR OE1 OE2 OPERATIONAL ENVIRONMENT 1 PARAMETER LIMIT UNITS Total Dose 1.0E5 rad(Si) SEL Immune >108 MeV-cm2/mg SEU Onset LET - 3.0V SEU Onset LET - 4.5V 48 95 MeV-cm2/mg SEU Error Rate - 3.0V2 1.4E-8 8.1E-10 errors/device-day 1.0E14 n/cm2 SEU Error Rate - 4.5V 2 Neutron Fluence3 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Adam’s 90% worst case particle environment, geosynchronous orbit, 100 mils aluminum shielding. 3. Not tested, inherent of CMOS technology. ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER LIMIT (Mil only) UNITS VI/O Voltage any pin during operation -.3 to VDD +.3 V VDD Supply voltage -0.3 to 7.0 V TSTG Storage Temperature range -65 to +150 C TJ Maximum junction temperature +175 C JC Thermal resistance junction to case 20 C/W II DC input current 10 mA PD Maximum power dissipation 200 mW Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS VDD Supply voltage 3.0 to 5.5 V VIN Input voltage any pin 0 to VDD V TC Temperature range -55 to + 125 C tINRISE tINFALL Maximum input rise or fall time (VIN transitioning between VIL (max) and VIH (min)) 20 ns 4 DC ELECTRICAL CHARACTERISTICS 1 ( -55C < TC < +125C) SYMBOL PARAMETER CONDITION MIN MAX UNIT 0.3 VDD V VIL Low level input voltage2 VDD from 3.0V to 5.5V VIH High level input voltage2 VDD from 3.0V to 5.5V 0.7 VDD IIN Input leakage current VDD from 3.0V to 5.5V -1 1 A -10 10 A -600 600 mA 0.4 0.2 V 0.36 0.5 V V VIN = VDD or VSS IOZ Three-state output leakage current VDD from 3.0V to 5.5V VIN = VDD or VSS IOS Short-circuit output current 4, 5 VO = VDD or VSS VDD from 3.0V to 5.5V VOL1 Low-level output voltage 6 IOL = 12mA IOL = 100A VDD = 3.0V to 3.6V VIN = 0.7VDD or 0.3VDD VOL2 Low-level output voltage 6 IOL= 24mA -55C, 25C IOL= 24mA +125C IOL= 100A 0.2 VDD = 4.5V to 5.5V VIN = 0.7VDD or 0.3VDD VOL3 Low-level output voltage6, 7 IOL= 50mA -55C, 25C VDD = 5.5V +125C 0.8 1.0 V VIN = 0.7VDD or 0.3VDD VOH1 High-level output voltage6 IOH = -12mA IOH = -100A VDD - 0.6 VDD - 0.2 V VDD - 0.64 VDD - 0.8 VDD - 0.2 V VDD = 3.0V to 3.6V VIN = 0.7VDD or 0.3VDD VOH2 High-level output voltage6 IOH= -24mA IOH= -24mA -55C, 25C +125C IOH= -100A VDD = 4.5V to 5.5V VIN = 0.7VDD or 0.3VDD 5 VOH3 High-level output voltage6, 7 IOH= -50mA -55C, 25C VDD = 5.5V +125C VDD - 1.1 V VDD - 1.25 VIN = 0.7*VDD or 0.3*VDD VIC+ Positive input clamp voltage For input under test, IIN = 18mA 0.4 1.5 V -1.5 -0.4 V 0.5 mW/ MHz 10 80 A A 17 pF 17 pF VDD = 0.0V VIC- Negative input clamp voltage For input under test, IIN = -18mA VDD = open Ptotal Power dissipation 3, 8, 9 CL = 20pF VDD from 3.0V to 5.5V IDDQ Standby Supply Current VDD VIN = VDD or VSS, VDD = 5.5 Pre-Rad 25oC OEn = VDD Pre-Rad -55 C to +125 C OEn = VDD Post-Rad 25oC OEn = VDD Input capacitance10 = 1MHz @ 0V o CIN o VDD from 3.0V to 5.5V COUT Output capacitance10 = 1MHz @ 0V VDD from 3.0V to 5.5V Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min) and VIL(max). 3. Guaranteed by characterization. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Supplied as a design limit, but not guaranteed or tested. 6. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF-MHz. 7. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested, for VIN=VIH minimum or VIL maximum. 8. Power does not include power contribution of any CMOS output sink current. 9. Power dissipation specified per switching output. 10.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. . 6 Test Load or Equivalent1 VDD VDD 100ohms 40pf 100ohms Notes: 1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform change necessitates a deviation from the applicable test circuit. 7 AC ELECTRICAL CHARACTERISTICS1 (3.3 Volt Operation) (VDD = 3.3V 0.3V, -55C < TC < +125C) SYMBOL PARAMETER MIN MAX UNIT tPLH1 Propagation delay CP to Q0 or Q7 (shift left or right) 4.5 10.5 ns tPHL1 Propagation delay CP to Q0 or Q7 (shift left or right) 4.5 10.5 ns tPLH2 Propagation delay CP to IOn 5 14 ns tPHL2 Propagation delay CP to IOn 5 14 ns tPHL3 Propagation delay MR to Q0 or Q7 6 11 ns tPHL4 Propagation delay MR to IOn 7 15.5 ns tPZL Output enable time OE to IOn 4 10.5 ns tPZH Output enable time OE to IOn 4 10.5 ns tPLZ Output disable time OE to IOn 3 6.5 ns tPHZ Output disable time OE to IOn 3 6.5 ns tW12 Pulse width CP 5.5 ns tW22 Pulse width MR 5.5 ns tS1 Setup time; high or low; Sn to CP 3 ns tH1 Hold time; high or low; Sn to CP 0.5 ns tS2 Setup time; high or low; DSn to CP 1 ns tH2 Hold time; high or low; DSn to CP 0.5 ns tS3 Setup time; high or low; IOn to CP 1.5 ns tH3 Hold time; high or low; IOn to CP 0.5 ns tREC Recovery time MR to CP 1 ns fMAX2 Maximum frequency CP 70 Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Verified by at speed functional test. 8 MHz Propagation Delay VDD VDD/2 CP 0V tPHL1,2 tPLH1,2 VOH VDD/2 VOL Output Enable Disable Times OEn 3V Output Normally Low 3V Output Normally High tPZL VDD/2-0.2 tPLZ .2VDD + .2V .2VDD tPHZ tPZH .8VDD .8VDD - .2V VDD/2+0.2 VDD VDD/2 0V VDD/2 VDD/2 Setup and Hold Measurements VDD VDD/2 0.0V Sn or DSn or IOn tH1,2,3 tS1,2,3 VDD VDD/2 0.0V CP Input tW1 tW2 VDD VDD/2 0.0V MR tREC VOH VDD/2 VOL Data Outputs Q0, Q7, IO<0:7> tPHL3 tPHL4 9 AC ELECTRICAL CHARACTERISTICS1 (5 Volt Operation) (VDD = 5v 10%, -55C < TC < +125C) SYMBOL PARAMETER MIN MAX UNIT tPLH1 Propagation delay CP to Q0 or Q7 (shift left or right) 4 8 ns tPHL1 Propagation delay CP to Q0 or Q7 (shift left or right) 4 8 ns tPLH2 Propagation delay CP to IOn 4.5 9 ns tPHL2 Propagation delay CP to IOn 4.5 9 ns tPHL3 Propagation delay MR to Q0 or Q7 5 9 ns tPHL4 Propagation delay MR to IOn 5.5 11 ns tPZL Output enable time OE to IOn 3 7 ns tPZH Output enable time OE to IOn 3 7 ns tPLZ Output disable time OE to IOn 3 6 ns tPHZ Output disable time OE to IOn 3 6 ns tW12 Pulse width CP 5 ns tW22 Pulse width MR 5 ns tS1 Setup time; high or low; Sn to CP 2 ns tH1 Hold time; high or low; Sn to CP 0.5 ns tS2 Setup time; high or low; DSn to CP 1 ns tH2 Hold time; high or low; DSn to CP .5 ns tS3 Setup time; high or low; IOn to CP 1 ns tH3 Hold time; high or low; IOn to CP 0.5 ns tREC Recovery time MR to CP 0.5 ns fMAX2 Maximum frequency CP 90 Notes: 1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Verified by at speed functional test. 10 MHz Propagation Delay VDD VDD/2 CP 0V tPHL1,2 tPLH1,2 VOH VDD/2 VOL Output Enable Disable Times OEn 5V Output Normally Low 5V Output Normally High tPZL VDD/2-0.2 VDD VDD/2 0V VDD/2 tPLZ .2VDD + .2V .2VDD tPHZ tPZH .8VDD .8VDD - .2V VDD/2+0.2 VDD/2 Setup and Hold Measurements VDD VDD/2 0.0V Sn or DSn or IOn tH1,2,3 tS1,2,3 VDD VDD/2 0.0V CP Input tW1 tW2 VDD VDD/2 0.0V MR tREC VOH VDD/2 VOL Data Outputs Q0, Q7, IO<0:7> tPHL3 tPHL4 11 PACKAGE NOTE: 1. Seal ring is connected to VSS. 2. Units are in inches. 3. All exposed metalized areas must be gold plated 100 to 225 microinches thick and all bottom side exposed metalized areas must be gold plated to 60 microinches thick nominal. Both sides shall be over electroplated nickel undercoating 100 to 350 microinches per MIL-PRF-38535. Figure 1. 20-Lead Flatpack 12 ORDERING INFORMATION UT54ACS299E: SMD 5962 R 06238 ** * * * Lead Finish: (Notes 1 & 2) (A) = Hot Solder Dip (C) = Gold (X) = Factory Option (Gold or Solder) Case Outline: (X) = 20 lead BB FP Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 8-bit Universal Shift/Storage Register (3.0V - 5.5V) Drawing Number: 06238 Total Dose: (Note 3) (R) = 1E5 rad(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q not available without radiation hardening. QML Q and QML V not available without radiation hardening. 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