UT54ACTS630 - Aeroflex Microelectronic Solutions

Standard Products
UT54ACS630
RadHard EDAC
Datasheet
May 16, 2012
www.aeroflex.com/radhard
PIN DESCRIPTION
FEATURES
 DC operating voltage range 4.5V to 5.5V
 Input logic levels
- VIL = 30% of VCC
- VIH = 70% of VCC
 Fast propagation delay 11ns (max)
Pin Names
 m Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
S0, S1
Description
Mode Control Inputs
DBn
Bidirectional Data Bus
CBn
Bidirectional Checkbit Bus
SEF
Single Error Flag Output
DEF
Double Error Flag Output
- SEU Onset LET: >108 MeV-cm2/mg
 Standard Microcircuit Drawing 5962-06239
- QML Q and V
 Package:
- 28-lead flatpack
28-Lead Flatpack
Top View
DESCRIPTION
DEF
1
28
VDD
The UT54ACS630 is a RadHard 16-bit parallel error detection
and correction circuit. It uses a modified Hamming code to generate a 6-bit checkword from each 16-bit data word. The checkword is stored with the data word during a memory write cycle;
during a memory read cycle a 22-bit word is taken from memory
and checked for errors. Single bit errors in the data words are
flagged and corrected. Single bit errors in the checkword are
flagged, but not corrected. The position of the incorrect bit is
pinpointed, in both cases, by the 6-bit error syndrome code
which is output during the error correction cycle.
DB0
2
27
SEF
DB1
3
26
DB2
DB3
4
5
25
24
S1
S0
DB4
6
23
CB1
DB5
DB6
DB7
7
8
9
22
21
20
CB2
CB3
DB8
10
19
DB9
DB10
11
12
18
17
CB5
DB15
DB11
13
16
VSS
14
15
1
CB0
CB4
DB14
DB13
DB12
FUNCTION TABLES
CONTROL FUNCTIONS
Memory
Cycle
Checkword
S0
EDAC
Function
Data I/O
S1
Control
Error Flags
SEF
DEF
WRITE
Low
Low
Generates Checkword
Input Data
Output Checkword
Low
Low
READ
Low
High
Read Data and Checkword
Input Data
Input Checkword
Low
Low
READ
High
High
Latch and Flag Error
Latch Data
Latch Checkword
Enabled
Enabled
READ
High
Low
Correct Data Word and
Generate Syndrome Bits
Output Correction
Data
Output Syndrome
Bits
Enabled
Enabled
CHECKWORD GENERATION
Check word bit
0
X
X
CB0
CB1
CB2
CB3
CB4
CB5
1
X
2
X
X
X
X
X
X
3
X
X
4
X
X
X
X
5
6
X
X
X
X
16-bit data word
7
8
X
X
X
X
X
X
X
X
9
X
10
X
11
12
13
X
14
X
X
X
X
15
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ERROR SYNDROME CODES
Syndrome error
code
Error locations
DB
0
L
L
H
L
H
H
CB0
CB1
CB2
CB3
CB4
CB5
1
L
H
L
L
H
H
2
H
L
L
L
H
H
3
L
L
H
H
L
H
4
L
H
L
H
L
H
5
H
L
L
H
L
H
6
H
L
H
L
L
H
7
H
H
L
L
L
H
CB
8
L
L
H
H
H
L
9
L
H
L
H
H
L
10
L
H
H
L
H
L
11
H
L
H
L
H
L
12
H
H
L
L
H
L
13
L
H
H
H
L
L
14
H
L
H
H
L
L
15
H
H
L
H
L
L
0
L
H
H
H
H
H
1
H
L
H
H
H
H
2
H
H
L
H
H
H
3
H
H
H
L
H
H
4
H
H
H
H
L
H
5
H
H
H
H
H
L
ERROR FUNCTIONS
Total number of errors
Error Flags
Data Correction
16-bit data
6-bit check word
SEF
DEF
0
0
L
L
Not applicable
1
0
H
L
Correction
0
1
H
L
Correction
1
1
H
H
Interrupt
2
0
H
H
Interrupt
0
2
H
H
Interrupt
2
No
Error
H
H
H
H
H
H
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rad(Si)
SEL Immune
>108
MeV-cm2/mg
SEU Onset LET
>108
MeV-cm2/mg
Neutron Fluence2
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 6.0
V
VI/O
Voltage any pin during operation
-0.3 to VDD +0.3
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
JC
Thermal resistance junction to case
20
C/W
II
DC input current
+10
mA
PD
Maximum power dissipation

mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature Range
-55 to +125
oC
tINRISE
tINFALL
Max input rise or fall time
(VIN transitions between VIL (max) and VIH (min))
20
ns
3
DC ELECTRICAL CHARACTERISTICS 1
( VDD = 5.0V +10%; VSS = 0V, -55C < TC < +125C)
SYMBOL
PARAMETER
VIL
Low level input voltage2
VIH
High level input voltage2
IIN
Input leakage current
CONDITION
MIN
MAX
UNIT
0.3 VDD
V
0.7 VDD
VDD from 4.5V to 5.5V
V
-5
+5
A
300
300
mA
-10
+10
A
V
VIN = VDD or VSS
IOS
Short-circuit output current3,4
VO = VDD or VSS
VDD from 4.5V to 5.5V
IOZ
VOL1
Three-state output leakage current
VIN = VDD or VSS, VDD from
4.5V to 5.5V
Low-level output voltage (except DEF and
SEF)5
IOL = 16mA
0.4
IOL = 100A
0.2
VIN = VIH min or VIL max
VDD from 4.5V to 5.5V
VOH1
High-level output voltage (except DEF and
SEF)5
IOL = -16mA
VDD-0.8
IOL = -100A
VDD-0.2
V
VIN = VIH min or VIL max
VDD from 4.5V to 5.5V
VOL2
Low-level output voltage (DEF and SEF
only)3,4
IOL = 8mA
0.4
IOL = 100A
0.2
V
VIN = VIH min or VIL max
VDD from 4.5V to 5.5V
VOH2
High-level output voltage (DEF and SEF
only)5
IOL = -8mA
VDD-0.8
IOL = -100A
VDD-0.2
V
VIN = VIH min or VIL max
VDD from 4.5V to 5.5V
IDDQ
Quiescent supply current
VDD = 5.5V
Pre-Rad -55oC to +125oC
VIN = VDD or VSS
100
A
2
mA/
MHz
Post-Rad 25oC
IDD (OP)
VDD supply current operating
VIH = 5.0V
VIL = 0.0V
VDD = 5.0V
4
CL=20pF
CIN
Input capacitance6
f= 1MHz @ 0V
24
pF
24
pF
0.4
1.5
V
-1.5
-0.4
V
400
W/
MHz
VDD from 4.5V to 5.5V
COUT
Output capacitance6
f= 1MHz @ 0V
VDD from 4.5V to 5.5V
VIC+
Positive input clamp voltage
For input under test, IIN = 18mA
VDD = 0.0V
VIC-
Negative input clamp voltage
For input under test, IIN = -18mA
VDD = open
PTOTAL
Power dissipation 7, 8, 9
CL = 20pf
VDD from 4.5V to 5.5V
Notes:
1. All specifications valid for radiation dose <1E5 rad(Si) per MIL-STD-883, method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3.Not more than one output may be shorted at a time for maximum duration of one second.
4.Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density  5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
7.This value is guaranteed based on characterization data, but not tested.
8.Power does not include power contribution of any CMOS output sink current.
9.Power dissipation specified per switching output.
.
5
AC ELECTRICAL CHARACTERISTICS2
(VDD = 5.0V +/- 10%; VSS = 0V1, -55C < TC < +125C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPLH1
Propagation delay time, DB to CBn
5.5
11
ns
tPHL1
Propagation delay time, DBn to CBn
5.5
11
ns
tPLH2
Propagation delay time, S1 to DEF
3
8
ns
tPLH3
Propagation delay time, S1 to SEF
3
8
ns
tPZH
Output enable time, S0 to DBn or CBn
2
9.5
ns
tPZL
Output enable time, S0 to DBn or CBn
2
9.5
ns
tPHZ
Output disable time, S0 to DBn or CBn
3.5
8
ns
tPLZ
Output disable time, S0 to DBn or CBn
3.5
8
ns
tS
Setup time, high or low, DBn or CBn to S1
0.5
ns
tH
Hold time, high or low, DBn or CBn from S1
3.5
ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose >1E6rad(Si).
6
Propagation Delay
Input
DBn or S1
VDD
0.5VDD
0V
tPHL
tPLH
VOH
VDD/2
VOL
Output
Enable Disable Times
SO Input
tPZLn
5V Output
Normally Low
5V Output
Normally High
tPLZ
.2VDD + .2V
VDD/2-0.2
tPHZ
tPZHn
VDD/2+0.2
VDD
0.5VDD
0V
VDD/2
.2VDD
.8VDD
.8VDD - .2V
VDD/2
Set up / Hold Waveforms
VDD
0.5VDD
0.0V
DBn or CBm
Input
th
tS
S1
Input
0.0V
Test Load or Equivalent1
VDD
VDD
100ohms
40pf
100ohms
VSS
Notes
1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform
change necessitates a deviation from the applicable test circuit.
PACKAGE
Figure 1. 28-pin Ceramic Flatpack
8
ORDERING INFORMATION
UT54ACS630: SMD
5962 R 06239 **
*
*
*
Lead Finish: (Notes 1 & 2)
(A) = Hot Solder Dip
(C) = Gold
(X) = Factory Option (Gold or Solder)
Case Outline:
(X) = 28 lead BB ceramic flatpack
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(01) = EDAC
Drawing Number: 06239
Total Dose: (Note 3)
(R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact
factory.
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