Standard Products UT16MX116/117 Analog Multiplexer Datasheet November 18, 2014 www.aeroflex.com/MUX 16FEATURES INTRODUCTION The UT16MX116/117 are low voltage analog multiplexers with a convenient LVCMOS (3.3V) or CMOS digital interface set by the voltage level of the VDD_IO pin. The analog muxes have Break-Before-Make architecture with a low channel resistance. The muxes support rail-to-rail input signal levels. The multiplexer supports serial (SPI™), or asynchronous parallel interface. 16-to-1 Analog Mux 100Ω Signal paths (typical) 5V single analog supply Rail-to-Rail signal handling Asynchronous RESET input SPI™/QSPI™ and MICROWIRE™compatible serial interface (UT16MX117) Asynchronous parallel input Interface (UT16MX116) LVCMOS or CMOS compatible inputs (set by voltage of VDD_IO pin) The UT16MX116/117 operates with a single 5V(+10%) analog power supply. An external 3.3V digital voltage supply is required, for the digital circuitry. The digital I/O supply may be set to 3.3V + 10% or 5V+ 10% by the VDD_IO pin. 2kV ESD Protection (per MIL-STD-883, Method 3015.7) Operational environment: - Total ionizing dose: 300 krad(Si) - SEL immune to a LET of 110 MeV-cm2/mg - SEU immune to a LET of 62.3 MeV-cm2/mg Packaging: 28-lead Ceramic Flatpack Standard Microcircuit Drawing 5962-10237 - QML Q, QML V Digital Interface Inputs Digital Interface Logic Break-Before-Make Architecture 4 S[0] S[1] S[2] COM ... S[15] Figure 1. UT16MX116/117 Block Diagram 36-01-02-000 Ver. 1.0.0 1 Aeroflex Microelectronics Solutions - HiRel FUNCTIONAL DESCRIPTION All mux decoding (whether for the UT16MX116 or UT16MX117 device) operation utilizes a Break-Before-Make process to prevent shorting between analog data inputs during address transitions. UT16MX116: The UT16MX116 utilizes a parallel interface which operates in asynchronous mode much like discrete logic switches. During operation, the connection between COM and the S[15:0] pins are steered, asynchronously, based on the binary decoding of the A[3:0] static logic levels. The address pins A[3:0] are required to hold static levels for proper mux operation. Any change in A[3:0] pins directs the COM connection to the appropriate S[x] input after approximately 100ns propagation delay (including the Break-Before-Make delay). All bits (A[3:0]) of any address change should be received by the UT16MX116 within 18 ns of the first bit change for proper operation. The asynchronous parallel interface mode requires CS to be low for accepting a change on the address pins A[3:0]. When CS is high, the UT16MX116 disables the address pins A[3:0], as well as holding the last valid address state, thereby mitigating against any single-event upsets or transients on the address bus. UT16MX117: The UT16MX117 utilizes a serial interface that supports the standard that is compatible with MICROWIRE™, SPI™, and QSPI™. The UT16MX117 SPI™ interface can be depicted as an 8-bit serial shift register controlled by SS, clocked by the rising edge of SCLK. The 8-bit shift register is for compatibility purposes, even though this UT16MX117 serial address setting requires only 4 bits. The four LSB of the 8-bit shift register are the four bits decoding the mux address. When shifting data into the part, the MSB enters the part first. The four MSB may be set to zeroes, e.g., the 8-bit command "00001001" would set the mux to connect COM to S[9]. SPI™ Operations: The SPI™ (Serial Peripheral Interface) is implemented as a synchronous 8-bit serial shift register controlled by four pins: MOSI, MISO, SCLK, and SS. This is compatible with the SPI™/QSPI™ standard as defined by Motorola on the MC68HCxx line of microcontrollers. This SPI™ also conforms to the MICROWIRE™ interface, an SPI™ subset interface, as defined by National Semiconductor. The UT16MX117 SPI™ is always a slave device, where MOSI, SCLK, and SS are controlled by a master device. MISO output is used as receiving slave data or to daisy chain several SPI™ devices in appropriate applications. The MUX select functionality is controlled by the four LSB of the 8-bit SPI™ shift registers. When shifting, the first SCLK rising edge clocks in the MSB first. The first falling edge of the SCLK clocks out the 6th bit of the current values in the SPI™ registers, since the 7th bit already appears at the MISO at the start of a serial transmission before the first SCLK (Figures 5 and 6). Reset Function (UT16MX117 Only): The RESET pin is used to reset all internal logic circuits. RESET held low also keeps all COM and S[15:0] analog I/Os in a high impedance state. This is the recommended condition at system power-up. Asserting RESET (active low) resets all of the internal address decoding registers to 0, thus steering the COM to connect to S[0] while in the high impedance state. When RESET is deasserted (high), both COM and S[0] will come out of the high impedance state and COM will be driven by S[0]. The UT16MX117 is considered a slave SPI™ device with MOSI (Master Out Slave In) as the data input pin to the device. The data is shifted with D7 as the first bit into the shift register, and also the first bit out to the MISO (Master In Slave Out) output pin after eight clock cycles of SCLK. The signal on the SS pin defines the window when the address bits are shifted into the device. This occurs when signal on SS is low. Only when SS is high at the close of the shifting window, does the mux decoding get updated and COM is directed to the decoded S[x] input (after Break-Before-Make delay). 36-01-02-000 Ver. 1.0.0 2 Aeroflex Microelectronics Solutions - HiRel Table 1: UT16MX116 Pin Description Pin No. Name I/O Type Description 1 AVDD -- Power Analog Positive Supply1 2 NC -- -- No Connection 3 VDD_IO -- Power Digital I/O Supply1 4-11 S[15:8] Input Analog Muxed Inputs 12 GND -- Power Digital Ground 13 VDD -- Power Digital Core Supply1 14 A3 Input Digital Parallel A3 15 A2 Input Digital Parallel A2 16 A1 Input Digital Parallel A1 17 A0 Input Digital Parallel A0 18 CS Input Digital Active Low Parallel Chip Select with Internal Pull-up 19-26 S[0:7] Input Analog Muxed Inputs 27 AVSS -- Power Analog Negative Supply 28 COM Output Analog Muxed Output2 Notes: 1. For proper operation, VDD and VDD-I0 must be applied before or simultaneously with AVDD. 2. Continuous operation with low load resistance is not recommended. (See Figure 9) AVDD 1 28 COM NC 2 27 AVSS VDD_IO 3 26 S7 S15 4 25 S6 S14 5 24 S5 S13 6 23 S4 S12 7 22 S3 S11 8 21 S2 S10 9 20 S1 S9 10 19 S0 S8 11 18 CS GND 12 17 VDD 13 16 A0 A1 A3 14 15 A2 UT16MX116 Figure 2. UT16MX116 Pinout 36-01-02-000 Ver. 1.0.0 3 Aeroflex Microelectronics Solutions - HiRel Table 2: UT16MX117 Pin Description Pin No. Name I/O Type Description 1 AVDD -- Power Analog Positive Supply1 2 RESET Input Digital Active Low Reset with Internal Pull-up 3 VDD_IO -- Power Digital I/O Supply1 4-11 S[15:8] Input Analog Muxed Inputs 12 GND -- Power Digital Ground 13 VDD -- Power Digital Core Supply1 14 NC -- -- No Connection 15 SCLK Input Digital SPI™ Clock 16 MOSI Input Digital Master-out-Slave-in (Din) 17 MISO Output Digital Master-in-Slave-out (Dout) 18 SS Input Digital Active Low SPI™ Shift Control with Internal Pull-up 19-26 S[0:7] Input Analog Muxed Inputs 27 AVSS -- Power Analog Negative Supply 28 COM Output Analog Muxed Output2 Notes: 1. For proper operation, VDD and VDD-I0 must be applied before or simultaneously with AVDD. 2. Continuous operation with low load resistance is not recommended. (See Figure 9) AVDD 1 28 COM RESET 2 27 AVSS VDD_IO 3 26 S7 S15 4 25 S6 S14 5 24 S5 S13 6 23 S4 S12 7 22 S3 S11 8 21 S2 S10 9 20 S1 S9 10 19 S0 S8 GND 11 18 SS 12 17 VDD 13 16 MISO MOSI NC 14 15 SCLK UT16MX117 Figure 3. UT16MX117 Pinout 36-01-02-000 Ver. 1.0.0 4 Aeroflex Microelectronics Solutions - HiRel Table 3: UT16MX116 Truth Table 36-01-02-000 Ver. 1.0.0 CS A3 A2 A1 A0 COM 1 X X X X Previous Decide State 0 0 0 0 0 S0 0 0 0 0 1 S1 0 0 0 1 0 S2 0 0 0 1 1 S3 0 0 1 0 0 S4 0 0 1 0 1 S5 0 0 1 1 0 S6 0 0 1 1 1 S7 0 1 0 0 0 S8 0 1 0 0 1 S9 0 1 0 1 0 S10 0 1 0 1 1 S11 0 1 1 0 0 S12 0 1 1 0 1 S13 0 1 1 1 0 S14 0 1 1 1 1 S15 5 Aeroflex Microelectronics Solutions - HiRel OPERATIONAL ENVIRONMENT PARAMETER LIMIT UNITS Total Ionizing Dose (TID) 300 krad(Si) Single Event Latchup (SEL) >110 MeV-cm2/mg Single Event Upset Threshold (SEU) >62.3 MeV-cm2/mg PARAMETER LIMITS ABSOLUTE MAXIMUM RATINGS1 SYMBOL AVDD Analog Positive Supply Voltage 7.5V AVSS Analog Negative Supply Voltage -0.3V Digital I/O Supply Voltage (referenced to GND) 6.5V Digital Supply Voltage (referenced to GND) 4.5V VDD_IO VDD PD Static Power Dissipation TJ Junction Temperature -55oC to +130oC TSTG Storage Temperature -65oC to +150oC ESDHBM Electrostatic Discharge using Human Body Model 150 mW 2kV Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS AVDD Analog Positive Supply Voltage 4.5V to 5.5V AVSS Analog Negative Supply Voltage 0.0V VDD_IO Digital I/O Supply Voltage (referenced to GND) 3.0V to 5.5V VDD Digital Supply Voltage (referenced to GND) 3.0V to 3.6V VIN Analog Switch Input Voltage AVSS to AVDD VI Digital Input Voltage 0V to VDD_IO TC Case Operating Temperature Range -55oC to +125oC TJ Junction Operating Temperature1 -55oC to +130oC Notes: 1. Thermal resistance, ΘJC, of juncition-to-case is 4.8o C/W. 36-01-02-000 Ver. 1.0.0 6 Aeroflex Microelectronics Solutions - HiRel DC ELECTRICAL CHARACTERISTICS 1 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, VDD_IO=3.0V to 5.5V, GND=0V; -55°C < TC < +125°C) SYMBOL VIL PARAMETER Digital input low CONDITION VDD_IO = 3.0V MIN TYP -0.3 VDD_IO = 4.5V VIH VOL Digital input high Digital output low (UT16MX117) MAX UNIT 0.8 V 1.35 V VDD_IO = 3.0V 2.0 V VDD_IO = 4.5V 3.15 V VDD_IO = 3.0V 0.2 V 0.4 V 0.5 V IOL = 100μA VDD_IO = 3.0V IOL = 2mA VDD_IO = 4.5V IOL = 2mA VOH Digital output high (UT16MX117) VDD_IO = 3.0V IOH = -100μA 2.8 V VDD_IO = 3.0V IOH = -2mA 2.4 V VDD_IO = 4.5V 3.7 V IOH = -2mA 300 Ω -1.6 1.6 μA -1.0 -380 1.0 -20 μΑ μΑ -1.0 -25 1.0 25 μΑ μΑ RON On resistance VIN= AVSS to AVDD VCOM = VIN - 0.3V 40 IOFF Analog I/O leakage current AVDD = 5.5V VDD = 3.6V VDD_IO = 5.5V VIN = AVSS or AVDD (switch IIL off)2 Digital input current low VDD_IO = 5.5V VIL = GND LVCMOS / CMOS inputs Inputs with pull-up IIH Digital input current high VDD_IO = 5.5V VIH = VDD_IO LVCMOS / CMOS inputs Inputs with pull-up 36-01-02-000 Ver. 1.0.0 145 7 Aeroflex Microelectronics Solutions - HiRel DC ELECTRICAL CHARACTERISTICS 1 (Cont’d) (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, VDD_IO=3.0V to 5.5V, GND=0V; -55°C < TC < +125°C) SYMBOL PARAMETER QIDD Quiescent analog supply current CONDITION AVDD = 5.5V VDD = 3.6V VDD_IO = 5.5V VIH = VDD_IO MIN TYP MAX UNIT 10 μΑ 2.2 mA VIL = GND QIDD_IO_CMOS Quiescent digital I/O supply current (CMOS) AVDD = 5.5V VDD = 3.6V VDD_IO = 5.5V VIH = VDD_IO VIL = GND QIDD_IO_LVCMOS QIDD_VDD Quiescent digital I/O supply current (LVCMOS) AVDD = 5.5V VDD = 3.6V VDD_IO = 3.6V VIH = VDD_IO VIL = GND 2.0 μΑ Quiescent digital supply current AVDD = 5.5V VDD = 3.6V VDD_IO = 5.5V VIH = VDD_IO VIL = GND 40 μΑ Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. This parameter cannot be tested on COM for the UT16MX116 device because the pin is continuously on. 36-01-02-000 Ver. 1.0.0 8 Aeroflex Microelectronics Solutions - HiRel AC ELECTRICAL CHARACTERISTICS 1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, VDD_IO=3.0V to 5.5V, GND=0V-55°C < TC < +125°C) SYMBOL TYP MAX UNIT FIN=1MHz @ 0V 10 20 pF Input digital capacitance3 FIN=1MHz @ 0V 46 55 pF COUT Output capacitance at COM3 FIN=1MHz @ 0V 28 40 pF OISO Off isolation feed through attenuation RL=600Ω -80 dB CIN PARAMETER CONDITION Input analog capacitance MIN 3 (switch off) CIN_DIGITAL CL=50pF FIN=1kHz sine wave (switch off)4 BW Bandwidth (frequency XTALK2 RSOURCE = 50Ω RL = 2.2MΩ CL = 12pF VIN = 1Vp-p response)4 Cross talk 4 (between any 2 channels) tS THD RL=1kΩ CL=50pF FIN=1kHz sine wave Settling time of output at COM Within 1% of final output 4 voltage within 1% of final output voltage RL=100kΩ CL=50pF Total Harmonic Distortion4 RL=1kΩ CL=50pF FIN=1MHz sine wave VIN=5Vp-p 51 MHz -80 dB 120 ns 5.0 % Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 9) 3. Parameters guaranteed by characterization. 4. Parameters guaranteed by design. 36-01-02-000 Ver. 1.0.0 9 Aeroflex Microelectronics Solutions - HiRel TIMING CHARACTERISTICS (UT16MX116)1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, VDD_IO=3.0V to 5.5V, GND=0V; -55°C < TC < +125°C) SYMBOL PARAMETER tPROP_S Propagation delay of analog input (S[x]) to analog output (COM) measured at 50% RT=50Ω Propagation delay of any changes in the digital inputs (A[3:0], CS, SS) affecting the analog output (COM) RT=50Ω CL=50pF See Figures 4 & 10 tMUX Mux decoding time RT=50Ω CL=50pF See Figures 4 & 10 tBBM Break-Before-Make-Delay RT=50Ω CL=50pF See Figures 4 & 10 15 tAS1 The minimum amount of time required for the address signals (A[3:0]) to be stable before the falling edge of CS3 See Figure 4 3.0 ns tAS2 The minimum amount of time required for the address signals (A[3:0]) to be stable after the rising edge of CS3 See Figure 4 5.0 ns tPROP_D CONDITION MIN TYP MAX UNIT 25 ns 140 ns 50 ns 90 ns CL=50pF See Figures 8 & 10 25 Notes: . 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 9) 3. Parameters guaranteed by design. 36-01-02-000 Ver. 1.0.0 10 Aeroflex Microelectronics Solutions - HiRel TIMING CHARACTERISTICS (UT16MX117)1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, VDD_IO=3.0V to 5.5V, GND=0V; -55°C < TC < +125°C) SYMBOL PARAMETER MAX UNIT tPROP_S Propagation delay of analog input (S[x]) to analog output (COM) measured at 50% RT=50Ω 25 ns Propagation delay of any changes in the digital inputs (A[3:0], CS, SS) affecting the analog output (COM) RT=50Ω CL=50pF 140 ns tMUX Mux decoding time RT=50Ω CL=50pF See Figures 5 & 10 50 ns tBBM Break-Before-Make-Delay RT=50Ω CL=50pF See Figures 5 & 10 90 ns tPZLH Output enable time from HiZ to low or high once RESET is pulled low RT=50Ω CL=50pF See Figures 7 & 10 90 ns tPLHZ Output disable time from low or high to HiZ once RESET is pulled high RT=50Ω 55 ns fSCLK SCLK frequency See Figure 5 2.0 MHz tH SCLK high time See Figure 5 190 ns tL SCLK low time See Figure 5 190 ns tSSU First SCLK setup time (for shifting window) See Figure 5 6.0 ns tSSH Last SCLK hold time (for shifting window) See Figure 5 10 ns tSU Data in (MOSI) setup time wrt rising edge SCLK See Figure 5 3.0 ns tHD Data in (MOSI) hold time wrt rising edge SCLK See Figure 5 5.0 ns tDO Data out (MISO) valid (after falling edge of SCLK) CL=50pF See Figure 5 43 ns tDR Data out (MISO) rise time 10-90% VDD_IO CL=50pF 70 ns tDF Data out (MISO) fall time 10-90% VDD_IO CL=50pF 70 ns tPROP_D CONDITION MIN TYP CL=50pF See Figures 8 & 10 25 See Figures 5 & 10 15 CL=50pF See Figures 7 & 10 Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 9) 36-01-02-000 Ver. 1.0.0 11 Aeroflex Microelectronics Solutions - HiRel Timing Diagrams Multiplexer Asynchronous Parallel Timing (UT16MX116) tAS2 tAS1 tAS1 VDD_IO 50% GND CS A[3:0] Am Valid AnValid VDD_IO 50% GND ApValid tCYCLE tCYCLE S[x] = Analog Inputs tPROP_D tMUX COM (Previous) tPROP_D tBBM HiZ tMUX COM = S[Am Valid] tPROP_D tMUX tBBM HiZ COM = S[An Valid] tBBM HiZ COM = S[Ap Valid] Note: 1. CS may be held in a continuous low state, holding CS high provides protection for false address change. 2. tCYCLE is the minimum cycle time between the falling edges of CS and/or any address changes. If tCYCLE is shorter than tPROP_D, an addressing error may occur. 3. All bits (A[3:0]) of any address change should be received by the UT16MX116 within 18ns of the first bit change for proper operation. Figure 4. UT16MX116 Timing Diagram 36-01-02-000 Ver. 1.0.0 12 Aeroflex Microelectronics Solutions - HiRel Multiplexer Serial Timing (UT16MX117) tSSH tSSU VDD_IO 50% GND SS tH tL VDD_IO 50% GND SCLK tHD tSU Bit 7 MSB MOSI Bit 6 Bit 1 Bit 0 LSB S[x] = Analog Inputs tPROP_D tMUX COM (Previous) COM MISO (MOSI previous) HiZ COM (Previous) Bit 7 MSB Bit 6 COM (MOSI[3:0]) VDD_IO 50% GND Bit 7 (MOSI Current) Bit 0 LSB Bit 1 tBBM tDO Figure 5. UT16MX117 Timing Diagram SPI™Protocol (UT16MX117) Start of serial transmission End of serial transmission SS SCLK MOSI (input) Bit 7 In MSB MISO Bit 7 (MOSI previous) Out Bit 6 In Bit 6 Out Bit 5 In Bit 5 Out Bit 4 In Bit 4 Out Bit 3 In Bit 3 Out Bit 2 In Bit 2 Out Bit 1 In Bit 1 Out Bit 0 Out Bit 7 Out (MOSI current) SPI register applies, MUX switches after TMUX delay S[x] COM Bit 0 In LSB COM (Previous) COM (MOSI[3:0]) Note: 1. See figure 5, Multiplexer Serial Timing (UT16MX117), for detailed timing. Figure 6. SPI™ Protocol Timing 36-01-02-000 Ver. 1.0.0 13 Aeroflex Microelectronics Solutions - HiRel Multiplexer RESET Enable/Disable Timing (UT116MX117) VDD_IO 50% GND RESET tPZLH tPLHZ HiZ COM, S[x] HiZ COM, S[0] Note: 1. S[x] represents the analog signal channel connected to COM prior to the falling edge of RESET. Figure 7. RESET Timing Diagram (UT116MX117 only) Multiplexer Analog Timing (UT16MX116/117) AVDD 50% S[x] AVSS tPROP_S tPROP_S AVDD 50% COM AVSS Note: 1. S[x] represents the analog signal channel connected to COM while in active mode of all device types with the address already set and all digital inputs held constant. Figure 8. Analog Timing Diagram (Used for UT16MX116/117) 36-01-02-000 Ver. 1.0.0 14 Aeroflex Microelectronics Solutions - HiRel Minimum Multiplexer Total Path Resistance (UT16MX116/117) Address/SPI TM Pins 4 S[0] S[1] S[2] R0 R1 R2 • • • UT16MX116 UT16MX117 COM S[13] S[14] S[15] R13 R14 R15 L O A D RL Ri + RL > 500Ω (0 < i < 15) Note: 1. Continuous DC operation on any single channel where Ri + RL < 500Ω may affect device reliability and performance. Aeroflex does not guarantee product reliability and performance where Ri + RL < 500Ω and the device operates continuously in a DC bias configuration. Figure 9. Minimum Total Path Resistance for Continuous DC Operation on Any Single Channel Multiplexer Load Conditions for Test (UT16MX116/117) Address/SPI TM Pins 4 S[0] S[1] S[2] . . . UT16MX116 UT16MX117 RT = 50 Ω Test Point COM CL = 50 pF S[13] S[14] S[15] Figure 10. UT16MX116/117 Test Circuit 36-01-02-000 Ver. 1.0.0 15 Aeroflex Microelectronics Solutions - HiRel PACKAGING Figure 11. 28-Lead Ceramic Flat Package 36-01-02-000 Ver. 1.0.0 16 Aeroflex Microelectronics Solutions - HiRel TRADEMARKS: SPI™ /QSPI™ are trademarks of Motorola, Inc. MICROWIRE™ is a trademark of National Semiconductor 36-01-02-000 Ver. 1.0.0 17 Aeroflex Microelectronics Solutions - HiRel ORDERING INFORMATION UT16MX116/117 ANALOG MULTIPLEXER UT ***** ** * * * * Lead Finish (Note 1): (C) = Gold Screening (Note 2 and 3): (P) = Prototype Flow (C) = HiRel Flow Package Type: (X) = 28-pin CFP ceramic flatpack TID Tolerance: (-) = None Device Type: (16) = Asychronous Parallel (17) = Serial (SPI™) Generic Part Number: (16MX1) = 16:1 MUX Notes: 1. Lead finish is "C" (Gold) only. 2. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25°C only. Lead finish is Gold "C" only. Radiation neither tested nor guaranteed. 3. HiRel Flow per Aeroflex Manufacturing Flows Document. 36-01-02-000 Ver. 1.0.0 18 Aeroflex Microelectronics Solutions - HiRel UT16MX116/117 ANALOG MULTIPLEXER: SMD 5962 * 10237 ** * * * Lead Finish: (Note 1) (C) = Gold Case Outline: (X) = 28-pin CFP ceramic flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type: (Note 2) (01) = Serial (SPITM) (03) = Asynchronous Parallel (04) = Asynchronous Parallel manufactured to QML-Q + Flow Drawing Number:10237 Total Dose: (R) = 100 krad(Si) (F) = 300 krad(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish is "C" (Gold) only. 2. Aeroflex's Q + Flow, as defined in Section 4.2.1d of SMD, provides QML-Q product through the SMD that is manufactured with Aeroflex's standard QML-V flow. Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel This product is controlled for export under the Export Administration Regulations (EAR). A license from the U.S. Government is required prior to the export of this product from the United States. www.aeroflex.com/HiRel Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. 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