Standard Products UT16MX113/114/115 Analog Multiplexer Data Sheet September 7, 2012 www.aeroflex.com/MUX FEATURES INTRODUCTION The UT16MX113/114/115 are low voltage analog multiplexers with a convenient LVCMOS (3.3V) digital interface. The analog muxes have Break-Before-Make architecture with a low channel resistance. The muxes support rail-to-rail input signal levels. The multiplexer supports serial (SPI™), or parallel (asynchronous or synchronous) interface. 16-to-1 Analog Mux 100Signal paths (typical) 5V single analog supply Rail-to-Rail signal handling Asynchronous RESET input SPI™/QSPI™ and MICROWIRE™ compatible serial interface (UT16MX115) Asynchronous parallel input Interface (UT16MX113) Synchronous parallel input Interface (UT16MX114) LVCMOS/LVTTL compatible inputs 2kV ESD Protection (per MIL-STD-883, Method 3015.7) Operational environment: - Total ionizing dose: 300 krad(Si) The UT16MX113/114/115 operates with a single 5V (+10%) analog power supply. An external 3.3V digital voltage supply is required, for the digital circuitry and the digital I/O. - SEL immune to a LET of 110 MeV-cm2/mg - SEU immune to a LET of 62.3 MeV-cm2/mg Packaging: 28-Lead Ceramic Flatpack Standard Microcircuit Drawing 5962-10236 - QML Q, QML V Digital Interface Inputs Digital Interface Logic Break-Before-Make Architecture 4 S[0] S[1] S[2] COM ... S[15] Figure 1. UT16MX113/114/115 Block Diagram 1 FUNCTIONAL DESCRIPTION All mux decoding (whether for the UT16MX113, UT16MX114, or UT16MX115 device) operation utilizes a Break-Before-Make process to prevent shorting between analog inputs during address transitions. UT16MX113: The UT16MX113 utilizes a parallel interface which operates in asynchronous mode much like discrete logic switches. During operation, the connection between COM and the S[15:0] pins are steered, asynchronously, based on the binary decoding of the A[3:0] static logic levels. The address pins A[3:0] are required to hold static levels for proper mux operation. Any change in A[3:0] pins directs the COM connection to the appropriate S[x] input after approximately 100ns propagation delay (including the Break-Before-Make delay). All bits (A[3:0]) of any address change should be received by the UT16MX113 within 18 ns of the first bit change for proper operation. The asynchronous parallel interface mode requires CS to be low for accepting a change on the address pins A[3:0]. When CS is high, the UT16MX113 disables the address pins A[3:0], as well as holding the last valid address state, thereby mitigating against any single-event upsets or transients on the address bus. UT16MX114: The UT16MX114 utilizes a parallel interface which operates in a synchronous mode which utilizes the PLATCH input as the latching clock. Upon rising edge of PLATCH, logic level at the A[3:0] pins will be registered and retained internally to decode the mux. Based on the values of the A[3:0] pins, COM is connected to the appropriate S[x] input after approximately 100ns propagation delay (including the Break-Before-Make delay). UT16MX115: The UT16MX115 utilizes a serial interface that supports the standard that is compatible with MICROWIRE™, SPI™, and QSPI™. The UT16MX115 SPI™ interface can be depicted as an 8-bit serial shift register controlled by SS, clocked by the rising edge of SCLK. The 8-bit shift register is for compatibility purposes, even though this UT16MX115 serial address setting requires only 4 bits. The four LSB of the 8-bit shift register are the four bits decoding the mux address. When shifting data into the part, the MSB enters the part first. The four MSB may be set to zeroes, e.g., the 8-bit command "00001001" would set the mux to connect COM to S[9]. into the device. This occurs when signal on SS is low. Only when SS is high at the close of the shifting window, does the mux decoding get updated and COM is directed to the decoded S[x] input (after Break-Before-Make delay). SPI™ Operations: The SPI™ (Serial Peripheral Interface) is implemented as a synchronous 8-bit serial shift register controlled by four pins: MOSI, MISO, SCLK, and SS. This is compatible with the SPI™/QSPI™ standard as defined by Motorola on the MC68HCxx line of microcontrollers. This SPI™ also conforms to the MICROWIRE™ interface, an SPI™ subset interface, as defined by National Semiconductor. The UT16MX115 SPI™ is always a slave device, where MOSI, SCLK, and SS are controlled by a master device. MISO output is used as receiving slave data or to daisy chain several SPI™ devices in appropriate applications. The MUX select functionality is controlled by the four LSB of the 8-bit SPI™ shift registers. When shifting, the first SCLK rising edge clocks in the MSB first. The first falling edge of the SCLK clocks out the 6th bit of the current values in the SPI™ registers, since the 7th bit already appears at the MISO at the start of a serial transmission before the first SCLK (Figures 7 and 8). Reset Function (UT16MX114/115 Only): The RESET pin is used to reset all internal logic circuits. RESET held low also keeps all COM and S[15:0] analog I/Os in a high impedance state. This is the recommended condition at system power-up. Asserting RESET (active low) resets all of the internal address decoding registers to 0, thus steering the COM to connect to S[0] while in the high impedance state. When RESET is deasserted (high), both COM and S[0] will come out of the high impedance state and COM will be driven by S[0]. The UT16MX115 is considered a slave SPI™ device with MOSI (Master Out Slave In) as the data input pin to the device. The data is shifted with D7 as the first bit into the shift register, and also the first bit out to the MISO (Master In Slave Out) output pin after eight clock cycles of SCLK. The signal on the SS pin defines the window when the address bits are shifted 2 Table 1: UT16MX113 Pin Description Pin No. Name I/O Type Description 1 AVDD -- Power Analog Positive Supply1 2 NC -- -- No Connection 3 NC -- -- No Connection 4-11 S[15:8] Input Analog Muxed Inputs 12 GND -- Power Digital Ground 13 VDD -- Power Digital Positive Supply1 14 A3 Input Digital Parallel A3 15 A2 Input Digital Parallel A2 16 A1 Input Digital Parallel A1 17 A0 Input Digital Parallel A0 18 CS Input Digital Active Low Parallel Chip Select with Internal Pull-up 19-26 S[0:7] Input Analog Muxed Inputs 27 AVSS -- Power Analog Negative Supply 28 COM Output Analog Muxed Output2 Notes: 1. For proper operation, VDD must be applied before or simultaneously with AVDD. 2. Continuous operation with low load resistance is not recommended. (See Figure 11) AVDD 1 28 COM NC 2 27 AVSS NC 3 26 S7 S15 4 25 S6 S14 5 24 S5 S13 6 23 S4 S12 7 22 S3 S11 8 21 S2 S10 9 20 S1 S9 10 19 S0 S8 11 18 CS GND 12 17 A0 VDD 13 16 A1 A3 14 15 A2 UT16MX113 Figure 2. UT16MX113 Pinout 3 Table 2: UT16MX114 Pin Description Pin No. Name I/O Type Description 1 AVDD -- Power Analog Positive Supply1 2 RESET Input Digital Active Low Reset with Internal Pull-up 3 PLATCH Input Digital Parallel Latch with Internal Pull-down 4-11 S[15:8] Input Analog Muxed Inputs 12 GND -- Power Digital Ground 13 VDD -- Power Digital Positive Supply1 14 A3 Input Digital Parallel A3 15 A2 Input Digital Parallel A2 16 A1 Input Digital Parallel A1 17 A0 Input Digital Parallel A0 18 NC -- -- No Connection 19-26 S[0:7] Input Analog Muxed Inputs 27 AVSS -- Power Analog Negative Supply 28 COM Output Analog Muxed Output2 Notes: 1. For proper operation, VDD must be applied before or simultaneously with AVDD. 2. Continuous operation with low load resistance is not recommended. (See Figure 11). AVDD 1 28 COM RESET 2 27 AVSS PLATCH 3 26 S7 S15 4 25 S6 S14 5 24 S5 S13 6 23 S4 S12 7 22 S3 S11 8 21 S2 S10 9 20 S1 S9 10 19 S0 S8 11 18 NC GND 12 17 A0 VDD 13 16 A1 A3 14 15 A2 UT16MX114 Figure 3. UT16MX114 Pinout 4 Table 3: UT16MX115 Pin Description Pin No. Name I/O Type Description 1 AVDD -- Power Analog Positive Supply1 2 RESET Input Digital Active Low Reset with Internal Pull-up 3 NC -- -- No Connection 4-11 S[15:8] Input Analog Muxed Inputs 12 GND -- Power Digital Ground 13 VDD -- Power Digital Positive Supply1 14 NC -- -- No Connection 15 SCLK Input Digital SPI™ Clock 16 MOSI Input Digital Master-out-Slave-in (Din) 17 MISO Output Digital Master-in-Slave-out (Dout) 18 SS Input Digital SPI™ Shift Control with Internal Pull-up 19-26 S[0:7] Input Analog Muxed Inputs 27 AVSS -- Power Analog Negative Supply 28 COM Output Analog Muxed Output2 Notes: 1. For proper operation, VDD must be applied before or simultaneously with AVDD. 2. Continuous operation with low load resistance is not recommended. (See Figure 11) AVDD 1 28 COM RESET 2 27 AVSS NC 3 26 S7 S15 4 25 S6 S14 5 24 S5 S13 6 23 S4 S12 7 22 S3 S11 8 21 S2 S10 9 20 S1 S9 10 19 S0 S8 11 18 SS GND 12 17 MISO VDD 13 16 MOSI NC 14 15 SCLK UT16MX115 Figure 4. UT16MX115 Pinout 5 Table 4: UT16MX113 Truth Table CS A3 A2 A1 A0 COM 1 X X X X Previous Decide State 0 0 0 0 0 S0 0 0 0 0 1 S1 0 0 0 1 0 S2 0 0 0 1 1 S3 0 0 1 0 0 S4 0 0 1 0 1 S5 0 0 1 1 0 S6 0 0 1 1 1 S7 0 1 0 0 0 S8 0 1 0 0 1 S9 0 1 0 1 0 S10 0 1 0 1 1 S11 0 1 1 0 0 S12 0 1 1 0 1 S13 0 1 1 1 0 S14 0 1 1 1 1 S15 6 Table 5: UT16MX114 Truth Table RESET PLATCH A3 A2 A1 A0 COM 0 X X X X X Tri-State (S[15:0] and COM) 1 Rising Edge 0 0 0 0 S0 1 Rising Edge 0 0 0 1 S1 1 Rising Edge 0 0 1 0 S2 1 Rising Edge 0 0 1 1 S3 1 Rising Edge 0 1 0 0 S4 1 Rising Edge 0 1 0 1 S5 1 Rising Edge 0 1 1 0 S6 1 Rising Edge 0 1 1 1 S7 1 Rising Edge 1 0 0 0 S8 1 Rising Edge 1 0 0 1 S9 1 Rising Edge 1 0 1 0 S10 1 Rising Edge 1 0 1 1 S11 1 Rising Edge 1 1 0 0 S12 1 Rising Edge 1 1 0 1 S13 1 Rising Edge 1 1 1 0 S14 1 Rising Edge 1 1 1 1 S15 7 OPERATIONAL ENVIRONMENT PARAMETER LIMIT UNITS Total Ionizing Dose (TID) 300 krad(Si) Single Event Latchup (SEL) >110 MeV-cm2/mg Single Event Upset Threshold (SEU) >62.3 MeV-cm2/mg ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER LIMITS AVDD Analog Positive Supply Voltage 7.5V AVSS Analog Negative Supply Voltage -0.3V VDD Digital Supply Voltage (referenced to GND) 4.5V PD Static Power Dissipation TJ Junction Temperature -55oC to +130oC TSTG Storage Temperature -65oC to +150oC ESDHBM Electrostatic Discharge using Human Body Model 150mW 2kV Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS AVDD Analog Positive Supply Voltage 4.5V to 5.5V AVSS Analog Negative Supply Voltage 0.0V VDD Digital Supply Voltage (referenced to GND) VIN Analog Switch Input Voltage VI Digital Input Voltage TC Case Operating Temperature Range -55oC to + 125oC TJ Junction Operating Temperature1 -55oC to + 130oC Notes: 1. Thermal resistance, JC, of junction-to-case is 4.8oC/W 8 3.0V to 3.6V AVSS to AVDD 0V to VDD DC ELECTRICAL CHARACTERISTICS 1 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, GND=0V; -55C < TC < +125C) SYMBOL PARAMETER CONDITION MIN VIL Digital input low VDD = 3.0V -0.3 VIH Digital input high VDD = 3.0V 2.0 VOL Digital output low (UT16MX115) VDD = 3.0V TYP MAX UNIT 0.8 V V 0.2 V 0.4 V IOL = 100A VDD = 3.0V IOL = 2mA VOH Digital output high (UT16MX115) VDD = 3.0V IOH = -100A 2.8 V VDD = 3.0V 2.4 V IOH = -2mA 300 -1.6 1.6 A -1.0 -380 -5.0 1.0 -20 5.0 -1.0 -60 20 1.0 60 380 10 250 RON On resistance VIN = AVSS to AVDD VCOM = VIN - 0.3V 40 IOFF Analog I/O leakage current AVDD = 5.5V VDD = 3.6V VIN = AVSS or AVDD 2 (switch off) IIL Digital input current low VDD = 3.6V VIL = GND LVCMOS / LVTTL inputs Inputs with pull-up Inputs with a pull-down IIH Digital input current high VDD = 3.6V VIH = VDD LVCMOS / LVTTL inputs pull-up3 Inputs with Inputs with a pull-down QIDD Quiescent analog supply current 145 AVDD = 5.5V VDD = 3.6V VIH = VDD VIL = GND QIDD_VDD Quiescent digital supply current AVDD = 5.5V VDD = 3.6V VIH = VDD VIL = GND Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. This parameter cannot be tested on COM for the UT16MX113 device because the pin is continuously on. 3. This parameter tested with PLATCH held low on the UT16MX114 device. 9 AC ELECTRICAL CHARACTERISTICS 1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, GND=0V; -55C < TC < +125C) SYMBOL TYP MAX UNIT FIN=1MHz @ 0V 40 50 pF Input digital capacitance3 FIN=1MHz @ 0V 46 55 pF COUT Output capacitance at COM3 FIN=1MHz @ 0V 68 80 pF OISO Off isolation feed through attenuation RL=600 CL=50pF -80 dB (switch off)4 FIN=1kHz sine wave CIN PARAMETER Input capacitance (switch off) CIN_DIGITAL BW Bandwidth THD RSOURCE = 50 RL = 2.2M CL = 12pF VIN = 1Vp-p 4 51 MHz -80 dB Settling time of output at COM Within 1% of final output voltage 4 R =100k within 1% of final output voltage L CL=50pF 120 ns Total Harmonic Distortion4 5.0 % Cross talk (between any 2 channels) tS MIN 3 (frequency response) XTALK2 CONDITION 4 RL=1k CL=50pF FIN=1kHz sine wave RL=1k CL=50pF FIN=1MHz sine wave VIN=5Vp-p Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 11) 3. Parameters guaranteed by characterization. 4. Parameters guaranteed by design. 10 DIGITAL TIMING CHARACTERISTICS (UT16MX113)1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, GND=0V; -55C < TC < +125C) SYMBOL PARAMETER tPROP_S Propagation delay of analog input (S[x]) to analog output (COM) measured at 50% CONDITION MIN RT=50 TYP MAX UNIT 25 ns 140 ns 50 ns 90 ns CL=50pF See Figures 10 & 12 25 Propagation delay of any changes in the digital inputs (A[3:0], CS, PLATCH, SS) affecting the analog output (COM) RT=50 CL=50pF See Figures 5 & 12 tMUX Mux decoding time RT=50 CL=50pF See Figures 5 & 12 tBBM Break-Before-Make-Delay RT=50 CL=50pF See Figures 5 & 12 15 tAS1 The minimum amount of time required for the address signals (A[3:0]) to be stable before the falling edge of CS3 See Figure 5 3.0 ns tAS2 The minimum amount of time required for the address signals (A[3:0]) to be stable after the rising edge of CS3 See Figure 5 5.0 ns tPROP_D Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 11) 3. Guaranteed by design. 11 DIGITAL TIMING CHARACTERISTICS (UT16MX114)1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, GND=0V; -55C < TC < +125C) SYMBOL PARAMETER tPROP_S Propagation delay of analog input (S[x]) to analog output (COM) measured at 50% tPROP_D tMUX CONDITION MIN RT = 50 TYP MAX UNIT 25 ns 140 ns 50 ns 90 ns 90 ns 55 ns CL = 50pF See Figures 10 & 12 Propagation delay of any changes in the digital inputs (A[3:0], CS, PLATCH, SS) affecting the analog output (COM) RT = 50 CL = 50pF See Figures 6 & 12 Mux decoding time RT = 50 25 CL = 50pF See Figures 6 & 12 tBBM Break-Before-Make-Delay RT = 50 15 CL = 50pF See Figures 6 & 12 tPZLH tPLHZ tLSU tLHD Output enable time from HiZ to low or high once RESET is pulled high RT = 50 Output disable time from low or high to HiZ once RESET is pulled low RT = 50 Address setup time wrt rising edge PLATCH RT = 50 Address hold time wrt rising edge PLATCH CL = 50pF See Figures 9 & 12 CL = 50pF See Figures 9 & 12 5.0 ns 10 ns CL = 50pF See Figures 6 & 12 RT = 50 CL = 50pF See Figures 6 & 12 Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 11) 12 DIGITAL TIMING CHARACTERISTICS (UT16MX115)1,2 (AVDD=5.0V + 0.5V, VDD=3.3V + 0.3V, GND=0V; -55C < TC < +125C) SYMBOL PARAMETER tPROP_S Propagation delay of analog input (S[x]) to analog output (COM) measured at 50% RT=50 CL=50pF See Figures 10 & 12 tPROP_D Propagation delay of any changes in the digital inputs (A[3:0], CS, PLATCH, SS) affecting the analog output (COM) RT=50 CL=50pF See Figures 7 & 12 Mux decoding time RT=50 tMUX CONDITION MIN 25 TYP MAX UNIT 25 ns 140 ns 50 ns 90 ns CL=50pF See Figures 7 & 12 15 tBBM Break-Before-Make-Delay RT=50 CL=50pF See Figures 7 & 12 tPZLH Output enable time from HiZ to low or high once RESET is pulled high RT=50 CL=50pF See Figures 9 & 12 90 ns tPLHZ Output disable time from low or high to HiZ once RESET is pulled low RT=50 CL=50pF See Figures 9 & 12 55 ns fSCLK SCLK frequency See Figure 7 2.0 MHz tH SCLK high time See Figure 7 190 ns tL SCLK low time See Figure 7 190 ns tSSU First SCLK setup time (for shifting window) See Figure 7 7.0 ns tSSH Last SCLK hold time (for shifting window) See Figure 7 10 ns tSU Data In (MOSI) setup time wrt rising edge SCLK See Figure 7 3.0 ns tHD Data In (MOSI) hold time wrt rising edge SCLK See Figure 7 5.0 ns tDO Data out (MISO) valid (after falling edge of SCLK) CL=50pF See Figure 7 43 ns tDR Data out (MISO) rise time 10-90% VDD CL=50pF 30 ns tDF Data out (MISO) fall time 10-90% VDD CL=50pF 20 ns Notes: 1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured (see ordering information). 2. Continuous operation with low load resistance is not recommended. (See Figure 11) 13 Timing Diagrams Multiplexer Asynchronous Parallel Timing (UT16MX113) tAS1 tAS2 tAS1 VDD 50% GND CS A[3:0] Am Valid AnValid VDD 50% GND ApValid tCYCLE tCYCLE S[x] = Analog Inputs tPROP_D tMUX tPROP_D tMUX tBBM COM (Previous) HiZ COM = S[Am Valid] tPROP_D tMUX tBBM HiZ tBBM HiZ COM = S[An Valid] COM = S[Ap Valid] Note: 1. CS may be held in a continuous low state, holding CS high provides protection for false address change. 2. tCYCLE is the minimum cycle time between the falling edges of CS and/or any address changes. If tCYCLE is shorter than tPROP_D, an addressing error may occur. 3. All bits (A[3:0]) of any address change should be received by the UT16MX113 within 18ns of the first bit change for proper operation. Figure 5. UT16MX113 Timing Diagram Multiplexer Synchronous Parallel Timing (UT16MX114) tCYCLE VDD 50% PLATCH tLHD A[3:0] GND tLHD tLSU tLSU Am Valid An Valid VDD 50% GND S[x] = Analog Inputs tPROP_D tMUX COM(Previous) tPROP_D tMUX tBBM HiZ tBBM HiZ COM = S[Am Valid] Note: 1. When PLATCH is in a high or low state, it provides protection for false address change. 2. tCYCLE must not be less than the maximum value of tPROP_D. Figure 6. UT16MX114 Timing Diagram 14 COM = S[An Valid] Multiplexer Serial Timing (UT16MX115) tSSH tSSU VDD 50% GND SS tH tL VDD 50% GND SCLK tHD tSU Bit 7 MSB MOSI Bit 6 Bit 0 LSB Bit 1 S[x] = Analog Inputs tPROP_D tMUX COM (Previous) COM MISO (MOSI previous) tBBM HiZ COM (Previous) Bit 7 MSB Bit 6 VDD 50% GND Bit 7 (MOSI Current) Bit 0 LSB Bit 1 COM (MOSI[3:0]) tDO Figure 7. UT16MX115 Timing Diagram Multiplexer Load Conditions for Test (UT16MX113/114/115) Start of serial transmission End of serial transmission SS SCLK MOSI (input) MISO (MOSI previous) Bit 7 In MSB Bit 7 Out Bit 6 In Bit 6 Out Bit 5 In Bit 5 Out Bit 4 In Bit 4 Out Bit 3 In Bit 2 In Bit 3 Out Bit 2 Out Bit 1 In Bit 1 Out Bit 0 In LSB Bit 0 Out Bit 7 Out (MOSI current) serial register applies, MUX switches after TMUX delay S[x] COM (Previous) COM Note: 1. See FIGURE 7. Multiplexer serial timing (UT16MX115), for detailed timing. Figure 8. SPI™ Protocol 15 COM (MOSI[3:0]) Multiplexer RESET Enable/Disable Timing (UT16MX114/115) VDD 50% RESET GND tPZLH tPLHZ HiZ COM, S[x] HiZ COM, S[0] Note: 1. S[x] represents the analog signal channel connected to COM prior to the falling edge of RESET. Figure 9. RESET Timing Diagram (Used for UT16MX114/115 only) Multiplexer Analog Timing (UT16MX113/114/115) AVDD 50% S[x] AVSS tPROP_S tPROP_S AVDD 50% COM AVSS Note: 1. S[x] represents the analog signal channel connected to COM while in active mode of all device types with the address already set and all digital inputs held constant. Figure 10. Analog Timing Diagram (Used for UT16MX113/114/115) 16 Minimum Multiplexer Total Path Resistance (UT16MX113/114/115) Address/SPI TM Pins 4 R0 R1 R2 S[0] S[1] S[2] UT16MX113 UT16MX114 UT16MX115 • • • R13 R14 R15 COM S[13] S[14] S[15] L O A D RL Ri + RL > 500 (0 < i < 15) Note: 1. Continuous DC operation on any single channel where Ri + RL < 500 will degrade device reliability and performance. Figure 11. Minimum Total Path Resistance for Continuous DC Operation on Any Single Channel Multiplexer Load Conditions for Test (UT16MX113/114/115) Address/SPI TM Pins 4 S[0] S[1] S[2] . . . UT16MX113 UT16MX114 UT16MX115 RT = 50 Test Point COM CL = 50 pF S[13] S[14] S[15] Figure 12. UT16MX113/114/115 Test Circuit 17 18 PACKAGING Figure 13. 28-Lead Ceramic Flat Package 19 TRADEMARKS: SPI™ /QSPI™ are trademarks of Motorola, Inc. MICROWIRE™ is a trademark of National Semiconductor 20 ORDERING INFORMATION UT16MX113/114/115 Analog Multiplexer UT ***** ** * * * * Lead Finish: (Note 1) (C) = Gold Screening Level: (Note 2 and 3) (P) = Prototype Flow (C) = HiRel Flow Case Outline: (X) = 28-pin CFP ceramic flatpack TID Tolerance: (-) = None Device Type: (13) = Asynchronous Parallel (14) = Synchronous Parallel (15) = Serial (SPI™) Generic Part Number: (16MX1) = 16:1 MUX Notes: 1. Lead finish is "C" (Gold) only. 2. Prototype flow per Aeroflex Manufacturing Flows Document. Devices are tested at 25C only. Lead finish is Gold "C" only. Radiation neither tested nor guaranteed. 3. HiRel Flow per Aeroflex Manufacturing Flows Document. 21 UT16MX113/114/115 ANALOG MULTIPLEXER: SMD 5962 * 10236 ** * * * Lead Finish (Note 1): (C) = Gold Case Outline: (X) = 28-pin CFP ceramic flatpack Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type (01) = Serial (SPI™) (02) = Asynchronous Parallel (03) = Synchronous Parallel Drawing Number:10236 Total Dose: (R) = 100 krad(Si) (F) = 300 krad(Si) Federal Stock Class Designator: No options Notes: 1. Lead finish is "C" (Gold) only. Aeroflex Colorado Springs - Datasheet Definition Advanced Datasheet - Product In Development Preliminary Datasheet - Shipping Prototype Datasheet - Shipping QML & Reduced Hi-Rel COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Colorado Springs, Inc., reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused