Standard Products Datasheet RadHard-by-Design RHD5950 16-Channel Multiplexed 14-Bit Analog-to-Digital Converter www.aeroflex.com/RHDseries January 14, 2016 FEATURES Single power supply operation 5.0V or Dual power supply for 3.3V I/O Radiation performance - Total dose: > 100krad(Si); Dose rate = 50 - 300 rads(Si)/s - ELDRS Immune - SEL Immune > 100 MeV-cm2/mg - Neutron Displacement Damage > 1014 neutrons/cm2 16-Channel Input Multiplexer Successive Approximation A-to-D Level Shifting Digital Output Drivers allow interfaces to 5.0 or 3.3 volt logic Tri-State digital outputs Power Down (Sleep) mode Single or continuous conversion 20us conversion period (20 clocks @ 1MHz Clock rate) Multiplexer address is latched on first clock rising edge of a cycle Busy and End-of-Conversion status outputs Full military temperature range Designed for aerospace and high reliability space applications Packaging – Hermetic Ceramic - 48 leads, 0.700"Sq x 0.125"Ht quad flat pack - Weight - 6 grams max Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G. GENERAL DESCRIPTION Aeroflex’s RHD5950 is a radiation hardened, single supply, 16-Channel Multiplexed Analog-to-Digital converter in a 48-pin Ceramic Quad Flat Package. The RHD5950 design uses specific circuit topology and layout methods to mitigate total ionizing dose effects and single event latchup. It is guaranteed operational from -55°C to +125°C. Available screened in accordance with MIL-PRF-38534 Class K, the RHD5950 is ideal for demanding military and space applications. ORGANIZATION AND APPLICATION The RHD5950 takes 16 analog sensor signals and using 4 address inputs and an enable input, selects one of the 16 analog inputs and performs a 14-bit successive approximation analog-to-digital conversion in a nominal period of 20 clock cycles (20uS nominal). The 14-bit digital output has a tri-state control allowing the connection of multiple RHD5950s. This provides the ability to interface many sensor voltage readings to the digital processor data bus. The full-scale range is determined by reference input voltages. The input impedance of the reference/span terminals is typically a constant 4K ohms. SCD5950 Rev G Gain compression will occur near either power supply extremes but can be avoided if the references are more than 200mV away from the respective supply terminals. The input span can be less than 4 volts at the expense of ultimate resolution The analog channel’s input impedance is primary capacitance (20pF typical). The input voltage charges a track-and-hold hold capacitor through transmission gates. The input bandwidth is determined by the slew rate of the hold amplifier and is adequate to allow input sampling in three clock periods (3uS nominal). The ultimate bandwidth is determined by the aperture uncertainty associated with the closing of the sample gate (approximately 5nS). The converter bandwidth is then determined by the sampling Nyquist frequency rather than the input signal; change rate (dv/dt) and the LSB weight in volts as would be the case if there were no sample-and-hold. Start-Convert (STCNV_H), Busy (BUSY_L) and End-Of-Convert (EOC_H) status and control lines are provided. The converter will operate in either continuous or single conversion modes. To operate in continuous mode, STCNV_H should be tied to BUSY_L. The digital output register changes at the end of a conversion and is latched when EOC_H is asserted High. The output data will remain latched until the next conversion is complete and will be updated when EOC_H is asserted High. The output circuitry operates from a voltage independent of the remainder of the chip such that I/O is compatible with digital systems from, less than 3.3 volts, to 5 volts. The converter divides the reference voltage into 16 segments with a linear weighted resistor network. The voltage on any segment is passed to a linear 10-bit DAC for interpolation. The sampled input voltage is compared to the output of the two stage DAC for a 14-bit successive approximation conversion. All inputs are protected to both power supply rails by semiconductor diodes. Inputs should be constrained to VCC +0.4 and GND-0.4 to avoid forward biasing protection paths. The devices will not latch with SEU events to above 100 MeV-cm2/mg. Displacement damage environments to neutron fluence equivalents in the mid 1014 neutrons per cm2 range are readily tolerated. There is no sensitivity to low-dose rate (ELDRS) effects. SEU effects are application dependent. Notes: - The STCNV_H is a dynamic input (positive edge triggered) and should not be tied to a static voltage. - The input signals should be low pass filtered to reduce high frequency noise - If Sleep mode is enabled (EN_H=0), when waking up (EN_H=1), the unit has to complete an entire conversion cycle so the digital logic is in the proper state. Ex. If using a 1MHz clock; after EN_H=1 and 20us after STCNV_H is applied. SCD5950 Rev G 1/14/16 2 Aeroflex Plainview FIGURE 1: BLOCK DIAGRAM SCD5950 Rev G 1/14/16 3 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS Parameter Range Units Case Operating Temperature Range -55 to +125 °C Storage Temperature Range -65 to +150 °C Junction Temperature +150 °C Supply Voltage VCC - GND +7.0 V VCC +0.4 GND -0.4 V Lead Temperature (soldering, 10 seconds) 300 °C Thermal Resistance, Junction to Case,jc 2.0 °C/W Input Voltage, PREF, NREF NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating only; functional operation beyond the “Operation Conditions” is not recommended and extended exposure beyond the “Operation Conditions” may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Typical Units +AvCC Analog Power Supply Voltage 5.0 V +DvCC Digital Power Supply Voltage 5.0 V DRVP Digital Output High Reference Level 3.3 to 5.0 V DRVN Digital Output Low Reference Level 0 V PREF High Analog Reference Voltage 4.5 V NREF Low Analog Reference Voltage 0.5 V ELECTRICAL PERFORMANCE CHARACTERISTICS (TC = -55°C TO +125°C, +AVCC = +5.0 V, +DVCC = +5.0 V, +DRVP = +5.0 V, unless stated otherwise) Parameter Symbol Conditions Min Max Units Analog Supply Current Quiescent 1/ AICCQ VEN = DvCC, VOE = DvCC, CLK = DGND - 10 mA Analog Supply Current Active 1/ AICCA VEN = DvCC, VOE = DvCC - 10 mA Analog Supply Current Sleep 1/ AICCS VEN = DGND, VOE = DGND - 4 mA Digital Supply Current Quiescent 1/ DICCQ VEN = DvCC, VOE = DvCC, CLK = DGND - 1 mA Digital Supply Current Active 1/ DICCA VEN = DvCC, VOE = DvCC - 2 mA Digital Supply Current Sleep 1/ DICCS VEN = DGND, VOE = DGND - 1 mA Digital Output Supply Current Quiescent 1/ 05ICCQ VEN = DvCC, VOE = DvCC, CLK = DGND, CL = 50 pF - 0.1 mA Digital Output Supply Current Active 1/ 05ICCA VEN = DvCC, VOE = DvCC, CL = 50 pF - 1 mA Digital Output Supply Current Sleep 1/ 05ICCD VEN = DvCC, VOE = DGND, CL = 50 pF - 1 mA VNREF VPREF V TC = +25°C - 50 pF PREF to NREF 2 6 KΩ VNREF 5.0 Full-scale Input Range 1/ VIN Input Capacitance 2/ CIN Analog Reference Impedance 1/ ZREF High Analog Reference Voltage VPREF Low Analog Reference Voltage Channel Isolation 2/ SCD5950 Rev G 1/14/16 VNREF ISO DVRP = 5.0 V 1/ DVRP = 3.3 V 2/ DVRP = 5.0 V 1/ DVRP = 3.3 V 2/ TC = +25°C 4 V 0 VPREF 80 - dB Aeroflex Plainview ELECTRICAL PERFORMANCE CHARACTERISTICS (TC = -55°C TO +125°C, +AVCC = +5.0 V, +DVCC = +5.0 V, +DRVP = +5.0 V, unless stated otherwise) Parameter Symbol Conditions Min Max Units Integral Nonlinearity 1/ INL PREF-NREF = 4.0 V -48 48 LSBs Differential Nonlinearity 1/ DNL PREF-NREF = 4.0 V -8.2 8.2 LSBs Offset Error 1/ OE PREF-NREF = 4.0 V -1 1 %FSR Gain Error 1/ AE PREF-NREF = 4.0 V -2 2 %FSR Clock Frequency 1/ fC PREF-NREF = 5.0 V - 1 MHz fC = 1 MHZ, 20 clocks per conversion - 50 kSPS +25°C -5 5 +125°C -50 50 +25°C -5 5 +125°C -50 50 DVRP = 5.0 V 1/ 3.5 - DVRP = 3.3 V 2/ 2.31 - DVRP = 5.0 V 1/ - 1.5 DVRP = 3.3 V 2/ - 0.99 +25°C -5 5 +125°C -50 50 +25°C -5 5 +125°C -50 50 DVRP = 5.0 V, VEN = DvCC, IOH = -4.0 mA 4.2 - DVRP = 3.3 V, VEN = DvCC, IOH = -4.0 mA 2.7 - -55°C, +25°C - 0.6 +125°C - 0.8 -55°C, +25°C - 0.6 +125°C - 0.8 Maximum Sampling Rate 2/ fSAMPLE (MAX) High Input Leakage Current (AIN00-AIN15) 1/ 3/ IINLKHI Input under test = AvCC, VEN = DVCC IINLKLO Input under test = AGND, VEN = DVCC Low Input Leakage Current (AIN00-AIN15) 1/ 3/ Digital High Level Input Voltage EN_H, STCNV_H, OE_H, CLK, (AD00-AD03) VIH Digital Low Level Input Voltage EN_H, STCNV_H, OE_H, CLK, (AD00-AD03) VIL Digital High Level Input Current EN_H, STCNV_H, OE_H, CLK, (AD00-AD03) 1/ 3/ IIH Digital Low Level Input Current EN_H, STCNV_H, OE_H, CLK, (AD00-AD03) 1/ 3/ Digital High Level Output Voltage (B00-B13) 1/ Digital Low Level Output Voltage (B00-B13) 1/ Digital High Level Output Current (B00-B13) 1/ Digital Low Level Output Current (B00-B13) 1/ High Output Leakage Current (B00-B13) 1/ 3/ Low Output Leakage Current (B00-B13) 1/ 3/ Notes: IIL VOH Digital input under test = 5.0 V All other digital inputs = DGND All digital inputs = DGND DVRP = 5.0 V, VEN = DvCC, IOL = +4.0 mA VOL DVRP = 3.3 V, VEN = DvCC, IOL = +4.0 mA IOH DVRP = 5.0 V, VEN = VIH - -4.0 (SOURCE) DVRP = 3.3 V, VEN = VIH - -4.0 IOL DVRP = 5.0 V, VEN = VIH - 4.0 (SINK) DVRP = 3.3 V, VEN = VIH - 4.0 +25°C -5 5 +125°C -50 50 +25°C -5 5 +125°C -50 50 IOUTLKHI IOUTLKLO VOE = DGND VOE = DGND nA V nA V V mA nA 1/ Specification derated to reflect Total Dose exposure to 100krad(Si) @ +25°C. 2/ Not tested. Shall be guaranteed by design, characterization, or correlation to other test parameters. 3/ These parameters for Tc = -55°C are guaranteed by design, characterization, or correlation to other test parameters. SCD5950 Rev G 1/14/16 5 Aeroflex Plainview SWITCHING CHARACTERISTICS (TC = -55°C TO +125°C, +AVCC = +5.0 V, +DVCC = +5.0 V, +DRVP = +5.0 V, unless stated otherwise) Parameter Symbol Conditions Min Typ Max Units STCNV_H to CLK 20 - - ns ADDRESS to CLK Setup 20 - - ns CLK to BUSY_L Low - 50 - ns CLK to EOC_H High - 50 - ns EOC_H to OUTPUT DATA - 50 - ns CLK to EOC_H Low - 50 - ns CLK to BUSY_L High - 50 - ns CLK Pulse Width 50 - - ns DATA Sampling Time 3 - 5 ns FIGURE 2: BASIC TIMING DIAGRAM SCD5950 Rev G 1/14/16 6 Aeroflex Plainview PACKAGE PIN-OUT AND SIGNAL DEFINITION Pin # Signal Definition Pin # Signal Definition 1 AIN01 Analog Multiplexer Input 01 25 B11 Digital Output 11 2 AIN00 Analog Multiplexer Input 00 26 B12 Digital Output 12 3 NREF Low Analog Reference Voltage 27 B13 Digital Output 13 4 AvCC Analog Supply Voltage 28 EOC_H End of Convert Output (Active High) 5 DvCC Digital Supply Voltage 29 BUSY_L Busy Output (Active Low) 6 AD03 Multiplexer Address 03 30 DRVN Digital Output Low Reference Level 7 AD02 Multiplexer Address 02 31 DRVP Digital Output High Reference Level 8 AD01 Multiplexer Address 01 32 DGND Digital Supply Return 9 AD00 Multiplexer Address 00 33 AGND Analog Supply Return 10 STCNV_H Start Convert: A Low-to-High transition starts the conversion cycle 34 PREF High Analog Reference Voltage 11 EN_H A Low places part in SLEEP mode. A High Enable the A2D converter 35 AIN15 Analog Multiplexer Input 15 12 OE_H A Low Tristates the outputs. A High Enables the outputs 36 AIN14 Analog Multiplexer Input 14 13 CLK Clock Input 37 AIN13 Analog Multiplexer Input 13 14 B00 Digital Output 00 38 AIN12 Analog Multiplexer Input 12 15 B01 Digital Output 01 39 AIN11 Analog Multiplexer Input 11 16 B02 Digital Output 02 40 AIN10 Analog Multiplexer Input 10 17 B03 Digital Output 03 41 AIN09 Analog Multiplexer Input 09 18 B04 Digital Output 04 42 AIN08 Analog Multiplexer Input 08 19 B05 Digital Output 05 43 AIN07 Analog Multiplexer Input 07 20 B06 Digital Output 06 44 AIN06 Analog Multiplexer Input 06 21 B07 Digital Output 07 45 AIN05 Analog Multiplexer Input 05 22 B08 Digital Output 08 46 AIN04 Analog Multiplexer Input 04 23 B09 Digital Output 09 47 AIN03 Analog Multiplexer Input 03 24 B10 Digital Output 10 48 AIN02 Analog Multiplexer Input 02 TRUTH TABLE (AIN00 – AIN15) A3 A2 A1 A0 EN "ON" CHANNEL X L L L L L L L L H H H H H H H H X L L L L H H H H L L L L H H H H X L L H H L L H H L L H H L L H H X L H L H L H L H L H L H L H L H L H H H H H H H H H H H H H H H H NONE AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 SCD5950 Rev G 1/14/16 7 Aeroflex Plainview ORDERING INFORMATION Model DLA SMD # Screening Package RHD5950-7 - Commercial Flow, +25°C testing only RHD5950-S - Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications RHD5950-201-1S 5962-1220301KXC In accordance with DLA SMD RHD5950-901-1S 5962R1220301KXC In accordance with DLA Certified RHA Program Plan to RHA Level "R", 100krads(Si) 48-lead CQFP Note: Outside ceramic tie bars not shown for clarity. Contact factory for details. FIGURE 3: PACKAGE OUTLINE EXPORT CONTROL: This product is controlled for export under the Export Administration Regulations (EAR), 15 CFR Parts 730-774. A license from the Department of Commerce may be required prior to the export of this product from the United States. www.aeroflex.com/HiRel [email protected] Datasheet Definitions: Advanced Preliminary Datasheet Product in Development Shipping Non-Flight Prototypes Shipping QML and Reduced HiRel Aeroflex Plainview, Inc. reserves the right to make changes to any products and services described herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. SCD5950 Rev G 1/14/16 8 Our passion for performance is defined by three attributes. Solution-Minded Performance-Driven Customer-Focused