UT54LVDS218 (9/15)

Standard Products
UT54LVDS218 Deserializer
Data Sheet
September, 2015
The most important thing we build is trust
FEATURES
INTRODUCTION
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The UT54LVDS218 Deserializer converts the three LVDS data
streams back into 21 bits of CMOS/TTL data. At a transmit clock
frequency of 75MHz, 21 bits of TTL data are transmitted at a rate
of 525Mbps per LVDS data channel. Using a 75MHz clock, the
data throughput is 1.575 Gbit/s (197 Mbytes/sec).
DATA (LVDS)
CLOCK (LVDS)
LVDS TO-PARALLEL TTL
15 to 75MHz shift clock support
50% duty cycle on receiver output clock
Low power consumption
Cold sparing all pins
+1V common mode range (around +1.2V)
Narrow bus reduces cable size and cost
Up to 1.575 Gbps throughput
Up to 197 Megabytes/sec bandwidth
325 mV (typ) swing LVDS devices for low EMI
PLL requires no external components
Rising edge strobe
Operational environment; total dose irradiation testing to MILSTD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
 Packaging options:
- 48-lead flatpack (1.4 grams)
 Standard Microcircuit Drawing 5962-01535
- QML Q and V compliant part
 Compatible with TIA/EIA-644 LVDS standard
PLL
The UT54LVDS218 Deserializer allows the use of wide, high
speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
21
CMOS/TTL OUTPUTS
RECEIVER CLOCK OUT
POWER DOWN
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Figure 1. UT54LVDS218 Deserializer Block Diagram
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RxOUT 17
1
48
VDD
RxOUT 18
2
3
47
RxOUT 16
46
RxOUT 15
45
44
43
RxOUT 14
GND
No.
RxIN+
I
3
Positive LVDS differential data inputs1
GND
RxOUT 13
RxIN-
I
3
Negative LVDS differential data output1
42
VDD
RxOUT
O
21
TTL level data outputs
RxCLK IN+
I
1
Positive LVDS differential clock input
RxCLK IN-
I
1
Negative LVDS differential clock input
RxCLK OUT
O
1
PWR DWN
I
1
VDD
I
4
GND
I
5
TTL level clock output. The rising edge acts
as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input)
the receiver outputs are low
Power supply pins for TTL outputs and logic
Ground pins for TTL outputs and logic
PLL VDD
I
1
Power supply for PLL
PLL GND
I
2
Ground pin for PLL
LVDS VDD
I
1
Power supply pin for LVDS pins
LVDS GND
I
3
Ground pins for LVDS inputs
4
5
LVDS GND
7
RxIN0-
8
9
41
RxOUT 12
40
RxOUT 11
39
RxOUT 10
RxIN1+
10
11
38
GND
LVDS VDD
LVDS GND
12
13
RxOUT 9
VDD
RxOUT 8
RxIN0+
RxIN1-
UT54LVDS218
RxIN2-
14
37
36
35
RxIN2+
15
34
RxOUT 7
RxCLK IN-
16
RxCLK IN+
17
33
32
RxOUT 6
GND
31
RxOUT 5
30
RxOUT 4
29
RxOUT 3
VDD
RxOUT 2
RxOUT 1
GND
PLL GND
18
19
PLL VDD
PLL GND
20
21
LVDS GND
PWR DWN
22
RxCLK OUT
23
28
27
26
RxOUT0
24
25
Pin Name
Description
I/O
RxOUT 19
RxOUT 20
N/C
6
PIN DESCRIPTION
Notes:
1. These receivers have input fail-safe bias circuitry to guarantee a stable receiver
output for floating or terminated receiver inputs. Under these conditions receiver
inputs will be in a HIGH state. If a clock signal is present, data outputs will all be
HIGH; if the clock input is also floating/terminated outputs will remain in the last
valid state. A floating/terminated clock input will result in a LOW clock output.
Figure 2. UT54LVDS218 Pinout
LVDS CABLE
TX
TxIN
MEDIA DEPENDENT DATA
(LVDS)
RX
RxOUT
0
1
2
0
1
2
CMOS/
TTL
18
19
20
18
19
20
CLOCK
(LVDS)
TxCLK
RxCLK
GND
PCB
PCB
SHIELD
Figure 3. UT54LVDS218 Typical Application
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OPERATIONAL ENVIRONMENT
PARAMETER
LIMIT
UNITS
Total Ionizing Dose (TID)
1.0E6
rad(Si)
Single Event Latchup (SEL)
>100
MeV-cm2/mg
Neutron Fluence1
1.0E13
n/cm2
Notes:
1. Guarnteed but not tested.
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
-0.3 to 4.0V
VI/O
Voltage on any pin
-0.3 to (VDD + 0.3V)
TSTG
Storage temperature
-65 to +150C
PD
Maximum power dissipation
1.25 W
TJ
Maximum junction temperature2
+150C
Thermal resistance, junction-to-case3
10C/W
DC input current
±10mA
JC
II
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
4. For cold spare mode (VDD = VSS), VI/O may be -0.3V to the maximum recommended operating VDD +0.3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
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PARAMETER
LIMITS
VDD
Positive supply voltage
3.0 to 3.6V
TC
Case temperature range
-55 to +125C
VIN
DC input voltage
0V to VDD
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DC ELECTRICAL CHARACTERISTICS*1
(VDD = 3.0V to 0.3V; -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature noted.
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (PWR DWN, RXOUT)
VIH
High-level input voltage
2.0
VDD
V
VIL
Low-level input voltage
GND
0.8
V
VOL
Low-level output voltage
IOL = 2mA
0.3
V
VOH
High-level output voltage
IOL = -0.4mA
2.7
IIH
High-level input current
VIN=3.6V; VDD = 3.6V
-10
+10
A
IIL
Low-level input current
VIN=0V; VDD = 3.6V
-10
+10
A
VCL
Input clamp voltage
ICL = -18mA
-1.5
V
ICS
Cold spare leakage current
VIN=3.6V; VDD = VSS
-20
+20
A
IOS2,3
Output short circuit current
VOUT = 0V
-15
-130
mA
+100
mV
V
LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)
V
Differential input high threshold
VCM = +1.2V
V3
Differential input low threshold
VCM = +1.2V
-100
Common mode voltage range
VID=210mV
0.2
2.00
V
Input current
VIN = +2.4V, VDD = 3.6V
-10
+10
A
VIN = 0V, VDD = 3.6V
-10
+10
A
VIN = 3.6V, VDD = VSS
-20
+20
A
VCMR4
IIN
ICSIN
Cold spare leakage current
mV
Supply Current
ICC3
ICCPD
Active supply current
CL=8pF (see Figure 5)
105
m
Power down supply current
PWR DWN = Low, LVDS inputs =
logic low, VDD = 3.6V
2.0
mA
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time for a maximum duration
of one second.
3. Guaranteed by characterization.
4. Tested functionally.
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RECEIVER SWITCHING CHARACTERISTICS*1
(VDD = 3.0V to 3.6V; Tc = -55C to +125C); Unless otherwise noted, Tc isper the temperature ordered.
SYMBOL
PARAMETER
MIN
MAX
UNIT
CLHT3
CMOS/TTL Low-to-High Transition Time (Figure 5)
3.5
ns
CHLT3
CMOS/TTL High-to-Low Transition Time (Figure 5)
3.5
ns
RSPos03
Receiver Input Strobe Position for Bit 0 (Figure 10)
0.50
1.24
ns
RSPos13
Receiver Input Strobe Position for Bit 1 (Figure 10)
2.41
3.15
ns
RSPos23
Receiver Input Strobe Position for Bit 2 (Figure 10)
4.31
5.05
ns
RSPos33
Receiver Input Strobe Position for Bit 3 (Figure 10)
6.22
6.96
ns
RSPos43
Receiver Input Strobe Position for Bit 4 (Figure 10)
8.12
8.86
ns
RSPos53
Receiver Input Strobe Position for Bit 5 (Figure 10)
10.03
10.77
ns
RSPos63
Receiver Input Strobe Position for Bit 6(Figure 10)
11.93
12.67
ns
RCOP3
RxCLK OUT Period (Figure 6)
13.3
66.7
ns
RCOH3
RxCLK OUT High Time (Figure 6)
RCOL3
RxCLK OUT Low Time (Figure 6)
RSRC4
RxOUT Setup to RxCLK OUT (Figure 6)
RHRC4
RxOUT Hold to RxCLK OUT (Figure 6)
RCCD2
RxCLK IN to RxCLK OUT Delay (Figure 7)
RPLLS5
Receiver Phase Lock Loop Set (Figure 8)
RPDD
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
f=75MHz
3.6
ns
3.6
ns
3.5
ns
3.5
ns
f=75MHz
f=75MHz
f=75MHz
f=75MHz
3.4
8.3
ns
10
ms
2
s
f=75MHz
f=75MHz
Receiver Powerdown Delay (Figure 9)
f=75MHz
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min and max)
and the receiver input setup and hold time (internal data sampling window). This margin allows LVDS interconnect skew, inter-symbol interference (both dependent
on type/length of cable), and source clock jitter less than 250 ps (calculated from TPOS - RPOS) - see Figure 11.
2. Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for
LVDS217 Serializer and the LVDS218 Deserializer is (T + TCCD) + 2*T + RCCD), where T = Clock period.
3. Guaranteed by characterization.
4. Guaranteed by design.
5. Tested functionally.
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T
RxCLK OUT
ODD Rx OUT
EVEN Rx OUT
Figure 4. Test Pattern
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AC TIMING DIAGRAMS
CMOS/TTL OUTPUT
80%
80%
20%
8pF
20%
CMOS/TTL OUTPUT
CLHT
CHLT
Figure 5. UT54LVDS218 Output Load and Transition Times
RCOP
RxCLK OUT
VDD/2
VDD/2
VDD/2
RCOH
RCOL
RSRC
RxOUT 0:20
RHRC
VDD/2
VDD/2
Figure 6. UT54LVDS218 Setup/Hold and High/Low Times
+
RxCLK IN
-
Vdiff=
0V
RCCD
VDD/2
RxCLK OUT
Figure 7. UT54LVDS218 Clock-to-Clock Out Delay
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VDD/2
POWER DOWN
VDD/2
VDD
RPLLS
RxCLK IN
RxCLK OUT
Figure 8. UT54LVDS218 Phase Lock Loop Set Time
POWER DOWN
VDD/2
RxCLKIN
RPDD
VDD/2
Low
RxCLK OUT
Figure 9. Receiver Powerdown Delay
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TCLK
RxCLK IN/
Differential
Previous Cycle
Next Cycle
RxIN0
RxIN1
RxIN2
RSPos0 MIN
RSPos0 MAX
RSPos1 MIN
RSPos1 MAX
RSPos2 MIN
RSPos2 MAX
RSPos3 MIN
RSPos3 MAX
RSPos4 MIN
RSPos4 MAX
RSPos5 MIN
RSPos5 MAX
RSPos6 MIN
RSPos6 MAX
Figure 10. Receiver LVDS Input Strobe Position
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Ideal Strobe Position
RxIN+ or RxIN-
~1.4V
C
RxIN- or RxIN+
~1.0V
RSKM
MIN
MAX
RSKM
MIN
Tpposn
MAX
MIN
Rsposn
MAX
Tpposn+1
C - Setup and Hold Time (Internal data sampling window) defined by RSPosN (receiver input strobe position min and max
TPPosN - Transmitter output pulse position (min and max)
Cable Skew – based on type and length, typically 10 ps-40 ps per foot, media dependent
Source Clock Jitter - Cycle-to-cycle jitter is less than 250 ps at 75MHz.
ISI - Inter-symbol interference, dependent on interconnect length, may be zero.
Cable Skew
Source Clock Jitter
ISI
RSKM(Side) > _________________+ _______________________ + ______________
2
2
2
Figure 11. Receiver LVDS Skew Margin
40pF
50
Vos
Generator
VoD
50
50
40pF
Figure 12. Driver VOD and VOS Test Circuit or Equivalent Circuit
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PACKAGING
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF-38535.
4. Lead position and colanarity are not measured.
5. ID mark symbol is vendor option.
6. With solder, increase maximum by 0.003.
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Figure 12.
1148-Lead Flatpack
Cobham Semiconductor Solutions
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ORDERING INFORMATION
UT54LVDS218 Deserializer:
UT 54LVDS218 - * *
* * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening:
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Package Type:
(U) = 48-lead Flatpack (dual-in-line)
Access Time:
Not applicable
Device Type:
UT54LVDS218 Deserializer
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C.
Radiation neither tested nor guaranteed.
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UT54LVDS218 Deserializer: SMD
5962 - 01535
** * * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(X) = 48-lead Flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type
01 = 50 MHz LVDS Deserializer
02 = 75 MHz LVDS Deserializer
Drawing Number: 01535
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Federal Stock Class Designator: No Options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
This product is controlled for export under the Export Administration Regulations (EAR), 15 CFR Parts 730-774. A
license from the Department of Commerce may be required prior to the export of this product from the United
States.
Cobham Semiconductor Solutions
4350 Centennial Blvd
Colorado Springs, CO 80907
E: [email protected]
T: 800 645 8862
Aeroflex Colorado Springs Inc., dba Cobham Semiconductor Solutions, reserves the right to make changes to any products and services described
herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current
before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service
described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex
convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties.
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DATA SHEET REVISION HISTORY
REV
Revision
Date
1.0.0
10-08
1.0.1
9-17-15
36-00-06-010
Version 1.0.1
Description of Change
Author
Last official release
MM
Page 1, added package weight.
Applied new Cobham Data Sheet template to the document.
MM
15
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