UT54LVDM328

Standard Products
UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater
Data Sheet
November 7, 2013
FEATURES
INTRODUCTION
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The UT54LVDM328 is an Octal Bus Repeater utilizing Low
Voltage Differential Signaling (LVDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. LVDS I/O enable high speed data transmission
for point-to point or multi-drop interconnects. This device is
designed for use as a high speed differential repeater.
400.0 Mbps low jitter fully differential data path
200MHz clock channel
3.3 V power supply
10mA LVDS output drivers
Cold sparing all pins
Fast propagation delay of 3.5ns max
Receiver input threshold < + 100 mV
Operational environment; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
 Packaging options:
- 48-lead flatpack
 Standard Microcircuit Drawing 5962-01536
- QML Q and V compliant part
 Compatible with TIA/EIA-899
The UT54LVDM328 is a repeater designed specifically for the
bridging of multiple backplanes in a system. The
UT54LVDM328 utilizes low voltage differential signaling to
deliver high speed while consuming minimal power with
reduced EMI. The UT54LVDM328 repeats signals between
backplanes and accepts or drives signals onto the local bus.
The individual LVDS outputs can be put into Tri-State by use
of the enable pins.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
END
IN1+
IN1-
+
-
OUT1+
IN2+
+
-
OUT2+
IN2-
OUT1-
OUT2-
Figure 1a. UT54LVDM328 Repeater Block Diagram
(Partial - see Page 2 for complete diagram)
1
END
IN1+
IN1-
+
-
OUT1+
IN2+
OUT2+
IN2-
+
-
IN3+
IN3-
+
-
OUT3+
IN4+
OUT4+
IN4-
+
-
IN5+
IN5-
+
-
OUT5+
IN6+
OUT6+
IN6-
+
-
IN7+
IN7-
+
-
OUT7+
IN8+
+
-
IN8-
OUT1-
OUT2-
OUT3-
OUT4-
OUT5-
OUT6-
OUT7-
OUT8+
OUT8-
ENCK
Clk In+
Clk In-
Clk Out+
+
-
Clk Out-
Figure 1b. UT54LVDM328 Repeater Diagram
1
IN1+
1
48
OUT1+
IN1-
47
OUT1-
IN2+
2
3
46
OUT2+
IN2VDD
4
5
OUT2-
VSS
6
45
44
43
IN3+
7
42
OUT3+
IN3-
8
9
41
IN4+
ENCK
10
11
CLK In+
CLK In-
12
13
END
14
IN5+
15
IN5-
16
IN6+
17
IN6VDD
18
19
VSS
IN7+
20
21
IN7IN8+
IN8-
IN4-
PIN DESCRIPTION
Name
# of Pins
Description
INn+
8
Non-inverting LVDS input
INn-
8
Inverting LVDS input
OUTn+
8
Non-inverting LVDS output
OUT3-
OUTn-
8
Inverting LVDS Output
40
OUT4+
END
1
39
OUT4-
A logic low on the enable puts
the LVDS data output into TriState and reduces the supply
current
ENCK
1
A logic low on the enable puts
the LVDS clock output into TriState and reduces the supply
current
VSS
5
Ground
VDD
VSS
38
VDD
37
36
35
CLK OUT+
CLK OUTVSS
34
OUT5+
33
32
OUT5OUT6+
31
OUT6-
30
VDD
VDD
5
Power supply
29
VSS
CLK IN+
1
OUT7+
OUT7-
Non-Inverting Clock LVDS
Input
22
23
28
27
26
CLK IN-
1
Inverting clock LVDS Input
24
25
OUT8-
CLK
OUT+
1
Non-Inverting Clock LVDS
Output
CLK
OUT-
1
Inverting Clock LVDS Output
UT54LVDM328
Bus Repeater
OUT8+
Figure 2. UT54LVDM328 Pinout
2
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.
APPLICATIONS INFORMATION
The UT54LVDM328 provides the basic bus repeater
function. The device operates as a 9 channel LVDS buffer.
Repeating the signal restores the LVDS amplitude, allowing
it to drive another media segment. This allows for isolation
of segments or long distance applications.
The intended application of these devices and signaling
technique is for both point-to-point baseband (single
termination) and multipoint (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the
environment, and other application specific characteristics.)
Compatibility with LVDS standard:
Input Fail-Safe:
In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50
differential impedance, the loading effects may reduce this to
the 35 range depending upon spacing and capacitance load.
Terminating the line with a 35 load is a better match than
with 50 and reflections are reduced.
The UT54LVDM328 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.
PCB layout and Power System Bypass:
Circuit board layout and stack-up for the UT54LVDM328
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thin
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at high
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01F to
0.1 F. Tantalum capacitors may be in the range of 2.2F to
10F. Voltage rating for tantalum capacitors should be at least
5X the power supply voltage being used. It is recommended
practice to use two vias at each power pin of the
UT54LVDM328, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.
3
OPERATIONAL ENVIRONMENT
PARAMETER
LIMIT
UNITS
Total Ionizing Dose (TID)
1.0E6
rad(Si)
Single Event Latchup (SEL)
>100
MeV-cm2/mg
Neutron Fluence1
1.0E13
n/cm2
Notes:
1. Guarnteed but not tested.
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
-0.3 to 4.0V
VI/O
Voltage on any pin
-0.3 to (VDD + 0.3V)
TSTG
Storage temperature
-65 to +150C
PD
Maximum power dissipation permitted @
Tc = +125oC
1.667 W
TJ
Maximum junction temperature2
+150C
Thermal resistance, junction-to-case3
15C/W
DC input current
±10mA
JC
II
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
4. For cold spare mode (VDD = VSS), VI/O may be -0.3V to the maximum recommended operating VDD +0.3V.
5. Per MIL-STD-883, Method 1012.1, Section 3.4.1, PD = (TJ(max) - Tc(max) / JC.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VDD
Positive supply voltage
3.0 to 3.6V
TC
Case temperature range
-55 to +125C
VIN
DC input voltage, receiver inputs
DC input voltage, logic inputs
4
0 to 2.4V
0 to VDD for END or ENCK
DC ELECTRICAL CHARACTERISTICS *1
(VDD = 3.3V + 0.3V; -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN)
VIH
High-level input voltage
2.0
VDD
V
VIL
Low-level input voltage
GND
0.8
V
IIH
High-level input current
VIN=3.6V; VDD = 3.6V
-10
+10
A
IIL
Low-level input current
VIN=0V; VDD = 3.6V
-10
+10
A
VCL
Input clamp voltage
ICL=-18mA
-1.5
V
ICS
Cold Spare Leakage current
VIN=3.6V, VDD=VSS
-20
+20

250
450
mV
35
mV
1.550
V
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD
Differential Output Voltage
RL= 35(See Figure 9)
VOD
Change in VOD between
complimentary output states
RL= 35(See Figure 9)
VOS
VOS
IOZ
ICSOUT
IOS2,3
RL= 35VOS=(VOH+VOL)
2
Offset Voltage
1.055
Change in VOS between complimentary
output states
RL=35
35
mV
Output Tri-State Current
Tri-State output, VDD = 3.6V
VOUT=VDD or GND
+10

Cold Sparing Leakage Current
VOUT=3.6V, VDD=VSS
+20

Output Short Circuit Current
VOUT+ OR VOUT = 0 V
-25
mA
+100
mV
-20
LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)
VTH3
Differential Input High Threshold
VCM = +1.2V
VTL3
Differential Input Low Threshold
VCM = +1.2V
-100
VCMR
Common Mode Voltage Range
VID=210mV
0.2
2.00
V
Input Current
VIN = +2.4V, VDD = 3.6V
-10
+10

VIN = 0V, VDD = 3.6V
-10
+10

VIN=3.6V, VDD=VSS
-20
+20

IIN
ICSIN
Cold Sparing Leakage Current
5
mV
DC ELECTRICAL CHARACTERISTICS 1 (CON"T)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
Supply Current
ICCL
Total Supply Current
RL = 35
END, ENCK= VDD, VDD= 3.6V
220
ma
ICCZ
Tri-State Supply Current
END, ENCK = VSS, VDD= 3.6V
20
ma
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.
3. Guaranteed by characterization.
6
AC SWITCHING CHARACTERISTICS
(VDD = +3.3V + 0.3V, TA = -55 C to +125 C); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
PARAMETER
Conditions
MIN
MAX
UNIT
tPHZ2
Disable Time (Active to Tri-State) High to Z
(See Figure 7)
RL= 35CL = 10pf
4.5
ns
tPLZ2
Disable Time (Active to Tri-State) Low to Z
(See Figure 7)
RL= 35CL = 10pf
4.5
ns
tPZH2
Enable Time (Tri-State to Active) Z to High
(See Figure 7)
RL= 35CL = 10pf
11.0
ns
tPZL2
Enable Time (Tri-State to Active) Z to Low
(See Figure 7)
RL= 35CL = 10pf
11.0
ns
tLHT1
Output Low-to-High Transition Time, 20% to 80%
(See Figures 4 and 5)
RL= 35CL = 10pf
600
ps
tHLT1
Output High-to-Low Transition Time, 80% to 20%
(See Figures 4 and 5)
RL= 35CL = 10pf
600
ps
tPLHD
Propagation Low to High Delay
(See Figures 4 and 6)
RL= 35CL = 10pf
3.5
ns
TPHLD
Propagation High to Low Delay
(See Figures 4 and 6)
RL= 35CL = 10pf
3.5
ns
TSKEW
Differential Skew TPHLD - TPLHD
(See Figures 4 and 6)
900
ps
TCCS
Output Channel-to-Channel Skew
(See Figures 4 and 6)
500
ps
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Guaranteed by design.
2. Guaranteed by characterization.
.
7
CL
RIN+
Pulse
Generator
R
RIN50
RL
D
50
CL
Figure 4. LVDS Output Load
80%
80%
0V
VDIFF
20%
20%
tHLT
tLHT
Figure 5. LVDS Output Transition Time
IN
Vdiff = 0V
tPLHD
OUT
tPHLD
Vdiff = 0V
Figure 6. Propagation Delay Low-to-High and High-to-Low
8
EN
VDD/2
VDD
VDD/2
tPHZ
OUT
tPZH
VOH
50%
50%
0VDiff
0VDiff
50%
50%
VOL
OUT
tPZL
tPLZ
Figure 7. Output active to TRI-STATE and TRI-STATE to active
OUT 0
Vdiff = 0V
TCCS
OUT 1
Vdiff = 0V
Figure 8. Output Channel-to-Channel Skew
DOUT+
20pF
DIN
D
Generator
RL = 35
50
Driver Enabled
20pF
DOUT-
Figure 9. Driver VOD and VOS Test Circuit or Equivalent Circuit
9
VOD
PACKAGING
Notes:
1. All exposed metallized areas are gold plated
over electrically plated nickel per MIL-PRF38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MILPRF-38535.
4. Dimension symbology is in accordance with
MIL-PRF-38535.
5. Lead position and coplanarity are not
measured.
6. ID mark symbol is vendor option: no
alphanumerics.
Figure 10. 48-pin Flatpack
10
ORDERING INFORMATION
UT54LVDM328 Bus LVDS Repeater:
UT 54LVDM328 - * *
* * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening:
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Package Type:
(U) = 48-lead Flatpack (dual-in-line)
Access Time:
Not applicable
Device Type:
UT54LVDM328 Bus LVDS Repeater
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY.
Radiation neither tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55C, room
temp, and 125C. Radiation neither tested nor guaranteed.
11
UT54LVDM328 Bus LVDS Repeater: SMD
5962 - 01536
** * * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(Y) = 48-lead Flatpack (dual-in-line)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type
01 = Bus LVDS Repeater
Drawing Number: 01536
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Federal Stock Class Designator: No Options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
12
NOTES
13