UT54LVDM228

Standard Products
UT54LVDM228 Quad 2x2 400 Mbps Crosspoint Switch
Data Sheet
November 7, 2013
FEATURES
INTRODUCTION
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The UT54LVDM228 is a quad 2x2 crosspoint switch utilizing
Low Voltage Differential Signaling (LVDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The non-blocking design allows connection of
any input to any output or outputs on each switch. LVDS I/O
enable high speed data transmission for point-to point or multidrop interconnects. This device can be used as a high speed
differential crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter. The mux and demux functions are useful for
switching between primary and backup circuits in fault tolerant
systems. The 1:2 signal splitter and 2:1 mux functions are useful
for distribution of a bus across several rack-mounted
backplanes.
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400.0 Mbps low jitter fully differential data path
200MHz clock channel
3.3 V power supply
10mA LVDS output drivers
Input receiver fail-safe
Cold sparing all pins
Configurable as quad 2:1 mux, 1:2 demux, repeater or1:2
signal splitter
Fast propagation delay of 3.5ns max
Receiver input threshold < + 100 mV
Operational environment; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 64-lead flatpack
Standard Microcircuit Drawing 5962-01537
- QML Q and V compliant part
Compatible with TIA/EIA-899
The individual LVDS outputs can be put into Tri-State by use
of the enable pins.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
En1
In1+
In1-
+
-
0
Out1+
1
Out1-
Sel1
En2
In2+
In2-
+
-
0
Out 2+
1
Out 2-
Sel2
Figure 1a. UT54LVDM228 Crosspoint Switch Block Diagram
(Partial - see Page 2 for complete diagram)
1
En1
In1+
In1-
+
-
0
Out1+
1
Out1-
Sel1
En2
In2+
+
-
In2-
0
Out 2+
1
Out 2-
0
Out3+
1
Out3-
Sel2
En3
In3+
In3-
+
-
Sel3
En4
In4+
+
-
In4-
0
Out4+
1
Out4-
0
Out5+
1
Out5-
Sel4
En5
In5+
In5-
+
-
Sel5
En6
In6+
+
-
In6-
0
Out6+
1
Out6-
0
Out7+
Sel6
En7
In7+
In7-
+
-
1
Out7-
Sel7
En8
In8+
+
-
In8Sel8
ENCK
Clk In+
Clk In-
+
-
0
Out8+
1
Out8-
Clk Out+
Skew
Match
Clk Out-
Figure 1b. UT54LVDM228 Crosspoint Switch Block Diagram
2
En1
1
64
Sel1
In1+
2
3
63
Out1+
In1-
62
Out1-
En2
In2+
4
5
Sel2
Out2+
Out2-
In2-
6
61
60
59
VDD
7
58
VDD
VSS
8
9
57
VSS
56
Sel3
55
Out3+
En3
10
11
54
Out3-
In4+
In4-
12
13
En4
14
53
52
51
ENCK
15
CLK In+
16
CLK In-
17
VSS
En5
18
19
In5+
In5-
20
21
En6
In3+
In3-
UT54LVDM228
Crosspoint
Switch
0
In1
In1
1:2 splitter
0
1
In1
In2
Repeater
1
0
In2
In1
Switch
1
1
In2
In2
1:2 splitter
PIN DESCRIPTION
Non-inverting LVDS input
In-
8
Inverting LVDS input
50
VDD
Out+
8
Non-inverting LVDS output
49
48
CLK Out+
CLK Out-
Out-
8
Inverting LVDS Output
47
VSS
En
8
A logic low on the enable puts
the LVDS output into Tri-State
and reduces the supply current
ENCK
1
A logic low on the enable puts
the LVDS output into Tri-State
and reduces the supply current
Out6-
Sel
8
2:1 mux input select
VDD
VSS
VSS
6
Ground
VDD
5
Power supply
CLK In+
1
Non-Inverting Clock LVDS
Input
CLK In-
1
Inverting clock LVDS Input
CLK Out+
1
Non-Inverting Clock LVDS
Output
CLK Out-
1
Inverting Clock LVDS Output
Out5Sel6
In6+
In6VDD
24
25
41
40
VSS
26
27
39
38
En8
0
8
44
43
42
In8-
Mode
In+
22
23
In8+
Out2
Sel4
Out4+
Out4-
Sel5
En7
Out1
Description
Out5+
28
29
Sel2
# of Pins
46
In7-
Sel1
Name
45
In7+
TRUTH TABLE
37
36
Out6+
Sel7
Out7+
30
35
Out7Sel8
31
32
34
Out8+
33
Out8-
Figure 2. UT54LVDS228 Pinout
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The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, these
planes must be tied to the ground supply plane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.
APPLICATIONS INFORMATION
The UT54LVDM228 provides three modes of operation. In
the 1:2 splitter mode, the two outputs are copies of the same
single input. This is useful for distribution / fan-out
applications. In the repeater mode, the device operates as a
9channel LVDS buffer. Repeating the signal restores the
LVDS amplitude, allowing it to drive another media segment.
This allows for isolation of segments or long distance
applications or buffers standard LVDS to 10mA multi-op
drivers.The switch mode provides a crosspoint function. This
can be used in a system when primary and redundant paths
are supported in a fault tolerant application.
The intended application of these devices and signaling
technique is for both point-to-point baseband (single
termination) and multipoint (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the
environment, and other application specific characteristics.
Compatibility with LVDS standard:
In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50
differential impedance, the loading effects may reduce this to
the 35range depending upon spacing and capacitance load.
Terminating the line with a 35load is a better match than
with 50and reflections are reduced.
Input Fail-Safe:
The UT54LVDM228 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.
PCB layout and Power System Bypass:
Circuit board layout and stack-up for the UT54LVDM228
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thin
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at high
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01F to
0.1 F. Tantalum capacitors may be in the range of 2.2F to
10F. Voltage rating for tantalum capacitors should be at least
5X the power supply voltage being used. It is recommended
practice to use two vias at each power pin of the
UT54LVDM228, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.
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OPERATIONAL ENVIRONMENT
PARAMETER
LIMIT
UNITS
Total Ionizing Dose (TID)
1.0E6
rad(Si)
Single Event Latchup (SEL)
>100
MeV-cm2/mg
Neutron Fluence1
1.0E13
n/cm2
Notes:
1. Guarnteed but not tested.
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
PARAMETER
LIMITS
VDD
DC supply voltage
-0.3 to 4.0V
VI/O4
Voltage on any pin
-0.3 to (VDD + 0.3V)
TSTG
Storage temperature
-65 to +150C
PD
Maximum power dissipation permitted @
Tc = +125oC
1.667 W
TJ
Maximum junction temperature2
+150C
Thermal resistance, junction-to-case3
15C/W
DC input current
±10mA
JC
II
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
4. For Cold Spare mode (VDD=VSS), VI/O may be -0.3V to the maximum recommended operating VDD + 0.3V.
5. Per MIL-STD-883, Method 1012.1, Section 3.4.1, PD = (TJ(max) - Tc(max) / JC.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
VDD
Positive supply voltage
3.0 to 3.6V
TC
Case temperature range
-55 to +125C
VIN
DC input voltage, receiver inputs
DC input voltage, logic inputs
5
0 to 2.4V
0 to VDD for EN, SEL
DC ELECTRICAL CHARACTERISTICS *1
(VDD = 3.3V + 0.3V; -55C < TC < +125C); Unless otherwise noted, Tc is per the temperature noted.
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
CMOS/TTL DC SPECIFICATIONS (EN, SEL)
VIH
High-level input voltage
2.0
VCC
V
VIL
Low-level input voltage
GND
0.8
V
IIH
High-level input current
VIN=3.6V; VDD = 3.6V
-10
+10
A
IIL
Low-level input current
VIN=0V; VDD = 3.6V
-10
+10
A
VCL
Input clamp voltage
ICL=-18mA
-1.5
V
ICS
Cold Spare Leakage
VIN=3.6V, VDD=VSS
-20
+20

250
450
mV
35
mV
1.550
V
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD
Differential Output Voltage
RL= 35(see Figure 10)
VOD
Change in VOD between
complimentary output states
RL= 35
Offset Voltage
RL= 35VOS=(VOH+VOL)
2
(see Figure 10)
Change in VOS between complimentary
output states
RL=35
35
mV
Output Tri-State Current
Tri-State output, VDD = 3.6V
VOUT=VDD or GND
+10

Cold Sparing Leakage Current
VOUT=3.6V, VDD=VSS
+20

Output Short Circuit Current
VOUT+ OR VOUT- = 0 V
-25
mA
+100
mV
VOS
VOS
IOZ
ICSOUT
IOS2,3
1.055
-20
LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)
VTH3
Differential Input High Threshold
VCM = +1.2V
VTL3
Differential Input Low Threshold
VCM = +1.2V
-100
VCMR
Common Mode Voltage Range
VID=200mV
0.2
2.00
V
Input Current
VIN = +2.4V, VDD = 3.6V
-10
+10

VIN = 0V, VDD = 3.6V
-10
+10

VIN=3.6V, VDD=VSS
-20
+20

IIN
ICSIN
Cold Sparing Leakage Current
mV
Supply Current
ICCD
Total Supply Current
RL = 35
EN1 - EN8, ENCK = VDD
220
ma
ICCZ
Tri-State Supply Current
EN1 - EN8, ENCK = VSS
20
ma
6
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.
3. Guaranteed by characterization.
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AC SWITCHING CHARACTERISTICS*
(VDD = +3.3V + 0.3V, TA = -55 C to +125 C); Unless otherwise noted, Tc is per the temperature noted.
SYMBOL
PARAMETER
Conditions
MIN
MAX
UNIT
tSET1, 2
Input to SEL Setup Time (Figure 3 & 4)
RL=35CL=10pf
1.6
ns
tHOLD1,2
Input to SEL Hold Time (Figure 3 & 4)
RL=35CL=10pf
1.5
ns
tSWITCH1
SEL to Switched Output (Figure 3 & 4)
RL=35CL=10pf
3.0
ns
tPHZ1
Disable Time (Active to Tri-State) High to Z
(Figure 5 & 8)
RL=35CL=10pf
4.5
ns
tPLZ1
Disable Time (Active to Tri-State) Low to Z
(Figure 5 & 8)
RL=35CL=10pf
4.5
ns
tPZH1,4
Enable Time (Tri-State to Active) Z to High
(Figure 5 & 8)
RL=35CL=10pf
EN on other channels = GND
11.0
ns
tPZL1,4
Enable Time (Tri-State to Active) Z to Low
(Figure 5 & 8)
RL=35CL=10pf
EN on other channels = GND
11.0
ns
tLHT3
Output Low-to-High Transition Time, 20% to 80%
(Figure 5 & 6)
RL=35CL=10pf
600
ps
tHLT3
Output High-to-Low Transition Time, 80% to 20%
(Figure 5 & 6)
RL=35CL=10pf
600
ps
tPLHD
Propagation Low to High Delay (Figure 5 & 7)
RL=35CL=10pf
3.5
ns
TPHLD
Propagation High to Low Delay (Figure 5 & 7)
RL=35CL=10pf
3.5
ns
TSKEW
Pulse Skew TPHLD - TPLHD (Figure 5 & 7)
900
ps
Output Channel-to-Channel Skew (Figure 5 & 9)
500
ps
TCCS
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Guaranteed by characterization.
2. TSET and THOLD time specify that data must be in a stable state before and after SEL transition.
3. Guaranteed by design.
4. Max tPZH and tPZL = 4.5ns when EN or ENCL = VDD on another channel.
8
AC TIMING DIAGRAMS
IN0
IN1
SEL
TSET
OUT
THOLD
IN1
IN0
TSWITCH
EN
Figure 3. Input-to-Select Rising Edge Setup and Hold Times and Mux Switch Time
IN0
IN1
SEL
TSET
OUT
EN
THOLD
IN0
IN1
TSWITCH
Figure 4. Input-to-Select Falling Edge Setup and Hold Times and Mux Switch Time
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CL
RIN+
Pulse
Generator
R
RIN50
RL
D
50
CL
Figure 5. LVDS Output Load
+VOD
80%
80%
0V
Vdiff=(OUT+) - (OUT-)
20%
20%
-VOD
tHLT
tLHT
Figure 6. LVDS Output Transition Time
IN
Vdiff = 0V
tPLHD
OUT
tPHLD
Vdiff = 0V
Figure 7. Propagation Delay Low-to-High and High-to-Low
10
EN
VDD/2
tPHZ
OUT
VDD
VDD/2
tPZH
VOH
50%
50%
0V Diff
0V Diff
50%
50%
VOL
OUT
tPZL
tPLZ
Figure 8. Output active to TRI-STATE and TRI-STATE to active
OUT 0
Vdiff = 0V
TCCS
OUT 1
Vdiff = 0V
Figure 9. Output Channel-to-Channel Skew in 1:2 splitter mode
DOUT+
20pF
DIN
D
Generator
RL = 35
50
Driver Enabled
20pF
DOUT-
Figure 10. Driver VOD and VOS Test Circuit or Equivalent Circuit
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VOD
PACKAGING
Figure 11. 64-pin Flatpack
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ORDERING INFORMATION
UT54LVDM228 Crosspoint Switch:
UT 54LVDM228 * *
* * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Screening:
(C) = HiRel Temperature Range flow
(P) = Prototype flow
Package Type:
(U) = 64-lead Flatpack (dual-in-line)
Access Time:
Not applicable
Device Type:
UT54LVDM228 Crosspoint Switch
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Colorado Springs Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY.
Radiation neither tested nor guaranteed.
4. HiRel Temperature Range flow per Aeroflex Colorado Springs Manufacturing Flows Document. Devices are tested at -55C, room
temp, and 125C. Radiation neither tested nor guaranteed.
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UT54LVDM228 Crosspoint Switch: SMD
5962 - 01537
** * * *
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
Case Outline:
(X) = 64-lead Flatpack (dual-in-line)
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Type
01 = LVDS Crosspoint Switch
Drawing Number: 01537
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Federal Stock Class Designator: No Options
Notes:
1.Lead finish (A,C, or X) must be specified.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
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NOTES
15