PDF Data Sheet Rev. 0

NatureVue Video Signal Processor with
Bitmap OSD, Dual HDMI Tx, and Encoder
ADV8005
Data Sheet
FEATURES
Easy to use software tool for developing OSDs
HDMI transmitters
Dual 4k × 2k HDMI transmitters
Audio return channel (ARC) support
Dual audio insertion from TMDS Rx or from audio input pins
Support for serial audio using the S/PDIF audio pin
8-channel I2S audio inputs supporting up to 192 kHz
sample frequency
6-channel direct stream digital (DSD) audio inputs
Noise shaped video (NSV) 6-DAC video encoder
Six 12-bit NSV video DACs supporting SD, ED and HD video
Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant
Professional video features
Capability to output up to 36-bit TTL pixel data
Full color space converter on the output TTL pixel data
TTL video, audio, SPI, and interrupt pins disabled by default
Ability to synchronize output video to externally applied
reference sync signals
Video signal processor
Full 12-bit, 4:4:4 YCbCr (color space) internal processing
Motion adaptive deinterlacing with ultralow angle
interpolation
Multiple video processing paths with up to 3 simultaneous
video streams including picture-in-picture (PiP) support
Upscaling and downscaling to/from 4k × 2k
Aspect ratio conversion/panorama scaling
Cadence detection for the recovery of original frames from
film-based content
Dual video scalers enable simultaneous output of multiple
different resolutions
Sharpness and detail enhancement
Noise reduction for random, mosquito, and block noise
Frame rate converter (FRC)
Video metrics readback to enable correct phase and
frequency selection for graphics inputs
On-screen display (OSD)
Internally generated bitmap-based OSD allowing overlay
on one or more video outputs
Overlay on 3D and 4k × 2k video formats
Dedicated OSD scaler
Alpha blending of OSD data on video data
Disturbance free blending of OSD on either of 2 zones
Support for external OSD
APPLICATIONS
High end A/V receivers
Upconverting DVD players/recorders
Video conferencing and distribution
HDMI splitters
Video walls
FUNCTIONAL BLOCK DIAGRAM
DDR2 INTERFACE
ADV8005
TTL DATA
60-BIT
TTL PORT
24-BIT/
36-BIT/
48-BIT
VIDEO
INPUT
36-BIT
VIDEO
OUTPUT
OSD BUILD
AND SCALE
LOW ANGLE
PROCESSING
DETAIL
ENHANCE
CADENCE
DETECTION
NOISE
REDUCTION
MOTION
DETECTION
ENHANCE
DUAL SCALER
AND
OSD BLEND
FRC
HDMI Tx1
HDMI
HDMI Tx2
HDMI
HD VIDEO
DACs
HD VIDEO
SD VIDEO
DACs
SD VIDEO
CUE
CORRECTION
DEINTERLACER
VIDEO PROCESSING
SERIAL
VIDEO
RECEIVER
AUDIO INPUT
12074-001
SERIAL VIDEO
FOR EXAMPLE, ADV7850
OUTPUT
Figure 1.
Rev. 0
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©2014 Analog Devices, Inc. All rights reserved.
Technical Support
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ADV8005
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Professional Configuration ....................................................... 45
Applications ....................................................................................... 1
External Sync mode ................................................................... 45
Functional Block Diagram .............................................................. 1
Flexible Digital Core .................................................................. 45
Revision History ............................................................................... 2
Video Signal Processor (VSP) ................................................... 45
General Description ......................................................................... 3
On-Screen Display (OSD) ......................................................... 46
ADV8005 Models ......................................................................... 3
External DDR2 Memory ........................................................... 46
Detailed Functional Block Diagram .............................................. 4
HDMI Transmitters ................................................................... 46
Specifications..................................................................................... 5
Video Encoder ............................................................................ 46
Electrical Characteristics ............................................................. 5
Typical Application Diagram .................................................... 47
Analog Specifications ................................................................... 7
Design Considerations................................................................... 48
2
Data and I C Timing Characteristics ......................................... 7
Power-Up Sequence ................................................................... 48
Absolute Maximum Ratings.......................................................... 17
Thermal Considerations............................................................ 48
ESD Caution ................................................................................ 17
Register Map Architecture ............................................................ 49
Pin Configurations and Function Descriptions ......................... 18
Outline Dimensions ....................................................................... 50
Theory of Operation ...................................................................... 45
Ordering Guide .......................................................................... 50
Video Input.................................................................................. 45
REVISION HISTORY
6/14—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
Data Sheet
ADV8005
GENERAL DESCRIPTION
The ADV8005 is a multiple input video signal processor that can
deinterlace and scale standard definition (SD), enhanced
definition (ED), or high definition (HD) video data to ultra HD
formats; generate a bitmap on-screen display (OSD); and output
the video with OSD overlaid on two High-Definition Multimedia
Interface (HDMI®) transmitters and a video encoder.
The 60-bit TTL video port can be used to input video to the
ADV8005 in a number of ways: using the 48-bit TTL pixel port,
using the 24-bit external OSD TTL pixel port, or from a device
with an HDMI transmitter such as the ADV7850. The ADV8005
supports many of the formats outlined in the CEA-861-F and
VESA specifications, as well as several other widely used timing
formats.
The ADV8005 features primary and secondary video scalers
that enable simultaneous output of multiple different resolutions.
The primary video scaler can upscale to 4k × 2k modes. The
secondary video scaler can upscale to 1080p or UXGA graphics.
4k × 2k downscaling is performed using the secondary video
scaler, leaving the primary video scaler available for other video
processing.
The ADV8005 primary video scaler can perform high
performance, motion adaptive interlaced to progressive
conversion on SD and HD content. Additional functionality has
also been added to ADV8005 to facilitate upscaling and
downscaling to VESA formats with pixel clock frequencies below
300 MHz.
Detail enhancement and image enhancing techniques such as
random, mosquito, and block noise reduction allow improved
final image quality. The frame rate converter of the ADV8005
allows the conversion between common frame rates with support
to output two different frame rates simultaneously under certain
conditions.
The ADV8005 can accept OSD information from an external OSD
source on one of its inputs, or it can internally generate a high
quality, bitmap-based OSD. The internal OSD is highly flexible
and allows the system designer to easily incorporate features
like scrolling text and animation in various color depths up to
24-bit true color.
Analog Devices, Inc., provides an OSD development tool (Blimp)
to assist in the design, debug, and emulation of the OSD prior
to integration with the system application. When the design is
complete, the OSD development tool automatically generates
code to which system application programming interfaces
(APIs) can be added before integration with the system
application and an OSD design resource, which must be
downloaded to an external SPI flash memory.
Video can be output from the ADV8005 using one or both of the
HDMI transmitters and/or the six-DAC SD/HD video encoder.
The six 12-bit NSV® video DACs allow composite (CVBS),
S-Video (Y/C), and component (YPrPb) analog outputs in
standard, enhanced, and high definition video formats.
Oversampling of 216 MHz (SD and ED) and 297 MHz (HD)
removes the requirement for external output filtering. Rovi® and
non-Rovi variants of the ADV8005 are available.
Both of the HDMI transmitters on the ADV8005 support 4k × 2k
and all mandatory and many optional 3D video resolutions. Each
transmitter features an audio return channel receiver (ARC).
The ADV8005 can receive up to eight channels of I2S, S/PDIF,
direct stream digital (DSD), and high bit rate (HBR) audio passed
from either the serial video Rx or from the externally available
audio input pins.
The ADV8005 supports the I2C protocol for communication
with the system microcontroller.
ADV8005 MODELS
The ADV8005 includes a number of models, each featuring
different capabilities; all are provided in the same 19 mm ×
19 mm, 425-ball CSP_BGA package (see Table 9).
Note that the functionality of the ADV8005KBCZ-8A is
described throughout this data sheet. Some sections are not
relevant to other models because not all of the blocks found in
the ADV8005KBCZ-8A are included in those models. Table 9
lists the functionality for each model.
Rev. 0 | Page 3 of 52
Rev. 0 | Page 4 of 52
Figure 2. ADV8005KBCZ-8A Functional Block Diagram
DDR_DQ[31:0]
RESET
GENERATION
AND POWER
MANAGEMENT
TOP LEVEL
CONTROL
CLOCK
GENERATION
POWER
SUPPLY
TO VBI
INSERTION
IN ENCODER
BLOCK
DETAIL
ENHANCEMENT
BLOCK
NOISE
REDUCTION
MOSQUITO
NOISE
REDUCTION
RANDOM
NOISE
REDUCTION
VIDEO
ENHANCEMENT
FRAME
RATE
CONVERTER
SCALER 2
SCALER 1
SCALING AND
FRAME RATE
CONVERSION
ARC PORT
HEAC_1+
MASTER
TIMING
BLOCK
HEAC
VIDEO PROCESSING AND OSD BLENDING
CUE
CORRECTION
CADENCE
DETECTION
LOW ANGLE
PROCESSING
MOTION
DETECTION
DE-INTERLACER
AND CADENCE
DETECTION
SPI
SLAVE
I2C SLAVE
I/O, OSD, ENCODER
VSP, HDMI Tx
REGISTER MAPS
SPI
MASTER
OSD
SCALER
BITMAP OSD
CONTROLLER
OSD
GENERATION
CONTROL
OSD VIDEO
BLEND
DDR_VREF
INT0
INT1
INT2
XTALP
XTALN
SPI SLAVE
OSD VIDEO
CAPTURE
AND
FORMATTING
DDR_DQS[3:0]
OSD_IN[15:13]/
VBI_x
OSD_IN[23:16]/
EXT_DIN[7:0],
OSD_IN[11:0]
OSD_DE
OSD_CLK
OSD_IN[12]
OSD_VS
OSD_HS
PCLK
DE
VS
DIGITAL
VIDEO
CAPTURE
AND
FORMATTING
RECEIVER
DDR_DM[3:0]
HS
P[35:0]
RX_0P
RX_0N
RX_1P
RX_1N
RX_2P
RX_2N
RX_CP
RX_CN
RX_HPD
RX_5V
DDR_DQS[3:0]
COLOR SPACE
CONVERSION
UPDITHER
DDR_BA[2:0]
COLOR SPACE
CONVERSION
UPDITHER
DDR_A[13:0]
VIDEO MUXING
DDR_CAS
DDR2 CONTROLLER INTERF ACE
DDR_RAS
COLOR SPACE
CONVERSION
UPDITHER
DDR_WE
COLOR SPACE
CONVERSION
DDR_CK
VBI DATA SERVICE
INSERTION
PROGRAMMABLE
CHROMINANCE
FILTERS
PROGRAMMABLE
LUMINANCE
FILTERS
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
SUBCARRIER
FREQ LOCK
SIN/COS
MODULATION/COS
SYNC
INSERTION
REFERENCE
AND CABLE
DETECTION
12-BIT
DAC6
12-BIT
DAC5
12-BIT
DAC4
12-BIT
DAC3
12-BIT
DAC2
12-BIT
DAC1
TMDS
OUTPUTS
HDCP
KEYS
TMDS
OUTPUTS
HDCP
ENCRYPTION
ENCODER
4:2:2
4:4:4
AND
COLOR SPACE
CONVERTER
HDMI Tx
VIDEO DATA
CAPTURE
PROGRAMMABLE
HDTV FILTERS
4:2:2
4:4:4
AND
COLOR SPACE
CONVERTER
HDMI Tx
VIDEO DATA
CAPTURE
HDCP
KEYS
I2C
MASTER
HDCP
ENCRYPTION
HDCP AND EDID
UNCONTROLLER
AUDIO DATA CAPTURE
Auto Position
Auto-Phase
ED/HD
PROCESSOR
DDR_CK
SD
PROCESSOR
DDR_CS
16×/4× OVERSAMPLING FILTERS
MCLK
2 × PLLs
SCLK
MULTIPLEXER
AUD_IN[5:0]
MUXING
DSD_CLK
DDR2 INTERFACE
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
TX2_0+
TX2_0–
TX2_1+
TX2_1–
TX2_2+
TX2_2–
TX2_C+
TX2_C–
TX1_0+
TX1_0–
TX1_1+
TX1_1–
TX1_2+
TX1_2–
TX1_C+
TX1_C–
HPD_TX1
HPD_TX2
DDC1_SCL
DDC1_SDA
DDC2_SCL
DDC2_SDA
ADV8005
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
COMPx
RSETx
VREF
ELPFx
SFL
ALSB
SCL
SDA
CS2
SCK2
MISO2
MOSI2
CS1
SCK1
MISO1
MOSI1
HEAC_1–
REF_CLK
HEAC_2–
HEAC_2+
ARC1_OUT
ARC2_OUT
REF_HS
REF_VS
DVDD_IO
PVDD_DDR
DVDD_DDR
AVDDx
CVDD1
PVDDx
DVDD
PDN
RESET
12074-003
Data Sheet
ADV8005
SPECIFICATIONS
Measured at DVDD = 1.746 V to 1.854 V, DVDD_DDR = 1.746 V to 1.854 V, PVDD1 = 1.746 V to 1.854 V, PVDD2 = 1.746 V to 1.854 V,
PVDD3 = 1.746 V to 1.854 V, PVDD5 = 1.789 V to 1.90 V, PVDD6 = 1.789 V to 1.90 V, PVDD_DDR = 1.746 V to 1.854 V, AVDD3 =
1.746 V to 1.854 V, AVDD4 = 1.746 V to 1.854 V, CVDD1 = 1.746 V to 1.854 V, AVDD1 = 3.20 V to 3.40 V, AVDD2 = 3.20 V to 3.40 V,
DVDD_IO = 3.20 V to 3.40 V, TMIN to TMAX = 0°C to 70°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity, +ve1
Integral Nonlinearity, −ve1
Differential Nonlinearity, +ve2
Differential Nonlinearity, −ve2
DIGITAL INPUTS
Input High Voltage
Symbol
Test Conditions/Comments
INL
INL
DNL
DNL
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
DAC outputs sampled at 500 kHz
VIH
Input Low Voltage
VIL
Input Leakage Current
IIN
Input Capacitance
DIGITAL INPUTS (5 V TOLERANT)
Input High Voltage
Input Low Voltage
Input Leakage Current
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage
Current
Output Capacitance
POWER REQUIREMENTS3, 4
Digital Power Supplies
PLL Analog Supply
PLL Digital Supply
Encoder PLL Supply
HDMI PLL Power Supply5
Transmitter 1 (Tx1)
Transmitter 2 (Tx2)
HDMI Analog Power Supply
Tx1
Tx2
Comparator Power Supply
HDMI Rx Inputs Analog
Supply
Encoder Analog Power
Supply
Digital Interface Supply
Min
Typ
Max
12
0.389
−0.322
0.183
−0.208
Bits
LSB
LSB
LSB
LSB
0.7 ×
DVDD_IO
V
HDMI Ethernet and audio channel
(HEAC_x±) inputs
DDR_DQS[x] inputs
Other digital inputs
RESET
CIN
0.3 ×
DVDD_IO
±60
V
±60
±10
±60
μA
μA
μA
pF
13
VIH
VIL
IIN
3.4
VOH
VOL
ILEAK
2.4
COUT
Unit
μA
0.8
±60
V
V
μA
0.4
±10
V
V
μA
13
pF
DVDD, DVDD_DDR,
PVDD_DDR
PVDD1
PVDD2
PVDD3
1.746
1.8
1.854
V
1.746
1.746
1.746
1.8
1.8
1.8
1.854
1.854
1.854
V
V
V
PVDD5
PVDD6
1.789
1.789
1.845
1.845
1.90
1.90
V
V
AVDD3
AVDD4
CVDD1
AVDD1
1.746
1.746
1.746
3.20
1.8
1.8
1.8
3.3
1.854
1.854
1.854
3.40
V
V
V
V
AVDD2
3.20
3.3
3.40
V
DVDD_IO
3.20
3.3
3.40
V
Rev. 0 | Page 5 of 52
ADV8005
Parameter
Digital Power Supply
Currents
Data Sheet
Symbol
IDVDD, IDVDD_DR, IPVDD_DDR
Test Conditions/Comments
Mode 1
Min
Typ
1693.9
Max
Unit
mA
PLL Analog Supply Current
IPVDD1
PLL Digital Supply Current
IPVDD2
Encoder PLL Supply Current
IPVDD3
HDMI Tx1 PLL Supply Current
IPVDD5
HDMI Tx2 PLL Supply Current
IPVDD6
HDMI Tx1 Analog Power
Supply Current
IAVDD3
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
IAVDD4
Mode 2
Power-down mode
Mode 1
19.7
0
26.6
mA
mA
mA
ICVDD1
Mode 2
Power-down mode
Mode 1
0.6
0
78.4
mA
mA
mA
IAVDD1
Mode 2
Power-down mode
Mode 1
73.4
1.1
63.1
mA
mA
mA
Mode 2
Power-down mode
Mode 1
Mode 2
Power-down mode
Mode 1
57.6
0.2
38.0
34.9
2.1
3.0
mA
mA
mA
mA
mA
mA
Mode 2
Power-down mode
1.3
0
mA
mA
HDMI Tx2 Analog Power
Supply Current
Comparator Power Supply
Current
HDMI Rx Inputs Analog
Supply Current
Encoder Analog Power Supply
IAVDD2
Digital Interface Supply
Current
IDVDD_IO
1
1508.1
11.7
23.0
20.5
0.9
21.3
19.26
0.06
13.8
3.27
0.01
74.9
59.0
0
75.0
0.5
0
29.4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Integral nonlinearity (INL) measures the deviation of the actual DAC transfer function from the ideal. For +ve INL, the actual line lies above the ideal line value. For −ve INL,
the actual line lies below the ideal line value.
2
Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
3
Mode 1 involves a 1080i, 60 Hz input to the ADV8005 receiver and a 720p, 60 Hz input to the ADV8005 TTL external OSD input. Both inputs are run through the frontend color space converters. The 1080i, 60 Hz video stream is deinterlaced and upscaled to 4k × 2k at 24 Hz. The 720p video stream is input to the OSD block and is
blended onto the 4k × 2k at 24 Hz video stream using the OSD block scaler. Both HDMI transmitters are then driven using the 4k × 2k at 24 Hz output.
4
Mode 2 involves a 1080i, 60 Hz input to the ADV8005 receiver. This input is run through the front-end color space converter. The 1080i, 60 Hz video stream is
deinterlaced and is output to HDMI Tx1. The secondary VSP is used to convert the 1080p video stream to 480i and is output using the SD encoder.
5
For normal operation, set the Tx PVDD5 and PVDD6 supplies to 1.845 V ± 3%. However, if the ADV8005 die temperature is kept below 100°C, it is possible to use
PVDD5 and PVDD6 with a reduced nominal voltage supply level of 1.8 V ± 3%. It is possible to measure the die temperature (TJ) of the ADV8005 using the method
outlined in the Thermal Considerations section. If using this reduced voltage level with Tx PVDD5 and PVDD6, it is the responsibility of the customer to ensure that the
die temperature is below 100°C when used in the highest power mode of the application and at its highest ambient temperature.
Rev. 0 | Page 6 of 52
Data Sheet
ADV8005
ANALOG SPECIFICATIONS
Table 2.
Parameter
OUTPUT
Low Drive Output Current (Full Scale)
Output Compliance
Output Capacitance
Symbol
VOC
COUT
DAC
DAC-to-DAC Matching
DAC Analog Output Skew
Test Conditions/Comments
Min
Typ
Max
Unit
RSET = 4.12 kΩ, RL = 300 Ω
3.95
0
4.3
4.5
1.4
DAC1, DAC2, DAC3
DAC4, DAC5, DAC6
9
9
mA
V
pF
pF
DAC1 to DAC6
DAC1 to DAC6
0.9
0.2
%
ns
DATA AND I2C TIMING CHARACTERISTICS
For input timing measurements, VIH = DVDD_IO and VIL = GND.
Table 3.
Parameter
TMDS CLOCK
TMDS Input Clock Frequency
TMDS Output Clock Frequency
CLOCK AND CRYSTAL
Crystal (XTAL) Frequency
Stability
Video Input Clock Frequency
Range
Primary
Secondary
Video Output Clock Frequency
Range
Serial Clock Frequency
Serial Port 1 (SCK1)
Serial Port 2 (SCK2)
Serial Port 3 (VBI_SCK)
Audio Frequency
SCLK
MCLK
DSD_CLK
FAST I2C PORTS1
SCL Frequency
SCL Minimum Pulse Width High
SCL Minimum Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
SDA Setup Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Stop Condition Setup Time
SERIAL PORT2, 3
Master Serial Port (Serial Port 2)
CS2 Falling Edge to SCK2
Rising/Falling Edge
SCK2 Rising/Falling Edge to
CS2 Rising Edge
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
297
297
MHz
MHz
±50
MHz
ppm
13.5
13.5
13.5
162
162
162
MHz
MHz
MHz
11.5
50
81
27
MHz
MHz
MHz
49.152
98.304
5.6448
MHz
MHz
MHz
400
kHz
ns
μs
ns
ns
ns
ns
ns
μs
25
25
27
See Figure 3
t1
t2
t3
t4
t5
t6
t7
t8
t9, t10
t11, t12
600
1.3
600
600
100
300
300
0.6
See Figure 4, Figure 5, and
Figure 6
t9 or t10, depending on the
values of CPHA and CPOL
t11 or t12, depending on the
values of CPHA and CPOL
1 × SCK24
1.5 × SCK24
ns
1 × SCK24
1.5 × SCK24
ns
Rev. 0 | Page 7 of 52
ADV8005
Parameter
CS2 Pulse Width
SCK2 High Time
SCK2 Low Time
MOSI2 Start of Data Invalid to
SCK2 Falling Edge
CS2 Start of Data Invalid to
SCK2 Falling Edge
SCK2 Falling Edge to MOSI2 End
of Data Invalid
SCK2 Falling Edge to CS2 End
of Data Invalid
MISO2 Setup Time
Data Sheet
Symbol
t13
t14
Test Conditions/Comments
t15
SPI Mode 0, SPI Mode 3
Max
1900
0.55 × SCK24
0.55 × SCK24
1.45
Unit
ns
% duty cycle
% duty cycle
ns
t15
SPI Mode 0, SPI Mode 3
1.21
ns
t16
SPI Mode 0, SPI Mode 3
0.08
ns
t16
SPI Mode 0, SPI Mode 3
0.19
ns
t17
MISO2 Hold Time
t18
MOSI2 Start of Data Invalid to
SCK2 Rising Edge
CS2 Start of Data Invalid to
SCK2 Rising Edge
SCK2 Rising Edge to MOSI2 End
of Data Invalid
SCK2 Rising Edge to CS2 End
of Data Invalid
MISO2 Setup Time
t19
Valid regardless of the
SCK2 active edge used
Valid regardless of the
SCK2 active edge used
SPI Mode 1, SPI Mode 2
t19
MISO2 Hold Time
Typ
11.19
ns
0.0
ns
1.45
ns
SPI Mode 1, SPI Mode 2
1.21
ns
t20
SPI Mode 1, SPI Mode 2
0.08
ns
t20
SPI Mode 1, SPI Mode 2
0.19
ns
t21
Valid regardless of the
SCK2 active edge used
Valid regardless of the
SCK2 active edge used
See Figure 7, Figure 8, and
Figure 9
t23 or t24, depending on the
values of CPHA and CPOL
t25 or t26, depending on the
values of CPHA and CPOL
t22
Slave Mode (Serial Port 1)
CS1 Falling Edge to SCK1
Rising/Falling Edge
SCK1 Rising/Falling Edge to
CS1 Rising Edge
CS1 Pulse Width
SCK1 High Time
SCK1 Low Time
MOSI1 Setup Time
MOSI1 Hold Time
SCK1 Falling Edge to MISO1
Start of Data Invalid
SCK1 Falling Edge to MISO1 End
of Data Invalid
MOSI1 Setup Time
MOSI1 Hold Time
SCK1 Rising Edge to MISO1 Start
of Data Invalid
SCK1 Rising Edge to MISO1 End
of Data Invalid
Slave Mode (Serial Port 3)
VBI_SCK High Time
VBI_SCK Low Time
VBI_CS Pulse Width
VBI_CS, VBI_MOSI Setup Time
VBI_CS, VBI_MOSI Hold Time
Min
1880
0.45 × SCK24
0.45 × SCK24
t23, t24
t25, t26
11.19
ns
0.0
ns
50.0
ns
50.0
ns
5 × SCK14
t27
t30
4
t31
t32
t33
SPI Mode 0, SPI Mode 3
SPI Mode 0, SPI Mode 3
SPI Mode 0, SPI Mode 3
t34
SPI Mode 0, SPI Mode 3
t35
t36
t37
SPI Mode 1, SPI Mode 2
SPI Mode 1, SPI Mode 2
SPI Mode 1, SPI Mode 2
t38
SPI Mode 1, SPI Mode 2
5.7
ns
% duty cycle
% duty cycle
ns
ns
ns
12.16
ns
5.7
ns
ns
ns
12.16
ns
0.55 × VBI_SCK4
0.55 × VBI_SCK4
% duty cycle
% duty cycle
ns
ns
ns
0.55 × SCK14
0.55 × SCK14
0.45 × SCK1
0.45 × SCK14
1.63
0.66
1.63
0.66
See Figure 10
0.45 × VBI_SCK4
0.45 × VBI_SCK4
t39
5 × VBI_SCK
t40
t41
SPI Mode 0 only
SPI Mode 0 only
1.27
0.15
Rev. 0 | Page 8 of 52
Data Sheet
Parameter
SPI Passthrough Mode
Data Transition on SCK1 to
Start of Data Invalid on SCK2
Data Transition on SCK1 to End
of Data Invalid on SCK2
Data Transition on MOSI1 to
Start of Data Invalid on
MOSI2
Data Transition on MOSI1 to
End of Data Invalid on
MOSI2
Data Transition on MISO2 to
Start of Data Invalid on
MISO1
Data Transition on MISO2 to
End of Data Invalid on
MISO1
Data Transition on CS1 to
Start of Data Invalid on CS2
Data Transition on CS1 to End
of Data Invalid on CS2
RESET FUNCTION
Reset Pulse Width
VIDEO DATA AND CONTROL INPUTS3
PCLK High Time
PCLK Low Time
OSD_CLK High Time
OSD_CLK Low Time
Main Video Input, SDR and DDR
Modes Setup Time (Data
Latched on Rising Edge)
Main Video Input, SDR and DDR
Modes Hold Time (Data
Latched on Rising Edge)
Main Video Input, DDR Mode
Setup Time (Data Latched on
Falling Edge)
Main Video Input, DDR Mode
Hold Time (Data Latched on
Falling Edge)
Interleaved Video Input, SDR
Setup Time (Data Latched on
Rising Edge)
Interleaved Video Input, SDR
Hold Time (Data Latched on
Rising Edge)
External OSD Input, SDR and DDR
Modes Setup Time (Data
Latched on Rising Edge)
External OSD Input, SDR and DDR
Modes Hold Time (Data
Latched on Rising Edge)
External OSD Input, DDR Mode
Setup Time (Data Latched on
Rising Edge)
External OSD Input, DDR Mode
Hold Time (Data Latched on
Rising Edge)
ADV8005
Symbol
Test Conditions/Comments
See Figure 11
Min
Typ
Max
Unit
t42
4.97
ns
t43
10.10
ns
t42
5.32
ns
t43
10.82
ns
t42
4.36
ns
t43
8.85
ns
t42
5.32
ns
t43
10.91
ns
5
ms
See Figure 12 to Figure 16
t45
0.45 × PCLK4
0.45 × PCLK4
0.45 × OSD_CLK4
0.45 × OSD_CLK4
1.28
t46
1.67
ns
t47
1.28
ns
t48
1.67
ns
t44
t51
OSD_CLK signal of Pin A3
OSD_CLK signal of Pin A3
0.55 × PCLK4
0.55 × PCLK4
0.55 × OSD_CLK4
0.55 × OSD_CLK4
% duty cycle
% duty cycle
% duty cycle
% duty cycle
ns
t49
Used for 300 MHz TTL data
1.28
ns
t50
Used for 300 MHz TTL data
1.67
ns
t52
1.28
ns
t53
1.67
ns
t54
1.28
ns
t55
1.67
ns
Rev. 0 | Page 9 of 52
ADV8005
Parameter
VIDEO DATA AND CONTROL
OUTPUTS3
OSD_CLK High Time
OSD_CLK Low Time
Data and Control Start of Data
Invalid to OSD_CLK Active
Edge (Data Latched on Falling
Edge)
OSD_CLK Active Edge to Data
and Control End of Data
Invalid (Data Latched on
Falling Edge)
Data and Control Start of Data
Invalid to OSD_CLK Active
Edge (Data Latched on Rising
Edge)
OSD_CLK Active Edge to Data
and Control End of Data
Invalid (Data Latched on Rising
Edge)
S/PDIF INPUT3
MCLK High Time
MCLK Low Time
S/PDIF Data Setup Time
S/PDIF Data Hold Time
I2S PORT, SLAVE MODE3
SCLK High Time
SCLK Low Time
I2S Data Setup Time
I2S Data Hold Time
DSD PORT3
DSD_CLK High Time
DSD_CLK Low Time
DSD Data Setup Time
DSD Data Hold Time
EXTERNAL SYNC TIMING MODE3
REF_CLK High Time
REF_CLK Low Time
REF Data Setup Time
REF Data Hold Time
Data Sheet
Symbol
Test Conditions/Comments
See Figure 17 and Figure 18
Min
Typ
Max
Unit
t57
0.60 × OSD_CLK4
0.60 × OSD_CLK4
0.3
% duty cycle
% duty cycle
ns
t58
1.66
ns
t59
0.62
ns
t60
1.12
ns
0.45 × MCLK4
0.45 × MCLK4
1.4
1.38
0.55 × MCLK4
0.55 × MCLK4
% duty cycle
% duty cycle
ns
ns
0.45 × SCLK4
0.45 × SCLK4
1.91
1.1
0.55 × SCLK4
0.55 × SCLK4
% duty cycle
% duty cycle
ns
ns
0.45 × DSD_CLK4
0.45 × DSD_CLK4
1.66
1.44
0.55 × DSD_CLK4
0.55 × DSD_CLK4
% duty cycle
% duty cycle
ns
ns
0.45 × REF_CLK4
0.45 × REF_CLK4
1.35
1.33
0.55 × REF_CLK4
0.55 × REF_CLK4
% duty cycle
% duty cycle
ns
ns
0.40 × OSD_CLK4
0.40 × OSD_CLK4
t56
See Figure 19 and Figure 20
t61
t62
t63
See Figure 21
t64
t65
t66
See Figure 26
t67
t68
t69
See Figure 27
t70
t71
t72
It is possible to run I2C at faster speeds; however, it has been characterized to run only in fast mode.
All serial port measurements are for the default polarity and phase settings (clock low in idle state and negative edge used).
3
All measurements are guaranteed by design only.
4
Specification is in clock periods; for example, 1 × SCK2 periods.
1
2
Rev. 0 | Page 10 of 52
Data Sheet
ADV8005
Timing Diagrams
t3
t5
t3
SDA
t6
t1
t2
t7
t4
12074-004
SCL
t8
Figure 3. I2C Timing
t13
t9
t11
t10
t12
CS2
0
0
0
SCK2
1
0
1
SCK2
2
1
0
SCK2
3
1
1
SCK2
INSTRUCTION (0x0B)
MOSI2
24-BIT ADDRESS
23 22 21 ... 3
2
1
DUMMY BYTE
0
7
6
5
4
3
2
1
0
DATA OUT 1
MISO2
7
6
5
4
3
2
DATA OUT 2
1
0
7
6
5
4
3
2
1
12074-005
SPI
MODE CPOL CPHA
0
Figure 4. Detailed SPI Master Timing Diagram (Serial Port 2)
t14
t17
t17
t18
t15
t18
t16
SCK2
MOSI2
CS2
MISO2
(FALLING EDGE CAPTURE)
12074-006
MISO2
(RISING EDGE CAPTURE)
Figure 5. Serial Port 2 Master Mode Timing (SPI Mode 0 and SPI Mode 3)
t14
t21
t19
t20
t21
t22
t22
SCK2
MOSI2
CS2
MISO2
(RISING EDGE CAPTURE)
12074-007
MISO2
(FALLING EDGE CAPTURE)
Figure 6. Serial Port 2 Master Mode Timing (SPI Mode 1 and SPI Mode 2)
Rev. 0 | Page 11 of 52
ADV8005
Data Sheet
t27
t23
SPI
MODE CPOL CPHA
CS1
0
0
0
SCK1
1
0
1
SCK1
2
1
0
SCK1
3
1
1
SCK1
t25
t26
t24
W/R
MOSI1
7
6
5
4
3
2
SUBADDRESS
1
0
7
6
5
4
3
2
DATA IN 0
1
0
7
6
5
4
3
2
DATA IN 1
1
0
7
6
5
DUMMY BYTE
7
6
5
DATA OUT 0
7
6
5
4
3
2
3
2
1
0
1
0
1
0
DATA OUT 0
DELAY MODE 1
MISO1
DELAY MODE 0
MISO1
4
4
3
2
DATA OUT 1
1
0
7
6
5
4
3
2
12074-008
DEVICE ADDRESS
Figure 7. Detailed SPI Slave Timing Diagram (Serial Port 1)
t30
t31
t34
t32
t33
SCK1
MOSI1
12074-009
MISO1
Figure 8. Serial Port 1 Slave Mode Timing (SPI Mode 0 and SPI Mode 3)
t30
t35
t38
t37
t36
SCK1
12074-010
MOSI1
MISO1
Figure 9. Serial Port 1 Slave Mode Timing (SPI Mode 1 and SPI Mode 2)
t39
t40
t41
VBI_SCK
12074-011
VBI_CS
VBI_MOSI
Figure 10. Serial Port 3 Slave Mode Timing (SPI Mode 0 Only)
Rev. 0 | Page 12 of 52
Data Sheet
ADV8005
t43
t42
SCK1
MISO2
MOSI1
CS1
12074-012
SCK2
MISO1
MOSI2
CS2
Figure 11. SPI Passthrough Mode (Serial Port 1 and Serial Port 2)
t45
t44
t46
PCLK
12074-013
P[35] TO P[0]
HS
VS
DE
Figure 12. Main Video Input, Noninterleaved SDR Video Data and Control Timing
t44
PCLK
t47
t45
t46
t48
12074-014
P[35] TO P[0]
HS
VS
DE
Figure 13. Main Video Input, Noninterleaved DDR Video Data and Control Timing
t44
PCLK
t49
t50
OSD_IN[11] TO OSD_IN[0]
P[35] TO P[24]
12074-015
P[23] TO P[0]
HS
VS
DE
Figure 14. Interleaved SDR Video Data and Control Input Timing
t51
OSD_CLK
t52
t53
12074-016
OSD_IN[23] TO OSD_IN[0]
OSD_HS
OSD_VS
OSD_DE
Figure 15. External OSD Input, Noninterleaved SDR Video Data and Control Timing
Rev. 0 | Page 13 of 52
ADV8005
Data Sheet
t51
OSD_CLK
t54
t53
t55
t52
12074-017
OSD_IN[23] TO OSD_IN[0]
OSD_HS
OSD_VS
OSD_DE
Figure 16. External OSD Input, Noninterleaved DDR Video Data and Control Timing
t56
OSD_CLK
t57
t58
12074-018
OSD_IN[23] TO OSD_IN[0]
P[35] TO P[24]
OSD_HS
OSD_VS
OSD_DE
Figure 17. SDR Video Data and Control Output Timing (Data Launched on Falling Edge)
t56
OSD_CLK
t59
t60
12074-019
OSD_IN[23] TO OSD_IN[0]
P[35] TO P[24]
OSD_HS
OSD_VS
OSD_DE
Figure 18. SDR Video Data and Control Output Timing (Data Launched on Rising Edge)
t61
MCLK
t63
12074-020
t62
AUD_IN[0]
Figure 19. S/PDIF Input Timing, Data Latched on Rising Edge
SYNC IMPULSE
DATA
1.5 × tMCLK
tMCLK
0.5 × tMCLK
Figure 20. S/PDIF Data Timing
Rev. 0 | Page 14 of 52
12074-021
AUD_IN[0]
Data Sheet
ADV8005
t64
SCLK
t65
t66
12074-022
AUD_IN[4] TO AUD_IN[1]
AUD_IN[5]
Figure 21. I2S Timing
AUD_IN[5]
LEFT
RIGHT
SCLK
LSB
LSB
MSBRIGHT
32 CLOCK SLOTS
32 CLOCK SLOTS
12074-023
MSBLEFT
AUD_IN[4] TO AUD_IN[1]
I2S STANDARD
I2S FORMAT = 00
Figure 22. I2S Standard Audio—Data Width of 16 Bits to 24 Bits per Channel
AUD_IN[5]
LEFT
RIGHT
SCLK
AUD_IN[4] TO AUD_IN[1]
MSB
MSB
MSB
MSB
MSB – 1
LSB
MSB
MSB
EXTENDED
MSB
MSB
MSB
MSB – 1
LSB
MSB
EXTENDED
32 CLOCK SLOTS
32 CLOCK SLOTS
12074-025
SERIAL AUDIO
RIGHT JUSTIFIED
I2S FORMAT = 01
Figure 23. Serial Audio—Right Justified
AUD_IN[5]
LEFT
RIGHT
SCLK
MSB
LSB
MSB
32 CLOCK SLOTS
LSB
32 CLOCK SLOTS
SERIAL AUDIO
LEFT JUSTIFIED
2
I S FORMAT = 10
Figure 24. Serial Audio—Left Justified
Rev. 0 | Page 15 of 52
12074-026
AUD_IN[4] TO AUD_IN[1]
ADV8005
AUD_IN[5]
Data Sheet
CHANNEL A
CHANNEL B
SCLK
MSB
V
U
C
P
LSB
MSB
V
U
32 CLOCK SLOTS
C
P
32 CLOCK SLOTS
FRAME n
FRAME n + 1
AES3 DIRECT AUDIO
I2S FORMAT = 11
Figure 25. AES3 Direct Audio
t67
DSD_CLK
t69
12074-028
t68
AUD_IN[4] TO AUD_IN[1]
Figure 26. DSD Timing
t70
REF_C LK
t71
REF_HS
REF_VS
t72
Figure 27. External Sync Timing
Rev. 0 | Page 16 of 52
12074-027
LSB
12074-028
AUD_IN[4] TO AUD_IN[1]
Data Sheet
ADV8005
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
AVDD1, ADDD2, DVDD_IO to GND
DVDD, PVDDx, CVDD1, AVDD3, AVDD4,
DVDD_DDR, PVDD_DDR to GND
DVDD to Other 1.8 V Power Supplies1
PVDD1 to Other 1.8 V Power Supplies1
PVDD2 to Other 1.8 V Power Supplies1
PVDD3 to Other 1.8 V Power Supplies1
PVDD5 to Other 1.8 V Power Supplies1
PVDD6 to Other 1.8 V Power Supplies1
CVDD1 to Other 1.8 V Power Supplies1
AVDD3 to Other 1.8 V Power Supplies1
AVDD4 to Other 1.8 V Power Supplies1
DVDD_DDR to Other 1.8 V Power
Supplies1
PVDD_DDR to Other 1.8 V Power
Supplies1
Digital Inputs to GND
Serial Video Inputs to GND
DDR_VREF to GND
DDR Inputs to GND
DDR Outputs to GND
5 V Tolerant Digital Inputs to GND2
1.8 V Analog Inputs to GND
3.3 V Analog Inputs to GND
HDMI Digital Outputs to GND
Digital Outputs Voltage to GND
Analog Outputs Voltage to GND3
Maximum Junction Temperature (TJ MAX)
Storage Temperature Range
Infrared Reflow Soldering (20 sec)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rating
3.9 V
2.2 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
ESD CAUTION
−0.3 V to +0.3 V
−0.3 V to DVDD_IO + 0.3 V
−0.3 V to CVDD1 + 0.3 V
−0.3 V to DVDD_DDR + 0.3 V
−0.3 V to DVDD_DDR + 0.3 V
−0.3 V to DVDD_DDR + 0.3 V
−0.3 V to +5.5 V
−0.3 V to AVDD3 + 0.3 V
−0.3 V to AVDD2 + 0.3 V
−0.3 V to AVDD3 + 0.3 V
−0.3 V to DVDD_IO + 0.3 V
−0.3 V to AVDD2 + 0.3 V
125°C
−65°C to +150°C
260°C
1
This includes the 1.8 V power supplies (DVDD, PVDD1, PVDD2, PVDD3,
CVDD1, AVDD3, AVDD4, DVDD_DDR, and PVDD_DR) and the 1.845 V
supplies (PVDD5 and PVDD6).
2
The following inputs are 5 V tolerant:, DDC1_SCL, DDC2_SCL, DDC1_SDA,
DDC2_SDA, HEAC_1−, HEAC_1+, HEAC_2−, HEAC_2+, RX_5V, and RX_HPD.
3
Except the ELPF1 and ELPF2 outputs, which are kept to −0.3 V to PVDD3 +
0.3 V; the RTERM output, which is kept to −0.3 V to CVDD1 + 0.3 V; and the
R_TX1 and R_TX2 outputs, which are kept to −0.3 V to PVDD5 + 0.3 V.
Rev. 0 | Page 17 of 52
ADV8005
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
3
4
5
6
9
10
A
OSD_
DE
OSD_
CLK/
EXT_
CLK
AUD_
IN[1]
AUD_
IN[2]
AUD_
IN[5]
ARC2_
OUT MOSI1
SCK2
CS2
B
OSD_
IN[21]/
EXT_
DIN[5]
OSD_
IN[22]/
EXT_
DIN[6]
OSD_
VS
AUD_
IN[0]
AUD_
IN[3]
SFL
ARC1_
MISO1
OUT
MOSI2 MISO2
C
OSD_
IN[19]/
EXT_
DIN[3]
OSD_
IN[20]/
EXT_
DIN[4]
GND
AUD_
IN[4]
DSD_
CLK
SCLK
SCL
SCK1
GND
D
OSD_
IN[16]/
EXT_
DIN[0]
OSD_
IN[17]/
EXT_
DIN[1]
OSD_
IN[18]/
EXT_
DIN[2]
GND
DVDD_
IO
MCLK
SDA
CS1
GND
E
OSD_
OSD_
OSD_
IN[13]/
IN[14]/
IN[15]/
VBI_SCK VBI_MOSI VBI_CS
7
8
11
12
13
RESET XTALN PVDD2
14
15
DNC
DNC
16
17
CVDD1 RX_C–
18
19
20
RX_0–
RX_1–
RX_2–
RX_2+
21
22
23
VREF
A
COMP1
DAC4
B
AVDD1 AVDD1
DAC5
DAC6
C
RTERM AVDD2 AVDD2
DAC1
DAC2
D
TEST2
COMP2
DAC3
E
RSET2 PVDD3
GND
DNC
F
GND
AVDD3
G
ALSB
XTALP
PVDD1
DNC
DNC
GND
RX_C+
RX_0+
RX_1+
INT0
PDN
GND
GND
DNC
REF_
CLK
RX_
HPD
AVDD1
GND
GND
INT1
INT2
DVDD_
IO
TEST1
REF_
HS
REF_
VS
RX_5V
DNC
DNC
DVDD_
IO
CVDD1 RSET1
GND
GND
F
OSD_
IN[9]
OSD_
IN[10]
OSD_
IN[11]
OSD_
IN[12]
G
OSD_
IN[5]
OSD_
IN[6]
OSD_
IN[7]
OSD_
IN[8]
GND
GND
GND
DVDD
GND
GND
DVDD
GND
GND
GND
GND
ELPF1
ELPF2
H
OSD_
IN[1]
OSD_
IN[2]
OSD_
IN[3]
OSD_
IN[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX1_2+ TX1_2–
H
J
DE
HS
OSD_
HS
OSD_
IN[0]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC1_
SDA
GND
TX1_1+ TX1_1–
J
K
VS
PCLK
DVDD_ DVDD_
IO
IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC1_
SCL
GND
TX1_0+ TX1_0–
K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_
TX1
GND
TX1_C+ TX1_C–
L
R_TX1
PVDD5
HEAC_ HEAC_
1+
1–
M
PVDD5 AVDD4 AVDD3
N
L
P[32]
P[33]
P[34]
P[35]
DVDD
M
P[28]
P[29]
P[30]
P[31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
N
P[24]
P[25]
P[26]
P[27]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
TX2_2+ TX2_2–
P
P
P[20]
P[21]
P[22]
P[23]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC2_
SCL
R
P[16]
P[17]
P[18]
P[19]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC2_
SDA
GND
TX2_1+ TX2_1–
R
T
P[14]
P[15]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_
TX2
GND
TX2_0+ TX2_0–
T
U
P[10]
P[11]
P[12]
P[13]
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DVDD
GND
GND
R_TX2
GND
TX2_C+ TX2_C–
U
V
P[6]
P[7]
P[8]
P[9]
GND
PVDD6
HEAC_ HEAC_
2+
2–
V
W
P[2]
P[3]
P[4]
P[5]
TEST3
PVDD6 AVDD4 AVDD4
W
Y
P[0]
P[1]
DDR_
DQS[2]
GND
DDR_
DQ[6]
AA
DDR_
DQ[18]
AB
DDR_
DDR_
DDR_
DQ[21] DQ[19] DQ[17]
AC
GND
GND
DDR_ DVDD_ DDR_
DQ[23] DDR
DQS[3]
2
3
DDR_
CAS
DVDD_
DDR
DDR_
CK
DDR_
A[2]
GND
DDR_
CS
DVDD_
DDR
DDR_
CK
DDR_
A[3]
DDR_
A[0]
DDR_
BA[0]
DDR_
RAS
DDR_
CKE
DDR_
VREF
16
DDR_
A[11]
DVDD_
DDR
DDR_
A[4]
DDR_ DDR_ DVDD_ DDR_
DDR_
DQS[2] DQ[26] DDR DQS[3] A[13]
DDR_
A[8]
DVDD_
DDR
DDR_
A[12]
DDR_
A[6]
DDR_
DM[2]
DDR_
DQ[30]
DDR_
DM[3]
DDR_ DDR_
DQ[31] DQ[29]
DDR_
DDR_ DDR_
DDR_
DDR_ DDR_
DDR_
DDR_
DQ[16] DQ[20] DQ[22] DQ[25] DQ[28] DQ[27] DQ[24] A[9]
1
GND
GND
4
5
6
7
8
DDR_
A[5]
DDR_
A[7]
9
10
DDR_
A[1]
11
DDR_
A[10]
DDR_
BA[1]
DDR_
BA[2]
DDR_
WE
12
13
14
15
GND
DDR_
DQ[9]
GND
DDR_ DVDD_
DQ[11]
DDR
DDR_
DDR_
DQ[12] DQS[1]
DVDD_ DDR_
DQ[14]
DDR
DDR_
DQ[8]
18
PVDD_
DDR
GND
Y
AA
DDR_
DM[1]
DDR_
DM[0]
GND
GND
DDR_
DQ[3]
DDR_
DQ[13]
DDR_
DQ[0]
DDR_
DQ[5]
DDR_
DQS[0]
DDR_
DQ[4]
AB
DDR_
DQ[7]
DDR_
DQ[2]
DDR_
DQS[0]
DDR_
DQ[1]
AC
20
21
22
23
DDR_
DDR_
DDR_
DQ[10] DQS[1] DQ[15]
17
GND
19
Figure 28. ADV8005KBCZ-8A and ADV8005KBCZ-8N Pin Configuration
Table 5. ADV8005KBCZ-8A and ADV8005KBCZ-8N Pin Function Descriptions
Pin No.
A1
Mnemonic
OSD_IN[23]/EXT_DIN[7]
A2
A3
OSD_DE
OSD_CLK/EXT_CLK
Type
OSD video input/
miscellaneous digital
OSD video sync
OSD video sync
A4
A5
A6
A7
A8
A9
A10
A11
AUD_IN[1]
AUD_IN[2]
AUD_IN[5]
ARC2_OUT
MOSI1
SCK2
CS2
RESET
Audio input
Audio input
Audio input
Audio output
Serial port control
Serial port control
Serial port control
Miscellaneous digital
Description
External OSD Video Pixel Input Port 23 (OSD_IN[23]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[7]).
Data Enable for the OSD Input Port.
Pixel Clock for the OSD Input Port (OSD_CLK).
Pixel Clock for External Video Data (EXT_CLK).
I2S0/DSD1 Audio Input.
I2S1/DSD2 Audio Input.
Left/Right Clock/DSD5 Audio Input.
Audio Return Channel for HDMI Tx2.
Master Output Slave Input (Serial Port 1). Serial Port 1 is used for OSD control.
Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Reset Pin.
Rev. 0 | Page 18 of 52
12074-029
1
OSD_
IN[23]/
EXT_
DIN[7]
Data Sheet
ADV8005
Pin No.
A12
Mnemonic
XTALN
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
PVDD2
DNC
DNC
CVDD1
RX_C−
RX_0−
RX_1−
RX_2−
CVDD1
RSET1
Type
Miscellaneous 1.8 V
Analog1
Power
Not applicable
Not applicable
Power
Rx input
Rx input
Rx input
Rx input
Power
Miscellaneous analog1
A23
VREF
Miscellaneous analog1
B1
OSD_IN[21]/EXT_DIN[5]
B2
OSD_IN[22]/EXT_DIN[6]
B3
B4
B5
B6
B7
B8
B9
B10
B11
OSD_VS
AUD_IN[0]
AUD_IN[3]
SFL
ARC1_OUT
MISO1
MOSI2
MISO2
ALSB
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video sync
Audio input
Audio input
SFL
Audio output
Serial port control
Serial port control
Serial port control
I2C control
B12
XTALP
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
PVDD1
DNC
DNC
GND
RX_C+
RX_0+
RX_1+
RX_2+
GND
COMP1
DAC4
OSD_IN[19]/EXT_DIN[3]
C2
OSD_IN[20]/EXT_DIN[4]
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
GND
AUD_IN[4]
DSD_CLK
SCLK
SCL
SCK1
GND
INT0
PDN
GND
GND
Miscellaneous 1.8 V
Analog1
Power
Not applicable
Not applicable
GND
Rx input
Rx input
Rx input
Rx input
GND
Miscellaneous analog1
Analog video output
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
GND
Audio input
Audio input
Audio input
I2C control
Serial port control
GND
Miscellaneous digital
Miscellaneous digital
GND
GND
Description
Crystal Output Pin. Leave this pin floating if a clock oscillator is used.
PLL Digital Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Comparator Supply Voltage (1.8 V).
Rx Clock Complement Input.
Rx Channel 0 Complement Input.
Rx Channel 1 Complement Input.
Rx Channel 2 Complement Input.
Comparator Supply Voltage (1.8 V).
Resistor Current Setting for DAC1, DAC2, and DAC3. Place the RSET1 resistor as close
as possible to the ADV8005.
Optional External Voltage Reference Input for DACx or Voltage Reference Output. Place
VREF voltage components as close as possible to the ADV8005.
External OSD Video Pixel Input Port 21 (OSD_IN[21]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[5]).
External OSD Video Pixel Input Port 22 (OSD_IN[22]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[6]).
Vertical Sync for the OSD Input Port.
S/PDIF/DSD0 Audio Input.
I2S2/DSD3 Audio Input.
Subcarrier Frequency Lock Signal.
Audio Return Channel for HDMI Tx1.
Master Input Slave Output (Serial Port 1). Serial Port 1 is used for OSD control.
Master Output Slave Input (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Master Input Slave Output (Serial Port 2). Serial Port 2 is used for the external flash ROM.
This pin sets the LSB of the I2C address. When the ALSB pin is set low, the I2C address is
0x18; when the ALSB pin is set high, the I2C address is 0x1A.
Input Pin for 27 MHz Crystal or an External 1.8 V, 27 MHz Clock Oscillator Source to
Clock the ADV8005.
PLL Analog Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Ground.
Rx Clock True Input.
Rx Channel 0 True Input.
Rx Channel 1 True Input.
Rx Channel 2 True Input.
Ground.
Compensation Pin. Connect a 2.2 nF capacitor from COMP1 to AVDD2.
Encoder DAC4 Output.
External OSD Video Pixel Input Port 19 (OSD_IN[19]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[3]).
External OSD Video Pixel Input Port 20 (OSD_IN[20]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[4]).
Ground.
I2S3/DSD4 Audio Input.
DSD Audio Clock Input.
I2S Bit Clock Input.
I2C Clock Input. SCL is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.
Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.
Ground.
Interrupt Pin 0. When the status bits change, this pin is triggered.
Power-Down. This pin controls the power state of the ADV8005.
Ground.
Ground.
Rev. 0 | Page 19 of 52
ADV8005
Data Sheet
Pin No.
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
D1
Mnemonic
DNC
REF_CLK
RX_HPD
AVDD1
GND
GND
AVDD1
AVDD1
DAC5
DAC6
OSD_IN[16]/EXT_DIN[0]
D2
OSD_IN[17]/EXT_DIN[1]
D3
OSD_IN[18]/EXT_DIN[2]
D4
D5
D6
D7
D8
D9
D10
GND
DVDD_IO
MCLK
SDA
CS1
GND
INT1
Type
Not applicable
Digital input
Rx input
Power
GND
GND
Power
Power
Analog video output
Analog video output
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
GND
Power
Audio input
I2C control
Serial port control
GND
Miscellaneous digital
D11
INT2
Miscellaneous digital
D12
D13
D14
D15
D16
D17
D18
D19
DVDD_IO
TEST1
REF_HS
REF_VS
RX_5V
DNC
DNC
RTERM
Power
Miscellaneous digital
Digital input
Digital input
Rx input
Not applicable
Not applicable
HDMI Rx input
D20
D21
D22
D23
E1
AVDD2
AVDD2
DAC1
DAC2
OSD_IN[13]/VBI_SCK
E2
OSD_IN[14]/VBI_MOSI
E3
OSD_IN[15]/VBI_CS
E4
E20
E21
E22
E23
F1
F2
F3
F4
DVDD_IO
TEST2
GND
COMP2
DAC3
OSD_IN[9]
OSD_IN[10]
OSD_IN[11]
OSD_IN[12]
F20
RSET2
Power
Power
Analog video output
Analog video output
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
Power
Miscellaneous analog
GND
Miscellaneous analog1
Analog video output
OSD video input
OSD video input
OSD video input
OSD video input/
miscellaneous digital
Miscellaneous analog1
F21
PVDD3
Power
Description
Do Not Connect. Do not connect to this pin.
Reference Clock Input for the Master Timing Block.
Hot Plug Assert Signal Output for the Rx Input.
HDMI Rx Inputs Analog Supply (3.3 V).
Ground.
Ground.
HDMI Rx Inputs Analog Supply (3.3 V).
HDMI Rx Inputs Analog Supply (3.3 V).
Encoder DAC5 Output.
Encoder DAC6 Output.
External OSD Video Pixel Input Port 16 (OSD_IN[16]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[0]).
External OSD Video Pixel Input Port 17 (OSD_IN[17]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[1]).
External OSD Video Pixel Input Port 18 (OSD_IN[18]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[2]).
Ground.
Digital Interface Supply (3.3 V).
Master Clock for S/PDIF Input Audio.
I2C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.
Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.
Ground.
Interrupt Pin for HDMI Transmitter Outputs. When the status bits change, an interrupt
is generated on this pin.
Interrupt Pin for HDMI Receiver Inputs. When the status bits change, an interrupt is
generated on this pin.
Digital Interface Supply (3.3 V).
Test Pin. Float this pin.
Reference Horizontal Sync Input for the Master Timing Block.
Reference Vertical Sync Input for the Master Timing Block.
5 V Detect Pin for the Receiver Input.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
This pin sets the internal termination resistance. Use a 500 Ω resistor between this pin
and GND. Place the RTERM resistor as close as possible to the ADV8005.
Analog Power Supply (3.3 V).
Analog Power Supply (3.3 V).
Encoder DAC1 Output.
Encoder DAC2 Output.
External OSD Video Pixel Input Port 13 (OSD_IN[13]).
Serial Clock for Video Blanking Interval (VBI) Data Serial Port 3 (VBI_SCK).
External OSD Video Pixel Input Port 14 (OSD_IN[14]).
Master Output Slave Input for VBI Data Serial Port 3 (VBI_MOSI).
External OSD Video Pixel Input Port 15 (OSD_IN[15]).
Chip Select for VBI Data Serial Port 3(VBI_CS).
Digital Interface Supply (3.3 V).
Test Pin. Float this pin.
Ground.
Compensation Pin. Connect a 2.2 nF capacitor to AVDD2.
Encoder DAC3 Output.
External OSD Video Pixel Input Port 9.
External OSD Video Pixel Input Port 10.
External OSD Video Pixel Input Port 11.
External OSD Video Pixel Input Port 12.
Resistor Current Setting for DAC4, DAC5, and DAC6. Place the RSET2 resistor as close
as possible to the ADV8005.
PLL Supply (1.8 V).
Rev. 0 | Page 20 of 52
Data Sheet
Pin No.
F22
F23
G1
G2
G3
G4
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G20
G21
G22
G23
H1
H2
H3
H4
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H20
H21
H22
H23
J1
J2
J3
J4
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
Mnemonic
GND
DNC
OSD_IN[5]
OSD_IN[6]
OSD_IN[7]
OSD_IN[8]
GND
GND
GND
DVDD
GND
GND
DVDD
GND
GND
GND
GND
ELPF1
ELPF2
GND
AVDD3
OSD_IN[1]
OSD_IN[2]
OSD_IN[3]
OSD_IN[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX1_2+
TX1_2−
DE
HS
OSD_HS
OSD_IN[0]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
ADV8005
Type
GND
Not applicable
OSD video input
OSD video input
OSD video input
OSD video input
GND
GND
GND
Power
GND
GND
Power
GND
GND
GND
GND
Miscellaneous analog1
Miscellaneous analog1
GND
Power
OSD video input
OSD video input
OSD video input
OSD video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
HDMI Tx1
Digital video sync
Digital video sync
Digital video sync
OSD video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Description
Ground.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 5.
External OSD Video Pixel Input Port 6.
External OSD Video Pixel Input Port 7.
External OSD Video Pixel Input Port 8.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
External Loop Filter for PLL 1. Connect to PVDD3.
External Loop Filter for PLL 2. Connect to PVDD3.
Ground.
HDMI Tx1 Analog Power Supply (1.8 V).
External OSD Video Pixel Input Port 1.
External OSD Video Pixel Input Port 2.
External OSD Video Pixel Input Port 3.
External OSD Video Pixel Input Port 4.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDMI1 Channel 2 True Output.
HDMI1 Channel 2 Complement Output.
Data Enable for Digital Input Video.
Horizontal Sync for Digital Input Video.
Horizontal Sync for the OSD Input Port.
External OSD Video Pixel Input Port 0.
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
Rev. 0 | Page 21 of 52
ADV8005
Data Sheet
Pin No.
J20
Mnemonic
DDC1_SDA
Type
HDMI Tx1
J21
J22
J23
K1
K2
K3
K4
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K20
GND
TX1_1+
TX1_1−
VS
PCLK
DVDD_IO
DVDD_IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC1_SCL
GND
HDMI Tx1
HDMI Tx1
Digital video sync
Digital video sync
Power
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
K21
K22
K23
L1
L2
L3
L4
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L20
L21
L22
L23
M1
M2
M3
M4
M7
M8
M9
M10
M11
M12
M13
M14
GND
TX1_0+
TX1_0−
P[32]
P[33]
P[34]
P[35]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_TX1
GND
TX1_C+
TX1_C−
P[28]
P[29]
P[30]
P[31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
GND
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
Description
HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI1 Channel 1 True Output.
HDMI1 Channel 1 Complement Output.
Vertical Sync for Digital Input Video.
Pixel Clock for Digital Input Video.
Digital Interface Supply (3.3 V).
Digital Interface Supply (3.3 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI1 Channel 0 True Output.
HDMI1 Channel 0 Complement Output.
Digital Video Input 32 of Bus (P[35] to P[0]).
Digital Video Input 33 of Bus (P[35] to P[0]).
Digital Video Input 34 of Bus (P[35] to P[0]).
Digital Video Input 35 of Bus (P[35] to P[0]).
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Hot Plug Assert Signal Input for HDMI Tx1.
Ground.
HDMI1 Clock True Output.
HDMI1 Clock Complement Output.
Digital Video Input 28 of Bus (P[35] to P[0]).
Digital Video Input 29 of Bus (P[35] to P[0]).
Digital Video Input 30 of Bus (P[35] to P[0]).
Digital Video Input 31 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. 0 | Page 22 of 52
Data Sheet
ADV8005
Pin No.
M15
M16
M17
M20
Mnemonic
GND
GND
GND
R_TX1
Type
GND
GND
GND
HDMI Tx11
M21
M22
M23
N1
N2
N3
N4
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N20
N21
N22
N23
P1
P2
P3
P4
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P20
PVDD5
HEAC_1+
HEAC_1−
P[24]
P[25]
P[26]
P[27]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
PVDD5
AVDD4
AVDD3
P[20]
P[21]
P[22]
P[23]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC2_SCL
Power1
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Not applicable
Power1
Power
Power
Digital video input
Digital video input
Digital video input
Digital video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
HDMI Tx2
P21
P22
P23
R1
R2
R3
R4
R7
R8
R9
R10
R11
GND
TX2_2+
TX2_2−
P[16]
P[17]
P[18]
P[19]
GND
GND
GND
GND
GND
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
Description
Ground.
Ground.
Ground.
This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance) between
this pin and ground, as close as possible to the ADV8005.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Ethernet and Audio Channel Positive Tx1 from the HDMI Connector.
HDMI Ethernet and Audio Channel Negative Tx1 from the HDMI Connector.
Digital Video Input 24 of Bus (P[35] to P[0]).
Digital Video Input 25 of Bus (P[35] to P[0]).
Digital Video Input 26 of Bus (P[35] to P[0]).
Digital Video Input 27 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Tx2 Analog Power Supply (1.8 V).
HDMI Tx1 Analog Power Supply (1.8 V).
Digital Video Input 20 of Bus (P[35] to P[0]).
Digital Video Input 21 of Bus (P[35] to P[0]).
Digital Video Input 22 of Bus (P[35] to P[0]).
Digital Video Input 23 of Bus (P[35] to P[0]).
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
HDCP Slave Serial Clock for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI2 Channel 2 True Output.
HDMI2 Channel 2 Complement Output.
Digital Video Input 16 of Bus (P[35] to P[0]).
Digital Video Input 17 of Bus (P[35] to P[0]).
Digital Video Input 18 of Bus (P[35] to P[0]).
Digital Video Input 19 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. 0 | Page 23 of 52
ADV8005
Data Sheet
Pin No.
R12
R13
R14
R15
R16
R17
R20
Mnemonic
GND
GND
GND
GND
GND
GND
DDC2_SDA
Type
GND
GND
GND
GND
GND
GND
HDMI Tx2
R21
R22
R23
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T20
T21
T22
T23
U1
U2
U3
U4
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U20
GND
TX2_1+
TX2_1−
P[14]
P[15]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_TX2
GND
TX2_0+
TX2_0−
P[10]
P[11]
P[12]
P[13]
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DVDD
GND
GND
R_TX2
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx2
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
Power
GND
GND
Power
GND
GND
Power
GND
GND
HDMI Tx21
U21
U22
U23
V1
V2
V3
V4
V20
V21
GND
TX2_C+
TX2_C−
P[6]
P[7]
P[8]
P[9]
GND
PVDD6
GND
HDMI Tx21
HDMI Tx21
Digital video input
Digital video input
Digital video input
Digital video input
GND
Power1
Description
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDCP Slave Serial Data for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI2 Channel 1 True Output.
HDMI2 Channel 1 Complement Output.
Digital Video Input 14 of Bus (P[35] to P[0]).
Digital Video Input 15 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Hot Plug Assert Signal Input for HDMI Tx2.
Ground.
HDMI2 Channel 0 True Output.
HDMI2 Channel 0 Complement Output.
Digital Video Input 10 of Bus (P[35] to P[0]).
Digital Video Input 11 of Bus (P[35] to P[0]).
Digital Video Input 12 of Bus (P[35] to P[0]).
Digital Video Input 13 of Bus (P[35] to P[0]).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance)
between this pin and ground, as close as possible to the ADV8005.
Ground.
HDMI2 Clock True Output.
HDMI2 Clock Complement Output.
Digital Video Input 6 of Bus (P[35] to P[0]).
Digital Video Input 7 of Bus (P[35] to P[0]).
Digital Video Input 8 of Bus (P[35] to P[0]).
Digital Video Input 9 of Bus (P[35] to P[0]).
Ground.
HDMI Transmitter PLL Power Supply (1.845 V).
Rev. 0 | Page 24 of 52
Data Sheet
ADV8005
Pin No.
V22
V23
W1
W2
W3
W4
W20
W21
W22
W23
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
Mnemonic
HEAC_2+
HEAC_2−
P[2]
P[3]
P[4]
P[5]
TEST3
PVDD6
AVDD4
AVDD4
P[0]
P[1]
DDR_DQS[2]
GND
DDR_DQ[23]
DVDD_DDR
DDR_DQS[3]
GND
DDR_A[11]
DVDD_DDR
DDR_A[4]
GND
DDR_CAS
DVDD_DDR
DDR_CK
GND
DDR_DQ[9]
DVDD_DDR
DDR_DQ[14]
GND
DDR_DQ[6]
PVDD_DDR
GND
DDR_DQ[18]
GND
GND
DDR_DQS[2]
DDR_DQ[26]
DVDD_DDR
DDR_DQS[3]
DDR_A[13]
Type
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
Digital video input
Digital video input
Miscellaneous digital
Power1
Power
Power
Digital video input
Digital video input
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
GND
DDR interface
GND
GND
DDR interface
DDR interface
Power
DDR interface
DDR interface
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
DDR_A[8]
DVDD_DDR
DDR_A[2]
GND
DDR_CS
DVDD_DDR
DDR_CK
GND
DDR_DQ[11]
DVDD_DDR
DDR_DM[1]
DDR_DM[0]
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
DDR interface
GND
Description
HDMI Ethernet and Audio Channel Positive Tx2 from the HDMI Connector.
HDMI Ethernet and Audio Channel Negative Tx2 from the HDMI Connector.
Digital Video Input 2 of Bus (P[35] to P[0]).
Digital Video Input 3 of Bus (P[35] to P[0]).
Digital Video Input 4 of Bus (P[35] to P[0]).
Digital Video Input 5 of Bus (P[35] to P[0]).
Test Pin. Connect this pin to ground through a 0.1 μF capacitor.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Tx2 Analog Power Supply (1.8 V).
HDMI Tx2 Analog Power Supply (1.8 V).
Digital Video Input 0 of Bus (P[35] to P[0]).
Digital Video Input 1 of Bus (P[35] to P[0]).
Data Strobe for DDR Data Bytes[23:16], True.
Ground.
Data Line 23. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Strobe for DDR Data Bytes[31:24], True.
Ground.
Address Line 11. Interface to external RAM address lines.
DDR Interface Supply (1.8 V).
Address Line 4. Interface to external RAM address lines.
Ground.
Column Address Strobe for DDR Memory.
DDR Interface Supply (1.8 V).
DDR Memory Clock. Interface to external DDR RAM clock lines.
Ground.
Data Line 9. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Line 14. Interface to external RAM data lines.
Ground.
Data Line 6. Interface to external RAM data lines.
DDR Interface PLL Supply (1.8 V).
Ground.
Data Line 18. Interface to external RAM data lines.
Ground.
Ground.
Data Strobe for DDR Data Bytes[23:16], Complement.
Data Line 26. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Strobe for DDR Data Bytes[31:24], Complement.
Address Line 13. Interface to external RAM address lines. For designs that must
maintain consistency with the ADV8002 or the ADV8003, this pin can be grounded or
left unconnected.
Address Line 8. Interface to external RAM address lines.
DDR Interface Supply (1.8 V).
Address Line 2. Interface to external RAM address lines.
Ground.
DDR Chip Select. Interface to external DDR RAM chip selects.
DDR Interface Supply (1.8 V).
DDR Memory Clock. Interface to external DDR RAM clock lines.
Ground.
Data Line 11. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Mask for Data Lines[15:8].
Data Mask for Data Lines[7:0].
Ground.
Rev. 0 | Page 25 of 52
ADV8005
Pin No.
AA22
AA23
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
1
Mnemonic
GND
DDR_DQ[3]
DDR_DQ[21]
DDR_DQ[19]
DDR_DQ[17]
DDR_DM[2]
DDR_DQ[30]
DDR_DM[3]
DDR_DQ[31]
DDR_DQ[29]
DDR_A[12]
DDR_A[6]
DDR_A[3]
DDR_A[0]
DDR_BA[0]
DDR_RAS
DDR_CKE
DDR_DQ[12]
DDR_DQS[1]
DDR_DQ[8]
DDR_DQ[13]
DDR_DQ[0]
DDR_DQ[5]
DDR_DQS[0]
DDR_DQ[4]
DDR_DQ[16]
DDR_DQ[20]
DDR_DQ[22]
DDR_DQ[25]
DDR_DQ[28]
DDR_DQ[27]
DDR_DQ[24]
DDR_A[9]
DDR_A[5]
DDR_A[7]
DDR_A[1]
DDR_A[10]
DDR_BA[1]
DDR_BA[2]
DDR_WE
DDR_VREF
DDR_DQ[10]
DDR_DQS[1]
DDR_DQ[15]
DDR_DQ[7]
DDR_DQ[2]
DDR_DQS[0]
DDR_DQ[1]
Data Sheet
Type
GND
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface1
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
Description
Ground.
Data Line 3. Interface to external RAM data lines.
Data Line 21. Interface to external RAM data lines.
Data Line 19. Interface to external RAM data lines.
Data Line 17. Interface to external RAM data lines.
Data Mask for Data Lines[23:16].
Data Line 30. Interface to external RAM data lines.
Data Mask for Data Lines[31: 24].
Data Line 31. Interface to external RAM data lines.
Data Line 29. Interface to external RAM data lines.
Address Line 12. Interface to external RAM address lines.
Address Line 6. Interface to external RAM address lines.
Address Line 3. Interface to external RAM address lines.
Address Line 0. Interface to external RAM address lines.
Bank Address Line 0. Indicates which data bank to write to/read from.
Row Address Strobe for DDR Memory.
Clock Enable for External DDR Memory.
Data Line 12. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[15:8], True.
Data Line 8. Interface to external RAM data lines.
Data Line 13. Interface to external RAM data lines.
Data Line 0. Interface to external RAM data lines.
Data Line 5. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[7:0], True.
Data Line 4. Interface to external RAM data lines.
Data Line 16. Interface to external RAM data lines.
Data Line 20. Interface to external RAM data lines.
Data Line 22. Interface to external RAM data lines.
Data Line 25. Interface to external RAM data lines.
Data Line 28. Interface to external RAM data lines.
Data Line 27. Interface to external RAM data lines.
Data Line 24. Interface to external RAM data lines.
Address Line 9. Interface to external RAM address lines.
Address Line 5. Interface to external RAM address lines.
Address Line 7. Interface to external RAM address lines.
Address Line 1. Interface to external RAM address lines.
Address Line 10. Interface to external RAM address lines.
Bank Address Line 1. Indicates which data bank to write to/read from.
Bank Address Line 2. Indicates which data bank to write to/read from.
Write Enable Signal for DDR RAM.
Reference Voltage for DDR RAM.
Data Line 10. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[15:8], Complement.
Data Line 15. Interface to external RAM data lines.
Data Line 7. Interface to external RAM data lines.
Data Line 2. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[7:0], Complement.
Data Line 1. Interface to external RAM data lines.
Sensitive node. Careful layout is important. Keep the associated circuitry as close as possible to the ADV8005.
Rev. 0 | Page 26 of 52
ADV8005
1
2
3
4
5
6
7
8
9
10
A
OSD_
IN[23]/
EXT_
DIN[7]
OSD_
DE
OSD_
CLK/
EXT_
CLK
AUD_
IN[1]
AUD_
IN[2]
AUD_
IN[5]
TEST4
MOSI1
SCK2
CS2
B
OSD_
IN[21]/
EXT_
DIN[5]
OSD_
IN[22]/
EXT_
DIN[6]
OSD_
VS
AUD_
IN[0]
AUD_
IN[3]
SFL
C
OSD_
IN[19]/
EXT_
DIN[3]
OSD_
IN[20]/
EXT_
DIN[4]
GND
AUD_
IN[4]
DSD_
CLK
SCLK
SCL
SCK1
GND
INT0
PDN
GND
D
OSD_
IN[16]/
EXT_
DIN[0]
OSD_
IN[17]/
EXT_
DIN[1]
OSD_
IN[18]/
EXT_
DIN[2]
GND
DVDD_
IO
MCLK
SDA
CS1
GND
INT1
INT2
DVDD_
IO
OSD_
IN[15]/
VBI_CS
E
OSD_
OSD_
IN[13]/
IN[14]/
VBI_SCK VBI_MOSI
18
19
20
21
22
23
RX_0–
RX_1–
RX_2–
CVDD1
DNC
DNC
A
RX_2+
GND
DNC
DNC
B
AVDD1 AVDD1
DNC
DNC
C
RTERM AVDD2 AVDD2
DNC
DNC
D
DVDD_
IO
TEST2
GND
DNC
DNC
E
DNC
PVDD3
GND
DNC
F
GND
AVDD3
G
ARC1_
MISO1
OUT
MOSI2 MISO2
11
12
13
RESET XTALN PVDD2
ALSB
14
15
16
17
CVDD1 RX_C–
DNC
DNC
DNC
DNC
GND
RX_C+
RX_0+
RX_1+
GND
DNC
REF_
CLK
RX_
HPD
AVDD1
GND
GND
TEST1
REF_
HS
REF_
VS
RX_5V
DNC
DNC
XTALP PVDD1
F
OSD_
IN[9]
OSD_
IN[10]
OSD_
IN[11]
OSD_
IN[12]
G
OSD_
IN[5]
OSD_
IN[6]
OSD_
IN[7]
OSD_
IN[8]
GND
GND
GND
DVDD
GND
GND
DVDD
GND
GND
GND
GND
ELPF1
ELPF2
H
OSD_
IN[1]
OSD_
IN[2]
OSD_
IN[3]
OSD_
IN[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX1_2+ TX1_2–
H
J
DE
HS
OSD_
HS
OSD_
IN[0]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC1_
SDA
GND
TX1_1+ TX1_1–
J
K
VS
PCLK
DVDD_ DVDD_
IO
IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC1_
SCL
GND
TX1_0+ TX1_0–
K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_
TX1
GND
TX1_C+ TX1_C–
L
PVDD5
HEAC_ HEAC_
1+
1–
M
PVDD5 AVDD4 AVDD3
N
L
P[32]
P[33]
P[34]
P[35]
DVDD
M
P[28]
P[29]
P[30]
P[31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R_TX1
N
P[24]
P[25]
P[26]
P[27]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
P
P[20]
P[21]
P[22]
P[23]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DNC
GND
DNC
DNC
P
R
P[16]
P[17]
P[18]
P[19]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
DNC
DNC
R
T
P[14]
P[15]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
DNC
DNC
T
U
P[10]
P[11]
P[12]
P[13]
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DNC
GND
DNC
DNC
U
V
P[6]
P[7]
P[8]
P[9]
GND
PVDD6
DNC
DNC
V
W
P[2]
P[3]
P[4]
P[5]
TEST3
Y
P[0]
P[1]
DDR_
DQS[2]
GND
AA
DDR_
DQ[18]
GND
GND
AB
DDR_
DDR_
DDR_
DQ[21] DQ[19] DQ[17]
AC
DDR_
DDR_
DDR_
DDR_ DDR_
DDR_
DDR_ DDR_
DQ[16] DQ[20] DQ[22] DQ[25] DQ[28] DQ[27] DQ[24] A[9]
1
2
3
GND
DDR_
A[11]
DVDD_
DDR
DDR_
A[4]
GND
DDR_
CAS
DVDD_
DDR
DDR_
CK
GND
DDR_
DQ[9]
DDR_
A[13]
DDR_
A[8]
DVDD_
DDR
DDR_
A[2]
GND
DDR_
CS
DVDD_
DDR
DDR_
CK
GND
DDR_ DVDD_
DQ[11]
DDR
DDR_ DDR_
DQ[31] DQ[29]
DDR_
A[12]
DDR_
A[6]
DDR_
A[3]
DDR_
A[0]
DDR_
BA[0]
DDR_
RAS
DDR_
CKE
DDR_
A[5]
DDR_
A[7]
DDR_
A[1]
DDR_
A[10]
DDR_
BA[1]
DDR_
BA[2]
DDR_
WE
DDR_
VREF
9
10
12
13
14
15
16
DDR_ DVDD_ DDR_
DQ[23] DDR
DQS[3]
DDR_ DDR_ DVDD_ DDR_
DQS[2] DQ[26] DDR DQS[3]
DDR_
DM[2]
DDR_
DQ[30]
4
5
DDR_
DM[3]
6
7
8
11
DDR_
DQ[6]
PVDD_
DDR
GND
Y
DDR_
DM[1]
DDR_
DM[0]
GND
GND
DDR_
DQ[3]
AA
DDR_
DQ[13]
DDR_
DQ[0]
DDR_
DQ[5]
DDR_
DQS[0]
DDR_
DQ[4]
AB
DDR_
DDR_
DDR_
DQ[10] DQS[1] DQ[15]
DDR_
DQ[7]
DDR_
DQ[2]
DDR_
DQS[0]
DDR_
DQ[1]
AC
20
21
22
23
17
DDR_
DQ[8]
18
19
Figure 29. ADV8005KBCZ-8B Pin Configuration
Table 6. ADV8005KBCZ-8B Pin Function Descriptions
Pin No.
A1
Mnemonic
OSD_IN[23]/EXT_DIN[7]
A2
A3
OSD_DE
OSD_CLK/EXT_CLK
A4
A5
A6
A7
A8
A9
A10
A11
A12
AUD_IN[1]
AUD_IN[2]
AUD_IN[5]
TEST4
MOSI1
SCK2
CS2
RESET
XTALN
A13
PVDD2
Type
OSD video input/
miscellaneous digital
OSD video sync
OSD video sync
Audio input
Audio input
Audio input
Miscellaneous digital
Serial port control
Serial port control
Serial port control
Miscellaneous digital
Miscellaneous 1.8 V
Analog1
Power
Description
External OSD Video Pixel Input Port 23 (OSD_IN[23]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[7]).
Data Enable for the OSD Input Port.
Pixel Clock for the OSD Input Port (OSD_CLK).
Pixel Clock for External Video Data (EXT_CLK).
I2S0/DSD1 Audio Input.
I2S1/DSD2 Audio Input.
Left/Right Clock/DSD5 Audio Input.
Test Pin. Connect this pin to ground through a 4.7 kΩ resistor.
Master Output Slave Input (Serial Port 1). Serial Port 1 is used for OSD control.
Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Reset Pin.
Crystal Output Pin. Leave this pin floating if a clock oscillator is used.
PLL Digital Supply Voltage (1.8 V).
Rev. 0 | Page 27 of 52
W
GND
DDR_
DDR_
DQ[12] DQS[1]
DVDD_ DDR_
DQ[14]
DDR
PVDD6 AVDD4 AVDD4
12074-030
Data Sheet
ADV8005
Data Sheet
Pin No.
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
Mnemonic
DNC
DNC
CVDD1
RX_C−
RX_0−
RX_1−
RX_2−
CVDD1
DNC
DNC
OSD_IN[21]/EXT_DIN[5]
Type
Not applicable
Not applicable
Power
Rx input
Rx input
Rx input
Rx input
Power
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video sync
Audio input
Audio input
SFL
Audio output
Serial port control
Serial port control
Serial port control
I2C control
B2
OSD_IN[22]/EXT_DIN[6]
B3
B4
B5
B6
B7
B8
B9
B10
B11
OSD_VS
AUD_IN[0]
AUD_IN[3]
SFL
ARC1_OUT
MISO1
MOSI2
MISO2
ALSB
B12
XTALP
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
PVDD1
DNC
DNC
GND
RX_C+
RX_0+
RX_1+
RX_2+
GND
DNC
DNC
OSD_IN[19]/EXT_DIN[3]
C2
OSD_IN[20]/EXT_DIN[4]
C3
C4
C5
C6
C7
GND
AUD_IN[4]
DSD_CLK
SCLK
SCL
Miscellaneous 1.8 V
Analog1
Power
Not applicable
Not applicable
GND
Rx input
Rx input
Rx input
Rx input
GND
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
GND
Audio input
Audio input
Audio input
I2C control
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
SCK1
GND
INT0
PDN
GND
GND
DNC
REF_CLK
RX_HPD
AVDD1
Serial port control
GND
Miscellaneous digital
Miscellaneous digital
GND
GND
Not applicable
Digital input
Rx input
Power
Description
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Comparator Supply Voltage (1.8 V).
Rx Clock Complement Input.
Rx Channel 0 Complement Input.
Rx Channel 1 Complement Input.
Rx Channel 2 Complement Input.
Comparator Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 21 (OSD_IN[21]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[5]).
External OSD Video Pixel Input Port 22 (OSD_IN[22]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[6]).
Vertical Sync for the OSD Input Port.
S/PDIF/DSD0 Audio Input.
I2S2/DSD3 Audio Input.
Subcarrier Frequency Lock Signal.
Audio Return Channel for HDMI Tx1.
Master Input Slave Output (Serial Port 1). Serial Port 1 is used for OSD control.
Master Output Slave Input (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Master Input Slave Output (Serial Port 2). Serial Port 2 is used for the external flash ROM.
This pin sets the LSB of the I2C address. When the ALSB pin is set low, the I2C address is
0x18; when the ALSB pin is set high, the I2C address is 0x1A.
Input Pin for 27 MHz Crystal or an External 1.8 V, 27 MHz Clock Oscillator Source to
Clock the ADV8005.
PLL Analog Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Ground.
Rx Clock True Input.
Rx Channel 0 True Input.
Rx Channel 1 True Input.
Rx Channel 2 True Input.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 19 (OSD_IN[19]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[3]).
External OSD Video Pixel Input Port 20 (OSD_IN[20]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[4]).
Ground.
I2S3/DSD4 Audio Input.
DSD Audio Clock Input.
I2S Bit Clock Input.
I2C Clock Input. This pin is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V
supply.
Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.
Ground.
Interrupt Pin 0. When status bits change, this pin is triggered.
Power-Down. This pin controls the power state of the ADV8005.
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
Reference Clock Input for the Master Timing Block.
Hot Plug Assert Signal Output for the Rx Input.
HDMI Rx Inputs Analog Supply (3.3 V).
Rev. 0 | Page 28 of 52
Data Sheet
Pin No.
C18
C19
C20
C21
C22
C23
D1
Mnemonic
GND
GND
AVDD1
AVDD1
DNC
DNC
OSD_IN[16]/EXT_DIN[0]
D2
OSD_IN[17]/EXT_DIN[1]
D3
OSD_IN[18]/EXT_DIN[2]
D4
D5
D6
D7
D8
D9
D10
GND
DVDD_IO
MCLK
SDA
CS1
GND
INT1
D11
INT2
D12
D13
DVDD_IO
TEST1
D14
D15
D16
D17
D18
D19
REF_HS
REF_VS
RX_5V
DNC
DNC
RTERM
D20
D21
D22
D23
E1
AVDD2
AVDD2
DNC
DNC
OSD_IN[13]/VBI_SCK
E2
OSD_IN[14]/VBI_MOSI
E3
OSD_IN[15]/VBI_CS
E4
E20
E21
E22
E23
F1
F2
F3
F4
DVDD_IO
TEST2
GND
DNC
DNC
OSD_IN[9]
OSD_IN[10]
OSD_IN[11]
OSD_IN[12]
F20
F21
F22
F23
G1
G2
DNC
PVDD3
GND
DNC
OSD_IN[5]
OSD_IN[6]
ADV8005
Type
GND
GND
Power
Power
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
GND
Power
Audio input
I2C control
Serial port control
GND
Miscellaneous
digital
Miscellaneous
digital
Power
Miscellaneous
digital
Digital input
Digital input
Rx input
Not applicable
Not applicable
HDMI Rx input
Power
Power
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
Power
Miscellaneous analog
GND
Not applicable
Not applicable
OSD video input
OSD video input
OSD video input
OSD video input/
miscellaneous digital
Not applicable
Power
GND
Not applicable
OSD video input
OSD video input
Description
Ground.
Ground.
HDMI Rx Inputs, Analog Supply (3.3 V).
HDMI Rx Inputs, Analog Supply (3.3 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 16 (OSD_IN[16]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[0]).
External OSD Video Pixel Input Port 17 (OSD_IN[17]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[1]).
External OSD Video Pixel Input Port 18 (OSD_IN[18]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[2]).
Ground.
Digital Interface Supply (3.3 V).
MCLK for S/PDIF Input Audio.
I2C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.
Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.
Ground.
Interrupt Pin for HDMI Transmitter Outputs. When the status bits change, an interrupt
is generated on this pin.
Interrupt Pin for HDMI Receiver Inputs. When the status bits change, an interrupt is
generated on this pin.
Digital Interface Supply (3.3 V).
Test Pin. Float this pin.
Reference Horizontal Sync Input for the Master Timing Block.
Reference Vertical Sync Input for the Master Timing Block.
5 V Detect Pin for the Rx Input.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
This pin sets the internal termination resistance. Use a 500 Ω resistor between this pin
and GND. Place the RTERM resistor as close as possible to the ADV8005.
Analog Power Supply (3.3 V).
Analog Power Supply (3.3 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 13 (OSD_IN[13]).
Serial Clock for Video Blanking Interval (VBI) Data Serial Port 3 (VBI_SCK).
External OSD Video Pixel Input Port 14 (OSD_IN[14]).
Master Output Slave Input for VBI Data Serial Port 3 (VBI_MOSI).
External OSD Video Pixel Input Port 15 (OSD_IN[15]).
Chip Select for VBI Data Serial Port 3 (VBI_CS).
Digital Interface Supply (3.3 V).
Test Pin. Float this pin.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 9.
External OSD Video Pixel Input Port 10.
External OSD Video Pixel Input Port 11.
External OSD Video Pixel Input Port 12.
Do Not Connect. Do not connect to this pin.
PLL Supply (1.8 V).
Ground.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 5.
External OSD Video Pixel Input Port 6.
Rev. 0 | Page 29 of 52
ADV8005
Data Sheet
Pin No.
G3
G4
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G20
Mnemonic
OSD_IN[7]
OSD_IN[8]
GND
GND
GND
DVDD
GND
GND
DVDD
GND
GND
GND
GND
ELPF1
G21
ELPF2
G22
G23
H1
H2
H3
H4
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H20
H21
H22
H23
J1
J2
J3
J4
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J20
GND
AVDD3
OSD_IN[1]
OSD_IN[2]
OSD_IN[3]
OSD_IN[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX1_2+
TX1_2−
DE
HS
OSD_HS
OSD_IN[0]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC1_SDA
Type
OSD video input
OSD video input
GND
GND
GND
Power
GND
GND
Power
GND
GND
GND
GND
Miscellaneous
analog1
Miscellaneous
analog1
GND
Power
OSD video input
OSD video input
OSD video input
OSD video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
HDMI Tx1
Digital video sync
Digital video sync
Digital video sync
OSD video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
HDMI Tx1
J21
GND
GND
Description
External OSD Video Pixel Input Port 7.
External OSD Video Pixel Input Port 8.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
External Loop Filter for PLL 1. Connect to PVDD3.
External Loop Filter for PLL 2. Connect to PVDD3.
Ground.
HDMI Tx1 Analog Power Supply (1.8 V).
External OSD Video Pixel Input Port 1.
External OSD Video Pixel Input Port 2.
External OSD Video Pixel Input Port 3.
External OSD Video Pixel Input Port 4.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDMI1 Channel 2 True Output.
HDMI1 Channel 2 Complement Output.
Data Enable for Digital Input Video.
Horizontal Sync for Digital Input Video.
Horizontal Sync for the OSD Input Port.
External OSD Video Pixel Input Port 0.
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
Rev. 0 | Page 30 of 52
Data Sheet
ADV8005
Pin No.
J22
J23
K1
K2
K3
K4
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K20
Mnemonic
TX1_1+
TX1_1−
VS
PCLK
DVDD_IO
DVDD_IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC1_SCL
Type
HDMI Tx1
HDMI Tx1
Digital video sync
Digital video sync
Power
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
K21
K22
K23
L1
L2
L3
L4
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L20
L21
L22
L23
M1
M2
M3
M4
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
GND
TX1_0+
TX1_0−
P[32]
P[33]
P[34]
P[35]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_TX1
GND
TX1_C+
TX1_C−
P[28]
P[29]
P[30]
P[31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
GND
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Description
HDMI1 Channel 1 True Output.
HDMI1 Channel 1 Complement Output.
Vertical Sync for Digital Input Video.
Pixel Clock for Digital Input Video.
Digital Interface Supply (3.3 V).
Digital Interface Supply (3.3 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI1 Channel 0 True Output.
HDMI1 Channel 0 Complement Output.
Digital Video Input 32 of Bus (P[35] to P[0]).
Digital Video Input 33 of Bus (P[35] to P[0]).
Digital Video Input 34 of Bus (P[35] to P[0]).
Digital Video Input 35 of Bus (P[35] to P[0]).
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Hot Plug Assert Signal Input for HDMI Tx1.
Ground.
HDMI1 Clock True Output.
HDMI1 Clock Complement Output.
Digital Video Input 28 of Bus (P[35] to P[0]).
Digital Video Input 29 of Bus (P[35] to P[0]).
Digital Video Input 30 of Bus (P[35] to P[0]).
Digital Video Input 31 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. 0 | Page 31 of 52
ADV8005
Data Sheet
Pin No.
M20
Mnemonic
R_TX1
Type
HDMI Tx11
M21
M22
M23
N1
N2
N3
N4
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N20
N21
N22
N23
P1
P2
P3
P4
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
R1
R2
R3
R4
R7
R8
R9
R10
R11
R12
R13
R14
R15
PVDD5
HEAC_1+
HEAC_1−
P[24]
P[25]
P[26]
P[27]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
PVDD5
AVDD4
AVDD3
P[20]
P[21]
P[22]
P[23]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DNC
GND
DNC
DNC
P[16]
P[17]
P[18]
P[19]
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power1
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Not applicable
Power1
Power
Power
Digital video input
Digital video input
Digital video input
Digital video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
Not applicable
GND
Not applicable
Not applicable
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
Description
This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance) between
this pin and ground, as close as possible to the ADV8005.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Ethernet and Audio Channel Positive Tx1 from the HDMI Connector.
HDMI Ethernet and Audio Channel Negative Tx1 from the HDMI Connector.
Digital Video Input 24 of Bus (P[35] to P[0]).
Digital Video Input 25 of Bus (P[35] to P[0]).
Digital Video Input 26 of Bus (P[35] to P[0]).
Digital Video Input 27 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Tx2 Analog Power Supply (1.8 V).
HDMI Tx1 Analog Power Supply (1.8 V).
Digital Video Input 20 of Bus (P[35] to P[0]).
Digital Video Input 21 of Bus (P[35] to P[0]).
Digital Video Input 22 of Bus (P[35] to P[0]).
Digital Video Input 23 of Bus (P[35] to P[0]).
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
Do Not Connect. Do not connect to this pin.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital Video Input 16 of Bus (P[35] to P[0]).
Digital Video Input 17 of Bus (P[35] to P[0]).
Digital Video Input 18 of Bus (P[35] to P[0]).
Digital Video Input 19 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. 0 | Page 32 of 52
Data Sheet
Pin No.
R16
R17
R20
R21
R22
R23
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T20
T21
T22
T23
U1
U2
U3
U4
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U20
U21
U22
U23
V1
V2
V3
V4
V20
V21
V22
V23
W1
W2
W3
W4
Mnemonic
GND
GND
DNC
GND
DNC
DNC
P[14]
P[15]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
DNC
DNC
P[10]
P[11]
P[12]
P[13]
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DNC
GND
DNC
DNC
P[6]
P[7]
P[8]
P[9]
GND
PVDD6
DNC
DNC
P[2]
P[3]
P[4]
P[5]
ADV8005
Type
GND
GND
Not applicable
GND
Not applicable
Not applicable
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Not applicable
GND
Not applicable
Not applicable
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
Power
GND
GND
Power
GND
GND
Power
GND
GND
Not applicable
GND
Not applicable
Not applicable
Digital video input
Digital video input
Digital video input
Digital video input
GND
Power1
Not applicable
Not applicable
Digital video input
Digital video input
Digital video input
Digital video input
Description
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital Video Input 14 of Bus (P[35] to P[0]).
Digital Video Input 15 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital Video Input 10 of Bus (P[35] to P[0]).
Digital Video Input 11 of Bus (P[35] to P[0]).
Digital Video Input 12 of Bus (P[35] to P[0]).
Digital Video Input 13 of Bus (P[35] to P[0]).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital Video Input 6 of Bus (P[35] to P[0]).
Digital Video Input 7 of Bus (P[35] to P[0]).
Digital Video Input 8 of Bus (P[35] to P[0]).
Digital Video Input 9 of Bus (P[35] to P[0]).
Ground.
HDMI Transmitter PLL Power Supply (1.845 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Digital Video Input 2 of Bus (P[35] to P[0]).
Digital Video Input 3 of Bus (P[35] to P[0]).
Digital Video Input 4 of Bus (P[35] to P[0]).
Digital Video Input 5 of Bus (P[35] to P[0]).
Rev. 0 | Page 33 of 52
ADV8005
Data Sheet
Pin No.
W20
W21
W22
W23
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
Mnemonic
TEST3
PVDD6
AVDD4
AVDD4
P[0]
P[1]
DDR_DQS[2]
GND
DDR_DQ[23]
DVDD_DDR
DDR_DQS[3]
GND
DDR_A[11]
DVDD_DDR
DDR_A[4]
GND
DDR_CAS
DVDD_DDR
DDR_CK
GND
DDR_DQ[9]
DVDD_DDR
DDR_DQ[14]
GND
DDR_DQ[6]
PVDD_DDR
GND
DDR_DQ[18]
GND
GND
DDR_DQS[2]
DDR_DQ[26]
DVDD_DDR
DDR_DQS[3]
DDR_A[13]
Type
Miscellaneous digital
Power1
Power
Power
Digital video input
Digital video input
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
GND
DDR interface
GND
GND
DDR interface
DDR interface
Power
DDR interface
DDR interface
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
AB2
AB3
AB4
DDR_A[8]
DVDD_DDR
DDR_A[2]
GND
DDR_CS
DVDD_DDR
DDR_CK
GND
DDR_DQ[11]
DVDD_DDR
DDR_DM[1]
DDR_DM[0]
GND
GND
DDR_DQ[3]
DDR_DQ[21]
DDR_DQ[19]
DDR_DQ[17]
DDR_DM[2]
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
DDR interface
GND
GND
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
Description
Test Pin. Connect this pin to ground through a 0.1 μF capacitor.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Tx2 Analog Power Supply (1.8 V).
HDMI Tx2 Analog Power Supply (1.8 V).
Digital Video Input 0 of Bus (P[35] to P[0]).
Digital Video Input 1 of Bus (P[35] to P[0]).
Data Strobe for DDR Data Bytes[23:16], True.
Ground.
Data Line 23. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Strobe for DDR Data Bytes[31:24], True.
Ground.
Address Line 11. Interface to external RAM address lines.
DDR Interface Supply (1.8 V).
Address Line 4. Interface to external RAM address lines.
Ground.
Column Address Strobe for DDR Memory.
DDR Interface Supply (1.8 V).
DDR Memory Clock. Interface to external DDR RAM clock lines.
Ground.
Data Line 9. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Line 14. Interface to external RAM data lines.
Ground.
Data Line 6. Interface to external RAM data lines.
DDR Interface PLL Supply (1.8 V).
Ground.
Data Line 18. Interface to external RAM data lines.
Ground.
Ground.
Data Strobe for DDR Data Bytes[23:16], Complement.
Data Line 26. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Strobe for DDR Data Bytes[31:24], Complement.
Address Line 13. Interface to external RAM address lines. For designs that must
maintain consistency with the ADV8002 or the ADV8003, this pin can be grounded or
left unconnected.
Address Line 8. Interface to external RAM address lines.
DDR Interface Supply (1.8 V).
Address Line 2. Interface to external RAM address lines.
Ground.
DDR Chip Select. Interface to external DDR RAM chip selects.
DDR Interface Supply (1.8 V).
DDR Memory Clock. Interface to external DDR RAM clock lines.
Ground.
Data Line 11. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Mask for Data Lines[15:8].
Data Mask for Data Lines[7:0].
Ground.
Ground.
Data Line 3. Interface to external RAM data lines.
Data Line 21. Interface to external RAM data lines.
Data Line 19. Interface to external RAM data lines.
Data Line 17. Interface to external RAM data lines.
Data Mask for Data Lines[23:16].
Rev. 0 | Page 34 of 52
Data Sheet
Pin No.
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
1
Mnemonic
DDR_DQ[30]
DDR_DM[3]
DDR_DQ[31]
DDR_DQ[29]
DDR_A[12]
DDR_A[6]
DDR_A[3]
DDR_A[0]
DDR_BA[0]
DDR_RAS
DDR_CKE
DDR_DQ[12]
DDR_DQS[1]
DDR_DQ[8]
DDR_DQ[13]
DDR_DQ[0]
DDR_DQ[5]
DDR_DQS[0]
DDR_DQ[4]
DDR_DQ[16]
DDR_DQ[20]
DDR_DQ[22]
DDR_DQ[25]
DDR_DQ[28]
DDR_DQ[27]
DDR_DQ[24]
DDR_A[9]
DDR_A[5]
DDR_A[7]
DDR_A[1]
DDR_A[10]
DDR_BA[1]
DDR_BA[2]
DDR_WE
DDR_VREF
DDR_DQ[10]
DDR_DQS[1]
DDR_DQ[15]
DDR_DQ[7]
DDR_DQ[2]
DDR_DQS[0]
DDR_DQ[1]
ADV8005
Type
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface1
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
Description
Data Line 30. Interface to external RAM data lines.
Data Mask for Data Lines[31: 24].
Data Line 31. Interface to external RAM data lines.
Data Line 29. Interface to external RAM data lines.
Address Line 12. Interface to external RAM address lines.
Address Line 6. Interface to external RAM address lines.
Address Line 3. Interface to external RAM address lines.
Address Line 0. Interface to external RAM address lines.
Bank Address Line 0. Indicates which data bank to write to/read from.
Row Address Strobe for DDR Memory.
Clock Enable for External DDR Memory.
Data Line 12. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[15:8], True.
Data Line 8. Interface to external RAM data lines.
Data Line 13. Interface to external RAM data lines.
Data Line 0. Interface to external RAM data lines.
Data Line 5. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[7:0], True.
Data Line 4. Interface to external RAM data lines.
Data Line 16. Interface to external RAM data lines.
Data Line 20. Interface to external RAM data lines.
Data Line 22. Interface to external RAM data lines.
Data Line 25. Interface to external RAM data lines.
Data Line 28. Interface to external RAM data lines.
Data Line 27. Interface to external RAM data lines.
Data Line 24. Interface to external RAM data lines.
Address Line 9. Interface to external RAM address lines.
Address Line 5. Interface to external RAM address lines.
Address Line 7. Interface to external RAM address lines.
Address Line 1. Interface to external RAM address lines.
Address Line 10. Interface to external RAM address lines.
Bank Address Line 1. Indicates which data bank to write to/read from.
Bank Address Line 2. Indicates which data bank to write to/read from.
Write Enable Signal for DDR RAM.
Reference Voltage for DDR RAM.
Data Line 10. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[15:8], Complement.
Data Line 15. Interface to external RAM data lines.
Data Line 7. Interface to external RAM data lines.
Data Line 2. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[7:0], Complement.
Data Line 1. Interface to external RAM data lines.
Sensitive node. Careful layout is important. Keep the associated circuitry as close as possible to the ADV8005.
Rev. 0 | Page 35 of 52
Data Sheet
1
2
3
4
5
6
9
10
A
OSD_
IN[23]/
EXT_
DIN[7]
OSD_
DE
OSD_
CLK/
EXT_
CLK
AUD_
IN[1]
AUD_
IN[2]
AUD_
IN[5]
ARC2_
OUT MOSI1
SCK2
CS2
B
OSD_
IN[21]/
EXT_
DIN[5]
OSD_
IN[22]/
EXT_
DIN[6]
OSD_
VS
AUD_
IN[0]
AUD_
IN[3]
SFL
ARC1_
MISO1
OUT
MOSI2 MISO2
C
OSD_
IN[19]/
EXT_
DIN[3]
OSD_
IN[20]/
EXT_
DIN[4]
GND
AUD_
IN[4]
DSD_
CLK
SCLK
SCL
SCK1
GND
D
OSD_
IN[16]/
EXT_
DIN[0]
OSD_
IN[17]/
EXT_
DIN[1]
OSD_
IN[18]/
EXT_
DIN[2]
GND
DVDD_
IO
MCLK
SDA
CS1
GND
OSD_
IN[15]/
VBI_CS
E
OSD_
OSD_
IN[13]/
IN[14]/
VBI_SCK VBI_MOSI
7
8
11
12
13
18
19
20
21
22
23
RX_0–
RX_1–
RX_2–
CVDD1
DNC
DNC
A
RX_2+
GND
DNC
DNC
B
AVDD1 AVDD1
DNC
DNC
C
RTERM AVDD2 AVDD2
DNC
DNC
D
DVDD_
IO
TEST2
GND
DNC
DNC
E
DNC
PVDD3
GND
DNC
F
GND
AVDD3
G
RESET XTALN PVDD2
14
15
DNC
DNC
16
17
CVDD1 RX_C–
ALSB
XTALP
PVDD1
DNC
DNC
GND
RX_C+
RX_0+
RX_1+
INT0
PDN
GND
GND
DNC
REF_
CLK
RX_
HPD
AVDD1
GND
GND
INT1
INT2
DVDD_
IO
TEST1
REF_
HS
REF_
VS
RX_5V
DNC
DNC
F
OSD_
IN[9]
OSD_
IN[10]
OSD_
IN[11]
OSD_
IN[12]
G
OSD_
IN[5]
OSD_
IN[6]
OSD_
IN[7]
OSD_
IN[8]
GND
GND
GND
DVDD
GND
GND
DVDD
GND
GND
GND
GND
ELPF1
ELPF2
H
OSD_
IN[1]
OSD_
IN[2]
OSD_
IN[3]
OSD_
IN[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX1_2+ TX1_2–
H
J
DE
HS
OSD_
HS
OSD_
IN[0]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC1_
SDA
GND
TX1_1+ TX1_1–
J
K
VS
PCLK
DVDD_ DVDD_
IO
IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC1_
SCL
GND
TX1_0+ TX1_0–
K
L
P[32]
P[33]
P[34]
P[35]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_
TX1
GND
TX1_C+ TX1_C–
L
M
P[28]
P[29]
P[30]
P[31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R_TX1
PVDD5
HEAC_ HEAC_
1+
1–
M
N
P[24]
P[25]
P[26]
P[27]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
AVDD AVDD3
PVDD5 AVDD4
N
DVDD
DDC2_
SCL
GND
TX2_2+ TX2_2–
P
GND
TX2_1+ TX2_1–
R
P
P[20]
P[21]
P[22]
DVDD
P[23]
GND
GND
GND
GND
GND
GND
GND
GND
GND
R
P[16]
P[17]
P[18]
P[19]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC2_
SDA
T
P[14]
P[15]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_
TX2
GND
TX2_0+ TX2_0–
T
U
P[10]
P[11]
P[12]
P[13]
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DVDD
GND
GND
R_TX2
GND
TX2_C+ TX2_C–
U
HEAC_ HEAC_
PVDD6
2+
2–
V
TEST3 PVDD6 AVDD4 AVDD4
W
V
P[6]
P[7]
W
P[2]
P[8]
P[9]
P[3]
P[4]
P[5]
Y
P[0]
P[1]
DDR_
DQS[2]
AA
DDR_
DQ[18]
GND
GND
GND
GND
DDR_ DVDD_ DDR_
DQ[23] DDR
DQS[3]
DDR_ DDR_ DVDD_ DDR_
DQS[2] DQ[26] DDR DQS[3]
AC
DDR_
DDR_
DDR_
DDR_ DDR_
DDR_
DDR_ DDR_
DQ[16] DQ[20] DQ[22] DQ[25] DQ[28] DQ[27] DQ[24] A[9]
3
4
5
DDR_
DM[3]
DDR_
A[8]
DDR_
DDR_
DDR_
DQ[21] DQ[19] DQ[17]
2
DDR_
DQ[30]
DDR_
A[13]
AB
1
DDR_
DM[2]
GND
DDR_
A[11]
6
DDR_ DDR_
DQ[31] DQ[29]
7
8
DVDD_
DDR
DDR_
A[4]
DVDD_
DDR
DDR_
A[2]
GND
DDR_
CAS
DVDD_
DDR
DDR_
CK
GND
DDR_
DQ[9]
GND
DDR_
CS
DVDD_
DDR
DDR_
CK
GND
DDR_ DVDD_
DQ[11]
DDR
DDR_
CKE
DDR_
DDR_
DQ[12] DQS[1]
DDR_
A[12]
DDR_
A[6]
DDR_
A[3]
DDR_
A[0]
DDR_
BA[0]
DDR_
RAS
DDR_
A[5]
DDR_
A[7]
DDR_
A[1]
DDR_
A[10]
DDR_
BA[1]
DDR_
BA[2]
DDR_
WE
DDR_
VREF
9
10
12
13
14
15
16
11
GND
DDR_
DQ[6]
PVDD_
DDR
GND
Y
DDR_
DM[1]
DDR_
DM[0]
GND
GND
DDR_
DQ[3]
AA
DDR_
DQ[13]
DDR_
DQ[0]
DDR_
DQ[5]
DDR_
DQS[0]
DDR_
DQ[4]
AB
DDR_
DDR_
DDR_
DQ[10] DQS[1] DQ[15]
DDR_
DQ[7]
DDR_
DQ[2]
DDR_
DQS[0]
DDR_
DQ[1]
AC
20
21
22
23
17
DVDD_ DDR_
DQ[14]
DDR
DDR_
DQ[8]
18
19
Figure 30. ADV8005KBCZ-8C Pin Configuration
Table 7. ADV8005KBCZ-8C Pin Function Descriptions
Pin No.
A1
Mnemonic
OSD_IN[23]/EXT_DIN[7]
A2
A3
OSD_DE
OSD_CLK/EXT_CLK
Type
OSD video input/
miscellaneous digital
OSD video sync
OSD video sync
A4
A5
A6
A7
A8
A9
A10
A11
AUD_IN[1]
AUD_IN[2]
AUD_IN[5]
ARC2_OUT
MOSI1
SCK2
CS2
RESET
Audio input
Audio input
Audio input
Audio output
Serial port control
Serial port control
Serial port control
Miscellaneous digital
Description
External OSD Video Pixel Input Port 23 (OSD_IN[23]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[7]).
Data Enable for the OSD Input Port.
Pixel Clock for the OSD Input Port (OSD_CLK).
Pixel Clock for External Video Data (EXT_CLK).
I2S0/DSD1 Audio Input.
I2S1/DSD2 Audio Input.
Left/Right Clock/DSD5 Audio Input.
Audio Return Channel for HDMI Tx2.
Master Output Slave Input (Serial Port 1). Serial Port 1 is used for OSD control.
Serial Clock (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Chip Select (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Reset Pin.
Rev. 0 | Page 36 of 52
12074-031
ADV8005
Data Sheet
Pin No.
A12
Mnemonic
XTALN
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
B1
PVDD2
DNC
DNC
CVDD1
RX_C−
RX_0−
RX_1−
RX_2−
CVDD1
DNC
DNC
OSD_IN[21]/EXT_DIN[5]
B2
OSD_IN[22]/EXT_DIN[6]
B3
B4
B5
B6
B7
B8
B9
B10
B11
OSD_VS
AUD_IN[0]
AUD_IN[3]
SFL
ARC1_OUT
MISO1
MOSI2
MISO2
ALSB
B12
XTALP
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
C1
PVDD1
DNC
DNC
GND
RX_C+
RX_0+
RX_1+
RX_2+
GND
DNC
DNC
OSD_IN[19]/EXT_DIN[3]
C2
OSD_IN[20]/EXT_DIN[4]
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
GND
AUD_IN[4]
DSD_CLK
SCLK
SCL
SCK1
GND
INT0
PDN
GND
GND
DNC
REF_CLK
ADV8005
Type
Miscellaneous 1.8 V
Analog1
Power
Not applicable
Not applicable
Power
Rx input
Rx input
Rx input
Rx input
Power
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video sync
Audio input
Audio input
SFL
Audio output
Serial port control
Serial port control
Serial port control
I2C control
Miscellaneous 1.8 V
Analog1
Power
Not applicable
Not applicable
GND
Rx input
Rx input
Rx input
Rx input
GND
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
GND
Audio input
Audio input
Audio input
I2C control
Serial port control
GND
Miscellaneous digital
Miscellaneous digital
GND
GND
Not applicable
Digital input
Description
Crystal Output Pin. Leave this pin floating if a clock oscillator is used.
PLL Digital Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Comparator Supply Voltage (1.8 V).
Rx Clock Complement Input.
Rx Channel 0 Complement Input.
Rx Channel 1 Complement Input.
Rx Channel 2 Complement Input.
Comparator Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 21 (OSD_IN[21]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[5]).
External OSD Video Pixel Input Port 22 (OSD_IN[22]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[6]).
Vertical Sync for the OSD Input Port.
S/PDIF/DSD0 Audio Input.
I2S2/DSD3 Audio Input.
Subcarrier Frequency Lock Signal.
Audio Return Channel for HDMI Tx1.
Master Input Slave Output (Serial Port 1). Serial Port 1 is used for OSD control.
Master Output Slave Input (Serial Port 2). Serial Port 2 is used for the external flash ROM.
Master Input Slave Output (Serial Port 2). Serial Port 2 is used for the external flash ROM.
This pin sets the LSB of the I2C address. When the ALSB pin is set low, the I2C address
is 0x18; when the ALSB pin is set high, the I2C address is 0x1A.
Input Pin for 27 MHz Crystal or an External 1.8 V, 27 MHz Clock Oscillator Source to
Clock the ADV8005.
PLL Analog Supply Voltage (1.8 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
Ground.
Rx Clock True Input.
Rx Channel 0 True Input.
Rx Channel 1 True Input.
Rx Channel 2 True Input.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 19 (OSD_IN[19]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[3]).
External OSD Video Pixel Input Port 20 (OSD_IN[20]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[4]).
Ground.
I2S3/DSD4 Audio Input.
DSD Audio Clock Input.
I2S Bit Clock Input.
I2C Clock Input. SCL is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.
Serial Clock (Serial Port 1). Serial Port 1 is used for OSD control.
Ground.
Interrupt Pin 0. When the status bits change, this pin is triggered.
Power-Down. This pin controls the power state of the ADV8005.
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
Reference Clock Input for the Master Timing Block.
Rev. 0 | Page 37 of 52
ADV8005
Data Sheet
Pin No.
C16
C17
C18
C19
C20
C21
C22
C23
D1
Mnemonic
RX_HPD
AVDD1
GND
GND
AVDD1
AVDD1
DNC
DNC
OSD_IN[16]/EXT_DIN[0]
D2
OSD_IN[17]/EXT_DIN[1]
D3
OSD_IN[18]/EXT_DIN[2]
D4
D5
D6
D7
D8
D9
D10
GND
DVDD_IO
MCLK
SDA
CS1
GND
INT1
Type
Rx input
Power
GND
GND
Power
Power
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
GND
Power
Audio input
I2C control
Serial port control
GND
Miscellaneous digital
D11
INT2
Miscellaneous digital
D12
D13
D14
D15
D16
D17
D18
D19
DVDD_IO
TEST1
REF_HS
REF_VS
RX_5V
DNC
DNC
RTERM
Power
Miscellaneous digital
Digital input
Digital input
Rx input
Not applicable
Not applicable
HDMI Rx input
D20
D21
D22
D23
E1
AVDD2
AVDD2
DNC
DNC
OSD_IN[13]/VBI_SCK
E2
OSD_IN[14]/VBI_MOSI
E3
OSD_IN[15]/VBI_CS
E4
E20
E21
E22
E23
F1
F2
F3
F4
DVDD_IO
TEST2
GND
DNC
DNC
OSD_IN[9]
OSD_IN[10]
OSD_IN[11]
OSD_IN[12]
F20
F21
F22
F23
DNC
PVDD3
GND
DNC
Power
Power
Not applicable
Not applicable
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
OSD video input/
miscellaneous digital
Power
Miscellaneous analog
GND
Not applicable
Not applicable
OSD video input
OSD video input
OSD video input
OSD video input/
miscellaneous digital
Not applicable
Power
GND
Not applicable
Description
Hot Plug Assert Signal Output for the Rx Input.
HDMI Rx Inputs Analog Supply (3.3 V).
Ground.
Ground.
HDMI Rx Inputs Analog Supply (3.3 V).
HDMI Rx Inputs Analog Supply (3.3 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 16 (OSD_IN[16]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[0]).
External OSD Video Pixel Input Port 17 (OSD_IN[17]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[1]).
External OSD Video Pixel Input Port 18 (OSD_IN[18]).
Additional TTL Input for External ITU-R BT.656 Video Data (EXT_DIN[2]).
Ground.
Digital Interface Supply (3.3 V).
MCLK for S/PDIF Input Audio.
I2C Data Input. SDA is open drain; use a 4.7 kΩ resistor to connect this pin to a 3.3 V supply.
Chip Select (Serial Port 1). Serial Port 1 is used for OSD control.
Ground.
Interrupt Pin for HDMI Transmitter Outputs. When the status bits change, an
interrupt is generated on this pin.
Interrupt Pin for HDMI Receiver Inputs. When the status bits change, an interrupt is
generated on this pin.
Digital Interface Supply (3.3 V).
Test Pin. Float this pin.
Reference Horizontal Sync Input for the Master Timing Block.
Reference Vertical Sync Input for the Master Timing Block.
5 V Detect Pin for the Rx Input.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
This pin sets the internal termination resistance. Use a 500 Ω resistor between this pin
and GND. Place the RTERM resistor as close as possible to the ADV8005.
Analog Power Supply (3.3 V).
Analog Power Supply (3.3 V).
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 13 (OSD_IN[13]).
Serial Clock for Video Blanking Interval (VBI) Data Serial Port 3 (VBI_SCK).
External OSD Video Pixel Input Port 14 (OSD_IN[14]).
Master Output Slave Input for VBI Data Serial Port 3 (VBI_MOSI).
External OSD Video Pixel Input Port 15 (OSD_IN[15]).
Chip Select for VBI Data Serial Port 3 (VBI_CS).
Digital Interface Supply (3.3 V).
Test Pin. Float this pin.
Ground.
Do Not Connect. Do not connect to this pin.
Do Not Connect. Do not connect to this pin.
External OSD Video Pixel Input Port 9.
External OSD Video Pixel Input Port 10.
External OSD Video Pixel Input Port 11.
External OSD Video Pixel Input Port 12.
Do Not Connect. Do not connect to this pin.
PLL Supply (1.8 V).
Ground.
Do Not Connect. Do not connect to this pin.
Rev. 0 | Page 38 of 52
Data Sheet
ADV8005
Pin No.
G1
G2
G3
G4
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G20
G21
G22
G23
H1
H2
H3
H4
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H20
H21
H22
H23
J1
J2
J3
J4
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J20
Mnemonic
OSD_IN[5]
OSD_IN[6]
OSD_IN[7]
OSD_IN[8]
GND
GND
GND
DVDD
GND
GND
DVDD
GND
GND
GND
GND
ELPF1
ELPF2
GND
AVDD3
OSD_IN[1]
OSD_IN[2]
OSD_IN[3]
OSD_IN[4]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX1_2+
TX1_2−
DE
HS
OSD_HS
OSD_IN[0]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC1_SDA
Type
OSD video input
OSD video input
OSD video input
OSD video input
GND
GND
GND
Power
GND
GND
Power
GND
GND
GND
GND
Miscellaneous analog1
Miscellaneous analog1
GND
Power
OSD video input
OSD video input
OSD video input
OSD video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
HDMI Tx1
Digital video sync
Digital video sync
Digital video sync
OSD video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
HDMI Tx1
J21
GND
GND
Description
External OSD Video Pixel Input Port 5.
External OSD Video Pixel Input Port 6.
External OSD Video Pixel Input Port 7.
External OSD Video Pixel Input Port.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
External Loop Filter for PLL 1. Connect to PVDD3.
External Loop Filter for PLL 2. Connect to PVDD3.
Ground.
HDMI Tx1 Analog Power Supply (1.8 V).
External OSD Video Pixel Input Port 1.
External OSD Video Pixel Input Port 2.
External OSD Video Pixel Input Port 3.
External OSD Video Pixel Input Port 4.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDMI1 Channel 2 True Output.
HDMI1 Channel 2 Complement Output.
Data Enable for Digital Input Video.
Horizontal Sync for Digital Input Video.
Horizontal Sync for the OSD Input Port.
External OSD Video Pixel Input Port.
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
HDCP Slave Serial Data for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
Rev. 0 | Page 39 of 52
ADV8005
Data Sheet
Pin No.
J22
J23
K1
K2
K3
K4
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K20
Mnemonic
TX1_1+
TX1_1−
VS
PCLK
DVDD_IO
DVDD_IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDC1_SCL
Type
HDMI Tx1
HDMI Tx1
Digital video sync
Digital video sync
Power
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
K21
K22
K23
L1
L2
L3
L4
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L20
L21
L22
L23
M1
M2
M3
M4
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
GND
TX1_0+
TX1_0−
P[32]
P[33]
P[34]
P[35]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_TX1
GND
TX1_C+
TX1_C−
P[28]
P[29]
P[30]
P[31]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx1
GND
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Description
HDMI1 Channel 1 True Output.
HDMI1 Channel 1 Complement Output.
Vertical Sync for Digital Input Video.
Pixel Clock for Digital Input Video.
Digital Interface Supply (3.3 V).
Digital Interface Supply (3.3 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
HDCP Slave Serial Clock for HDMI Tx1. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI1 Channel 0 True Output.
HDMI1 Channel 0 Complement Output.
Digital Video Input 32 of Bus (P[35] to P[0]).
Digital Video Input 33 of Bus (P[35] to P[0]).
Digital Video Input 34 of Bus (P[35] to P[0]).
Digital Video Input 35 of Bus (P[35] to P[0]).
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Hot Plug Assert Signal Input for HDMI Tx1.
Ground.
HDMI1 Clock True Output.
HDMI1 Clock Complement Output.
Digital Video Input 28 of Bus (P[35] to P[0]).
Digital Video Input 29 of Bus (P[35] to P[0]).
Digital Video Input 30 of Bus (P[35] to P[0]).
Digital Video Input 31 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. 0 | Page 40 of 52
Data Sheet
ADV8005
Pin No.
M20
Mnemonic
R_TX1
Type
HDMI Tx11
M21
M22
M23
N1
N2
N3
N4
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N20
N21
N22
N23
P1
P2
P3
P4
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P20
PVDD5
HEAC_1+
HEAC_1−
P[24]
P[25]
P[26]
P[27]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
PVDD5
AVDD4
AVDD3
P[20]
P[21]
P[22]
P[23]
DVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
DVDD
DDC2_SCL
Power1
HDMI Tx1
HDMI Tx1
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Not applicable
Power1
Power
Power
Digital video input
Digital video input
Digital video input
Digital video input
Power
GND
GND
GND
GND
GND
GND
GND
GND
GND
Power
HDMI Tx2
P21
P22
P23
R1
R2
R3
R4
R7
R8
R9
R10
R11
R12
R13
R14
GND
TX2_2+
TX2_2−
P[16]
P[17]
P[18]
P[19]
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
Description
This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance) between
this pin and ground, as close as possible to the ADV8005.
HDMI Tx PLL Power Supply (1.845 V).
HDMI Ethernet and Audio Channel Positive Tx1 from the HDMI Connector.
HDMI Ethernet and Audio Channel Negative Tx1 from the HDMI Connector.
Digital Video Input 24 of Bus (P[35] to P[0]).
Digital Video Input 25 of Bus (P[35] to P[0]).
Digital Video Input 26 of Bus (P[35] to P[0]).
Digital Video Input 27 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Do Not Connect. Do not connect to this pin.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Tx2 Analog Power Supply (1.8 V).
HDMI Tx1 Analog Power Supply (1.8 V).
Digital Video Input 20 of Bus (P[35] to P[0]).
Digital Video Input 21 of Bus (P[35] to P[0]).
Digital Video Input 22 of Bus (P[35] to P[0]).
Digital Video Input 23 of Bus (P[35] to P[0]).
Digital Power Supply (1.8 V).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Digital Power Supply (1.8 V).
HDCP Slave Serial Clock for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI2 Channel 2 True Output.
HDMI2 Channel 2 Complement Output.
Digital Video Input 16 of Bus (P[35] to P[0]).
Digital Video Input 17 of Bus (P[35] to P[0]).
Digital Video Input 18 of Bus (P[35] to P[0]).
Digital Video Input 19 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Rev. 0 | Page 41 of 52
ADV8005
Data Sheet
Pin No.
R15
R16
R17
R20
Mnemonic
GND
GND
GND
DDC2_SDA
Type
GND
GND
GND
HDMI Tx2
R21
R22
R23
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T20
T21
T22
T23
U1
U2
U3
U4
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U20
GND
TX2_1+
TX2_1−
P[14]
P[15]
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPD_TX2
GND
TX2_0+
TX2_0−
P[10]
P[11]
P[12]
P[13]
GND
GND
DVDD
GND
GND
DVDD
GND
GND
DVDD
GND
GND
R_TX2
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HDMI Tx2
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
Digital video input
Digital video input
GND
GND
Power
GND
GND
Power
GND
GND
Power
GND
GND
HDMI Tx21
U21
U22
U23
V1
V2
V3
V4
V20
V21
V22
V23
W1
GND
TX2_C+
TX2_C−
P[6]
P[7]
P[8]
P[9]
GND
PVDD6
HEAC_2+
HEAC_2−
P[2]
GND
HDMI Tx2
HDMI Tx2
Digital video input
Digital video input
Digital video input
Digital video input
GND
Power1
HDMI Tx2
HDMI Tx2
Digital video input
Description
Ground.
Ground.
Ground.
HDCP Slave Serial Data for HDMI Tx2. This pin is open drain; use a 2 kΩ resistor to
connect this pin to the HDMI transmitter 5 V supply.
Ground.
HDMI2 Channel 1 True Output.
HDMI2 Channel 1 Complement Output.
Digital Video Input 14 of Bus (P[35] to P[0]).
Digital Video Input 15 of Bus (P[35] to P[0]).
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Ground.
Hot Plug Assert Signal Input for HDMI Tx2.
Ground.
HDMI2 Channel 0 True Output.
HDMI2 Channel 0 Complement Output.
Digital Video Input 10 of Bus (P[35] to P[0]).
Digital Video Input 11 of Bus (P[35] to P[0]).
Digital Video Input 12 of Bus (P[35] to P[0]).
Digital Video Input 13 of Bus (P[35] to P[0]).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
Digital Power Supply (1.8 V).
Ground.
Ground.
This pin sets the internal reference currents. Place a 470 Ω resistor (1% tolerance)
between this pin and ground, as close as possible to the ADV8005.
Ground.
HDMI2 Clock True Output.
HDMI2 Clock Complement Output.
Digital Video Input 6 of Bus (P[35] to P[0]).
Digital Video Input 7 of Bus (P[35] to P[0]).
Digital Video Input 8 of Bus (P[35] to P[0]).
Digital Video Input 9 of Bus (P[35] to P[0]).
Ground.
HDMI Transmitter PLL Power Supply (1.8 V).
HDMI Ethernet and Audio Channel Positive Tx2 from the HDMI Connector.
HDMI Ethernet and Audio Channel Negative Tx2 from the HDMI Connector.
Digital Video Input 2 of Bus (P[35] to P[0]).
Rev. 0 | Page 42 of 52
Data Sheet
ADV8005
Pin No.
W2
W3
W4
W20
W21
W22
W23
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
Mnemonic
P[3]
P[4]
P[5]
TEST3
PVDD6
AVDD4
AVDD4
P[0]
P[1]
DDR_DQS[2]
GND
DDR_DQ[23]
DVDD_DDR
DDR_DQS[3]
GND
DDR_A[11]
DVDD_DDR
DDR_A[4]
GND
DDR_CAS
DVDD_DDR
DDR_CK
GND
DDR_DQ[9]
DVDD_DDR
DDR_DQ[14]
GND
DDR_DQ[6]
PVDD_DDR
GND
DDR_DQ[18]
GND
GND
DDR_DQS[2]
DDR_DQ[26]
DVDD_DDR
DDR_DQS[3]
DDR_A[13]
Type
Digital video input
Digital video input
Digital video input
Miscellaneous digital
Power1
Power
Power
Digital video input
Digital video input
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
GND
DDR interface
GND
GND
DDR interface
DDR interface
Power
DDR interface
DDR interface
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AB1
DDR_A[8]
DVDD_DDR
DDR_A[2]
GND
DDR_CS
DVDD_DDR
DDR_CK
GND
DDR_DQ[11]
DVDD_DDR
DDR_DM[1]
DDR_DM[0]
GND
GND
DDR_DQ[3]
DDR_DQ[21]
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
GND
DDR interface
Power
DDR interface
DDR interface
GND
GND
DDR interface
DDR interface
Description
Digital Video Input 3 of Bus (P[35] to P[0]).
Digital Video Input 4 of Bus (P[35] to P[0]).
Digital Video Input 5 of Bus (P[35] to P[0]).
Test Pin. Connect this pin to ground through a 0.1 μF capacitor.
HDMI Transmitter PLL Power Supply (1.845 V).
HDMI Tx2 Analog Power Supply (1.8 V).
HDMI Tx2 Analog Power Supply (1.8 V).
Digital Video Input 0 of Bus (P[35] to P[0]).
Digital Video Input 1 of Bus (P[35] to P[0]).
Data Strobe for DDR Data Bytes[23:16], True.
Ground.
Data Line 23. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Strobe for DDR Data Bytes[31:24], True.
Ground.
Address Line 11. Interface to external RAM address lines.
DDR Interface Supply (1.8 V).
Address Line 4. Interface to external RAM address lines.
Ground.
Column Address Strobe for DDR Memory.
DDR Interface Supply (1.8 V).
DDR Memory Clock. Interface to external DDR RAM clock lines.
Ground.
Data Line 9. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Line 14. Interface to external RAM data lines.
Ground.
Data Line 6. Interface to external RAM data lines.
DDR Interface PLL Supply (1.8 V).
Ground.
Data Line 18. Interface to external RAM data lines.
Ground.
Ground.
Data Strobe for DDR Data Bytes[23:16], Complement.
Data Line 26. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Strobe for DDR Data Bytes[31:24], Complement.
Address Line 13. Interface to external RAM address lines. For designs that must
maintain consistency with the ADV8002 or the ADV8003, this pin can be grounded or
left unconnected.
Address Line 8. Interface to external RAM address lines.
DDR Interface Supply (1.8 V).
Address Line 2. Interface to external RAM address lines.
Ground.
DDR Chip Select. Interface to external DDR RAM chip selects.
DDR Interface Supply (1.8 V).
DDR Memory Clock. Interface to external DDR RAM clock lines.
Ground.
Data Line 11. Interface to external RAM data lines.
DDR Interface Supply (1.8 V).
Data Mask for Data Lines[15:8].
Data Mask for Data Lines[7:0].
Ground.
Ground.
Data Line 3. Interface to external RAM data lines.
Data Line 21. Interface to external RAM data lines.
Rev. 0 | Page 43 of 52
ADV8005
Pin No.
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
1
Mnemonic
DDR_DQ[19]
DDR_DQ[17]
DDR_DM[2]
DDR_DQ[30]
DDR_DM[3]
DDR_DQ[31]
DDR_DQ[29]
DDR_A[12]
DDR_A[6]
DDR_A[3]
DDR_A[0]
DDR_BA[0]
DDR_RAS
DDR_CKE
DDR_DQ[12]
DDR_DQS[1]
DDR_DQ[8]
DDR_DQ[13]
DDR_DQ[0]
DDR_DQ[5]
DDR_DQS[0]
DDR_DQ[4]
DDR_DQ[16]
DDR_DQ[20]
DDR_DQ[22]
DDR_DQ[25]
DDR_DQ[28]
DDR_DQ[27]
DDR_DQ[24]
DDR_A[9]
DDR_A[5]
DDR_A[7]
DDR_A[1]
DDR_A[10]
DDR_BA[1]
DDR_BA[2]
DDR_WE
DDR_VREF
DDR_DQ[10]
DDR_DQS[1]
DDR_DQ[15]
DDR_DQ[7]
DDR_DQ[2]
DDR_DQS[0]
DDR_DQ[1]
Data Sheet
Type
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface1
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
DDR interface
Description
Data Line 19. Interface to external RAM data lines.
Data Line 17. Interface to external RAM data lines.
Data Mask for Data Lines[23:16].
Data Line 30. Interface to external RAM data lines.
Data Mask for Data Lines[31:24].
Data Line 31. Interface to external RAM data lines.
Data Line 29. Interface to external RAM data lines.
Address Line 12. Interface to external RAM address lines.
Address Line 6. Interface to external RAM address lines.
Address Line 3. Interface to external RAM address lines.
Address Line 0. Interface to external RAM address lines.
Bank Address Line 0. Indicates which data bank to write to/read from.
Row Address Strobe for DDR Memory.
Clock Enable for External DDR Memory.
Data Line 12. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[15:8], True.
Data Line 8. Interface to external RAM data lines.
Data Line 13. Interface to external RAM data lines.
Data Line 0. Interface to external RAM data lines.
Data Line 5. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[7:0], True.
Data Line 4. Interface to external RAM data lines.
Data Line 16. Interface to external RAM data lines.
Data Line 20. Interface to external RAM data lines.
Data Line 22. Interface to external RAM data lines.
Data Line 25. Interface to external RAM data lines.
Data Line 28. Interface to external RAM data lines.
Data Line 27. Interface to external RAM data lines.
Data Line 24. Interface to external RAM data lines.
Address Line 9. Interface to external RAM address lines.
Address Line 5. Interface to external RAM address lines.
Address Line 7. Interface to external RAM address lines.
Address Line 1. Interface to external RAM address lines.
Address Line 10. Interface to external RAM address lines.
Bank Address Line 1. Indicates which data bank to write to/read from.
Bank Address Line 2. Indicates which data bank to write to/read from.
Write Enable Signal for DDR RAM.
Reference Voltage for DDR RAM.
Data Line 10. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[15:8], Complement.
Data Line 15. Interface to external RAM data lines.
Data Line 7. Interface to external RAM data lines.
Data Line 2. Interface to external RAM data lines.
Data Strobe for DDR Data Bytes[7:0], Complement.
Data Line 1. Interface to external RAM data lines.
Sensitive node. Careful layout is important. Keep the associated circuitry as close as possible to the ADV8005.
Rev. 0 | Page 44 of 52
Data Sheet
ADV8005
THEORY OF OPERATION
VIDEO INPUT
PROFESSIONAL CONFIGURATION
To accommodate professional applications where HDMI and
analog video output are not desired, the ADV8005 offers a 30-bit
TTL input, 30-bit TTL output mode. This mode suits applications
where a video signal processor is required between two TTL
interfaces (for example, an HDMI receiver and an FPGA).
4-BIT VBI
12-BIT
VIDEO
24-BIT
VIDEO
CORE
48-BIT
VIDEO
12074-033
SERIAL VIDEO
RECEIVER
EXTERNAL SYNC MODE
Figure 31. Digital Video Interface
The ADV8005 can receive data via the 48-bit input pixel port,
the 24-bit OSD input port, or from the output of an HDMI
transmitter.
The 48-bit input pixel port can receive data from an upstream
analog/HDMI front-end device such as the ADV7619. This bus
can accept multiple input formats in both RGB and YPrPb color
spaces. Single data rate (SDR) and double data rate (DDR) input
formats are supported.
The 24-bit input pixel port can also receive video data from an
upstream analog/HDMI front-end device such as the ADV7844
or OSD data from an external OSD generator. This bus can accept
multiple input formats up to UXGA. SDR and DDR input
formats are supported. The video input on the 24-bit pixel port
can be scaled and overlaid onto the main video path.
The serial video receiver can accept the output of an HDMI
transmitter such as the ADV7850 or ADV7623. Using this
configuration, the front-end device can extract HDMI audio for
processing before reinserting the audio into the ADV8005 via
the audio pins, for output through the HDMI transmitters.
Audio can also be passed through the serial video link from the
HDMI transmitter. This input, however, does not support EDID
or HDCP operations.
To alleviate the challenges involved in synchronizing multiple
video streams, the ADV8005 supports an external sync mode.
In this mode, an external sync (VS and/or HS) is applied to
the ADV8005. The video outputs from the ADV8005 then acts
as a slave to the master sync timing. The ADV8005 can also
synchronize two inputs to externally applied reference sync
signals. An externally applied master sync signal (VS and/or
HS) is. Using this external sync mode, it is possible to
synchronize multiple ADV8005 output video streams to an
external sync input.
FLEXIBLE DIGITAL CORE
The ADV8005 has a flexible digital core that enables many
different configurations of single, dual, and triple video
processing paths. Video processing can be placed first in the
signal chain to ensure that all outputs are processed to the highest
quality. OSD can be placed at numerous locations within the signal
chain to vary the number of outputs on which the OSD is
displayed. PiP can also be supported via the OSD block, using a
pixel port input that is connected to the OSD block. Several
modes of operation are defined to help the user quickly integrate
the ADV8005 into a system.
VIDEO SIGNAL PROCESSOR (VSP)
LOW ANGLE
PROCESSING
CADENCE
DETECTION
MOTION
DETECTION
Picture-in-picture (PiP) support is possible when receiving
video data on more than one of the video inputs, such as the
48-bit pixel port and the serial video receiver.
CUE
CORRECTION


NOISE
REDUCTION
ENHANCE
DUAL SCALER
AND
OSD BLEND
DEINTERLACER
Up to 48-bit pixel input port
Up to 24-bit pixel port for external OSD, if the ADV8005
internal OSD is not used
Up to 36-bit pixel output port
An SPI interface enabling video blanking interval (VBI)
data insertion
FRC
Figure 32. Video Processing
The 60-pin TTL video interface supports the following features:


DETAIL
ENHANCE
12074-034
8-BIT
CCIR 656
The ADV8005 offers video deinterlacing and scaling. The
deinterlacer, located in the primary VSP, is motion adaptive and
offers high performance on low angle edges. It supports input
video resolutions of 480i, 576i, and 1080i.
The dual scalers in the ADV8005 support the Analog Devices
proprietary scaling algorithm, which provides very high quality
video upscaling and downscaling. This scaling algorithm helps
eradicate many of the common problems that are encountered
when scaling video data, such as saw tooth, edge blurring, and
ringing.
The ADV8005 is capable of upscaling and downscaling between
a range of SD, HD, and ultra HD video resolutions (for example,
Rev. 0 | Page 45 of 52
ADV8005
Data Sheet
480p, 576p, 720p, 1080p, and 4k × 2k). The presence of two video
scalers allows the generation of multiple different video resolutions on the ADV8005 outputs. The ADV8005 is also capable of
upscaling and downscaling to and from a wide range of non-CEA
(for example, VESA) formats.
Cadence detection and frame rate conversion are also supported
in the ADV8005, which allows film formats to be displayed
at their native frame rate, as well as being converted to the
native refresh rate of the TV. Additional video processing in
the ADV8005 helps with reduction of common video artifacts
such as mosquito, random, and block noise. The ADV8005 also
includes an aspect ratio converter, as well as a panorama mode
feature.
Video metrics readbacks are provided to enable a system
application to select the correct phase and frequency for VGAtype graphics inputs. These readbacks can be used to assist in
tuning the sampling phase of an ADC front-end device.
system APIs to link the functionality of the OSD with the
functionality of the system.
The OSD design resource is loaded into external DDR2 memories
on power-up by the OSD coprocessor of the ADV8005. This
coprocessor is responsible for handling upper level commands
from the user and translating them into lower level operations
for the OSD and direct memory access (DMA).
OSD features include the following:


Pixel-by-pixel alpha blending and priority levels assigned
to the different OSD components
A high performance OSD scaler allows the rendering
of OSDs at a single resolution, as well as blending at
different resolutions
EXTERNAL DDR2 MEMORY
DDR2 INTERFACE






High performance motion adaptive SD/HD deinterlacer
and scaler
Two scalers, allowing independent scaling on ADV8005
outputs
Frame rate converter, supporting conversion between multiple
frame rates (23.976 Hz, 24 Hz, 25 Hz, 29.97 Hz, 30 Hz, 50 Hz,
59.94 Hz, and 60 Hz)
Noise reduction, which helps with the reduction of random,
block, and mosquito noise
Six manually programmable color space converters that are
distributed between inputs and outputs
Autophase and frequency readbacks
INTERNAL
OSD GENERATOR
FRAME RATE
CONVERSION
BIT MAP OSD
DATA
Figure 34. External DDR2 Memory Interface
External DDR2 memory is required for motion adaptive
deinterlacing, scaling, frame rate conversion, and bit map OSD
overlay. The bandwidth of external memory required is
determined by the input video formats that the ADV8005 must
support, as well as the level of video processing required (scaling,
conversion, and OSD). Depending on the exact application
requirements, the ADV8005 can support various combinations
of memory (single or double memories) and memory sizes (up
to two 2 Gb memories).
OSD BUILD
OSD SCALER
OSD BLEND
The ADV8005 features dual HDMI transmitters. The transmitters
support all HDTV formats up to 4k × 2k, all mandatory, and
many optional, 3D formats. Each HDMI transmitter features an
audio return channel (ARC) receiver and on-chip
microprocessor units with display data channel (DDC) I2C
masters to perform HDCP operations and EDID operations.
HDMI Tx features include the following:
12074-035
DDR2
VIDEO
VIDEO
SCALING
HDMI TRANSMITTERS
ON-SCREEN DISPLAY (OSD)
EXTERNAL OSD
MOTION
ADAPTIVE
DEINTERLACER
12074-036
The following VSP features are included:
Figure 33. Bit Map-Based OSD




Support for all formats up to 4k × 2k
Audio return channel (ARC) support
Mandatory 3D formats and many optional 3D formats
HDMI audio interface with support for multiple audio
formats (S/PDIF, I2S, DSD, HBR); data can be applied
externally or passed through from the serial video receiver
The ADV8005 incorporates a bit map-based OSD block that
allows users to create impressive OSD designs that can include
bit map images, as well as motion and animation. Individual
regions of the OSD can be alpha blended and prioritized over
other regions.
VIDEO ENCODER
An OSD development tool, Blimp, is provided to assist in the
design and development of custom OSDs and to abstract the
OSD hardware from the user. This tool automatically generates
two design elements: a design resource (containing character
sets and images) that must be downloaded to an external SPI
flash on the board, and code that must be integrated with
The ADV8005 features a high speed digital-to-analog video
encoder. Six 12-bit NSV, 3.3 V video DACs provide support for
worldwide composite (CVBS), S-Video (Y/C), and component
(YPrPb/RGB) analog outputs in SD, ED, or HD video formats. It
is also possible to enable the video encoder of the ADV8005 to
work in simultaneous modes where both SD and ED/HD
Rev. 0 | Page 46 of 52
Data Sheet
ADV8005




formats are output. Rovi (ADV8005KBCZ-8A) and non-Rovi
(ADV8005KBCZ-8N) variants of the ADV8005 are available.
Encoder features include the following:

Six 12-bit NSV video DACs capable of outputting video
standards of up to 1080p with additional oversampling
Multiformat video output support; composite (CVBS),
S-Video (Y/C), component YPrPb (SD, ED and HD), and
component RGB (SD, ED and HD)
HDMI
HDMI
S-VIDEO
HDMI
60-BIT
INPUT
VIDEO
48-BIT
INPUT
VIDEO DECODER/
HDMI Rx
(FOR EXAMPLE,
ADV7844)
SERIAL
VIDEO
RECEIVER
HDMI
HDMI
HDMI
HDMI
HDMI
EXTERNAL DDR2
DDR2 INTERFACE
SPI/I2C
COMPOSITE
COMPONENT
See Figure 35 for an example of a typical application diagram.
SPI
FLASH
SYSTEM
MCU
DUAL HIGH SPEED
HDMI Rx
(FOR EXAMPLE,
ADV7619)
TYPICAL APPLICATION DIAGRAM
HDMI Tx1
HDMI
HDMI Tx2
HDMI
VIDEO SIGNAL
PROCESSING
HD VIDEO
DACs
HDMI
FRONT END
(FOR EXAMPLE,
ADV7850)
SD VIDEO
DACs
COMPONENT
S-VIDEO
COMPOSITE
ADV8005
AUDIO INSERTED INTO
HDMI VIDEO STREAMS
AUDIO FROM
HDMI
SHARC ®
AUDIO
PROCESSING
Figure 35. System Block Diagram
Rev. 0 | Page 47 of 52
12074-038

Simultaneous SD and ED/HD operation
Copy generation management system (CGMS)
Closed captioning and widescreen signaling (WSS)
Rovi Rev. 7.1.L1 (SD) and Rev. 1.4 (ED) compliant
ADV8005
Data Sheet
DESIGN CONSIDERATIONS
POWER-UP SEQUENCE
THERMAL CONSIDERATIONS
The power-up sequence of the ADV8005 is as follows:
The thermal performance of the ADV8005 is influenced by a
number of factors, for example, power dissipation of the
ADV8005, printed circuit board (PCB) design, and ambient
temperature.
1.
2.
3.
4.
5.
6.
Hold the RESET and PDN pins low.
Power up the 3.3 V supplies (DVDD_IO, AVDD1,
AVDD2).
A minimum delay of 20 ms is required from the point at
which the 3.3 V reaches its minimum recommended value
(that is, 3.14 V) before powering up the 1.8 V supplies.
Power up the 1.8 V supplies (DVDD, PVDD1, PVDD2,
PVDD3, CVDD1, AVDD3, AVDD4, DVDD_DDR,
PVDD_DDR) and the 1.845 V supplies (PVDD5 and
PVDD6). Power these up together, that is, with a difference
of less than 0.3 V between them.
RESET can be pulled high after powering up the supplies.
A complete reset is recommended after power-up. This
can be performed by the system microcontroller.
PDN
(C11)
0V
3.3V
RESET
(A11)
0V
The flexibility of the ADV8005 can, in theory, result in the
device being configured in modes where the junction
temperature exceeds the maximum rated specification. To
ensure that this does not happen, the ADV8005 must be
characterized on the final customer PCB to ensure that the
maximum rated specifications are not exceeded in the planned
modes of operation. Using fewer internal layers on a PCB
reduces the amount of thermal conductivity between the
ADV8005 and the PCB itself. This decreased thermal
conductivity may necessitate some thermal management effort,
or it may affect the modes in which the ADV8005 can be
configured.
Calculate thermal conductivity as follows:
1.8V
1.
1.8V
SUPPLY
2.
3.
DELAY ≥
20ms
RESET >
5ms
0V
Figure 36. Supply Power-Up Sequence
Configure the ADV8005 in the highest required power
mode of operation.
Measure the ambient temperature of the enclosure.
Measure the case temperature at the top of the ADV8005.
TJ = TC + 5°C
12074-032
0V
3.3V
3.14V
3.3V
SUPPLY
These factors, along with any other application specific factors
that may affect the thermal performance of ADV8005, must be
considered to ensure that the junction temperature of the
ADV8005 does not exceed 125°C.
TJ MAX = TA MAX − TA (actual) + TC (actual) + 5°C
where:
TJ is the junction temperature (inside the ADV8005).
TC is the case temperature (top surface of the ADV8005).
TA is the ambient temperature (in the locality of the ADV8005).
Maximum specified TA MAX for the ADV8005 is 70°C. Depending
on the result of the previous calculations/measurement for the
specific system, a lower TA MAX limit may need to be specified for
that system to ensure that TJ MAX remains safely below 125°C.
Rev. 0 | Page 48 of 52
Data Sheet
ADV8005
REGISTER MAP ARCHITECTURE
The registers of the ADV8005 are controlled via a 2-wire serial
(I2C-compatible) interface. Addressing in the ADV8005 is
16-bit with 8-bit data. This means that I2C writes to the device
are in the following format: <I2C Address>, <Address MSBs>,
<Address LSBs>, <Data>.
For example, to write 0xFF to the encoder register map, which
is Register 0xE4AF, the bytes sent over the I2C interface are:
0x1A, 0xE4, 0xAF, 0xFF. The addresses are outlined in Table 8.
Figure 37 shows the register map architecture for the ADV8005.
The ADV8005 also has a number of SPI register maps used for
OSD functions. These are accessed through the APIs defined in
the Blimp software tool.
Table 8. I2C Address and Register Address Ranges
Register Map Name
IO Map
Primary VSP Map 1
Primary VSP Map 2
Secondary VSP Map
DPLL Map
Rx Main Map
Rx InfoFrame Map
Encoder Map
Tx1 Main Map
Tx1 EDID Map
Tx1 UDP Map
Tx1 Test Map
Tx2 Main Map
Tx2 EDID Map
Tx2 UDP Map
Tx2 Test Map
I2C
ADDRESS
0x18/0x1A
I2C Address
0x1A (when the ALSB pin is set high) or 0x18 (when the ALSB pin is set low)
Register Address
0x1A00 to 0x1BFF
0xE800 to 0xE8FF
0xE900 to 0xE9FF
0xE600 to 0xE6FF
0xE000 to 0xE0FF
0xE200 to 0xE2FF
0xE300 to 0xE3FF
0xE400 to 0xE4FF
0xEC00 to 0xECFF
0xEE00 to 0xEEFF
0xF200 to 0xF2FF
0xF300 to 0xF3FF
0xF400 to 0xF4FF
0xF600 to 0xF6FF
0xFA00 to 0xFAFF
0xFB00 to 0xFBFF
IO
MAP
PRIMARY VSP
MAP 1
PRIMARY VSP
MAP 2
SECONDARY
VSP MAP
DPLL
MAP
Rx MAIN
MAP
Rx INFOFRAME
MAP
ENCODER
MAP
Tx1 TEST
MAP
0x1A00 TO
0x1BFF
0xE800 TO
0xE8FF
0xE900 TO
0xE9FF
0xE600 TO
0xE6FF
0xE000 TO
0xE0FF
0xE200 TO
0xE2FF
0xE300 TO
0xE3FF
0xE400 TO
0xE4FF
0xF300 TO
0xF3FF
0xEC00 TO
0xECFF
0xEE00 TO
0xEEFF
0xF200 TO
0xF2FF
0xF400 TO
0xF4FF
0xF600 TO
0xF6FF
0xFA00 TO
0xFAFF
0xFB00 TO
0xFBFF
Tx1 MAIN
MAP
Tx1 EDID
MAP
Tx1 UDP
MAP
Tx2 MAIN
MAP
Tx2 EDID
MAP
Tx2 UDP
MAP
Tx2 TEST
MAP
Figure 37. Register Map Architecture
Rev. 0 | Page 49 of 52
12074-037
SCL
SDA
ADV8005
Data Sheet
OUTLINE DIMENSIONS
A1 BALL
CORNER
19.20
19.00 SQ
18.80
A1 BALL
CORNER
22 20 18 16 14 12 10 8 6 4 2
23 21 19 17 15 13 11 9 7 5 3 1
A
C
E
G
17.60
BSC SQ
J
L
N
0.80
BSC
R
U
W
B
D
F
H
K
M
P
T
V
Y
AA
AB
AC
TOP VIEW
DETAIL A
0.65
NOM
DETAIL A
0.35 NOM
0.30 MIN
0.35
NOM
SEATING
PLANE
1.11
1.01
0.91
0.50
COPLANARITY
0.12
0.45
0.40
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-PPAB-2.
11-22-2011-A
1.50
1.36
1.21
BOTTOM VIEW
Figure 38. 425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-425-1)
Dimensions shown in millimeters
Table 9. Features Sets of the ADV8005 Models
Model Number
ADV8005KBCZ-8A1
ADV8005KBCZ-8N
ADV8005KBCZ-8B
ADV8005KBCZ-8C
1
Maximum
Data Rate
3 Gbps
3 Gbps
3 Gbps
3 Gbps
Maximum Video Format
4k × 2k at 30 Hz (8-bit)
4k × 2k at 30 Hz (8-bit)
4k × 2k at 30 Hz (8-bit)
4k × 2k at 30 Hz (8-bit)
HDMI Tx
Outputs
2
2
1
2
Analog
Outputs
Six 12-bit DACs
Six 12-bit DACs
No
No
Rovi
Output
Yes
No
No
No
VSP
Yes
Yes
Yes
Yes
OSD
Yes
Yes
Yes
Yes
TTL
Output
Yes
Yes
No
No
Rovi enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are capable of outputting Rovi compliant video. The ADV8005KBCZ-8A
incorporates copy protection technology that is protected by U.S. patents and other intellectual property rights of Rovi Corporation. Reverse engineering and
disassembly are prohibited.
ORDERING GUIDE
Model1, 2
ADV8005KBCZ-8A
ADV8005KBCZ-8A-RL
ADV8005KBCZ-8N
ADV8005KBCZ-8N-RL
ADV8005KBCZ-8B
ADV8005KBCZ-8B-RL
ADV8005KBCZ-8C
ADV8005KBCZ-8C-RL
EVAL-ADV8005-SMZ
1
2
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Package Description
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
425-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
Z = RoHS Compliant Part.
The -RL versions are supplied on 13” reels. The non-RL versions are supplied on trays.
Rev. 0 | Page 50 of 52
Package Option
BC-425-1
BC-425-1
BC-425-1
BC-425-1
BC-425-1
BC-425-1
BC-425-1
BC-425-1
Data Sheet
ADV8005
NOTES
Rev. 0 | Page 51 of 52
ADV8005
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12074-0-6/14(0)
Rev. 0 | Page 52 of 52