IDT72103 IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 Integrated Device Technology, Inc. FEATURES: APPLICATIONS: • 35ns parallel port access time, 45ns cycle time • 50MHz serial input/output frequency • Serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel operations • Expandable in both depth and width with no external components • Flexishift — Sets programmable serial word width from 4 bits to any width with no external components • Multiple flags: Full, Almost-Full (Full-1/8),Full-MinusOne, Empty, Almost-Empty (Empty + 1/8), Empty-Plus One, and Half-Full • Asynchronous and simultaneous read or write operations • Dual-Port, zero fall-through time architecture • Retransmit capability in single-device mode • Packaged in 44-pin PLCC • Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications • • • • • • • • • High-speed data acquisition systems Local area network (LAN) buffer High-speed modem data buffer Remote telemetry data buffer FAX raster video data buffer Laser printer engine data buffer High-speed parallel bus-to-bus communications Magnetic media controllers Serial link buffer DESCRIPTION: The IDT72103/72104 are high-speed Parallel-Serial FlFOs to be used with high-performance systems for functions such as serial communications, laser printer engine control and local area networks. A serial input, a serial output and two 9-bit parallel ports make four modes of data transfer possible: serial-to-parallel, parallel-to-serial, serial-to-serial, and parallel-to-parallel. The IDT72103/72104 are expandable in both depth and width for all of these operational configurations. FUNCTIONAL BLOCK DIAGRAM SERIAL INPUT SI SIX SICP DATA INPUTS (D 0 -D 8 ) SERIAL INPUT CIRCUITRY FLAG LOGIC SI/PI SO/PO SERIAL/ PARALLEL CONTROL W WRITE POINTER XI XO FL/RT RAM ARRAY 2048 x 9 4096 x 9 READ POINTER RESET LOGIC DEPTH EXPANSION LOGIC SERIAL OUTPUT CIRCUITRY OE DATA OUTPUTS (Q 0 -Q 8 ) FF FF-1 EF+1 EF AEF HF R RS SERIAL OUTPUT SO SOX SOCP 2753 drw 01 The IDT logo is a registered trademark of Integrated Device Technology,Inc. COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. DECEMBER 1996 For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.37 DSC-2753/8 1 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES DESCRIPTION (CONTINUED) The IDT72103/72104 may be configured to handle serial word widths of four or greater using IDT’s unique Flexishift feature. Flexishift allows serial width and depth expansion without external components. For example, you may configure a 4K x 24 FIFO using three IDT72104s in a serial width expansion configuration. Seven flags are provided to signal memory status of the FIFO. The flags are FF (Full), AF (7/8 full), FF–1 (Full-minusone), EF (Empty), AE (1/8 full), EF+1 (Empty-plus-one), and HF (Half-full). Read (R) and Write (W) control pins are provided for asynchronous and simultaneous operations. An output enable (OE) control pin is available on the parallel output port for high-impedance control. The depth expansion control pins XO and Xl are provided to allow cascading for deeper FlFOs. The IDT72103/72104 are manufactured using IDT’s CMOS technology. GND D1 D2 D3 D4 W VCC D5 D6 D7 D8 PIN CONFIGURATIONS INDEX 6 7 5 4 3 2 1 44 43 42 41 40 39 8 9 38 37 10 11 36 35 J44-1 12 13 34 33 14 32 15 31 16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 Q1 Q2 Q3 Q4 GND R Q5 Q6 Q7 Q8 GND D0 XI SO/PO SOX SOCP SO AEF FF-1 FF Q0 GND GND FL/RT RS SI SICP SIX SI/PI OE EF+1 EF XO/HF 2753 drw 03 PLCC TOP VIEW 5.37 2 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Rating Commercial Unit VTERM Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current –0.5 to +7.0 V 0 to +70 –55 to +125 –55 to +125 50 °C °C °C mA TA TBIAS TSTG IOUT Symbol Parameter(1) Conditions Max. Unit pF CIN Input Capacitance VIN = 0V 10 COUT Output Capacitance VOUT = 0V 12 pF NOTE: 1. This parameter is sampled and not 100% tested. 2753 tbl 01 2753 tbl 02 RECOMMENDED DC OPERATING CONDITIONS Symbol NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V VCCC Commercial Supply Voltage GND Supply Voltage VIH Input High Voltage Commercial 2.0 — — V VIL(1) Input Low Voltage — — 0.8 V NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. 2753 tbl 03 PIN DESCRIPTION Symbol D0-D8 Name Data Inputs Serial Input Word Width Select I/O I/O RS Reset I W Write I R Read I First Load/ Retransmit I Xl Expansion In I OE Output Enable I O FF Data Outputs / Serial Output Word Width Select Full Flag O FF-1 Full-1 Flag O FL/RT Q0-Q8 Description In a parallel input configuration – data inputs for 9-bit wide data. In a serial input configuration – one of the nine output pins is used to select the serial input word width. When RS is set low, internal READ and WRITE pointers are set to the first location of the RAM array. EF, EF+1, AEF are all LOW after a reset, while FF, FF-1, HF are HIGH after a reset. A parallel word write cycle is initiated on the falling edge of W if the FF is high. When the FIFO is full, FF will go low inhibiting further write operations to prevent data overflow. In a serial input configuration, data bits are clocked into the input shift register and the write pointer does not advance until a full parallel word is assembled. One of the pins, Di, is connected to W and advances the write pointer every i-th serial input clock. A read cycle is initiated on the falling edge of R if the EF is HIGH. After all the data from the FIFO has been read EF will go LOW inhibiting further read operations. In a serial output configuration, a data word is read from memory into the output shift register. One of the pins, Qj, is connected to R and advances the read pointer every j-th serial output clock. This is a dual-purpose pin. In multiple-device mode, FL/RT is grounded to indicate the first device loaded. In single-device mode, FL/RT acts as the retransmit input. Single-device mode is initiated by grounding the XI pin. In single-device mode, XI is grounded.In depth expansion or daisy chain mode, XI is con nected to the XO pin of the previous device. When OE is LOW, both parallel and serial outputs are enabled. When OE is HIGH, the parallel output buffers are placed in a high-impedance state. In a parallel output configuration - data outputs for 9-bit wide data. In a serial output configuration - one of nine output pins used to select the serial output word width. FF is asserted LOW when the FIFO is full and further write operations are inhibited. When the FF is HIGH, the FIFO is not full and data can be written into the FIFO. FF-1 goes LOW when the FIFO memory array is one word away from being full. It will remain LOW when every memory location is filled. 2753 tbl 04 5.37 3 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES PIN DESCRIPTION (Continued) Symbol XO/HF Name Expansion Out/ Half-Full Flag I/O O Description HF is LOW when the FIFO is more than half-full in the single device or width expansion modes. The HF will remain LOW until the difference between the write and read pointers is less than or equal to one-half of the FIFO memory. In depth expansion mode, a pulse is written from XO to XI of the next device when the last location in the FIFO is filled. Another pulse is sent from XO to Xl of the next device when the last FIFO location is read. AEF When AEF is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If then the FIFO is greater than 1/8 full, but less than 7/8 full. AEF is HIGH, Almost-Empty/ Almost-Full Flag O Empty+1 Flag O Empty Flag O EF+ 1 is LOW when there is zero or one word word in the FIFO memory array. EF goes LOW when the FIFO is empty and further read operations are inhibited. FF is HIGH Sl Serial Input I Data input for serial data. SO Serial Output O Data output for serial data. SICP Serial Input Clock I This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits are read into the serial input shift register. SOCP Serial Output Clock I This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits are read from the serial output shift register. SIX Serial Input Expansion I SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other devices is connected to the D8 pin of the previous device. In parallel input configurations or serial input configurations of 9 bits or less, SIX is tied HIGH. SOX Serial Output Expansion I SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other devices is connected to the Q8 pin of the previous device. In parallel output configurations or serial output configurations of 9 bits or less, SOX is tied HIGH. SI/PI Serial/Parallel Input I When this pin is HIGH, the FIFO is in a parallel input configuration and accepts input data through D0-D8. When SI/PI is LOW, the FIFO is in a serial input configuration and data is input through Sl. SO/PO Serial/Parallel Output I When this pin is HIGH, the FIFO is in a parallel output configuration and sends output data through Q0-Q8. When SO/PO is LOW the FIFO is in a serial output configuration and data is input through SO. GND Ground One ground pin for the DIP package and five ground pins for the LCC/PLCC packages. VCC Power One + 5V power pin. EF+1 EF when the FIFO is not empty and data reads are permitted. 2753 tbl 05 5.37 4 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) IDT72103/72104 Commercial tA = 35, 50ns Symbol Min. Typ. Max. Unit IIL(1) Input Leakage Current (Any Input) –1 — 1 µA IOL(2) Output Leakage Current –10 — 10 µA VOH Output Logic "1" Voltage, IOUT = -2mA(4) 2.4 — — V VOL Output Logic "0" Voltage, IOUT = 8mA(5) — — 0.4 V ICC1(3) Average VCC Power Supply Current — 90 140 mA I Average Standby Current (R = W = RS = FL/RT = VIH) (SOCP = SICP = VIL) — 8 12 mA ICC3(L)(3,6) Power Down Current — — 2 (3) CC2 Parameter mA NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. R ≥ VIH, SOCP ≤ VIL, 0.4 ≤ VOUT ≤ VCC. 3. ICC measurements are made with outputs open. 4. For SO, IOUT = -8mA. 5. For SO, IOUT =16mA. 6. SOCP = SICP ≤ 0.2V; other Inputs = VCC -0.2V. 2753 tbl 06 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 5V GND to 3.0V 1.1KΩ See Figure 1 2753 tbl 07 D.U.T. 680Ω 30pF* 2753 drw 04 or equivalent circuit Figure 1. Ouput Load *Including jig and scope capacitances 5.37 5 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Symbol Parameter fS Parallel Shift Frequency fSOCP Serial-Out Shift Frequency fSICP Serial-In Shift Frequency PARALLEL-OUTPUT MODE TIMINGS tA Access Time tRR Read Recovery Time tRPW Read Pulse Width tRC Read Cycle Time tWLZ Write Pulse LOW to Data Bus at Low-Z(1) tRLZ Read Pulse LOW to Data Bus at Low-Z(1) tRHZ Read Pulse HIGH to Data Bus at High-Z(1) tDV Data Valid from Read Pulse HIGH PARALLEL-INPUT MODE TIMINGS tDS Data Set-up Time tDH Data Hold Time tWC Write Cycle Time tWPW Write Pulse Width tWR Write Recovery Time RESET TIMINGS tRSC Reset Cycle Time tRS Reset Pulse Width tRSS Reset Set-up Time tRSR Reset Recovery Time RESET TO FLAG TIMINGS tRSF1 Reset to EF, AEF, and EF+1 LOW tRSF2 Reset to HF, FF, and FF-1 LOW RESET TO OUTPUT TIMINGS – SERIAL MODE ONLY tRSQL Reset Going LOW to Q0-8 LOW tRSQH Reset Going HIGH to Q0-8 HIGH tRSDL Reset Going LOW to D0-8 LOW RETRANSMIT TIMINGS tRTC Retransmit Cycle Time tRT Retransmit Pulse Width tRTS Retransmit Set-up Time tRTR Retransmit Recovery Time tRTF Retransmit to Flags PARALLEL MODE FLAG TIMINGS tREF Read LOW to EF LOW tRFF Read HIGH to FF HIGH tRF Read HIGH to Transitioning HF, AEF and FF-1 tRE Read LOW to EF+1 LOW tRPE Read Pulse Width after EF HIGH tWEF Write HIGH to EF HIGH tWFF Write LOW to FF LOW tWF Write LOW to Transitioning HF, AEF and FF-1 tWE Write HIGH to EF+1 HIGH tWPF Write Pulse Width after FF HIGH Commercial IDT72103L35 IDT72103L50 IDT72104L35 IDT72104L50 Min. Max. Min. Max. — 22.2 — 15 — 50 — 40 — 50 — 40 Unit MHz MHz MHz Timing Figure — — — — 10 35 45 5 5 — 5 35 — — — — — 20 — — 15 50 65 15 10 — 5 50 — — — — — 30 — ns ns ns ns ns ns ns ns 4 4 4 4 15 4 4 4 18 0 45 35 10 — — — — — 20 0 50 40 10 — — — — — ns ns ns ns ns 3 3 3 3 3 45 35 35 10 — — — — 50 40 40 10 — — — — ns ns ns ns 2,18 2,18 2,18 2,17,18 — — 45 45 — — 65 65 ns ns 2 2 20 20 20 — — — 20 20 20 — — — ns ns ns 18 18 17 45 35 35 10 — — — — — 35 50 40 40 10 — — — — — 50 ns ns ns ns ns 5 5 5 5 5 — — — — 35 — — — — 35 30 30 45 45 — 30 30 45 45 — — — — — 40 — — — — 40 45 45 65 65 — 45 45 65 65 — ns ns ns ns ns ns ns ns ns ns 6 7 8,9,10 11 15 6 7 8,9,10 11 16 NOTE: 1. Values guaranteed by design, not tested. 2753 tbl 08 5.37 6 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C) Symbol Parameter DEPTH EXPANSION MODE TIMINGS tXOL Read/Write to XO LOW tXOH Read/Write to XO HIGH tXI XI Pulse Width tXIR XI Recovery Time tXIS XI Set-up Time SERIAL-INPUT MODE TIMINGS tS2 Serial Data In Set-up Time to SICP Rising Edge tH2 Serial Data In Hold Time to SICP Rising Edge tS3 SIX Set-up Time to SICP Rising Edge tS4 W Set-up Time to SICP Rising Edge tH4 W Hold Time to SICP Rising Edge tSICW Serial In Clock Width High/Low tS5 SI/PI Set-up Time to SICP Rising Edge SERIAL-OUTPUT MODE TIMINGS tS6 SO/PO Set-up Time to SOCP Rising Edge tS7 SOX Set-up Time to SOCP Rising Edge tS8 R Set-up Time to SOCP Rising Edge tH8 R Hold Time to SOCP Rising Edge tSOCW Serial Out Clock Width HIGH/LOW SERIAL MODE RECOVERY TIMINGS tREFSO Recovery Time SOCP after EF Goes HIGH tRFFSI Recovery Time SICP after FF Goes HIGH SERIAL MODE FLAG TIMINGS tSOCEF SOCP Rising Edge (Bit 0- Last Word) to EF LOW tSOCFF SOCP Rising Edge (Bit 0- First Word) to FF HIGH tSOCF SOCP Rising Edge to FF-1, HF, AEF HIGH tSOCF SOCP Rising Edge to AEF, EF, EF+1 LOW tSICEF SICP Rising Edge (Last Bit-First Word) to EF HIGH tSICFF SICP Rising Edge (Bit 1-Last Word) to FF LOW tSICF SICP Rising Edge to EF+1, AEF HIGH tSICF SICP Rising Edge to FF-1, HF, AEF HIGH SERIAL-INPUT MODE TIMINGS tPD1 SICP Rising Edge to D(1) SERIAL-OUTPUT MODE TIMINGS tPD2 SOCP Rising Edge to Q(1) tSOHZ SOCP Rising Edge to SO at High-Z(1) tSOLZ SOCP Rising Edge to SO at Low-Z(1) tSOPD SOCP Rising Edge to Valid Data on SO OUTPUT ENABLE/DISABLE TIMINGS tOEHZ Output Enable to High-Z (Disable)(1) tOELZ Output Enable to Low-Z (Enable)(1) tAOE Output Enable to Data Valid (Q0-8) Commercial IDT72103L35 IDT72103L50 IDT72104L35 IDT72104L50 Min. Max. Min. Max. Unit Timing Figure — — 35 10 15 35 35 — — — — — 50 10 15 50 50 — — — ns ns ns ns ns 13 13 14 14 14 12 0 5 5 7 8 35 — — — — — — — 15 0 5 5 7 10 50 — — — — — — — ns ns ns ns ns ns ns 19 19 19 19 19 19 19 35 5 5 7 8 — — — — — 50 5 5 7 10 — — — — — ns ns ns ns ns 20 20 20 20 20 35 15 — — 80 15 — — ns ns 22 23 — — — — — — — — 20 30 30 30 45 30 45 45 — — — — — — — — 25 40 40 40 65 40 65 65 ns ns ns ns ns ns ns ns 22 24 24,26 22,26 21 23 21,25 23,25 5 17 5 20 ns 17,19 5 5 5 — 17 16 22 18 5 5 5 — 20 16 22 18 ns ns ns ns 20 20 20 20 — 5 — 16 — 20 — 5 — 16 — 22 ns ns ns 12 12 12 NOTE: 1. Values guaranteed by design, not tested. 2753 tbl 09 5.37 7 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES GENERAL SIGNAL DESCRIPTION INPUTS: Data Inputs (D0-D8) The parallel-in mode is selected by connecting the SI/PI pin to VCC. D0-D8 are the data input lines. The serial-input mode is selected by grounding the SI/PI pin. The D0-D8 lines are control output pins used to program the serial word width. Reset (RS) Reset is accomplished whenever the RS input is taken to a low state. Both internal read and write pointers are set to the first location during reset. A reset is required after power up before a write operation can take place. Both Read (R) and Write (W) inputs must be HIGH during reset. Write (W) A write cycle is initiated on the falling edge of W provided the Full Flag (FF) is not asserted. Data set-up and hold times must be met with respect to the rising edge of W. Data is stored in the RAM array sequentially and independently of any on going read operation. When the FIFO is full, the FF will go LOW inhibiting further write operations to prevent data overflow. After a valid read operation is completed, the FF will go HIGH after tRFF allowing a valid write to begin. Read (R) A read cycle is initiated on the falling edge of R, provided the EF is not set. Data is accessed on a first-in/first out basis independent of any on going write operations. After R goes HIGH, the Data Outputs (Q0-Q8) go to a high-impedance condition until the next read operation. When all the data has been read from the FIFO, the EF will go LOW, and Q0-Q8 will go to a high-impedance state inhibiting further read operations. After the completion of a valid write operation, the EF will go HIGH after tWEF allowing a valid read to begin. First Load/Retransmit (FL/RT) In the depth-expansion mode, the FL/RT pin is grounded to indicate that it is the first device loaded. In the single-device mode, the FL/RT pin acts as the retransmit input. The singledevice mode is initiated by grounding the Expansion-ln (XI) pin. The IDT72103/72104 can be made to retransmit data when the RT input is pulsed LOW. A retransmit operation will set the internal read pointer to the first location and will not affect the write pointer. During retransmit, R and W must be set HIGH and the FF will be affected depending on the relative locations of the read and write pointers. This feature is useful when less than 2048/4096 writes are performed between resets. The retransmit feature is not available in the depth expansion mode. Expansion In (XI) The XI pin is grounded to indicate an operation in the the single-device mode. In the depth expansion or daisy-chain mode, the XI pin is connected to the XO pin of the previous device. Output Enable (OE) When OE is HIGH, the parallel output buffers are tristated. When OE is LOW, both parallel and serial outputs are enabled. Serial Input (SI) Serial data is read into the serial input register via the Sl pin. In both depth and serial width expansion modes, the serialinput signals of the different FlFOs in the expansion array are connected together. Serial Input Clock (SICP) Serial data is read into the serial input register on the rising edge of the SICP signal. In both depth and serial width expansion modes, the SICP signals of the different FlFOs in the expansion array are connected together. Serial Output Clock (SOCP) New serial data bits are read from the serial output register on the rising edge of the SOCP signal. In both depth and serial width expansion modes, the SOCP signals of the different FlFOs in the expansion array are connected together. Serial Input Expansion (SIX) The SlX pin is tied HIGH for single-device serial or parallel input operation. In a serial input configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other devices is connected to the D8 pin of the previous device. Serial Output Expansion (SOX) The SOX pin is tied HIGH for single-device serial or parallel output operation. In a serial output configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other devices is connected to the Q8 pin of the previous device. Serial/Parallel Input (SI/PI) The SI/PI pin programs whether the IDT72103/72104 accepts parallel or serial data as input. When this pin is LOW, the FIFO expects serial data and the D0-D8 pins become output pins used to program the write signal and the serial input word width. For instance, connecting D8 to W will program a serial word width of 9 bits; connecting D7 to W will program a serial word width of 8 bits and so on. Serial/Parallel Output (SO/PO) The SO/PO pin programs whether the IDT72103/72104 outputs parallel or serial data. When this pin is LOW, the FIFO expects serial data and the Q0-Q8 pins output signals used to program the read signal and the serial output word width. 5.37 8 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES OUTPUTS: Data Outputs (Q0–Q8) Data outputs for 9-bit wide data. These output lines are in a high-impedance condition whenever R is in a high state. The serial output mode is selected by grounding the SO/PO pin. The Q0-Q8 lines are control pins used to program the serial word width. Serial Output (SO) Serial data is output on the SO pin. In both depth and serial width expansion modes the serial output signals of the different FlFOs in the expansion array are connected together. Following reset, SO is tristated until the first rising edge of the Serial Out Clock (SOCP) signal. Data is clocked out least significant bit first. In the serial width expansion mode, SO is tristated again after the ninth bit is output. Full Flag (FF) FF is asserted LOW when the FIFO is full. When the FIFO is full, the internal write pointer will not be incremented by any additional write pulses. Full Flag — Serial In Mode When the FIFO is loaded serially, the Serial In Clock (SICP) asserts the FF. On the second rising edge of the SICP for the last word in the FIFO, the FF will assert LOW, and it will remain asserted until the next read operation. Note that when the FF is asserted, the last SICP for that word will have to be stretched as shown in Figure 23. Full Flag — Parallel–ln Mode When the FIFO is in the Parallel-ln mode, the falling edge of W asserts the FF (LOW). The FF is then de-asserted (HIGH) by subsequent read operations - either serial or parallel. Full–Minus — One Flag (FF–1) The FF–1 flag is asserted low when the FIFO is one word away from being full. It will remain asserted when the FIFO is full. Expansion Out/Half–Full Flag (XO/HF) In the single-device mode, the XO/HF pin operates as a HF pin when the Xl pin is grounded. After half of the memory is filled, the HF will be set to LOW at the falling edge of the next write operation. It will remain set until the difference between the write pointer and read pointer is less than or equal to onehalf of the FIFO total memory. The HF is then reset by the rising edge of the read operation. In the multiple-device mode, the XI pin is connected to the XO pin of the previous device. The XO pin signals a pulse to the next device when the previous device reaches the best location of memory in the daisy chain configuration. Almost–Empty or Almost–Full Flag (AEF) The AEF asserts LOW if there are 0-255 or 1793-2048 bytes in the IDT72103, 2K x 9 FIFO. The AEF asserts LOW if there are 0-511 or 3585-4096 bytes in the IDT72104, 4K x 9 FIFO. Empty–Plus–One Flag (EF+1) In the parallel-output mode, the EF+1 flag is asserted LOW when there is one word or less in the FIFO. It will remain LOW when the FIFO is empty. In the serial-output mode, the EF+1 flag operates as an EF+2 flag. It goes LOW when the second to the last word is read from the RAM array and is ready to be shifted out. Empty Flag (EF) — Parallel–Out Mode When the FIFO is in the parallel out mode and there is only one word in the FIFO, the falling edge of the R line will cause the EF line to be asserted LOW. This is shown in Figure 6. The EF is then de-asserted HIGH by either the rising edge of W or the rising edge of SICP, as shown in Figure 6. Empty Flag — Serial–Out Mode The use of the EF is important for proper serial-out operation when the FIFO is almost empty. The EF flag is asserted LOW after the first bit of the last word is shifted out. This is shown in Figure 22. TABLE 1 — STATUS FLAGS Number of Words in FIFO IDT72103 IDT72104 ' (1) FF FF-1 AEF HF EF+1 EF 0 0 H H L H L L 1 1 H H L H L H 2-255 2-511 H H L H H H 256-1024 512-2048 H H H H H H 1025-1792 2049-3584 H H H L H H 1793-2046 3585-4094 H H L L H H 2047 4095 H L L L H H 2048 4096 L L L L H NOTE: 1. EF+1 acts as EF+2 in the serial out mode. 5.37 H 2753 tbl 10 9 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES PARALLEL TIMINGS: t RSC t RS RS t RSS t RSR W t RSS R t RSF1 AEF, EF+1, EF t RSF2 FF-1, HF, FF 2753 drw 05 Figure 2. Reset t RC t WC R W t RPW t WPW t WR Q 0–8 VALID DATA 0–8 t RLZ t DS t DH t RR t DV tA 2753 drw 06 t RHZ 2753 drw 07 Figure 3. Write Operation in Parallel Data In Mode Figure 4. Read Operation in Parallel Data Out Mode t RTC t RT RT t RTS t RTR W, R t RTF FLAG VALID All Flags 2753 drw 08 Figure 5. Retransmit 5.37 10 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES (1) R EF t REF (2) (3) W t WEF 2753 drw 09 NOTES: 1. Data is valid on this edge. 2. The Empty Flag is asserted by R in the Parallel-Out mode and is specified by tREF. The EF flag is deasserted by the rising edge of W. 3. First rising edge of Write after EF is set. Figure 6. Empty Flag Timings in Parallel Out Mode W FF t RFF (1) R t WFF 2753 drw 10 NOTE: 1. For the assertion time, tWFF is used when data is written in the Parallel mode. The FF is de-asserted by the rising edge of R. Figure 7. Full Flag Timings in Parallel-In Mode t WF t WF W W t RF t RF R AEF R Almost Empty Almost Empty AEF Almost Full 2753 drw 11 2753 drw 12 Figure 8. Almost-Empty Flag Region Figure 9. Almost-Full Flag Region 5.37 11 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES W t WF HF, FF-1 t RF R 2753 drw 13 Figure 10. Half-Full and Full-minus-1 Flag Timings R t RE EF+1 t WE W 2753 drw 14 Figure 11. Empty+1 Flag Timings t RC t RR R TERMINATE READ CYCLE tA OE tRLZ Q0-8 SECOND READ BY CONTROLLING OE tAOE tOELZ tOEHZ DATA 1 tDV DATA 1 2753 drw 15 Figure 12. Output Enable Timings W WRITE TO LAST PHYSICAL LOCATION READ FROM LAST PHYSICAL LOCATION R t XOL t XOH t XOL t XOH XO 2753 drw 16 Figure 13. Expansion-Out 5.37 12 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES t XI t XIR XI t XIS W WRITE TO FIRST PHYSICAL LOCATION t XIS READ FROM FIRST PHYSICAL LOCATION R 2573 drw 17 Figure 14. Expansion-In Dn W t RPE R EF t WEF t REF tA t WLZ Qn DATA OUT VALID 2753 drw 18 Figure 15. Read Data Flow-Through Mode R t WPF W t RFF t WFF FF t DH t DS DATA IN VALID Dn tA Qn DATA OUT VALID 2753 drw 19 Figure 16. Write Data Flow-Through Mode 5.37 13 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES SERIAL TIMINGS: t RS RS t RSS SICP (1) SICP (1) t RSR 0 0 i i-1 i t PD1 D0 t PD1 D 1-8 t RSDL 2753 drw 20 NOTE: 1. SICP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR. Figure 17. Reset Timings for Serial-In Mode t RSC t RS RS t RSS SOCP (1) SOCP (1) t RSR Q 0-8 t RSQH t RSQL 2753 drw 21 NOTE: 1. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR. igure 18. Reset Timings for Serial-Out Mode 5.37 14 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES t SICW 0 t SICW (1) n–1 2 1 SICP 1/t SICP SI/PI (3) t S5 SIX t S3 SI t S2 t H2 Di t S4 (2) t PD1 t H4 (2) W 2753 drw 22 NOTES: 1. For the stand alone mode, n ≥ 4 and the input bits are numbered 0 to n-1. 2. For the recommended interconnections, Di is to be directly tied to W and the tS4 and tH4 requirements will be satisfied. For users that modify W externally, tS4 and tH4 requirements have to be met. 3. After SI/PI has been set up, it cannot be dynamically changed; it can only be changed after a reset operation. Figure 19. Write Operation In Serial-ln Mode t SOCW t SOCW 1 0 n–1 SOCP 1/t SOCP SO/PO (1) t S6 SOX t S7 Qi t PD2 t S8 t H8 R (2) SO t SOHZ SO (3) t SOLZ t SOPD 2753 drw 23 NOTES: 1. After SO/PO has been set up, it cannot be dynamically changed; it can only be changed after a reset operation. 2. For single device: Read out the last bit after EF is asserted. For Serial Width Expansion mode: Read out the last bit of the current memory location from the active device. 3. For single device: The operation starts after Reset. For Serial Width Expansion mode: Read the first bit of the current memory location from the active device. Figure 20. Read Operation In Serial-Out Mode 5.37 15 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES FIRST SERIAL-IN WORD 0 1 n–1 SECOND SERIAL-IN WORD 0 1 n–1 THIRD SERIAL-IN WORD 0 SICP D n-1 =W t PD1 t SICEF (2) EF tREF (3) t SICF EF+1 t RE R (1) 2753 drw 24 NOTES: 1. Parallel Read shown for reference only. Can also use serial output mode. 2. The Empty Flag is de-asserted after the N–1 rising edge of SICP of the first serial-in word. In the Serial-Out mode, a new read operation can begin tREFSO after EF goes HIGH. In the Parallel-Out mode, a new read operation can occur immedately after FF goes HIGH. 3. The EF+1 Flag is de-asserted after the N–1 rising edge of SICP of the second serial-in word. Figure 21. Empty Flag and Empty+1 Flag De-assertion in the Serial-ln Mode 0 1 SERIAL WORD A n-2 n-1 0 1 SERIAL WORD B n-2 n-1 LAST SERIAL WORD 1 n-2 0 n-1 0 1 SOCP tSOCF R=Q n-1 EF+1 t SOCEF t REFSO (2) EF t WEF (1) (3) W WORD A WORD THIRD B WORD 2753 drw 25 NOTES: 1. Parallel write shown for reference only. Can also use serial input mode. 2. The Empty Flag (EF) is asserted in Serial-Out mode by using the tSOCEF parameter. This parameter is measured in the worst case condition from the rising edge of the SOCP used to clock data bit 0. Whenever EF goes LOW, there is only one word to be shifted out. In the Parallel-ln mode, the EF flag is de-asserted by the rising edge of W. In the Serial-ln mode, the EF flag is de-asserted by the rising edge of W. 3. First Write rising edge after EF is set. 4. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH. Figure 22. Empty Flag and Empty+1 Flag Assertion in the Serial-Out Mode (FIFO Being Emptied) 5.37 16 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 0 NEXT TO LAST SERIAL WORD 1 n-2 COMMERCIAL TEMPERATURE RANGES n-1 LAST SERIAL WORD 1 n-2 0 n-1 0 1 SICP W=D n-1 t SICF FF-1 t SICFF t RFFSI (1) FF t RFF (2) R 2753 drw 26 NOTES: 1. The Full Flag is asserted in the Serial-ln mode by using the tSICFF parameter. This parameter is measured in the worst case condition from the rising edge of SICP following a (tPD1+tWFF) delay from the first SICP rising edge of the last word. 2. First Read rising edge after FF is set. 3. After FF goes LOW and the last bit of the final word has been clocked in, SICP should not be clocked until FF goes HIGH. Figure 23. Full Flag and Full-1 Flag Assertlon in the Serial-ln Mode (FIFO Being Filled) FIRST SERIAL-OUT WORD 0 1 n–1 SECOND SERIAL-OUT WORD 0 1 n–1 SOCP Q n+1 =R (1) t PD2 (2) FF tWFF t SOCFF t SOCF FF-1 t WF W 2753 drw 27 NOTES: 1. The FIFO is full and a new read sequence is started. 2. On the first rising edge of SOCP, the FF is de-asserted. In the Serial-ln mode, a new write operation can begin following tRFFS1 after FF, goes HIGH. In the Parallel-ln mode, a new write operation can occur immediately after FF goes HIGH. 3. The FF-1 flag is de-asserted after the first SOCP of the second serial word. Figure 24. Full Flag and Full-1 Flag De-assertion in the Serial-Out Mode 5.37 17 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES R HF HALF-FULL (1/2) HALF-FULL + 1 t RF HALF-FULL + 1 t SICF 0 1 n–1 0 SICP t SICF AEF ALMOST-FULL (7/8 Full) ALMOST-FULL + 1 (7/8 Full + 1) ALMOST-EMPTY – 1 (1/8 Full–1) ALMOST-EMPTY (1/8 Full) ALMOST-FULL + 1 (7/8 Full + 1) t RF AEF ALMOST-EMPTY (1/8 Full) 2753 drw 28 Figure 25. Half-Full, Almost-Full and Almost-Empty Timings for Serial-In Mode W HF HALF-FULL +1 HALF-FULL (1/2) tWF t SOCF HALF-FULL (1/2) 0 1 n–1 0 SOCP t SOCF AEF ALMOST-FULL (7/8 Full) ALMOST-FULL + 1 (7/8 Full+1) ALMOST-FULL (7/8 Full) ALMOST-EMPTY (1/8 Full) ALMOST-EMPTY – 1 (1/8 Full–1) tWF AEF ALMOST-EMPTY – 1 (1/8 Full–1) 2753 drw 29 Figure 26. Half-Full, Almost-Full and Almost-Empty Timings for Serial-Out Mode 5.37 18 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES enable and disable timings for OE are shown in Figure 12. OPERATING DESCRIPTION PARALLEL OPERATING MODES: Parallel Data Input By setting SI/PI HIGH, data is written into the FIFO in parallel through the D0-D8 input data lines. Parallel Data Output By setting SO/PO HIGH, the parallel-out mode is chosen. In the parallel-out mode, as shown in Figure 4, data is available tA after the falling edge of R and the output bus Q goes into high-impedance after R goes HIGH. Alternately, the user can access the FIFO by keeping R LOW and enabling data on the bus by asserting OE. When R is LOW, the OE is HIGH and the output bus is tri-stated. When R is HIGH, the output bus is disabled irrespective of OE. The Single Device Mode A single IDT172103/72104 may be used when application requirements are for 2048/4096 words or less. The IDT72103/ 72104 is in the Single Device Configuration when the Expansion In (Xl) control input is grounded (See Figure 27). In this mode, the HF/XO is used as a Half-Full flag. Wldth Expanslon Mode Word width may be increased simply by connecting the corresponding input control signals of multiple devices. Status flags can be detected from any one of the connected devices. Figure 28 demonstrates an 18-bit word width by using two IDT72103/72104s. Any word width can be attained by adding additional IDT72103/72104. HALF-FULL FLAG HF VCC (SI/PI) WRITE (W) DATAIN 9 (D) FULL FLAG VCC (SO/PO) (R) READ 9 IDT 72103/04 (Q) (EF) (FF) DATA OUT EMPTY FLAG (EF+1) EMPTY-PLUS-ONE FULL-MINUS-ONE (FF-1) ALMOST FULL (AEF) (AEF) RESET (RS) (RT) RETRANSMIT (OE) OUPUT ENABLE EXPANSION IN (XI) ALMOST EMPTY 2573 drw 30 Figure 27. Block Diagram of Single 2048 x 9/4096 x 9 FIFO in Parallel Mode 5.37 19 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES INPUT CONFIGURATION TABLE Serial Input Width Expansion Parallel Input HIGH Single Device LOW Least Significant Device LOW All Other Devices LOW Most Significant Device LOW Sl HIGH or LOW Input Data Input Data Input Data Input Data SICP HIGH or LOW Input Clock Input Clock Input Clock Input Clock HIGH HIGH HIGH D 8 of next least significant device D 8 of next least significant device Write Control Di Di of most significant device Di of most significant device Di of most significant device Input Data No connect except Di No connect except D8 No connect except D8 No connect except Di — W — — W of all devices — — SIX of next most significant device SIX of next most significant device Pin SI /PI SIX W D0 -D 8 Di(1) D8 — NOTE: 2753 tbl 11 1. Di refers to the rnost significant bit of the serial word. If multiple devices are width cascaded, Di is the rnost significant bit from the most significant device. OUTPUT CONFIGURATION TABLE Serial Output Width Expansion Pin SO/PO SO Parallel Output Single Device Least Significant Device All Other Devices Most Significant Device HIGH LOW LOW LOW LOW — Output Data Output Data Output Data Output Data HIGH or LOW Output Clock Output Clock Output Clock Output Clock HIGH HIGH HIGH Q 8 of next least significant device Q 8 of next least significant device R Read Control Qi Qi of most significant device Qi of most significant device Qi of most significant device Q0 -Q8 Output Data No connect except Di No connect except Q 8 No connect except Q 8 No connect except Qi — — R of all devices SOX of next most significant device SOX of next most significant device SOCP SOX Qi(1) Q8 — R — — — NOTE: 2753 tb l 12 1. Qi refers to the most significant bit of the serial word. If multiple devices are width cascaded, Qi is the rnost significant bit from the most significant device. 5.37 20 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 18 DATAIN COMMERCIAL TEMPERATURE RANGES HF HF 9 9 (SO/PO) (D) (SO/PO) WRITE (W) FULL FLAG (FF) RESET (RS) (R) IDT 72103/04 IDT 72103/04 9 VCC (SI/PI) VCC OUTPUT (OE) ENABLE READ (EF) EMPTY FLAG (RT) RETRANSMIT 9 (SI/PI) (XI) (XI) (Q) DATAOUT 18 2753 drw 31 NOTE: 1. Flag detection is accomplished by monitoring all the flag signals of either (any) device used in the width expansion configuration. Do not connect any flag signals together. Figure 28. Block Diagram of 2048 x 18/4096 x 18 FIFO Memory Used in Width Expansion in Parallel Mode TRUTH TABLES TABLE 2: RESET AND RETRANSMIT — SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION IN PARALLEL MODE Inputs(2) Internal Status(1) RS FL XI Read Pointer Reset 0 X 0 Retransmit 1 0 0 Mode Read/Write 1 1 0 NOTES: 1. Pointer will increment if appropriate flag is HIGH. 2. RS = Reset Input, FL/RT = First Load/Retransmit, Outputs Write Pointer AEF , EF FF HF Location Zero Location Zero 0 1 1 Location Zero Unchanged X X X (1) X X (1) Increment Increment X 2753 tbl 13 EF = Empty Flag Output, FF = Full Flag Output, 5.37 XI = Expansion Input. 21 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES DEPTH EXPANSION (DAISY CHAIN) MODE The IDT72103/4 can be easily adapted to applications where the requirements are for greater than 2048/4096 words. Figure 29 demonstrates Depth Expansion using three IDT72103/4s. Any memory depth can be attained by adding additional IDT72103/4s. The IDT72103/4 operates in the Depth Expansion configuration when the following conditions are met: 1. The first device must be designated by grounding the First Load (FL) control input pin. 2. All other devices must have the FL pin in the high state. 3. The Expansion Out (XO) pin of each device must be tied to the Expansion In (Xl) pin of the next device. See Figure 29. 4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag (EF). This requires the OR-ing of all EFs and OR-ing of all FFs (i.e., all must be set to generate the correct composite FF or EF). See Figure 29. 5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth Expansion mode. XO W R 9 FF 9 D EF 9 IDT 72103/04 Q FL Vcc XI XO FF 9 FULL EF IDT 72103/04 EMPTY FL XI XO FF 9 EF IDT 72103/04 FL RS XI 2753 drw 32 NOTE: 1. SI/PI and SO/PO pins are tied to VCC. Figure 29. Block Diagram of 6,144 x 9/12,288 x 9-FIFO Memory, Depth Expansion in Parallel Mode 5.37 22 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES BIDIRECTIONAL MODE Applications requiring data buffering between two systems (each system capable of Read and Write operations) can be achieved by pairing IDT72103/4 as shown in Figure 30. Both Depth Expansion and Width Expansion may be used in this mode. WA FF A IDT 72103/04 D A 0–8 RB EF B HF B OE Q B 0–8 SYSTEM A SYSTEM B Q A 0–8 OE RA HF A EF A D B 0–8 IDT 72103/04 WB FF B 2573 drw 33 NOTE: 1. SI/PI and SO/PO pins are tied to VCC. Figure 30. Bidirectional FIFO Mode COMPOUND EXPANSION MODE The two expansion techniques described above can be applied together in a straightforward manner to achieve large FIFO arrays (see Figure 31). Q 0–Q 8 Q 0 –Q 8 R, W, RS IDT72103/72104 DEPTH EXPANSION BLOCK Q N–8 –Q N Q 9 –Q 17 Q N–8 –Q N IDT72103/72104 DEPTH EXPANSION BLOCK D 0 –D 8 D 0 –D N Q 9–Q 17 IDT72103/72104 DEPTH EXPANSION BLOCK D 9 –D 17 D 9 –D N D 18 –D N D N–8 –D N D N–8 –D N 2753 drw 34 NOTE: 1. SI/PI and SO/PO pins are tied to VCC. 2. For depth expansion block see DEPTH EXPANSION Section and Figure 29. 3. For Flag Detection see WIDTH EXPANSION SECTION and Figure 28. Figure 31. Compound FIFO Expansion 5.37 23 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES TABLE 3: RESET AND FIRST LOAD TRUTH TABLE — DEPTH EXPANSION/COMPOUND EXPANSION MODE Inputs (2) Internal Status RS FL XI Read Pointer Reset-First Device 0 0 (1) Retransmit all Other Devices 0 1 Read/Write 1 X Mode NOTES: 1. XI is connected to 2. RS = Reset Input, Outputs Write Pointer EF FF Location Zero Location Zero 0 1 (1) Location Zero Location Zero 0 1 (1) X X X X XO of previous device. FL/RT = First Load/Retransmit, EF = Empty Flag Ouput, SERIAL OPERATING MODES: Serial Data Input The Serial Input mode is selected by grounding the Sl/PI line. The D0-8 lines are then outputs which are used to program the width of the serial word. They are taps off a digital delay line which are meant for connection to the W input. For instance, connecting D6 to W will program a serial word width of 7 bits, connecting D7 to W will program a serial word width of 8 bits and so on. By programming the serial word width, an economy of clock cycles is achieved. As an example, if the word width is 6 bits, then on every 6th clock cycle the serial data register is written in parallel into the FIFO RAM array. Thus, the possible clock cycles for an extra 3 bits of width in the RAM array are not required. The SIX signal is used for Serial-ln Expansion. When the serial word width is 9 or less, the SIX input must be tied HIGH. When more than 9 bits of serial word width is required, more than one device is required. The SIX input of the least significant device must be tied HIGH. The D8 pin of the least significant device must be tied to SIX of the next significant device. In other words, the SIX input of the most significant and intermediate devices must always be connected to the D8 of the next least significant device. Figure 32 shows the relationship of the SIX, SICP and D08 lines. In the stand alone case (Figure 32), on the first LOWto-HlGH of SICP, the D1-8 lines go LOW and the D0 line remains HIGH. On the next SICP clock edge, the D1 goes HIGH, then D2 and so on. This continues until the D line, which is connected to W, goes HIGH. On the next clock cycle, after W is HIGH, all of the D lines go LOW again and a new serial word input starts. 2753 tbl 14 FF = Full Flag Output, XI = Expansion Input. In the cascaded case, the first LOW-to-HlGH SICP clock edge for a serial word will cause all timed outputs (D) to go LOW except for D0 of the least significant device. The D outputs of the least significant device will go high on consecutive clock cycles until D8. When D8 goes HlGH, the SlX of the next device goes HlGH. On the next cycle after the SIX input is brought HIGH, the D0 goes HIGH; then on the next cycle D1 and so on. A Di output from the most significant device is issued to create the W for all cascaded devices. The minimum serial word width is 4 bits and the maximum is virtually unlimited. When in the Serial mode, the Least Significant Bit of a serial stream is shifted in first. If the FIFO output is in the Parallel mode, the first serial bit will come out on Q0. The second bit shifted in is on Q1 and so on. In the Serial Cascade mode, the serial input (Sl) pins must be connected together. Each of the devices then receives serial information together and uses the SIX and D0-8 lines to determine whether to store it or not. The example shown in Figure 34 shows the interconnections for a serializing FIFO that transfers data to the internal RAM in 16-bit quantities (i.e. every 16 SlCP cycles). This corresponds to incrementing the write pointer every 16 SICP cycles. Once W goes HIGH With the last serial bit in, SICP should not be clocked again until FF goes HIGH. 5.37 24 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES SINGLE DEVICE SERIAL INPUT CONFIGURATION SICP SERIAL-IN CLOCK V CC 1 2 3 V CC SI/PI SO/PO SI SERIAL-IN DATA 0 GND IDT72103/4 Q 0-7 8 SIX W D0 D1 D2 D3 D4 D5 D6 D7 D8 4 5 6 7 0 1 2 3 4 5 6 7 0 SICP D 0 =1 D1 D2 D3 D4 D5 D6 D7 W 2753 drw 35 Figure 32. Serial-In Mode Where 8-Bit Parallel Output Data is Read SERIAL DATA IN SERIAL-INPUT CLOCK DATA IN/TIMED OUTPUTS D0-8 RGTR 9 9 MUX W DELAYED TIMING GENERATOR SI/PI DATA IN TO FIFO RAM Figure 33. Serial-Input Circuitry 5.37 25 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES SERIAL INPUT WIDTH EXPANSION SERIAL-IN DATA SERIAL-IN CLOCK V CC GND V CC SI/PI SO/PO SI GND V CC SI/PI SO/PO SI SICP SIX Q 0-8 IDT72103/104 FIFO #1 SICP IDT72103/104 FIFO #2 SIX D8 W W D 6 Q 0-6 7 9 9 16-BIT PARALLEL OUTPUT 0 1 7 8 9 10 14 15 0 SICP D 8 OF FIFO #1 AND SIX OF FIFO #2 D 6 OF FIFO #2 AND W OF FIFO #1 AND FIFO #2 2753 drw 37 Figure 34. Serial-In Configuration for Serial-In to Parallel-Out Data of 16 bits SERIAL INPUT WITH DEPTH EXPANSION Q 0-7 VCC GND VCC SI/PI SO/PO SIX IDT72104 FL/RT SOX SI SICP XO XI Q 0-7 R D7 R W VCC SICP GND VCC VCC XI XO SI/PI SO/PO SIX IDT72104 FL/RT SOX SI SICP Q 0-7 R D7 W VCC 2753 drw 38 SI NOTE: 1. All SI/PI pins are tied to GND and SO/PO pins are tied to VCC. OE is tied LOW. For FF and EF connections see Figure 29. Figure 35. An 8K x 8 Serial-In, Parallel-Out FIFO 5.37 26 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES SERIAL INPUT WITH WIDTH AND DEPTH EXPANSION SERIAL DATA IN VCC SI SIX SICP D8 IDT72104 SI SIX SIX SI SICP IDT72104 W SICP IDT72104 R Q 0-8 D8 W Q 0-8 XI XO D5 R W R Q 0-5 XI XO XI XO VCC SERIAL INPUT CLOCK SIX SI D 8 XO XI SIX SI D 8 XO XI W SICP IDT72104 SIX SI D 5 XO XI W SICP R IDT72104 W SICP R IDT72104 Q 0-8 Q 0-8 Q 0-5 P 0-8 P 9-17 P 18-23 R READ 2753 drw 39 PARALLEL DATA OUT NOTE: 1. All SI/PI pins are tied to GND. SO/PO pins are tied to VCC. For FL/RT, FF and EF connections see Figure 29. Figure 36. An 8K x 24 Serial-In, Parallel-Out FIFO Using Six IDT72104s SERIAL DATA OUTPUT The Serial Output mode is selected by setting the SO/PO line LOW. When in the Serial-Out mode, one of the Q1-8 lines should be used to control the R signal. In the Serial-Out mode, the Q0-8 are taps off a digital delay line. By selecting one of these taps and connecting it to R, the width of the serial word to be read and shifted is programmed. For instance, if the Q5 line is connected to the R input, on every sixth clock cycle a new word is read from the FIFO RAM array and begins to be shifted out. The serial word is shifted out Least Significant Bit first. If the input mode of the FIFO is parallel, the information that was written into the D0 bit will come out as the first bit of the serial word. The second bit of the serial stream will be the D1 bit and so on. In the stand alone case, the SOX line is tied HIGH and not used. On the first LOW-to-HIGH of the SOCP clock, all of the Q outputs except for Q0 go LOW and a new serial word is started. On the next clock cycle, Q1 will go HIGH, Q2 on the next clock cycle and so on, as shown in Figure 37. This continues until the Q line, which is connected to R, goes HIGH at which point all of the Q lines go LOW on the next clock and a new word is started. In the cascaded case, word width of more than 9 bits can be achieved by using more than one device. By tying the SOX line of the least significant device HIGH and the SOX of the subsequent devices to Q8 of the previous device, a cascaded serial word is achieved. On the first LOW-to-HIGH clock edge of SOCP, all the Q lines go low except for Q0. Just as in the stand alone case, on each consecutive clock cycle, each Q line goes HIGH in the order of least to most significant. When Q8 (which is connected to the SOX input of the next device) goes HIGH, the D0 of that device goes HIGH, thus cascading from one device to the next. The Q line of the most significant device, which programs the serial word width, is connected to all R inputs. The Serial Data Output (SO) of each device in the serial word must be tied together. Since the SO pin is tri-stated, only the device which is currently shifting out is enabled and driving the 1-bit bus. Figure 39 shows an example of the interconnections for a 16-bit serialized FIFO. Once R goes HIGH with the last serial bit out, SOCP should not be clocked again until EF goes HIGH. 5.37 27 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES V CC SOCP SI/PI SERIAL-OUT CLOCK IDT72103/4 OE SOX R Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 V CC 1 2 3 D 0-7 SO/PO SO SERIAL-OUT DATA 0 GND PARALLEL DATA IN 4 5 6 7 0 1 2 GND 3 4 5 6 7 0 SOCP Q 0 =1 Q1 Q2 Q3 Q4 Q5 Q6 Q7 R 2753 drw 40 NOTE: 1. Input data is loaded in 8-bit quantities and read out serially. Figure 37. Serial-Out Configuration 5.37 28 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES OUTPUT FROM RAM ARRAY SOCP-SERIAL OUTPUT CLOCK SO/PO 9 DELAYED TIMING GENERATOR R SO/PO CONTROL CIRCUIT SERIALOUTPUT DATA (SO) SERIAL-OUT REGISTER MUX 9 PARALLEL-OUT DATA/ TIMED OUTPUT Q 0-8 2753 drw 41 Figure 38. Serial-Output Circuitry PARALLEL DATA IN 16-BITS WIDE 9 V CC D 0-8 SO SERIAL-OUTPUT CLOCK V CC GND SI/PI SERIAL-OUT DATA SO/PO D 0-6 SO FIFO #1 SOCP GND SI/PI SO/PO SOX Q8 R 1 V CC FIFO #2 SOCP SOX 0 7 7 R 8 9 10 14 Q6 15 0 SOCP Q 8OF FIFO #1 AND SOX OF FIFO #2 Q 6 OF FIFO #2 AND R OF FIFO #1 AND FIFO #2 2753 drw 42 NOTE: 1. The parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2. Figure 39. Serial-Output for 16-Bit Parallel Data In 5.37 29 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9 COMMERCIAL TEMPERATURE RANGES D 0-7 SERIAL OUTPUT WITH DEPTH EXPANSION D 0-7 W IDT72104 FL/RT W R SOX SO SOCP XO XI Q7 XI XO D 0-7 VCC SOCP VCC W IDT72104 FL/RT SOX SOCP SO Q7 R VCC 2753 drw 43 SO NOTE: 1. All SI/PI pins are tied to VCC and SO/PO pins are tied to GND. OE is tied LOW. For FF and EF connections see Figure 17. Figure 40. An 8K x 8 Parallel-In Serial-Out FIFO SERIAL IN AND SERIAL OUT WITH WIDTH AND DEPTH EXPANSION SICP SI V CC V CC SIX SI SICP D8 FL/RT W IDT72104 FF R EF SOX SO SOCP XO XI Q 8 SIX FL/RT SI SICP D6 W IDT72104 R SOX SO SOCP XO XI Q 6 FULL FLAG EMPTY FLAG V CC V CC V CC SIX SI SICP XI XO D 8 W IDT72104 R FL/RT FF EF SOX SO SOCP V CC Q8 SIX SI SICP XI XO D 6 FL/RT W IDT72104 R SOX SO SOCP Q6 SOCP SO 2753 drw 44 NOTE: 1. All RS pins are connected together. All OE pins are connected LOW. All SI/PI and SO/PO pins are grounded. Figure 41. 128K x 1 Serial-In Serial-Out FIFO 5.37 30 IDT72103, IDT72104 CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT XXXXX Device Type X Power XXX Speed X Package X Process/ Temperature Range 5.37 Blank Commercial (0°C to +70°C) J 40-pin Plastic Leaded Chip Carrier 35 50 Commerical (50MHz serial shift rate) Commercial (40MHz serial shift rate) L Low Power 72103 72104 2048 x 9-Bit Configurable Parallel-Serial FIFO 4096 x 9-Bit Configurable Parallel-Serial FIFO 2753 drw 45 31