Six LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK946 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.3 V power supply APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM ADCLK946 LVPECL Q0 Q0 VREF REFERENCE Q1 Q1 VT Q2 CLK Q2 CLK Q3 Q3 Q4 Q4 Q5 Q5 08053-001 FEATURES Figure 1. The ADCLK946 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs. The ADCLK946 features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V. The ADCLK946 is available in a 24-lead LFCSP and is specified for operation over the standard industrial temperature range of −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009-2010 Analog Devices, Inc. All rights reserved. ADCLK946 TABLE OF CONTENTS Features .............................................................................................. 1 Thermal Performance ...................................................................5 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Functional Description .....................................................................9 Revision History ............................................................................... 2 Clock Inputs ...................................................................................9 Specifications..................................................................................... 3 Clock Outputs ................................................................................9 Electrical Characteristics ............................................................. 3 PCB Layout Considerations ...................................................... 10 Absolute Maximum Ratings............................................................ 5 Input Termination Options ....................................................... 11 Determining Junction Temperature .......................................... 5 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 12 REVISION HISTORY 5/10—Rev. 0 to Rev. A Changes to Table 1, DC Output Characteristics........................... 3 4/09—Revision 0: Initial Version Rev. A | Page 2 of 12 ADCLK946 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (typ) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs Parameter DC INPUT CHARACTERISTICS Input Voltage High Level Input Voltage Low Level Input Differential Range Input Capacitance Input Resistance Single-Ended Mode Differential Mode Common Mode Input Bias Current Hysteresis DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage, Single-Ended Reference Voltage Output Voltage Output Resistance Symbol Min VIH VIL VID CIN VEE + 1.6 VEE 0.4 VOH VOL VO VREF Typ Max Unit VCC VCC − 0.2 3.4 0.4 V V V p-p pF 50 100 50 20 10 Ω Ω kΩ µA mV Open VT V V mV 50 Ω to (VCC − 2.0 V) 50 Ω to (VCC − 2.0 V) VOH − VOL, output static V Ω −500 µA to +500 µA VCC − 1.26 VCC − 1.99 610 VCC − 0.76 VCC − 1.54 960 (VCC + 1)/2 235 Test Conditions/Comments ±1.7 V between input pins Table 2. Timing Characteristics Parameter AC PERFORMANCE Maximum Output Frequency Symbol Output Rise/Fall Time Propagation Delay Temperature Coefficient Output-to-Output Skew Part-to-Part Skew 1 Additive Time Jitter Integrated Random Jitter Broadband Random Jitter 2 Crosstalk-Induced Jitter 3 CLOCK OUTPUT PHASE NOISE Absolute Phase Noise fIN = 1 GHz tR, tF tPD Min Typ 4.5 4.8 40 150 75 185 50 9 Max Unit Test Conditions/Comments GHz See Figure 4 for differential output voltage vs. frequency, >0.8 V differential output swing ps ps fs/°C ps ps 20% to 80% measured differentially VICM = 2 V, VID = 1.6 V p-p 28 75 90 fs rms fs rms fs rms BW = 12 kHz − 20 MHz, CLK = 1 GHz VID = 1.6 V p-p, 8 V/ns, VICM = 2 V −119 −134 −145 −150 −150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 90 220 28 45 VID = 1.6 V p-p Input slew rate > 1 V/ns (see Figure 11 for more details) @ 100 Hz offset @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset >1 MHz offset The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. 3 The amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs. 1 2 Rev. A | Page 3 of 12 ADCLK946 Table 3. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 2 Symbol Min VCC − VEE 2.97 IVEE IVCC PSRVCC PSRVCC Typ 90 245 <3 28 Change in tPD per change in VCC. Change in output swing per change in VCC. Rev. A | Page 4 of 12 Max Unit Test Conditions/Comments 3.63 V 115 275 mA mA ps/V dB 3.3 V + 10% Static VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% ADCLK946 ABSOLUTE MAXIMUM RATINGS DETERMINING JUNCTION TEMPERATURE Table 4. Parameter Supply Voltage VCC − VEE Input Voltage CLK, CLK CLK, CLK to VT Pin (CML, LVPECL Termination) CLK to CLK Input Termination, VT to CLK, CLK Maximum Voltage on Output Pins Maximum Output Current Voltage Reference (VREF) Operating Temperature Range Ambient Junction Storage Temperature Range To determine the junction temperature on the application printed circuit board (PCB), use the following equation: Rating 6.0 V TJ = TCASE + (ΨJT × PD) where: TJ is the junction temperature (°C). TCASE is the case temperature (°C) measured by the customer at the top center of the package. ΨJT is as indicated in Table 5. PD is the power dissipation. VEE − 0.5 V to VCC + 0.5 V ±40 mA ±1.8 V ±2 V VCC + 0.5 V 35 mA VCC to VEE Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation TJ = TA + (θJA × PD) −40°C to +85°C 150°C −65°C to +150°C where TA is the ambient temperature (°C). Values of θJB are provided in Table 5 for package comparison and PCB design considerations. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION THERMAL PERFORMANCE Table 5. Parameter Junction-to-Ambient Thermal Resistance Still Air 0.0 m/sec Airflow Moving Air 1.0 m/sec Airflow 2.5 m/sec Airflow Junction-to-Board Thermal Resistance Moving Air 1.0 m/sec Airflow Junction-to-Case Thermal Resistance (Die-to-Heat Sink) Moving Air Junction-to-Top-of-Package Characterization Parameter Still Air 0 m/sec Airflow Symbol Description Value 1 Unit θJA Per JEDEC JESD51-2 54.3 °C/W θJMA θJMA Per JEDEC JESD51-6 Per JEDEC JESD51-6 47.5 42.6 °C/W °C/W θJB Per JEDEC JESD51-8 (moving air) 33.0 °C/W θJC Per MIL-Std. 883, Method 1012.1 2.0 °C/W ΨJT Per JEDEC JESD51-2 0.9 °C/W Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. 1 Rev. A | Page 5 of 12 ADCLK946 24 23 22 21 20 19 VCC Q0 Q0 Q1 Q1 VEE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 PIN 1 INDICATOR ADCLK946 TOP VIEW (Not to Scale) 18 17 16 15 14 13 VCC Q2 Q2 Q3 Q3 VCC NOTES: 1. EXPOSED PADDLE MUST BE CONNECTED TO VEE. 08053-002 VEE Q5 Q5 Q4 Q4 VEE 7 8 9 10 11 12 VEE CLK CLK VREF VT VEE Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 6, 7, 12, 19 2 3 4 5 8, 9 10, 11 13, 18, 24 14, 15 16, 17 20, 21 22, 23 Mnemonic VEE CLK CLK VREF VT Q5, Q5 Q4, Q4 VCC Q3, Q3 Q2, Q2 Q1, Q1 Q0, Q0 EPAD Description Negative Supply Pin. Differential Input (Positive). Differential Input (Negative). Reference Voltage. This pin provides the reference voltage for biasing ac-coupled CLK and CLK inputs. Center Tap. This pin provides the center tap of a 100 Ω input resistor for CLK and CLK inputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Positive Supply Pin. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. EPAD must be soldered to VEE. Rev. A | Page 6 of 12 ADCLK946 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, VEE = 0.0 V, VICM = VREF, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted. C4 C3 C4 C3 C4 500ps/DIV 100mV/DIV Figure 3. LVPECL Output Waveform @ 200 MHz 08053-006 C3 08053-003 100mV/DIV 100ps/DIV Figure 6. LVPECL Output Waveform @ 1000 MHz 1.8 189 1.6 188 1.5 PROPAGATION DELAY (ps) DIFFERENTIAL OUTPUT VOLTAGE (V) 1.7 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 187 186 185 184 183 0 1000 2000 3000 4000 5000 FREQUENCY (MHz) 182 –40 08053-004 0.4 –20 0 20 40 60 08053-007 0.5 80 TEMPERATURE (°C) Figure 4. Differential Output Swing vs. Frequency Figure 7. Propagation Delay vs. Temperature 205 205 PROPAGATION DELAY (ps) 195 190 185 180 175 170 195 +85°C 185 +25°C 175 –40°C 160 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 DIFFERENTIAL INPUT VOLTAGE SWING (V) Figure 5. Propagation Delay vs. Differential Input Voltage 165 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 DC COMMON-MODE VOLTAGE (V) 2.7 2.9 3.1 08053-008 165 08053-005 PROPAGATION DELAY (ps) 200 Figure 8. Propagation Delay vs. Common-Mode Voltage vs. Temperature, Input Slew Rate > 25 V/ns Rev. A | Page 7 of 12 ADCLK946 –90 –100 1.54 1.52 +25°C 1.50 +85°C 1.48 1.46 –110 –120 –130 –150 1.44 –160 1.42 2.75 –170 10 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 Figure 9. Differential Output Swing vs. Power Supply Voltage vs. Temperature, VID = 1.6 V p-p CLOCK SOURCE 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 11. Absolute Phase Noise Measured @1 GHz with Agilent E5052 300 300 IVCC 250 RANDOM JITTER (fS rms) 250 200 +85°C +25°C –40°C 150 100 IVEE 200 150 100 50 0 2.97 3.30 POWER SUPPLY (V) 3.63 08053-010 50 Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature, All Outputs Loaded (50 Ω to VCC − 2 V) Rev. A | Page 8 of 12 0 0 5 10 15 20 INPUT SLEW RATE (V/ns) Figure 12. RMS Jitter vs. Input Slew Rate, VID Method 25 08053-012 2.85 POWER SUPPLY (V) CURRENT (mA) ADCLK946 –140 08053-011 PHASE NOISE (dBc/Hz) –40°C 08053-009 DIFFERENTIAL OUTPUT VOLTAGE SWING (V) 1.56 ADCLK946 FUNCTIONAL DESCRIPTION The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs (see Figure 1). Maintain the differential input voltage swing from approximately 400 mV p-p to no more than 3.4 V p-p. See Figure 14 through Figure 17 for various clock input termination schemes. Output jitter performance is degraded by an input slew rate below 1 V/ns, as shown in Figure 12. The ADCLK946 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. VS_DRV VS = VS_DRV Z0 = 50Ω 50Ω VCC – 2V LVPECL 50Ω Z0 = 50Ω Figure 14. DC-Coupled, 3.3 V LVPECL CLOCK OUTPUTS The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK946 are designed to directly drive 800 mV into a 50 Ω cable or into microstrip/stripline transmission lines terminated with 50 Ω referenced to VCC − 2 V, as shown in Figure 14. The LVPECL output stage is shown in Figure 13. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse-width-dependent, propagation delay dispersion. ADCLK946 08053-014 The ADCLK946 accepts a differential clock input and distributes it to all six LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK946 should equal VCC of the receiving buffer. Although the resistor combination shown in Figure 15 results in a dc bias point of VS_DRV − 2 V, the actual common-mode voltage is VS_DRV − 1.3 V because there is additional current flowing from the ADCLK946 LVPECL driver through the pull-down resistor. VS_DRV VS_DRV ADCLK946 50Ω VCC 127Ω 127Ω SINGLE-ENDED (NOT COUPLED) LVPECL 50Ω 83Ω 83Ω 08053-015 CLOCK INPUTS Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination VS_DRV ADCLK946 VS = VS_DRV Z0 = 50Ω VCC 50Ω 50Ω LVPECL 08053-016 50Ω Z0 = 50Ω Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination Q VS_DRV ADCLK946 VCC 0.1nF Q 200Ω Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage LVPECL 200Ω Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line Figure 14 through Figure 17 depict various LVPECL output termination schemes. When dc-coupled, VCC of the receiving buffer should match the VS_DRV. Rev. A | Page 9 of 12 08053-017 VEE 08053-013 100Ω DIFFERENTIAL 100Ω (COUPLED) 0.1nF TRANSMISSION LINE ADCLK946 PCB LAYOUT CONSIDERATIONS The ADCLK946 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. The following references to the ground plane assume that the VEE power plane is grounded for LVPECL operation. Note that, for ECL operation, the VCC power plane becomes the ground plane. ensure that the pins are within the rated input differential and common-mode ranges. If the return is floated, the device exhibits a 100 Ω crosstermination, but the source must then control the commonmode voltage and supply the input bias currents. There are ESD/clamp diodes between the input pins to prevent the application from developing excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is required, it is recommended that appropriate external diodes be used. Exposed Metal Paddle When properly mounted, the ADCLK946 also dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK946. The PCB attachment must provide a good thermal path to a larger heat dissipation area. This requires a grid of vias from the top layer down to the VEE power plane (see Figure 18). The ADCLK946 evaluation board (ADCLK946/PCBZ) provides an example of how to attach the part to the PCB. In a 50 Ω environment, input and output matching have a significant impact on performance. The buffer provides internal 50 Ω termination resistors for both CLK and CLK inputs. Normally, the return side is connected to the reference pin that is provided. Carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If the inputs are dc-coupled to a source, take care to VIAS TO VEE POWER PLANE 08053-018 It is also important to adequately bypass the input and output supplies. Place a 1 µF electrolytic bypass capacitor within several inches of each VCC power supply pin to the ground plane. In addition, place multiple high quality 0.001 µF bypass capacitors as close as possible to each of the VCC supply pins, and connect the capacitors to the ground plane with redundant vias. Carefully select high frequency bypass capacitors for minimum inductance and ESR. To improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. Also, avoid discontinuities along input and output transmission lines that can affect jitter performance. The exposed metal paddle on the ADCLK946 package is both an electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the VEE pin. Figure 18. PCB Land for Attaching Exposed Paddle Rev. A | Page 10 of 12 ADCLK946 INPUT TERMINATION OPTIONS VCC VREF VREF VT VT 50Ω CLK 50Ω CLK 50Ω CLK 50Ω CONNECT VT TO VCC. CONNECT VT TO VREF . Figure 19. Interfacing to CML Inputs 08053-021 08053-019 CLK Figure 21. AC-Coupling Differential Signals Inputs, Such as LVDS VREF VT 50Ω CLK VREF VT 50Ω CLK VCC – 2V 50Ω CLK 50Ω 08053-020 CONNECT VT TO VCC − 2V. CONNECT VT, VREF , AND CLK. PLACE A BYPASS CAPACITOR FROM VT TO GROUND. ALTERNATIVELY, VT, VREF , AND CLK CAN BE CONNECTED, GIVING A CLEANER LAYOUT AND A 180° PHASE SHIFT. Figure 20. Interfacing to PECL Inputs 08053-022 CLK Figure 22. Interfacing to AC-Coupled Single-Ended Inputs Rev. A | Page 11 of 12 ADCLK946 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP SEATING PLANE 19 18 *2.45 EXPOSED PAD 2.30 SQ 2.15 (BOTTOMVIEW) 13 12 7 6 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 PIN 1 INDICATOR 24 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION 080808-A PIN 1 INDICATOR 0.60 MAX Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad CP-24-2 Dimensions shown in millimeters ORDERING GUIDE Model 1 ADCLK946BCPZ ADCLK946BCPZ-REEL7 ADCLK946/PCBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Evaluation Board Z = RoHS Compliant Part. ©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08053-0-5/10(A) Rev. A | Page 12 of 12 Package Option CP-24-2 CP-24-2