Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer ADCLK914 FEATURES 7.5 GHz operating frequency 160 ps propagation delay 100 ps output rise/fall 110 fs random jitter On-chip input terminations Extended industrial temperature range: −40°C to +125°C 3.3 V power supply (VCC − VEE) FUNCTIONAL BLOCK DIAGRAM VCC VREF ADCLK914 VT 50Ω 50Ω 50Ω 50Ω Q D Q D Clock and data signal restoration High speed converter clocking Broadband communications Cellular infrastructure High speed line receivers ATE and high performance instrumentation Level shifting Threshold detection VEE 06561-001 APPLICATIONS Figure 1. GENERAL DESCRIPTION The ADCLK914 is an ultrafast clock/data buffer fabricated on the Analog Devices, Inc., proprietary, complementary bipolar (XFCB-3) silicon-germanium (SiGe) process. The ADCLK914 features high voltage differential signaling (HVDS) outputs suitable for driving the latest Analog Devices high speed digitalto-analog converters (DACs). The ADCLK914 has a single, differential open-collector output. The input has a center tapped, 100 Ω, on-chip termination resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS (ac-coupled only). A VREF pin is available for biasing ac-coupled inputs. The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps propagation delay and adds only 110 fs random jitter (RJ). The ADCLK914 is available in a 16-lead LFCSP. It is specified for operation over the extended industrial temperature range of −40°C to +125°C. The HVDS output stage is designed to directly drive 1.9 V each side into 50 Ω terminated to VCC for a total differential output swing of 3.8 V. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADCLK914 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Applications Information .................................................................9 Functional Block Diagram .............................................................. 1 Power/Ground Layout and Bypassing ........................................9 General Description ......................................................................... 1 HVDS Output Stage ......................................................................9 Revision History ............................................................................... 2 Interfacing to High Speed DACs .................................................9 Specifications..................................................................................... 3 Optimizing High Speed Performance ........................................9 Electrical Characteristics ............................................................. 3 Random Jitter .................................................................................9 Absolute Maximum Ratings............................................................ 5 Typical Application Circuits ..................................................... 10 Thermal Resistance ...................................................................... 5 Outline Dimensions ....................................................................... 11 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 11 Pin Configuration and Function Descriptions ............................. 6 REVISION HISTORY 10/08—Rev. 0 to Rev. A Changes to Input Low Voltage Parameter, Table 1 ....................... 3 Changes to Output High Voltage Parameter, Table 1 ................ 3 Changes to Output Low Voltage Parameter, Table 1 .................. 3 Output Differential Range Parameter, Table 1 ............................ 3 Changes to Absolute Maximum Ratings Section ........................ 5 7/08—Revision 0: Initial Version Rev. A | Page 2 of 12 ADCLK914 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VCC = 3.3 V, VEE = 0 V, TA = −40°C to +125°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input Differential Range Input Capacitance Input Resistance Differential Mode Common Mode Input Bias Current DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage Output Differential Range Reference Voltage Output Voltage Output Resistance AC PERFORMANCE Operating Frequency Propagation Delay Propagation Delay Temperature Coefficient Propagation Delay Skew (Device to Device) Output Rise Time Output Fall Time Wideband Random Jitter 1 Additive Phase Noise 622.08 MHz 245.76 MHz Symbol Min VIH VIL VID Max Unit VEE + 1.65 VEE 0.2 VCC VCC − 0.2 3.4 V V V p-p 0.2 2.8 V p-p CIN VOH VOL VOD VREF tPD Typ 0.4 50 100 50 20 VCC − 0.55 VCC − 2.75 1.54 127 VCC − 0.40 VCC − 2.35 1.95 pF Ω Ω kΩ μA VCC − 0.25 VCC − 1.9 2.22 TA = −40°C to +85°C (±1.7 V between input pins) TA = 85°C to 125°C (±1.4 V between input pins) Open termination V V V (VCC + 1)/2 250 V Ω −500 μA to +500 μA 7.5 GHz >1.1 V differential output swing, VCC = 3.3 V ± 10% VCC = 3.3 V ± 10%,VICM = VREF, VID = 1.6 V p-p 158 202 140 tR tF RJ Test Conditions/Comments 100 80 110 −132 −143 −151 −156 −157 −156 −133 −143 −153 −158 −159 −158 Rev. A | Page 3 of 12 ps fs/°C 65 ps VID = 1.6 V p-p 125 95 ps ps fs rms 20%/80% 80%/20% VID = 1.6 V p-p, 6 V/ns, VICM = 1.85 V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz @10 Hz offset @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset @10 Hz offset @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset ADCLK914 Parameter 122.88 MHz POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 2 Output Swing Supply Rejection 3 Symbol Min VCC 2.97 IVEE IVCC PSRVCC 66 34 Typ −150 −156 −160 −161 −161 −160 111 55 13 −15 1 Calculated from SNR of ADC method. See Figure 8 for rms jitter vs. input slew rate. Change in tPD per change in VCC. 3 Change in output swing per change in VCC. 2 Rev. A | Page 4 of 12 Max Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 3.63 V 150 73 mA mA ps/V dB Test Conditions/Comments @10 Hz offset @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset Includes output current VCC = 3.3 V ± 10% VCC = 3.3 V ± 10% ADCLK914 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage (VCC to GND) Input Voltage Maximum Output Voltage Minimum Output Voltage Input Termination Voltage Reference Operating Temperature Range, Ambient Operating Temperature, Junction Storage Temperature Range Rating 6.0 V −0.5 V to VCC + 0.5 V VCC + 0.5 V VEE − 0.5 V ±2 V VCC − VEE −40°C to +125°C 150°C −65°C to +150°C Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation TJ = TA + (θJA × PD) where TA is the ambient temperature (°C). Values of θJB are provided for package comparison and PCB design considerations. Table 3. Thermal Parameters for ADCLK914 16-Lead LFCSP Symbol θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL PERFORMANCE The ADCLK914 is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, use an airflow source. θJMA θJMA θJB θJC To determine the junction temperature on the application PCB ΨJT TJ = TCASE + (ΨJT × PD) where: TJ is the junction temperature (°C). TCASE is the case temperature (°C) measured by the customer at top center of package. ΨJT is determined by the values listed in Table 3. PD is the power dissipation. 1 Description1 Junction-to-ambient thermal resistance, 0.0 meters per sec air flow per JEDEC JESD51-2 (still air) Junction-to-ambient thermal resistance, 1.0 meter per sec air flow per JEDEC JESD51-6 (moving air) Junction-to-ambient thermal resistance, 2.5 m/s air flow per JEDEC JESD51-6 (moving air) Junction-to-board thermal resistance, 1.0 meter per sec air flow per JEDEC JESD51-8 (moving air) Junction-to-case thermal resistance (die-to-heatsink) per MIL-Std 883, Method 1012.1 Junction-to-top-of-package characterization parameter, 0 meters per sec air flow per JEDEC JESD51-2 (still air) Descriptions based on using a 2s2p test board. ESD CAUTION Rev. A | Page 5 of 12 Value 78.4 Units °C/W 68.5 °C/W 61.4 °C/W 48.8 °C/W 1.5 °C/W 2.0 °C/W ADCLK914 12 Q 11 Q 10 NC 9 NC 06561-002 VCC 8 VEE 7 NC = NO CONNECT TOP VIEW (Not to Scale) NC 5 NC 4 ADCLK914 NC 6 NC 3 14 VEE 13 VCC PIN 1 INDICATOR D 1 D 2 15 VREF 16 VT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3, 4, 5, 6, 9, 10 7, 14 8, 13 11 12 15 16 Heat Sink/ Exposed Pad Mnemonic D D NC VEE VCC Q Q VREF VT NC Description Noninverting Input. Inverting Input. No Connect. No physical connection to the die. Negative Supply Voltage. Positive Supply Voltage. Inverting Output. Noninverting Output. Reference Voltage. Reference voltage for biasing ac-coupled inputs. Center Tap. Center tap of 100 Ω input resistor. No Connect. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to ground on the application board if improved thermal and/or mechanical stability is needed. Exposed metal at the corners of the package is connected to this back surface. Allow sufficient clearance for vias and other components. Rev. A | Page 6 of 12 ADCLK914 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, VEE = 0 V, TA = 25°C. All outputs terminated through 50 Ω to VCC, unless otherwise noted. Q 250mV/DIV 250mV/DIV Q Q 62.5ps/DIV 100ps/DIV Figure 6. Output Waveform at 1 GHz, VCC = 3.3 V –120 –120 –130 –130 PHASE NOISE (dBc/Hz) –140 –150 –150 –160 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M 06561-004 –160 –140 –170 10 100 Figure 4. Phase Noise at 122.88 MHz 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M Figure 7. Phase Noise at 622.08 MHz –120 350 TA = 25°C 300 RMS JITTER (fs) 250 –140 –150 200 150 100 –160 –170 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M Figure 5. Phase Noise at 245.76 MHz 0 0 1 2 3 4 5 INPUT SLEW RATE (V/ns) 6 Figure 8. RMS Jitter vs. Input Slew Rate Rev. A | Page 7 of 12 7 8 06561-008 50 06561-005 PHASE NOISE (dBc/Hz) –130 06561-007 PHASE NOISE (dBc/Hz) Figure 3. Output Waveform at 1 GHz, VCC = 3.3 V –170 10 06561-006 06561-003 Q ADCLK914 162 160 PROPAGATION DELAY (ps) 3.75 3.70 3.65 3.60 3.55 158 156 154 152 150 3.50 2.97 3.13 3.30 3.46 POWER SUPPLY VOLTAGE (V) 3.63 146 0.4 Figure 9. Differential Output Swing vs. Power Supply Voltage 4.0 113 112 111 110 109 108 107 106 3.13 3.30 3.46 POWER SUPPLY VOLTAGE (V) 3.63 200 180 160 140 120 100 80 60 40 1.5 2.0 INPUT COMMON MODE (V) 2.5 06561-011 20 1.0 2.5 2.0 1.5 1.0 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 FREQUENCY (GHz) 9.5 10.5 11.5 12.5 Figure 13. Toggle Rate, Differential Output Swing vs. Frequency Figure 10. Power Supply Current vs. Power Supply Voltage 0 0.5 3.0 0 0.5 06561-010 105 2.97 3.5 Figure 11. Propagation Delay vs. VICM; VID = 1.6 V p-p Rev. A | Page 8 of 12 06561-013 DIFFERENTIAL OUTPUT SWING (V) 114 POWER SUPPLY CURRENT (mA) 2.0 Figure 12. Propagation Delay vs. VID; VICM = 2.15 V 115 PROPAGATION DELAY (ps) 0.8 1.2 1.6 INPUT DIFFERENTIAL (V p-p) 06561-012 148 06561-009 DIFFERENTIAL OUTPUT SWING (V) 3.80 ADCLK914 APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING The ADCLK914 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Place a 1 μF electrolytic bypass capacitor within several inches of each power supply pin to ground. In addition, place multiple high quality 0.001 μF bypass capacitors as close as possible to each VEE and VCC supply pin and connect these capacitors to the GND plane with redundant vias. Carefully select high frequency bypass capacitors for minimum inductance and ESR. To maximize the effectiveness of the bypass capacitors at high frequencies, strictly avoid parasitic layout inductance. Slew currents may also appear at the VDD and VSS pins of the device being driven by the ADCLK914. HVDS OUTPUT STAGE The ADCLK914 has been developed to provide a bipolar interface to any CMOS device that requires extremely low jitter, high amplitude clocks. It is intended to be placed as close as possible to the receiving device and allows the rest of the clock distribution to run at standard CML or PECL levels. Interconnects must be short and very carefully designed because the single terminated design provides much less margin for error than lower voltage, double terminated transmission techniques. Q 7mA 7mA VEE VEE As with any high speed circuit, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power, and ground impedances, as well as other layout issues, can severely limit performance and can cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified jitter performance by reducing the effective input slew rate. Input and output matching have a significant impact on performance. The ADCLK914 buffer provides internal 50 Ω termination resistors for both D and D inputs. The return side can be connected to the reference pin provided or to a current sink at VCC − 2 V for use with differential PECL, or to VCC for direct coupled CML. The VREF pin should be left floating any time that it is not used to minimize power consumption. Note that the ADCLK914 VREF source is current-limited to resist damage from momentary shorts to VEE or VCC and from capacitor charging currents; for this reason, the VREF source cannot be used as a PECL termination supply. Carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If the inputs are directly coupled to a source, care must be taken to ensure that the pins remain within the rated input differential and common-mode ranges. ESD/clamp diodes between the input pins prevent the application of excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. If a clamp is needed, it is recommended that appropriate external diodes be used. 06561-015 VEE OPTIMIZING HIGH SPEED PERFORMANCE If the return is floated, the device exhibits 100 Ω cross-termination, but the source must then control the common-mode voltage and supply the input bias currents. Q 40mA losses. The ADCLK914, in turn, may be driven directly by standard or low swing PECL, CML, CMOS, or LVTTL sources, or by LVDS with simple ac coupling, as illustrated in Figure 15 through Figure 19. RANDOM JITTER Figure 14. Simplified Schematic Diagram of the ADCLK914 HVDS Output Stage INTERFACING TO HIGH SPEED DACs The ADCLK914 is designed to drive high amplitude, low jitter clock signals into high speed, multi-GSPS DACs. The ADCLK914 should be placed as close as possible to the clock input of the DAC so that the high slew rate and high amplitude clock signal that these devices require do not cause routing difficulties, generate EMI, or become degraded by dielectric and other The ADCLK914 buffer has been specifically designed to minimize random jitter over a wide input range. Provided that sufficient voltage swing is present, random jitter is affected most by the slew rate of the input signal. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. Rev. A | Page 9 of 12 ADCLK914 TYPICAL APPLICATION CIRCUITS VCC VREF VREF VT VT D CONNECT VT TO VCC – 2V. Figure 15. Interfacing to CML Inputs Figure 18. Interfacing to ECL Inputs VREF VREF VT VT D D D D CONNECT VT TO VREF . CONNECT VT, VREF , AND D. PLACE A BYPASS CAPACITOR FROM VT TO GROUND. ALTERNATIVELY, VT, VREF , AND D CAN BE CONNECTED, GIVING A CLEANER LAYOUT AND A 180º PHASE SHIFT. 06561-019 NOTES 1. PLACING A BYPASS CAPACITOR FROM VT TO GROUND CAN IMPROVE THE NOISE PERFORMANCE. Figure 19. Interfacing to AC-Coupled, Single-Ended Inputs Figure 16. AC Coupling Differential Signals VCC Q Q 7mA VEE 7mA VEE VEE 06561-021 40mA 06561-020 CONNECT VT TO VCC. 06561-017 D D 06561-018 VCC – 2V D Figure 17. Interfacing to High Speed DAC Rev. A | Page 10 of 12 ADCLK914 OUTLINE DIMENSIONS 0.60 MAX 3.00 BSC SQ BOTTOM VIEW 0.45 13 12 2.75 BSC SQ TOP VIEW 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 0.05 MAX 0.02 NOM 0.30 0.23 0.18 1 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 16 9 4 8 5 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 0.25 MIN 1.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. 071708-A PIN 1 INDICATOR 0.50 0.40 0.30 Figure 20. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADCLK914BCPZ-WP 1 ADCLK914BCPZ-R71 ADCLK914BCPZ-R21 ADCLK914/PCBZ1 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 11 of 12 Package Option CP-16-3 CP-16-3 CP-16-3 ADCLK914 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06561-0-10/08(A) Rev. A | Page 12 of 12