Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK948 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.3 V power supply LVPECL ADCLK948 Q0 Q0 Q1 Q1 APPLICATIONS Q2 Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation Q2 The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. Q3 REFERENCE Q3 Q4 V T0 Q4 CLK0 CLK0 Q5 V T1 Q5 CLK1 Q6 CLK1 Q6 Q7 IN_SEL VREF 1 Q7 REFERENCE 08280-001 GENERAL DESCRIPTION VREF 0 Figure 1. The ADCLK948 features eight full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V. The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved. ADCLK948 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................6 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Functional Description .....................................................................9 Functional Block Diagram .............................................................. 1 Clock Inputs ...................................................................................9 Revision History ............................................................................... 2 Clock Outputs ................................................................................9 Specifications..................................................................................... 3 Clock Input Select (IN_SEL) Settings...................................... 10 Electrical Characteristics ............................................................. 3 PCB Layout Considerations ...................................................... 10 Absolute Maximum Ratings............................................................ 5 Input Termination Options ....................................................... 11 Determining Junction Temperature .......................................... 5 Outline Dimensions ....................................................................... 12 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 12 Thermal Performance .................................................................. 5 REVISION HISTORY 6/10—Rev. 0 to Rev. A Changed Output Voltage Differential Parameter to Output Voltage, Single Ended Parameter, Table 1 ..................................... 3 Changes to Output Voltage, Single Ended Parameter, Table 1 ... 3 7/09—Revision 0: Initial Version Rev. A | Page 2 of 12 ADCLK948 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (Typ column) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs Parameter DC INPUT CHARACTERISTICS Input Common Mode Voltage Input Differential Range Input Capacitance Input Resistance Single-Ended Mode Differential Mode Common Mode Input Bias Current Hysteresis DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage, Single Ended Reference Voltage Output Voltage Output Resistance Symbol Min VICM VID CIN VEE + 1.5 0.4 VOH VOL VO VREF Typ Max Unit Test Conditions/Comments VCC − 0.1 3.4 ±1.7 V between input pins 0.4 V V p-p pF 50 100 50 20 10 Ω Ω kΩ μA mV Open VTx V V mV 50 Ω to (VCC − 2.0 V) 50 Ω to (VCC − 2.0 V) VOH − VOL, output static V Ω −500 μA to +500 μA Unit Test Conditions/Comments GHz See Figure 4 for differential output voltage vs. frequency, >0.8 V differential output swing 20% to 80% measured differentially VCC − 1.26 VCC − 1.99 610 VCC − 0.76 VCC − 1.54 960 (VCC + 1)/2 235 Table 2. Timing Characteristics Parameter AC PERFORMANCE Maximum Output Frequency Symbol Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient Output-to-Output Skew 1 Part-to-Part Skew Additive Time Jitter Integrated Random Jitter Broadband Random Jitter 2 Crosstalk-Induced Jitter 3 CLOCK OUTPUT PHASE NOISE Absolute Phase Noise tR tF tPD fIN = 1 GHz 1 2 3 Min Typ 4.5 4.8 40 40 175 75 75 210 50 9 Max 90 90 245 25 45 28 75 90 −119 −134 −145 −150 −150 ps ps ps fs/°C ps ps fs rms fs rms fs rms dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz VICM = 2 V, VID = 1.6 V p-p VID = 1.6 V p-p BW = 12 kHz − 20 MHz, CLK = 1 GHz VID = 1.6 V p-p, 8 V/ns, VICM = 2 V Input slew rate > 1 V/ns (see Figure 11, the phase noise plot, for more details) @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs. Rev. A | Page 3 of 12 ADCLK948 Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Symbol VIH VIL IIH IIL Min VCC − 0.4 VEE Typ 2 Max VCC 1 100 0.6 Unit V V μA mA pF Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 2 Symbol Min VCC − VEE 2.97 IVEE IVCC PSRVCC PSRVCC Typ 96 288 <3 28 Change in tPD per change in VCC. Change in output swing per change in VCC. Rev. A | Page 4 of 12 Max Unit Test Conditions/Comments 3.63 V 120 330 mA mA ps/V dB 3.3 V + 10% Static VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% ADCLK948 ABSOLUTE MAXIMUM RATINGS DETERMINING JUNCTION TEMPERATURE Table 5. Parameter Supply Voltage VCC − VEE Input Voltage CLK0, CLK1, CLK0, CLK1, IN_SEL CLK0, CLK1, CLK0, CLK1 to VTx Pin (CML, LVPECL Termination) CLK0, CLK1 to CLK0, CLK1 Input Termination, VTx to CLK0, CLK1, CLK0, and CLK1 Maximum Voltage on Output Pins Maximum Output Current Voltage Reference (VREFx) Operating Temperature Range Ambient Junction Storage Temperature Range To determine the junction temperature on the application printed circuit board (PCB), use the following equation: Rating 6V TJ = TCASE + (ΨJT × PD) where: TJ is the junction temperature (°C). TCASE is the case temperature (°C) measured by the customer at the top center of the package. ΨJT is from Table 6. PD is the power dissipation. VEE − 0.5 V to VCC + 0.5 V ±40 mA ±1.8 V ±2 V Values of θJA are provided for package comparison and PCB design considerations. θJA can be used for a first-order approximation of TJ by the equation VCC + 0.5 V 35 mA VCC to VEE TJ = TA + (θJA × PD) where TA is the ambient temperature (°C). −40°C to +85°C 150°C −65°C to +150°C Values of θJB are provided in Table 6 for package comparison and PCB design considerations. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION THERMAL PERFORMANCE Table 6. Parameter Junction-to-Ambient Thermal Resistance Still Air 0 m/sec Air Flow Moving Air 1 m/sec Air Flow 2.5 m/sec Air Flow Junction-to-Board Thermal Resistance Moving Air 1 m/sec Air Flow Junction-to-Case Thermal Resistance Moving Air Die-to-Heatsink Junction-to-Top-of-Package Characterization Parameter Still Air 0 m/sec Air Flow 1 Symbol Description Value 1 Unit 49.8 °C/W 43.5 39.0 °C/W °C/W 30.7 °C/W 8.8 °C/W 0.7 °C/W θJA Per JEDEC JESD51-2 θJMA Per JEDEC JESD51-6 θJB Per JEDEC JESD51-8 θJC Per MIL-STD 883, Method 1012.1 ΨJT Per JEDEC JESD51-2 Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. Rev. A | Page 5 of 12 ADCLK948 32 31 30 29 28 27 26 25 IN_SEL VCC Q0 Q0 Q1 Q1 VCC VCC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADCLK948 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 Q2 Q2 Q3 Q3 Q4 Q4 Q5 Q5 NOTES 1. NC = NO CONNECT. 2. EPAD MUST BE SOLDERED TO VEE POWER PLANE. 08280-002 NC VCC Q7 Q7 Q6 Q6 VCC VCC 9 10 11 12 13 14 15 16 CLK0 CLK0 VREF 0 VT0 CLK1 CLK1 VT1 VREF 1 Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10, 15, 16, 25, 26, 31 11, 12 13, 14 17, 18 19, 20 21, 22 23, 24 27, 28 29, 30 32 Mnemonic CLK0 CLK0 VREF0 VT0 CLK1 CLK1 VT1 VREF1 NC VCC Q7, Q7 Q6, Q6 Q5, Q5 Q4, Q4 Q3, Q3 Q2, Q2 Q1, Q1 Q0, Q0 IN_SEL EPAD Description Differential Input (Positive) 0. Differential Input (Negative) 0. Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs. Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs. Differential Input (Positive) 1. Differential Input (Negative) 1. Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs. Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs. No Connection. Positive Supply Pin. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Differential LVPECL Outputs. Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs. The exposed pad (EPAD) must be connected to VEE. Rev. A | Page 6 of 12 ADCLK948 TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, VEE = 0 V, VICM = VREFx, TA = 25°C, clock outputs terminated at 50 Ω to VCC − 2 V, unless otherwise noted. C4 C3 C4 C3 C4 500ps/DIV 100mV/DIV Figure 3. LVPECL Output Waveform @ 200 MHz 08280-006 C3 08280-003 100mV/DIV 100ps/DIV Figure 6. LVPECL Output Waveform @ 1000 MHz 1.8 214 213 1.6 1.5 PROPAGATION DELAY (ps) DIFFERENTIAL OUTPUT VOLTAGE (V) 1.7 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 212 211 210 209 208 0.6 0 1000 2000 3000 4000 5000 FREQUENCY (MHz) 207 –40 08280-004 0.4 –20 0 20 40 60 08280-007 0.5 80 TEMPERATURE (°C) Figure 4. Differential Output Voltage vs. Frequency, VID > 1.1 V p-p Figure 7. Propagation Delay vs. Temperature, VID = 1.6 V p-p 225 230 PROPAGATION DELAY (ps) 215 210 205 200 195 190 220 +85°C 210 +25°C 200 –40°C 180 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DIFFERENTIAL INPUT VOLTAGE SWING (V) Figure 5. Propagation Delay vs. Differential Input Voltage 1.8 190 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 DC COMMON-MODE VOLTAGE (V) 2.7 2.9 3.1 08280-008 185 08280-005 PROPAGATION DELAY (ps) 220 Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature, Input Slew Rate > 25 V/ns Rev. A | Page 7 of 12 ADCLK948 –90 ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). –100 –40°C PHASE NOISE (dBc/Hz) 1.52 +25°C 1.50 +85°C 1.48 1.46 –110 –120 –130 ADCLK948 –140 –150 1.44 –160 1.42 2.75 –170 10 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 POWER SUPPLY (V) CLOCK SOURCE 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs. Temperature, VID = 1.6 V p-p 08280-011 1.54 08280-009 DIFFERENTIAL OUTPUT VOLTAGE SWING (V) 1.56 Figure 11. Absolute Phase Noise Measured @1 GHz 300 350 ICC 250 RANDOM JITTER (fS rms) 250 200 +85°C +25°C –40°C 150 100 IEE 3.25 SUPPLY VOLTAGE (V) 3.50 3.75 08280-010 3.00 150 100 50 50 0 2.75 200 Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature, All Outputs Loaded (50 Ω to VCC − 2 V). Rev. A | Page 8 of 12 0 0 5 10 15 20 25 INPUT SLEW RATE (V/ns) Figure 12. RMS Random Jitter vs. Input Slew Rate, VID Method 08280-012 SUPPLY CURRENT (mA) 300 ADCLK948 FUNCTIONAL DESCRIPTION Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK948 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. VS_DRV ADCLK948 VS = VS_DRV Z0 = 50Ω CLOCK OUTPUTS The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK948 are designed to directly drive 800 mV into a 50 Ω cable or into microstrip/stripline transmission lines terminated with 50 Ω referenced to VCC − 2 V, as shown in Figure 14. The LVPECL output stage is shown in Figure 13. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion. 50Ω VCC – 2V 50Ω LVPECL 08280-014 The ADCLK948 accepts a differential clock input from one of two inputs and distributes the selected clock to all eight LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). See the functional block diagram (Figure 1) and the General Description section for more clock input details. See Figure 19 through Figure 23 for various clock input termination schemes. Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK948 should equal VS of the receiving buffer. Although the resistor combination shown (in Figure 15) results in a dc bias point of VS_DRV − 2 V, the actual common-mode voltage is VS_DRV − 1.3 V because there is additional current flowing from the ADCLK948 LVPECL driver through the pull-down resistor. Z0 = 50Ω Figure 14. DC-Coupled, 3.3 V LVPECL VS_DRV VS_DRV ADCLK948 50Ω 127Ω 127Ω SINGLE-ENDED (NOT COUPLED) VS LVPECL 50Ω 83Ω 83Ω 08280-015 CLOCK INPUTS VCC Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination ADCLK948 VS = VS_DRV Z0 = 50Ω 50Ω Qx 50Ω 50Ω LVPECL 08280-016 VS_DRV Z0 = 50Ω Qx VEE 08280-013 Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination VS_DRV ADCLK948 VS 0.1nF Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage 100Ω DIFFERENTIAL 100Ω (COUPLED) 0.1nF TRANSMISSION LINE 200Ω LVPECL 200Ω Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line Rev. A | Page 9 of 12 08280-017 Figure 14 through Figure 17 depict various LVPECL output termination schemes. When dc-coupled, VS of the receiving buffer should match VS_DRV. ADCLK948 A Logic 0 on the IN_SEL pin selects the Input CLK0 and Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1. PCB LAYOUT CONSIDERATIONS The ADCLK948 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. The following references to the GND plane assume that the VEE power plane is grounded for LVPECL operation. Note that, for ECL operation, the VCC power plane becomes the ground plane. It is also important to adequately bypass the input and output supplies. Place a 1 μF electrolytic bypass capacitor within several inches of each VCC power supply pin to the GND plane. In addition, place multiple high quality 0.001 μF bypass capacitors as close as possible to each of the VCC supply pins, and connect the capacitors to the GND plane with redundant vias. Carefully select high frequency bypass capacitors for minimum inductance and ESR. To improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. Also, avoid discontinuities along input and output transmission lines that can affect jitter performance. If the return is floated, the device exhibits a 100 Ω cross termination, but the source must then control the common-mode voltage and supply the input bias currents. There are ESD/clamp diodes between the input pins to prevent the application from developing excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is required, it is recommended that appropriate external diodes be used. Exposed Metal Paddle The exposed metal paddle on the ADCLK948 package is both an electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the VEE power plane. When properly mounted, the ADCLK948 also dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK948. The PCB attachment must provide a good thermal path to a larger heat dissipation area. This requires a grid of vias from the top layer down to the VEE power plane (see Figure 18). The ADCLK948 evaluation board (ADCLK948/PCBZ) provides an example of how to attach the part to the PCB. In a 50 Ω environment, input and output matching have a significant impact on performance. The buffer provides internal 50 Ω termination resistors for both CLKx and CLKx inputs. Normally, the return side is connected to the reference pin that is provided. Carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If the inputs are dccoupled to a source, take care to ensure that the pins are within the rated input differential and common-mode ranges. Rev. A | Page 10 of 12 VIAS TO VEE POWER PLANE 08280-018 CLOCK INPUT SELECT (IN_SEL) SETTINGS Figure 18. PCB Land for Attaching Exposed Paddle ADCLK948 INPUT TERMINATION OPTIONS VREF x VREF x VTx VTx 50Ω CLKx 50Ω 50Ω CLKx CLKx 50Ω CLKx ADCLK948 08280-019 ADCLK948 CONNECT VTx TO VCC. 08280-021 VCC CONNECT VTx TO VREF x. Figure 19. DC-Coupled CML Input Termination Figure 21. AC-Coupled Input Termination, Such as LVDS and LEVPECL VREF x V Tx VCC 50Ω CLKx CLKx 50Ω ADCLK948 CONNECT VTx, VREF x, AND CLKx. PLACE A BYPASS CAPACITOR FROM VTx TO GROUND. ALTERNATIVELY, VTx, VREF x, AND CLKx CAN BE CONNECTED, GIVING A CLEANER LAYOUT AND A 180º PHASE SHIFT. ADCLK948 08280-020 CLKx Figure 20. DC-Coupled LVPECL Input Termination 08280-022 50Ω VTx 50Ω Figure 22. AC-Coupled Single-Ended Input Termination VREF x V Tx 50Ω CLKx 50Ω CLKx ADCLK948 08280-023 0.01µF (OPTIONAL) 50Ω CLKx VREF x Figure 23. DC-Coupled 3.3 V CMOS Input Termination Rev. A | Page 11 of 12 ADCLK948 OUTLINE DIMENSIONS 5.00 BSC SQ TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 12° MAX 32 1 2.85 2.70 SQ 2.55 EXPOSED PAD (BOTTOM VIEW) 17 16 PIN 1 INDICATOR 9 8 0.20 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 25 24 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 032807-A PIN 1 INDICATOR 0.60 MAX 0.60 MAX Figure 24. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADCLK948BCPZ ADCLK948BCPZ-REEL7 ADCLK948/PCBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Evaluation Board Z = RoHS Compliant Part. ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08280-0-6/10(A) Rev. A | Page 12 of 12 Package Option CP-32-8 CP-32-8