SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet SiI-DS-1120-B February 2016 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Contents 1. General Description ......................................................................................................................................................7 1.1. Video Processor ....................................................................................................................................................7 1.2. On-screen Display .................................................................................................................................................7 1.3. Video Input ...........................................................................................................................................................7 1.4. Video Output ........................................................................................................................................................7 1.5. Digital Audio Interface ..........................................................................................................................................7 1.6. Control ..................................................................................................................................................................7 1.7. Package .................................................................................................................................................................7 2. Functional Description ..................................................................................................................................................8 2.1. Video Processor ..................................................................................................................................................10 2.1.1. Supported Input Resolutions to Video Processing Core .............................................................................10 2.1.2. Special Considerations for 4K x 2K Inputs ...................................................................................................10 2.1.3. Supported Output Resolutions ...................................................................................................................10 2.1.4. Video Processing Blocks ..............................................................................................................................10 2.1.5. Bypass Modes .............................................................................................................................................12 2.1.6. Processing Mode .........................................................................................................................................12 2.2. Input Preprocessing ............................................................................................................................................12 2.2.1. Picture Controls ..........................................................................................................................................12 2.2.2. 3 x 3 Matrix (Multicolor Space Converter) ..................................................................................................13 2.2.3. Chroma Subsampler ....................................................................................................................................13 2.3. Mosquito Noise Reduction .................................................................................................................................13 2.4. Video Smoothing.................................................................................................................................................13 2.5. Detail/Edge Enhancement ..................................................................................................................................13 2.6. Scaler...................................................................................................................................................................14 2.7. Keystoning ..........................................................................................................................................................14 2.8. Standalone Video Timing Generators .................................................................................................................14 2.9. Test Pattern Generator .......................................................................................................................................15 2.10. On-screen Display ...........................................................................................................................................15 2.11. Output Postprocessing ....................................................................................................................................15 2.11.1. Chroma Upsampler .....................................................................................................................................15 2.11.2. 3 x 3 Matrix (Multicolor Space Converter) ..................................................................................................15 2.12. 4:2:0 Output ....................................................................................................................................................15 2.13. HDMI Output ..................................................................................................................................................17 2.13.1. TMDS Transmitter Core ..............................................................................................................................17 2.13.2. Deep Color Support.....................................................................................................................................17 2.13.3. Source Termination.....................................................................................................................................17 2.13.4. HDCP Encryption Engine/XOR Mask ...........................................................................................................17 2.13.5. HDCP Key ROM ...........................................................................................................................................17 2.13.6. Audio Return Channel .................................................................................................................................18 2 2.13.7. DDC Master I C Interface ............................................................................................................................18 2.13.8. Receiver Sense and Hot Plug Detection ......................................................................................................18 2.13.9. Interrupts ....................................................................................................................................................18 2.14. HDMI Input .....................................................................................................................................................18 2.14.1. TMDS Receiver Core ...................................................................................................................................18 2.14.2. Deep Color Support.....................................................................................................................................19 2.14.3. MHL Receiver ..............................................................................................................................................19 2.14.4. HDCP Decryption Engine/XOR Mask ...........................................................................................................19 2.14.5. HDCP Embedded Keys .................................................................................................................................19 2.14.6. EDID RAM Block ..........................................................................................................................................19 2.15. Audio Input Processing ...................................................................................................................................19 2 2.15.1. I S Audio Input ............................................................................................................................................19 2.15.2. Direct Stream Digital Input .........................................................................................................................20 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.15.3. S/PDIF Input ................................................................................................................................................ 20 2.15.4. Requirement for an MCLK .......................................................................................................................... 20 2.15.5. Audio Downsampler ................................................................................................................................... 20 2.15.6. High-bitrate Audio on HDMI ....................................................................................................................... 21 2 2.15.7. I S-to-SPDIF Conversion .............................................................................................................................. 22 2.16. Audio Output Processing ................................................................................................................................ 22 2.16.1. S/PDIF Output ............................................................................................................................................. 22 2 2.16.2. I S Audio Output ......................................................................................................................................... 22 2.16.3. One-bit Audio Output ................................................................................................................................. 23 2.16.4. High-bitrate Audio Support......................................................................................................................... 23 2.16.5. Auto Audio Configuration ........................................................................................................................... 23 2.16.6. Soft Mute .................................................................................................................................................... 23 2.17. CEC Interface .................................................................................................................................................. 24 2.18. GPIO ................................................................................................................................................................ 24 2.19. Control and Configuration .............................................................................................................................. 24 2.19.1. Register/Configuration Logic ...................................................................................................................... 24 2 2.19.2. I C Serial Ports ............................................................................................................................................. 24 2.19.3. SPI Serial Bus ............................................................................................................................................... 24 2.19.4. Delay from Reset Deactivation to Register Access ..................................................................................... 24 2.20. Pin Strapping ................................................................................................................................................... 25 2.21. Power Supply Sequencing ............................................................................................................................... 25 2.22. Audio PLL Reset .............................................................................................................................................. 25 3. Electrical Specifications .............................................................................................................................................. 26 3.1. Absolute Maximum Conditions .......................................................................................................................... 26 3.2. Normal Operating Conditions ............................................................................................................................. 26 3.3. DC Specifications ................................................................................................................................................ 27 3.3.1. DC Power Supply Pin Specifications ............................................................................................................ 29 3.4. AC Specifications ................................................................................................................................................. 29 3.5. Control Timing Specifications ............................................................................................................................. 31 4. Timing Diagrams ......................................................................................................................................................... 33 4.1. Reset Timing Diagrams ....................................................................................................................................... 33 4.2. TMDS Input Timing Diagrams ............................................................................................................................. 33 4.3. Digital Audio Input Timing Diagrams .................................................................................................................. 34 4.4. Digital Audio Output Timing Diagrams ............................................................................................................... 35 4.5. Control Signal Timing Diagrams .......................................................................................................................... 36 2 4.5.1. I C Timing Diagram ..................................................................................................................................... 36 4.5.2. SPI Timing Diagrams ................................................................................................................................... 36 2 4.6. Calculating Setup and Hold Times for I S Audio Output Bus .............................................................................. 37 5. Pin Diagram and Pin Descriptions ............................................................................................................................... 38 5.1. Pin Diagram......................................................................................................................................................... 38 5.2. Pin Descriptions .................................................................................................................................................. 39 5.2.1. HDMI Receiver Control Signal Pins ............................................................................................................. 39 5.2.2. HDMI Receiver Differential Signal Data Pins............................................................................................... 39 5.2.3. Digital Audio Output Pins............................................................................................................................ 40 5.2.4. HDMI Transmitter TMDS Output Pins......................................................................................................... 40 5.2.5. HDMI Transmitter Control Signal Pins ........................................................................................................ 41 5.2.6. Audio Input Pins .......................................................................................................................................... 41 5.2.7. Configuration/Programming Pins ............................................................................................................... 42 5.2.8. Crystal Clock Pins ........................................................................................................................................ 42 5.2.9. Power and Ground Pins .............................................................................................................................. 43 5.2.10. Reserved Pins .............................................................................................................................................. 43 6. Feature Information ................................................................................................................................................... 44 2 6.1. I C and SPI Interfaces .......................................................................................................................................... 44 2 6.1.1. E-DDC/I C Interface ..................................................................................................................................... 44 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 3 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2 6.1.2. Local I C Interface .......................................................................................................................................45 2 6.1.3. Video Requirement for I C Access ..............................................................................................................46 6.1.4. Local SPI Serial Interface .............................................................................................................................46 7. Package Information ...................................................................................................................................................48 7.1. ePad Requirements .............................................................................................................................................48 7.2. PCB Layout Guidelines ........................................................................................................................................48 7.3. Package Dimensions ...........................................................................................................................................49 7.4. Marking Specification .........................................................................................................................................50 7.5. Ordering Information ..........................................................................................................................................50 References ..........................................................................................................................................................................51 Standards Documents .....................................................................................................................................................51 Standards Groups ...........................................................................................................................................................51 Lattice Semiconductor Documents .................................................................................................................................51 Technical Support ...........................................................................................................................................................51 Revision History ..................................................................................................................................................................52 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Figures Figure 1.1. Typical Application .............................................................................................................................................. 7 Figure 2.1. Functional Video Path Block Diagram ................................................................................................................. 8 Figure 2.2. Audio Path Block Diagram .................................................................................................................................. 9 Figure 2.3. Video Processing Blocks .................................................................................................................................... 11 Figure 2.4. Bypass Options ................................................................................................................................................. 12 Figure 2.5. Location of Cb/Cr with Respect to Y in YCbCr 4:2:0 .......................................................................................... 16 Figure 2.6. YCbCr 4:2:0 Signal Mapping and Timing Diagram ............................................................................................. 16 Figure 2.7. High-speed Data Transmission ......................................................................................................................... 21 Figure 2.8. High-bitrate Stream before and after Reassembly and Splitting ...................................................................... 21 Figure 2.9. High-bitrate Stream after Splitting ................................................................................................................... 22 2 Figure 2.10. Layout of High-bitrate Audio Samples on I S .................................................................................................. 23 Figure 3.1. Crystal Clock Schematic .................................................................................................................................... 31 Figure 4.1. Conditions for Use of RESET# ........................................................................................................................... 33 Figure 4.2. RESET# Minimum Timing .................................................................................................................................. 33 Figure 4.3. TMDS Channel-to-Channel Skew Timing .......................................................................................................... 33 2 Figure 4.4. I S Input Timings ............................................................................................................................................... 34 Figure 4.5. S/PDIF Input Timings ......................................................................................................................................... 34 2 Figure 4.6. I S Output Timings ............................................................................................................................................ 35 Figure 4.7. S/PDIF Output Timings ...................................................................................................................................... 35 Figure 4.8. MCLK Timings.................................................................................................................................................... 35 2 Figure 4.9. I C Data Valid Delay .......................................................................................................................................... 36 Figure 4.10. SPI Write Setup and Hold Times ..................................................................................................................... 36 Figure 4.11. SPI Read Setup and Hold Times ...................................................................................................................... 36 Figure 5.1. Pin Diagram....................................................................................................................................................... 38 Figure 6.1. DDC Byte Read .................................................................................................................................................. 44 Figure 6.2. DDC Byte Write ................................................................................................................................................. 44 Figure 6.3. Short Read Sequence ........................................................................................................................................ 44 2 Figure 6.4. DDC Master I C Supported Transactions .......................................................................................................... 45 2 Figure 6.5. Register Write Cycle on Local I C ...................................................................................................................... 45 2 Figure 6.6. Register Read Cycle on Local I C ....................................................................................................................... 45 Figure 6.7. SPI Serial Connection Example: Host ↔ Single SPI Slave Device ..................................................................... 46 Figure 6.8. SPI Serial Connection Example: Host ↔ Dual SPI Slave Devices...................................................................... 46 Figure 6.9: SPI Serial Write Operation ................................................................................................................................ 47 Figure 6.10: SPI Serial Read Operation ............................................................................................................................... 47 Figure 7.1. Package Diagram .............................................................................................................................................. 49 Figure 7.2. Marking Diagram .............................................................................................................................................. 50 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 5 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Tables Table 2.1. Audio Multiplexing Options .................................................................................................................................9 Table 2.2. Multicolor Space Converter Input/Output Formats ...........................................................................................13 Table 2.3. DSD Input Pin Mapping ......................................................................................................................................20 Table 2.4. Channel Status Bits Used for Word Length ........................................................................................................21 Table 2.5. Supported MCLK Frequencies ............................................................................................................................22 Table 2.6. DSD Output Pin Mapping ...................................................................................................................................23 Table 2.7. Pin Strapping Options ........................................................................................................................................25 Table 3.1. Absolute Maximum Conditions ..........................................................................................................................26 Table 3.2. Normal Operating Conditions ............................................................................................................................26 Table 3.3. Digital I/O Specifications ....................................................................................................................................27 Table 3.4. TMDS Input DC Specifications – HDMI Mode ....................................................................................................27 Table 3.5. TMDS Input DC Specifications – MHL Mode ......................................................................................................27 Table 3.6. TMDS Output DC Specifications .........................................................................................................................28 Table 3.7. Single Mode Audio Return Channel DC Specifications .......................................................................................28 Table 3.8. CEC DC Specifications .........................................................................................................................................28 Table 3.9. CBUS DC Specifications ......................................................................................................................................28 Table 3.10. Total Power Dissipation ...................................................................................................................................29 Table 3.11. Power-down Mode Power Dissipation ............................................................................................................29 Table 3.12. TMDS Input AC Timing Specifications – HDMI Mode .......................................................................................29 Table 3.13. TMDS Input AC Timing Specifications – MHL Mode.........................................................................................29 Table 3.14. TMDS Output AC Timing Specifications Mode .................................................................................................30 Table 3.15. CEC AC Specifications .......................................................................................................................................30 Table 3.16. CBUS AC Specifications ....................................................................................................................................30 2 Table 3.17. I S Audio Input Port Timing Specifications .......................................................................................................30 Table 3.18. S/PDIF Input Port Timing Specifications ...........................................................................................................30 2 Table 3.19. I S Audio Output Port Timing Specifications ....................................................................................................31 Table 3.20. S/PDIF Output Port Timing Specifications ........................................................................................................31 Table 3.21. Crystal Clock Timings ........................................................................................................................................31 Table 3.22. Reset Timings ...................................................................................................................................................31 2 Table 3.23. I C Control Signal Timings ................................................................................................................................32 Table 3.24. SPI Control Signal Timings ................................................................................................................................32 2 Table 4.1. I S Setup and Hold Time Calculations ................................................................................................................37 2 Table 6.1. Control of Local I C Device Address with AO_MUTE Pin ....................................................................................46 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 1. General Description 1.2. On-screen Display The Lattice Semiconductor SiI9612 video processor supports High-definition Multimedia Interface (HDMI®) and video processing requirements for a Blu-ray Player/Recorder, Audio Video Receiver (AVR), and other video processors. It incorporates an integrated HDMI/Mobile High-definition Link 2 (MHL®) receiver and an HDMI transmitter that supports HDCP repeaters. 1.3. Video Input Lattice Semiconductor VRS® ClearView video processing enhances video streaming quality with noise reduction, Video Smoothing™, and picture enhancement. VRS® ClearView also includes a 4K adaptive scaler to drive the emerging 4K display market. The SiI9612 device is preprogrammed with Highbandwidth Digital Content Protection (HDCP) keys for both receiver and transmitter, which helps reduce programming overhead and lowers manufacturing costs. 300 MHz HDMI transmitter port 1.5. Digital Audio Interface Supports video input formats up to 1080p and UXGA including 4K x 2K pass-through Supports video output formats up to 1080p, WUXGA, and 4K x 2K Full 10-bit Adaptive Scaler Mosquito Noise Reduction Supports upscaling to 4K x 2K Supports downscaling from 1080p @ 60 Hz Video smoothing (pre- and postscaler) Detail and edge enhancement (prescaler) 12-bit preprocessing including color space conversion and picture control 12-bit postprocessing including color space conversion Picture controls Test Pattern Generator (TPG) 300 MHz HDMI receiver port with 3D support MHL with 1080p @ 60 Hz support 1.4. Video Output 1.1. Video Processor Character-based Supports On-screen Display (OSD) over 3D video Supports alpha-blending Inputs 2 I S input with multichannel support S/PDIF input Audio Return Channel (ARC) input Outputs 2 I S output with four data signals for multichannel formats, and flexible programmable channel mapping including DSD High Bitrate Audio output including Dolby® TrueHD and DTS-HD Master Audio™ S/PDIF output supports LPCM, Dolby Digital, DTS digital audio transmission with a 32 kHz – 192 kHz fS sample rate Intelligent audio mute capability avoids pops and noise with automatic soft mute and unmute IEC60958 or IEC61937 compatible 1.6. Control 2 I C and Serial Peripheral Interface (SPI) Bus DDC for HDMI receiver and transmitter Consumer Electronics Control (CEC) interface incorporates an HDMI CEC I/O and an integrated CEC Programming Interface (CPI) 1.7. Package BD SoC HDMI SiI9612 9 mm × 9 mm, 76 pin MQFN package with ePad HDMI TV DDR2/3 Figure 1.1. Typical Application © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 7 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2. Functional Description The SiI9612 video processor is ideally suited for Blu-ray players, A/V receivers, and video processing applications. It features a digital processing core that performs real-time video format conversion and image improvement. Format conversion is achieved through an innovative adaptive scaler that allows the device to upscale from any input format to 4K x 2K resolutions. Proprietary video processing algorithms improve the picture q uality by removing unnaturally appearing noise or artifacts, smoothing edges and sharpening the image. Image improvement is supported for both standard and high-definition video. An on-chip character generated On-screen Display (OSD), organized as 108 x 30 rows and columns, is included in the SiI9612 device. The OSD has split-screen mode to support display of the OSD over a 3D image. The SiI9612 device provides a Test Pattern Generator (TPG) that is fully programmable by software and is able to generate test patterns without a valid input signal. With a maximum supported resolution of 4096 x 2208, it is able to generate test patterns for both 4K x 2K and 1080p 3D video output formats. The SiI9612 video processor integrates a full 300 MHz HDMI receiver and HDMI transmitter. Mobile High-definition Link (MHL) technology is available on the HDMI receiver. The MHL receiver supports PackedPixel mode. The Audio Return Channel (ARC), provided for the HDMI transmitter port, allows the SiI9612 device to receive a S/PDIF signal from the connected DTV. The SiI9612 video processor supports audio extraction and insertion. Audio extracted from the HDMI receiver can be 2 output simultaneously to a S/PDIF port, a multichannel I S port, and to the HDMI transmitter for repacketization. Audio to be transmitted on the HDMI output can be selected from one of four other sources: S/PDIF input , 2 2 2-channel I S input, multichannel I S input, and ARC input. The video processor can also convert the LPCM data 2 2 received from the 2-channel I S input or the I S output of the HDMI receiver to an IEC60958 stream to output on the S/PDIF port. Figure 2.1 below and Figure 2.2 on the next page show the functional blocks of the chip. Internal OSD Adaptive Scaler and Video Enhancement TMDS Overlay Mixer HDMI Rx M u x HDMI Tx TMDS Figure 2.1. Functional Video Path Block Diagram © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Note: I2S_Rx incudes 4 data signals, and MCLK TMDS HDMI Rx 7 I2S_Input_SD0,1,2,3 6 SPDIF_Rx 1 I2S_Input_SD0 3 SPDIF_Rx 1 SPDIF_Input 1 Audio Input 1 1 I2S_Input SPDIF_Input ARC_Input Audio Conversion 7 I2S_Rx Audio Extraction 3 Audio Insertion I2S_Rx ARC_Input 3 1 1 I2S_Tx 7 TMDS HDMI Tx 1 Audio Output Mux’s SPDIF_Tx 1 I2S_Output/Input I2S_Input_SD0 7 I2S_Rx 6 I2S_Input_SD0,1,2,3 Note: MCLK is not included in I2S_Input SPDIF_Input ARC_Input I2S_Rx SPDIF_Rx 1 SPDIF_Input 1 SPDIF_Convert 1 ARC_Input 1 1 SPDIF_Out SPDIF_Out 1 7 3 I2S_Input_SD0 7 I2S_Output 3 I2S To SPDIF 1 SPDIF_Convert Figure 2.2. Audio Path Block Diagram Table 2.1 summarizes the audio outputs that are available with each audio input. Table 2.1. Audio Multiplexing Options Audio Input SPDIF_Input I2S_Input HDMI SPDIF_Rx HDMI I2S_Rx ARC_Input SPDIF_Out Audio Output I2S_Output HDMI SPDIF_Tx HDMI I2S_Tx Supported — Supported — Supported (2-channel formats) Supported — Supported Supported — Supported — Supported (2-channel formats) Supported — Supported Supported — Supported — © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 9 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.1. Video Processor The SiI9612 video processor features the latest VRS® technologies from Lattice Semiconductor including a 4K Adaptive Scaler, Video Smoothing, enhanced Mosquito Noise Reduction, and Detail and Edge Enhancement. These technologies improve the picture quality of highly compressed video sources by enhancing resolution through scaling and removing video noise without side effects. Adaptive scaling delivers automatically optimized performance for all sources including internet video, high-definition video, and computer graphics. All processing resources are included on-chip and external RAM is not required. 2.1.1. Supported Input Resolutions to Video Processing Core The SiI9612 video processing core supports several input formats as defined in the CEA-861E Specification. It also supports several PC formats. Supported formats include, but are not limited to, the following: 720 x 480i 1920 x 1080i50 UXGA 720 x 576i 1920 x 1080i60 4K x 2K @ 23.98 Hz, 24 Hz, 25 Hz, 29.97 Hz, and 30 Hz pass 1440 x 480i 1920 x 1080p50 through 1440 x 576i 1920 x 1080p60 4K x 2K YCbCr 4:2:0 @ 59.94 Hz, 720 x 480p VGA 60 Hz, and 50 Hz pass-through 720 x 576p SVGA 1280 x 720p50 XGA 1280 x 720p60 SXGA 1080p resolutions may require a small amount of vertical zoom when scaling down to certain SD resolutions. The SiI9612 video processor does not support frame rate conversion. The output frame rate always needs to be the same as the input frame rate. 2.1.2. Special Considerations for 4K x 2K Inputs 4K x 2K inputs must bypass all major processing blocks. In this mode, color space conversion and picture controls are still available. The exception is YCbCr 4:2:0 encoded 4K x 2K @ 60 Hz (59.94 Hz) and 50 Hz inputs, in which color space conversion and picture controls must also be bypassed. Figure 2.4 on page 12 shows the bypass modes available on the SiI9612 video processor. 2.1.3. Supported Output Resolutions The SiI9612 video processing core supports several output formats including the following: 480i 1080i SXGA 480p 1080p UXGA 576i VGA 4K x 2K @ 23.98 Hz, 24 Hz, 25 Hz, 29.97 Hz, and 30 Hz 576p SVGA 4K x 2K YCbCr 4:2:0 720p XGA @ 59.94 Hz, 60 Hz, 50 Hz The SiI9612 device does not support frame rate conversion. The output frame rate always needs to be the same as the input frame rate. 2.1.4. Video Processing Blocks The SiI9612 video processor contains the following video processing blocks: Input Preprocessing reformats the input signal to YCbCr 4:2:2 format Mosquito Noise Reduction Standard Definition Edge Smoothing High-definition Detail and Edge Enhancement Adaptive Video Scaling High-definition Edge Smoothing Test Pattern Generation Internal OSD Blending Output Postprocessing reformats the video data to many different output formats © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Figure 2.3 shows a block diagram indicating the placement of these blocks in the video path. HDMI Input HDMI Receiver Format Detector Multi-CSC Picture Controls Chroma Subsampler Pixel Capture Mosquito Noise Reduction Standard Definition Edge Smoothing High Definition Enhancement Adaptive Scaler High Definition Edge Smoothing Chroma Upsampler Pixel Capture Test Pattern Gen. Multi-CSC Internal OSD Mixer Int. OSD Index, Char.RAM, LUT Video Generator Luma Upsampler MUX HDMI Transmitter HDMI Output Figure 2.3. Video Processing Blocks © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 11 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.1.5. Bypass Modes The SiI9612 device provides two options for bypassing the internal processing blocks using control registers that are described in the SiI9612 programmer’s reference (SiI-PR-1069; requires NDA with Lattice Semiconductor). Figure 2.4 shows the available bypass options. Core Mosquito Noise Reduction RX Standard Definition Edge Smoothing High Definition Detail & Edge Enhancement Scaler Input RX 4:4: 4 Bypass Path High Definition Edge Smoothing Output TX Figure 2.4. Bypass Options 2.1.6. Processing Mode In processing mode, the output of the SiI9612 video processor can be in RGB or YCbCr mode. Multiple color space converters, chroma upsampler, and chroma downsampler logic blocks are available on the input and output of the processing block to ensure support for a wide range of applications. 2.2. Input Preprocessing The SiI9612 video processor provides a number of video processing functions that can be used to adjust the incoming video signal before it is sent to the scaler and enhancement blocks. These functions are color space conversion, picture controls, and chroma subsampling. All processing is done in 36 bits. 2.2.1. Picture Controls Picture controls are used to adjust the following aspects of the video input signal: Input Black Level: 4096 levels of black level control. Contrast: 1 integer bit, 8 fractional bits. Range is from 0 to 1.996 with a 1/256 resolution for a total of 512 levels of contrast control. Saturation:1 integer bit, 8 fractional bits. Range is from 0 to 1.996 with a 1/256 resolution for a total of 512 levels of saturation control. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.2.2. 3 x 3 Matrix (Multicolor Space Converter) In addition to the built-in picture controls, the SiI9612 device features a 3 x 3 matrix module at the input path. These can be used as programmable linear control to adjust the brightness, contrast, saturation, and hue in the three components of the input signal. It can also be used to perform RGB-to-YCbCr and YCbCr-to-RGB color space conversions. The 3x3 matrix also comes with 64 sets of predefined coefficients to support all standard color space conversions. Table 2.2 shows the eight possible formats available for the input and output of the 3 x 3 matrix. Table 2.2. Multicolor Space Converter Input/Output Formats Color Space YCbCr Levels Video Colorimetry 709 YCbCr YCbCr YCbCr Video PC PC 601 709 601 RGB RGB Video Video 709 601 RGB RGB PC PC 709 601 2.2.3. Chroma Subsampler The chroma subsampler module converts YCbCr 4:4:4 input signals to YCbCr 4:2:2 format. 2.3. Mosquito Noise Reduction The SiI9612 video processor detects and removes mosquito noise. Mosquito noise is a common compression artifact caused by MPEG decoders, and is often exhibited around the edges of text and computer generated graphics. The SiI9612 algorithm detects areas where mosquito noise would be the most likely, and then works to diminish the mosquito noise without blurring the edge of the text or graphic. The maximum resolution supported by mosquito noise reduction is 576p. 2.4. Video Smoothing The Lattice Semiconductor Video Smoothing technology removes the rough edges in an image, such as the staircase appearance of a diagonal line drawn on the screen without edge smoothing (stair stepped effect). Digital compression, scaling artifacts, poor quality deinterlacing, or resolution limitations in the digital sampling of an image cause these effects. Smoothing technology creates the effect of a high resolution image without softening the entire image. The SiI9612 device offers two smoothing blocks. The Standard Definition Edge Smoothing block comes before the scaler block and removes any rough edges on the original image. The High-definition Edge Smoothing block comes after the scaler and it reduces rough edges caused by upscaling the video. 2.5. Detail/Edge Enhancement There are two types of sharpening in the SiI9612 device: general and edge-qualified. Sharpening is done before scaling in the High-definition Enhancement block. The High-definition Enhancement block works well for sharpening both SD and HD video. Detail enhancement can be used to increase fine detail or reduce noise for overly enhanced images. Detail enhancement is controlled with an 8-bit signed register. Positive control numbers from 1 to 127 increase sharpening and negative numbers in two's complement format decrease sharpening. This means that if the control word is negative, the image is low-pass filtered. The control register defaults to 0, which does not apply any sharpening. Edge enhancement can be used to sharpen edges or reduce overly enhanced edges. The edge qualified sharpening or edge enhancement works only on object edges. It also uses an 8-bit signed control word, like general sharpening, so © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 13 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet sharpening can increase around object edges if the control word is positive, and edges of objects can be filtered if the control word is negative. There is a clipping control for edge-qualified sharpening that allows for adjustment of edge sensitivity. The clipping control is also an 8-bit number, but it is unsigned. The clipping control allows the user to select the strength of object edges to which sharpening is applied. The detail enhancement and edge-qualified enhancement methods are additive, so the results of both sharpening methods are combined. An example of this would be to use general sharpening to increase detail in the entire image. If object edges are overenhanced, then negative edge qualified sharpening is applied to reduce the overenhancement of the edges. If general sharpening is applied to a noisy image, the increase in noise may be objectionable. In that case, positive edge qualified sharpening should be applied to sharpen object edges, but not increase the noise level. 2.6. Scaler The scaler provides format conversion capability to the SiI9612 video processor. It reads the input data from internal line memory and applies horizontal and vertical scaling. Adaptive scaling ensures that the converted format is free of ringing artifacts regardless of content, whether video, graphic, or a mix of both. Format conversion is supported for both video and PC formats. The scaler does not support a frame buffer. The output frame rate is locked to the input frame rate. A small amount of vertical zoom is necessary when scaling down from 1080p resolutions to some SD resolutions such as 480p. The scaler can perform scaling on a limited set of Frame Packed 3D formats. The only 3D format conversions that work are conversions from 720p Frame Packed to 1080p Frame Packed, or from 1080p Frame Packed to 720p Frame Packed. The scaler supports panorama mode that changes the aspect ratio of the image. It can be used to fit a 4:3 SD image into a 16:9 HD format with minimal distortion. This is achieved by keeping the original image aspect ratio in the center of the scaled image, and gradually stretching the image towards its left and right edges. This results in no distortion at the image center while horizontal distortion gradually increases towards the left and right edges of the image. The panorama mode features an enhanced algorithm that reduces the distortion at the far edges of the image. The scaler also includes both a border generator and a mask generator. The border generator is used to create a grey frame about the video image whereas the mask generator can be used to create a black frame around the border. Borders provide another method for correcting the aspect ratio of the displayed image, such as displaying a 4:3 image on a 16:9 frame without horizontal distortion by adding appropriately sized pillars on the left and right side of the image. Other functions supported by the scaler block include Y/C delay that allows a horizontal offset between the chroma and luma signal to compensate for delay differences caused by other parts of the system, automatic Chroma Upsampling Error (CUE) correction, which detects chroma data that has been upsampled incorrectly in the vertical direction and suppresses the visual artifacts caused by these errors, and user-defined zoom and pan functions. Scaler processing is done in YCbCr 4:2:2, 20-bit (10 bits per component) color space format. 2.7. Keystoning The SiI9612 device supports Keystoning. Keystoning is necessary when an image is projected onto a surface at an angle resulting in a distorted image of a trapezoid. For example, if a projector is lower than the surface onto which it is projecting, the image is larger at the top than at the bottom. 2.8. Standalone Video Timing Generators The SiI9612 device features a standalone Video Timing Generator (VTG) which allows it to generate a solid colored screen with any output format supported by the device. For example, a 1080p signal which produces a solid blue screen can be output when there are no inputs to the video processor. The input clock for the VTG can be selected from among these clock sources: 27 MHz system clock, HDMI input clock and internal video PLLs. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.9. Test Pattern Generator The SiI9612 video processor has a programmable Test Pattern Generator (TPG). The TPG is flexible and under software control. It is able to generate test patterns without a valid input signal. The maximum output resolution of the TPG is 4096 x 2208. The 4096 horizontal resolution supports all 4K x 2K formats. The 2208 vertical resolution supports Frame Packed 3D formats up to 1080p. The TPG operates in YCbCr 4:4:4 color space format at 12 bits per color component. 2.10.On-screen Display The SiI9612 video processor comes with a built-in character-based On-screen Display (OSD). The OSD is organized as a 108 x 30 character map that can be positioned anywhere on the screen. 384 characters can be created at 12 x 24 pixels per character or 192 characters at 24 x 24 pixels per character. The OSD can support transparency and a maximum of 64 pairs of foreground and background colors. The maximum resolution of the OSD is 1296 x 720 pixels. The OSD supports a split mode that allows it to be overlaid onto some 3D video formats. The OSD can be split vertically or horizontally. When split vertically the OSD can be overlaid onto Frame Packed 3D formats or Top-and-Bottom 3D formats. When split horizontally, the OSD can be overlaid onto Side-by-Side 3D formats. However, 3D processing downstream from the SiI9612 device of Side-by-Side (Half) and Top-and-Bottom formats will distort the characters as they will be expanded by 2x horizontally in a Side-by-Side (Half) format, or they will be expanded by 2x vertically in a Top-and-Bottom format. 2x, 3x, and 4x pixel and line replication are supported for increasing the size of the OSD characters. Pixel replication is independent for horizontal and vertical. Pixel and line replication may be used to increase the legibility of the OSD for 4K x 2K output. The OSD is rendered in YCbCr 4:4:4 or RGB color space. 2.11.Output Postprocessing Additional processing can be performed on the output data after the scaling/enhancement data path before it is sent to the HDMI transmitter. These functions are color space conversion and chroma upsampling. All processing is done in 36 bits. 2.11.1. Chroma Upsampler The chroma upsampler module converts YCbCr 4:2:2 input signals to YCbCr 4:4:4 format. 2.11.2. 3 x 3 Matrix (Multicolor Space Converter) The 3 x 3 matrix module is the same as the one in the input path. It performs color space conversion using a userprogrammed coefficient and offset values, or 64 predefined sets of coefficients for all standard color space conversions. 2.12.4:2:0 Output The SiI9612 video processor supports YCbCr 4:2:0 ready displays. The primary purpose of this pixel encoding format is to support the transmission of 4K x 2K @ 50/60 Hz formats using a link clock rate that is half the pixel clock rate, or 297 MHz, by reducing the bandwidth through chroma subsampling. In YCbCr 4:2:0 format, the chroma components, Cb and Cr, are subsampled both horizontally and vertically with respect to the Y component by a factor of two. This produces a Y-to-Cb/Cr ratio of 4:1, which results in half the bandwidth of YCbCr 4:4:4 format. As shown in Figure 2.5 on the next page, the subsampled Cb and Cr components are co-sited and aligned with Y horizontally, but are shifted by half a line vertically. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 15 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet pixel 0 pixel 1 pixel 2 pixel 3 Y00 Y01 Y02 pixel 4 pixel 5 pixel 6 Y04 Y03 Y05 Y06 pixel 7 Y07 line 0 line 1 CB04 CR04 CB02 CR02 CB00 CR00 CB06 CR06 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 line 2 CB22 CR22 CB20 CR20 line 3 Y30 Y31 Y32 CB24 CR24 Y34 Y33 CB26 CR26 Y35 Y36 Y37 Figure 2.5. Location of Cb/Cr with Respect to Y in YCbCr 4:2:0 Figure 2.6 illustrates the organization and timing of the Y, Cb and Cr samples when transported across the HDMI link in YCbCr 4:2:0 format. Two horizontally successive Y samples are transmitted in TMDS channel 1 and 2 in order, respectively. The Cb and Cr samples are transmitted on alternate lines in TMDS channel 0, with Cb being transferred first. line0 Pixel 00/01 Pixel 02/03 Pixel 04/05 Pixel 06/07 Pixel 08/09 ... TMDS Channel 0 CB00 CB02 CB04 CB06 CB08 ... 1 Y00 Y02 Y04 Y06 Y08 ... 2 Y01 Y03 Y05 Y07 Y09 ... line1 Pixel 10/11 Pixel 12/13 Pixel 14/15 Pixel 16/17 Pixel 18/19 ... TMDS Channel 0 CR00 CR02 CR04 CR06 CR08 ... 1 Y10 Y12 Y14 Y16 Y18 ... 2 Y11 Y13 Y15 Y17 Y19 ... Figure 2.6. YCbCr 4:2:0 Signal Mapping and Timing Diagram The SiI9612 video processor provides a special mode for scaling any input format with 50/60 Hz frame rate to 4K x 2K @ 50/60 Hz in 4:2:0 output format. In this mode the scaler is configured to scale the input vertically to the full 4K x 2K vertical resolution of 2160 lines and horizontally to half the horizontal resolution, either 1920 or 2048 pixels. A half line vertical shift is then applied to the chroma component of the generated signal before being upsampled by a factor of two. The resultant 4:4:4 signal then goes to a luma upsampler module where the luma component is upsampled to create two times the number of samples. In the final stage, the luma component is sent out in two pixels per clock while the chroma components Cb and Cr are clocked out on alternating lines. All processing is done with an output clock of 297 MHz. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.13.HDMI Output The SiI9612 video processor features an HDMI transmitter with 300 MHz TMDS core for 1080p @ 60 Hz 3D and 4K x 2K outputs, full digital video and audio pipelines, integrated HDCP keys and encryption engine, and Audio Return Channel (ARC) input. 2.13.1. TMDS Transmitter Core The TMDS transmitter core performs 8-bit-to-10-bit TMDS encoding on the data received from the HDCP XOR mask, and is then sent over three TMDS data and one TMDS clock differential lines. See the HDCP Encryption Engine/XOR Mask on page 17 for more details. The transmitter core supports link clocks from 25 MHz to 300 MHz. The internal PLL has the option to multiply the pixel clock to implement deep color or pixel repetition modes. 2.13.2. Deep Color Support The SiI9612 video processor provides support for deep color video data up to the maximum specified link speed of 3 Gb/s (300 MHz internal clock rate for the deep color packetized data). It supports 30-bit and 36-bit video input formats, and converts the data to 8-bit packets for encryption and encoding for transferring across the TMDS link. When the input data width is wider than desired, the device can be programmed to dither or truncate the video data to the desired size. For example, if the input data width is a 12 bits per pixel component, but the sink device only supports 10 bits, the HDMI transmitter can be programmed to dither or truncate the 12-bit input data to the desired 10-bit output data. 2.13.3. Source Termination TMDS transmitters use a current source to develop the low-voltage differential signal at the receiver end of the DC-coupled TMDS transmission line, and constitute open termination for reflected waveforms. As a result, signal reflections created by traces, packaging, connectors, and the cable can arrive at the transmitter with increased amplitude. To reduce these reflections, the HDMI transmitter port has an internal termination option of 150 Ω for single-ended termination, and 300 Ω for differential termination. This termination reduces the amplitude of the reflected signal, but it also lowers the common mode input voltage at the sink. Lattice Semiconductor recommends turning internal source termination off when the transmitter operates less than or equal to 165 MHz, and turning it on for frequencies above 165 MHz. 2.13.4. HDCP Encryption Engine/XOR Mask The HDMI transmitter provides an HDCP encryption engine that contains the logic necessary to encrypt the incoming audio and video data, and includes support for HDCP authentication and repeater checks. The system microcontroller controls the encryption process by using a set sequence of register reads and writes. An algorithm uses HDCP keys and a Key Selection Vector (KSV), stored in the HDCP key ROM to calculate a number that is then applied to an XOR mask. This process encrypts the audio and video data on a pixel-by-pixel basis during each clock cycle. 2.13.5. HDCP Key ROM The SiI9612 video processor comes preprogrammed with a set of production HDCP keys for the HDMI transmitter. The keys are stored in an internal ROM. System manufacturers do not need to purchase key sets from the Digital Content Protection LLC. Lattice Semiconductor handles all purchasing, programming, and security for the HDCP keys. The preprogrammed HDCP keys provide the highest level of security because there is no way to read the keys once the device is programmed. Customers must sign the HDCP license agreement (www.digital-cp.com) or be under a specific NDA with Lattice Semiconductor before receiving SiI9612 samples. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 17 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.13.6. Audio Return Channel The SiI9612 video processor provides an Audio Return Channel (ARC) input to receive an IEC60958-1 or IEC61937 audio stream from the connected sink device through the utility pin of the HDMI cable. The SiI9612 device supports only single mode ARC. The SiI9612 ARC input can be made compatible for common mode ARC by using an AC-coupling network between the HPD and utility pins of the HDMI connector of the HDMI output port and the SiI9612 ARC pin. 2.13.7. DDC Master I2C Interface 2 The SiI9612 HDMI transmitter includes a DDC master I C interface for direct connection to the HDMI cable. The DDC 2 master I C interface is used for two purposes: To read the EDID of the connected downstream device, To perform HDCP authentication of the connected downstream device. The host uses the DDC master logic to read the EDID by programming the target address, offset, and number of bytes. When completed, or when the DDC master FIFO becomes full, an interrupt signal is sent to the host so that the host can read data out of the FIFO. The TPI hardware uses the DDC master to carry out HDCP authentication tasks. The request to perform HDCP authentication is initiated by the host, but it does not access the DDC master directly. 2.13.8. Receiver Sense and Hot Plug Detection The HDMI transmitter can detect a connected device through the Hot Plug Detect (HPD) input signal or the internal Receiver Sense (RSEN) logic. When HIGH, the HPD signal indicates to the transmitter that the EDID of the connected receiver is readable. The RSEN can be used to detect whether the attached device is powered by sensing the termination in the attached device. An interrupt can be generated whenever there is a change in the state of the HPD or RSEN signal. 2.13.9. Interrupts The Interrupt logic in the HDMI transmitter buffers interrupt events from different sources. Receiver Sense and Hot Plug Interrupts are also available in power-down mode. The logic for handling these interrupts when all clocks are disabled is also part of this block. The INT pin provides an interrupt signal to the system microcontroller when any of the following occur: Monitor Detect (either from the HPD input level or from the receiver sense feature) changes VSYNC (useful for synchronizing a microcontroller to the vertical timing interval) Error in the audio format DDC FIFO status changes HDCP authentication error 2.14.HDMI Input The SiI9612 video processor integrates an HDMI receiver that accepts 300 MHz inputs such as 1080p @ 60 Hz 3D and 4K x 2K video formats. It offers a full video and audio processing pipeline, integrated HDCP keys, and a decryption engine. MHL mode is available with support for PackedPixel mode. 2.14.1. TMDS Receiver Core The HDMI receiver core is the latest generation core and can receive TMDS data up to 300 MHz. The core performs 10to 8-bit TMDS decoding on the video data, and 10- to 4-bit TMDS decoding on the audio data received from the three TMDS differential data lines, along with a TMDS differential clock. The TMDS core can sense a stopped clock or stopped video and software can put the video processor into power down mode. Adaptive equalization is applied to the input signal to counter high-frequency attenuation resulting from long cables, thus ensuring reliable data recovery. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet The receiver core operates in either HDMI or MHL mode. In MHL mode, the receiver core demultiplexes a single TMDS data channel into its three component logical channels (two for PackedPixel mode) of 8 bits each using a common mode clock signal carried on the same TMDS channel. 2.14.2. Deep Color Support The SiI9612 video processor detects deep color packets in the HDMI data stream and automatically decodes the proper pixel clock setting and output bus width. The deep color mode can be read from registers as 24 bits, 30 bits, or 36 bits per pixel, up to 1080p @ 60 Hz. An interrupt can be generated whenever the deep color mode changes. 2.14.3. MHL Receiver The HDMI input of the SiI9612 video processor can be configured as a Mobile High-definition Link (MHL) receiver. When an MHL source is connected, an MHL cable detect sense signal from the cable is asserted and sent to the SiI9612 device, and also to the host microcontroller as an interrupt to configure the receiver port as an MHL port, and to prepare for the CBUS discovery process. The MHL receiver supports PackedPixel mode, which encodes YCbCr 4:2:2 pixel data using 16 bits per pixel rather than 24 bits per pixel as in the other pixel encoding modes. The incoming pixel clock rate may be as high as 150 MHz in this mode, with a link clock rate of half of the pixel clock, which allows MHL to support 1080p @ 60 Hz video. The maximum link clock rate remains 75 MHz in PackedPixel mode. 2.14.4. HDCP Decryption Engine/XOR Mask The HDMI receiver provides an HDCP decryption engine to decrypt protected audio and video data transmitted by the source device. Decryption is enabled only after the successful completion of an authentication protocol between the source device and the HDMI receiver. This process is driven by the source device through a set sequence of read and writes through the DDC channel. A resulting calculated value is applied to an XOR mask during each clock cycle to decrypt the audio-visual data. The HDMI receiver also contains all the necessary logic to support full HDCP repeaters. The KSV FIFO can store a KSV list consisting of up to 16 devices. 2.14.5. HDCP Embedded Keys The SiI9612 device is preprogrammed with a set of production HDCP keys for the HDMI receiver. The keys are stored on the chip in nonvolatile memory. Lattice Semiconductor handles all purchasing, programming, and security for the HDCP keys. Before receiving samples of the SiI9612 video processor, customers must sign the HDCP license agreement (available from Digital Content Protection LLC) or a special NDA with Lattice Semiconductor. 2.14.6. EDID RAM Block An EDID block is supported on the HDMI receiver port. The EDID block consists of 256 bytes of RAM to contain the EDID data structure. This memory, comprised of SRAM, is volatile and must be initialized by software during power up. 2.15.Audio Input Processing The SiI9612 video processor provides multiple ways to accept digital audio signals for insertion onto the HDMI output 2 stream. The HDMI transmitter receives the audio stream through an I S or S/PDIF port. Audio data can come from one of many sources for each interface, controlled by a multiplexer. This is illustrated in Figure 2.2 on page 9. All major audio encoding formats are supported, including LPCM audio, one-bit audio, and bitstream audio formats including high-bitrate audio. 2.15.1. I2S Audio Input 2 2 There are two external I S ports on the SiI9612 device. The first I S port is comprised of three signal pins: AI_SCK, AI_WS, and AI_SD. The signal pins are dedicated inputs intended to support 2-channel linear pulse code modulation 2 (LPCM) audio. This I S input port accepts audio sample frequencies of 32, 44.1, 48, 88.2, 96, 176.4, and 192 kHz. 2 The second I S port has seven signal pins: AO_MCLK, AO_SCK, AO_WS, and AO_SD[3:0]. All pins except AO_MCLK are bidirectional. The direction of these pins is controlled by a software programmable register. These pins default to © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 19 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet outputs. When the pins are configured as inputs, they enable an input of up to eight channels of LPCM audio for 2 insertion onto the HDMI output. The I S input supports sampling frequencies of 32 to 192 kHz. 2 The multichannel I S interface also supports high-bitrate audio formats like Dolby® TrueHD and DTS-HD Master Audio™. 2 Only one of the I S ports can be selected to send audio data to the HDMI transmitter at any given time. 2.15.2. Direct Stream Digital Input Seven pins are used for the Direct Stream Digital (DSD) interface that provides 6-channel one-bit audio data. This interface 2 is for Super Audio Compact Disc (SACD) applications. The DSD input pins are mapped to the multichannel I S pins and the S/PDIF input pin of the SiI9612 device as shown in Table 2.3 below. The one-bit audio inputs are sampled on the positive edge of the DSD clock, assembled into 56-bit packets, and mapped to the appropriate FIFO. The Audio InfoFrame, instead of the Channel Status bits, carries the sampling information for one-bit audio. The one-bit audio interface supports input clock frequencies of 2.822 MHz (64 • 44.1 kHz) and 5.645 MHz (64 • 88.2 kHz). Table 2.3. DSD Input Pin Mapping DSD Signal DCLK DR0 Pin # 33 34 Pin Name AO_SCK AO_WS DL0 DR1 32 31 AO_SD0 AO_SD1 DL1 DR2 DL2 30 29 28 AO_SD2 AO_SD3 AI_SPDIF 2.15.3. S/PDIF Input The SiI9612 device can accept digital audio from a S/PDIF input pin. The Sony/Philips Digital Interface Format (S/PDIF) interface is usually associated with compressed audio formats such as Dolby® Digital (AC-3), DTS, and the more advanced variants of these formats. The S/PDIF interface also supports the LPCM format at sampling frequencies of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. 2.15.4. Requirement for an MCLK The video processor includes an integrated MCLK generator for operation without requiring an external clock PLL. This removes the requirement for an MCLK input on the device for creating the time stamp value used in audio clock recovery. 2.15.5. Audio Downsampler The SiI9612 device has an audio downsampler function that downsamples the incoming two-channel audio data and sends the result over the HDMI link. The audio data can be downsampled by one-half or one-fourth with register control. Conversions from 192 kHz to 48 kHz, 176.4 kHz to 44.1 kHz, 96 kHz to 48 kHz, and 88.2 kHz to 44.1 kHz are supported. Some limitations in the audio sample word length, when using this feature, may need special consideration in a real application. When enabling the audio downsampler, the Channel Status registers for the audio sample word lengths sent over the HDMI link always indicate the maximum possible length. For example, if the input S/PDIF stream was in 20-bit mode with 16 bits valid after enabling the downsampler, the Channel Status indicates 20-bit mode with 20 bits valid. Audio sample word length is carried in bits 33 through 35 of the Channel Status register over the HDMI link, as shown in Table 2.4 on the next page. These bits are always set to 0b101 when enabling the downsampler feature. Audio data is not affected because zeroes are placed into the LSBs of the data, and the wider word length is sent across the HDMI link. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Table 2.4. Channel Status Bits Used for Word Length Bit Audio Sample Word Length 35 34 33 0 0 0 Maximum Word Length 32 0 1 Sample Word Length (bits) Note Not Indicated — 0 0 0 1 1 0 0 0 16 18 2 2 1 1 0 0 0 1 0 0 19 20 2 2, 4 1 0 0 1 0 0 0 0 1 0 1 1 17 Not Indicated 20 2 3 3 0 1 1 0 0 0 1 1 22 23 3 3 1 1 0 1 1 0 1 1 24 21 3, 4 3 Notes: 1. Maximum audio sample word length (MAXLEN) is 20 bits if MAXLEN = 0 and 24 bits if MAXLEN = 1. 2. Maximum audio sample word length is 20. 3. Maximum audio sample word length is 24. 4. Bits [35:33] are always 0b101 when the downsampler is enabled. 2.15.6. High-bitrate Audio on HDMI The high-bitrate compression standards, such as Dolby® TrueHD and DTS-HD Master Audio™, transmit data at bitrates as high as 18 Mb/s or 24 Mb/s. Because these bit rates are so high, Blu-ray decoders, HDMI transmitters (as source 2 devices), and DSPs and HDMI receivers (as sink devices) must carry the data using four I S lines rather than using a 2 single very-high-speed S/PDIF interface or I S bus (see Figure 2.7). MPEG Transmitter Receiver DSP Figure 2.7. High-speed Data Transmission 2 The high-bitrate audio stream is originally encoded as a single stream. To send the stream over four I S lines, the DVD 2 decoder splits it into four streams. Figure 2.8 shows the high-bitrate stream before it has been split into four I S lines, and Figure 2.9 on the next page shows the same audio stream after being split. Each sample requires 16 cycles of the 2 I S clock (SCK). Sample 0 Sample 1 Sample 2 Sample 3 Sample 4 Sample 5 ... Sample N-1 Sample N 16-Bits 0 1 2 3 4 5 6 7 8 9 101112131415 Figure 2.8. High-bitrate Stream before and after Reassembly and Splitting © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 21 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet WS Left Right Left Right SD0 Sample 0 Sample 1 Sample 8 Sample 9 SD1 Sample 2 Sample 3 Sample 10 Sample 11 SD2 Sample 4 Sample 5 Sample 12 Sample 13 SD3 Sample 6 Sample 7 Sample 14 Sample 15 Figure 2.9. High-bitrate Stream after Splitting 2.15.7. I2S-to-SPDIF Conversion 2 The SiI9612 video processor includes audio processing to convert LPCM audio from the 2-channel I S input or from the 2 I S output of the HDMI receiver to an IEC 60958 formatted audio stream. The converted audio stream is sent to the S/PDIF output pin. The conversion works only for 2-channel audio. 2.16.Audio Output Processing The SiI9612 video processor supports audio extraction from the received HDMI/MHL streams. It can send the digital 2 audio to a S/PDIF output, four I S outputs (SD[3:0]), or six one-bit audio outputs. In addition, the audio output signals can be routed directly to the audio input ports of the HDMI transmitter using an internal audio data path. 2 Internal routing, multiplexing and processing of I S and S/PDIF audio signals are illustrated in Figure 2.2 on page 9. 2.16.1. S/PDIF Output The S/PDIF output transmits 2-channel uncompressed LPCM data (IEC 60958) or a compressed bitstream for multichannel (IEC 61937) formats. The audio data output logic forms the audio data output stream from the HDMI audio packets. The S/PDIF output supports audio sampling rates from 32 kHz to 192 kHz. A separate master clock output (MCLK), coherent with the S/PDIF output, is provided for time stamping purposes. 2.16.2. I2S Audio Output 2 An I S output port with four data lines on the SiI9612 device enables 8-channel digital audio output at sample rates 2 from 32 to 192 kHz. The I S interface is highly programmable through registers to allow interfacing with a wide range of 2 2 audio DACs or audio DSPs with I S inputs. The I S output port consists of signal pins AO_MCLK, AO_SCK, AO_WS, and AO_SD[3:0]. Additionally, an MCLK output signal is provided with a frequency that is programmable as an integer multiple of the audio sample rate fS. MCLK frequencies support various audio sample rates as shown in Table 2.5. Table 2.5. Supported MCLK Frequencies 2 Multiple of fS Audio Sample Rate, fS: I S and S/PDIF Supported Rates 32 kHz 44.1 kHz 48 kHz 88.2 kHz 96 kHz 176.4 kHz 192 kHz 128 256 384 4.096 MHz 8.192 MHz 12.288 MHz 5.645 MHz 11.290 MHz 16.934 MHz 6.144 MHz 12.288 MHz 18.432 MHz 11.290 MHz 22.579 MHz 33.864 MHz 12.288 MHz 24.576 MHz 36.864 MHz 22.579 MHz 45.158 MHz — 24.576 MHz 49.152 MHz — 512 16.384 MHz 22.579 MHz 24.576 MHz 45.158 MHz 49.152 MHz — — 2 The I S output pins can be reconfigured as inputs for source-specific applications, such as a Blu-ray player where the 2 SoC supplies the multichannel audio to the SiI9612 device directly through the I S bus. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.16.3. One-bit Audio Output The SiI9612 device can output six DSD/SACD streams and a clock for up to 6-channel support. The DSD streams are 2 output on the multichannel I S pins and the S/PDIF output pin according to Table 2.6. One-bit audio supports 64 • fS, with fS being 44.1 kHz or 88.2 kHz. The one-bit audio outputs are synchronous to the positive edge of the DSD Clock. For one-bit audio, the sampling information is carried in the Audio InfoFrame instead of the Channel Status bits. Table 2.6. DSD Output Pin Mapping DSD Signal Pin # Pin Name DCLK DR0 DL0 33 34 32 AO_SCK AO_WS AO_SD0 DR1 DL1 31 30 AO_SD1 AO_SD2 DR2 DL2 29 37 AO_SD3 AO_SPDIF 2.16.4. High-bitrate Audio Support The SiI9612 video processor supports the extraction of high-bitrate audio packets from the HDMI input. The extracted 2 2 data is streamed out through the I S output port on four I S data lines at 192 kHz packet rate each. 2 Figure 2.10 shows the layout of the high-bitrate audio samples on the four I S lines. WS Left Right Left Right SD0 Sample 0 Sample 1 Sample 8 Sample 9 SD1 Sample 2 Sample 3 Sample 10 Sample 11 SD2 Sample 4 Sample 5 Sample 12 Sample 13 SD3 Sample 6 Sample 7 Sample 14 Sample 15 2 Figure 2.10. Layout of High-bitrate Audio Samples on I S 2.16.5. Auto Audio Configuration The SiI9612 video processor can control the audio output based on the current states of CablePlug, FIFO, Video, ECC, ACR, PLL, InfoFrame and HDMI. Audio output is only enabled when all necessary conditions are met. If any critical condition is missing, the audio output is disabled automatically. Each of these events, which the logic monitors, can be turned on or off separately through a set of programmable registers. 2.16.6. Soft Mute On command from a register bit or when automatically triggered with Automatic Audio Control (AAC), the video processor progressively reduces the audio data amplitude to mute the sound in a controlled manner. This is useful when there is an interruption to the HDMI audio stream (or an error) to prevent any audio pop from being sent to the 2 I S or S/PDIF outputs. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 23 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.17.CEC Interface The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC devices and a CEC master. A CEC controller compatible with the Lattice Semiconductor CEC Programming Interface (CPI) 2 is included on the chip. This CEC controller has a high-level register interface accessible through the I C or SPI interface and can send and receive CEC commands. This controller makes CEC control very easy and straightforward, and removes the burden of having a host CPU perform these low-level transactions on the CEC bus. 2.18.GPIO The SiI9612 video processor has four General Purpose I/O (GPIO) pins. Each GPIO pin supports the following functions: Input mode: The value can be read through a register. Output mode: The value can be set through a programmable register. The GPIO pins can be reconfigured as a Serial Peripheral Interface (SPI) interface for programming the chip. Refer to the Pin Strapping section on page 25 for more information. 2.19.Control and Configuration 2.19.1. Register/Configuration Logic The register/configuration logic block incorporates all the registers required for configuring and managing the features of the SiI9612 video processor. These registers are used to perform HDCP authentication, audio/video/auxiliary format processing, CEA-861B InfoFrame packet format, and power-down control. 2 The registers are accessible from one of two I C serial ports. The first is the DDC port located on the HDMI receiver port, and is connected through the HDMI cable to the upstream HDMI transmitter. It is used to exchange values 2 between the transmitter and the SiI9612 video processor for HDCP operation. The second is the local I C port that controls the SiI9612 device from the display system. The local device registers controlled by the display system can also be accessed through a Serial Peripheral Interface (SPI) bus. The local device registers are accessed using a 16-bit addressing scheme. Refer to the Feature Information section on page 44 for details. 2.19.2. I2C Serial Ports 2 The SiI9612 video processor provides three I C serial interfaces: DDC receiver port to communicate back to the upstream HDMI or DVI host, DDC master port to read the EDID or perform HDCP authentication of the downstream device, I C port for initialization and control by a local microcontroller in the display. 2 Refer to the Feature Information section on page 44 for a more detailed description of these serial ports. 2 The device address for the local I C interface can be set as 0x30 or 0x32 through a strapping pin (see Table 2.7). 2.19.3. SPI Serial Bus The SiI9612 device SPI serial interface employs a simple four-wire synchronous serial interface with unidirectional data lines. The SPI interface allows the local microcontroller to access the SiI9612 device registers at up to 10 MHz bitrate. 2 This is a more efficient method of configuring the device when compared to I C mode. Refer to the Feature Information section on page 44 for a more detailed description of SPI. 2.19.4. Delay from Reset Deactivation to Register Access Once the Reset pin of the SiI9612 device is deactivated, the software must wait 100 ns before accessing the device 2 registers through either the local I C or SPI bus. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2.20.Pin Strapping 2 The SiI9612 device supports pin strapping configuration to select the default device I C address and the mode of the SPI pins. These settings are shown in Table 2.7. The logical value on these pins is latched by the SiI9612 device on the rising edge of RESET. See the Digital Audio Output Pins table on page 40 for more information. Table 2.7. Pin Strapping Options Pin Name AO_MUTE Mode Name I2C_ADDRSEL AO_SPDIF/DL2(OUT) GPIO_MODE Description 2 Select I C Address (0x30/0x32). 0 – Address 0x30 1 – Address 0x32 Select GPIO Mode. 0 – SPI pins used as SPI 1 – SPI pins used as GPIO 2.21.Power Supply Sequencing There are no power supply sequencing requirements for the SiI9612 device. 2.22.Audio PLL Reset Once the SiI9612 device is powered on and all the power supplies of the device have reached their normal operating voltages, the audio PLL must be reset to ensure normal operation. The audio PLL is reset by asserting its Power Down bit for at least 1 ms. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 25 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 3. Electrical Specifications 3.1. Absolute Maximum Conditions Table 3.1. Absolute Maximum Conditions Symbol IO_VDD33 IO_APVDD33 Parameter I/O Pin Supply Voltage Audio PLL I/O Supply Voltage Min –0.3 –0.3 Typ — — Max 4.0 4.0 Units V V Notes 1, 2, 3 1, 2, 3 RX_AVDD10 RX_AVDD33 TMDS RX Analog 1.0 V Supply Voltage TMDS RX Analog 3.3 V Supply Voltage –0.3 –0.3 — — 1.5 4.0 V V 1, 2 1, 2 TX_AVDD10 TX_PVDD10 VP_AVDD10 TMDS TX Analog Supply Voltage TMDS TX PLL Supply Voltage Video PLL Supply Voltage –0.3 –0.3 –0.3 — — — 1.5 1.5 1.5 V V V 1, 2 1, 2 1, 2 AP_AVDD10 DVDD10 Audio PLL Supply Voltage Digital Logic Supply Voltage –0.3 –0.3 — — 1.5 1.5 V V 1, 2 1, 2 IO_VDD5 VI V5V-Tolerant I/O Pin 5 V Supply Voltage Input Voltage Input Voltage on 5 V tolerant Pins –0.3 –0.3 –0.3 — — — 5.7 IO_VDD33 + 0.3 5.7 V V V 1, 2 1, 2 — TJ Junction Temperature — — 125 C — C — TSTG Storage Temperature –65 — 150 Notes: 1. Permanent device damage can occur if absolute maximum conditions are exceeded. 2. Functional operation should be restricted to the conditions described under normal operating conditions. 3. Voltage undershoot or overshoot cannot exceed absolute maximum conditions. 4. Refer to the SiI9612 Qualification Report for information on ESD performance. 3.2. Normal Operating Conditions Table 3.2. Normal Operating Conditions Symbol Parameter Min Typ Max Units Notes IO_VDD33 IO_APVDD33 RX_AVDD10 I/O Pin Supply Voltage Audio PLL I/O Supply Voltage TMDS RX Analog 1.0 V Supply Voltage 3.14 3.14 0.95 3.3 3.3 1.0 3.47 3.47 1.05 V V V — — — RX_AVDD33 TX_AVDD10 TMDS RX Analog 3.3 V Supply Voltage TMDS TX Analog Supply Voltage 3.14 0.95 3.3 1.0 3.47 1.05 V V — — TX_PVDD10 VP_AVDD10 AP_AVDD10 TMDS TX PLL Supply Voltage Video PLL Supply Voltage Audio PLL Supply Voltage 0.95 0.95 0.95 1.0 1.0 1.0 1.05 1.05 1.05 V V V — — — DVDD10 IO_VDD5 Digital Logic Supply Voltage I/O Pin 5 V Supply Voltage 0.95 4.75 1.0 5.0 1.05 5.25 V V — 1 TA Ambient Temperature (with power applied) 0 25 70 C — Ambient Thermal Resistance (Theta JA) — — 25 ja C/W Notes: 1. The IO_VDD5 pin is the supply voltage for the CSCL, CSDA, CEC, CDSENSE, TX_DSCL, TX_DSDA, RX_DSDA, RX_DSCL and RX_HPD/CBUS pins. It must be connected to a 5 V power supply. 2. Airflow at 0 m/s. 4-layer PCB. 2 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 3.3. DC Specifications Table 3.3. Digital I/O Specifications Symbol Parameter VIH HIGH-level Input Voltage VIL LOW-level Input Voltage DDC VTH+ DDC VTH- LOW-to-HIGH Threshold, DDC Bus HIGH-to-LOW Threshold, DDC Bus VOH VOL Pin Type LVTTL Schmitt LVTTL Schmitt 1 Conditions Min Typ Max Units Notes — 2.0 — — V — — — — 0.8 V — Schmitt Schmitt — — 3.0 — — — — 1.5 V V 2 2 HIGH-level Output Voltage LOW-level Output Voltage LVTTL LVTTL — — 2.4 — — — — 0.4 V V — — VOL DDC VOL I2C LOW-level Output Voltage LOW-level Output Voltage Open-drain Open-drain IOL = –3 mA IOL = –3 mA — — — — 0.4 0.4 V V — — IOL Output Leakage Current — High-impedance –10 — 100 A 3 IIL Input Leakage Current — High-impedance –10 — 100 VOUT = 2.4 V 6 — — A mA — VOUT = 0.4 V VOUT = 2.4 V 6 8 — — — — mA mA — — 4 IOD6 6 mA Digital Output Drive Output IOD8 8 mA Digital Output Drive Output RPD Internal Pull-down Resistor Outputs VOUT = 0.4 V — 8 — — 46 — — mA kΩ — — IOPD Output Pull-down Current Outputs IO_VDD33 = 3.47 V — — 100 A 3 IIPD Input Pull-down Current Input IO_VDD33 = 3.47 V — — 100 A 4 Notes: 1. Refer to the Pin Diagram and Pin Descriptions section beginning on page 38 for pin type designations for all package pins. 2. Schmitt trigger input pin thresholds VTH+ and VTH- correspond to VIH and VIL, respectively. 3. The chip includes an internal pull-down resistor on many of the output pins. When in the high-impedance state, these pins draw a pull down current according to this specification when the signal is driven HIGH by another source device. 4. The chip includes an internal pull-down resistor on many of the input pins. These pins draw a pull-down current according to these values when the signal is driven HIGH by another device. Table 3.4. TMDS Input DC Specifications – HDMI Mode Symbol Parameter Conditions Min Typ Max Units VIDFH Differential Mode Input Voltage — 150 — 1200 mV VICMH Common Mode Input Voltage — RX_AVDD33 – 400 — RX_AVDD33 – 37.5 mV Conditions Min Typ Max Units Table 3.5. TMDS Input DC Specifications – MHL Mode Symbol Parameter VIDC Single-ended Input DC Voltage — RX_AVDD33 – 1200 — RX_AVDD33 – 300 mV VIDFM Differential Mode Input Swing Voltage — 200 — 1000 mV VICMM Common Mode Input Swing Voltage — 170 — Min (720, 0.85 VIDF) mV © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 27 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Table 3.6. TMDS Output DC Specifications Symbol Parameter VSWING Single-ended Output Swing Voltage VH VL Conditions Min Typ Max Units 400 — 600 mV TX_AVDD33 – 10 — TX_AVDD33 + 10 mV TX_AVDD33 – 200 — TX_AVDD33 + 10 mV AVDD33 – 600 — AVDD33 – 400 mV AVDD33 – 700 — AVDD33 – 400 mV Conditions Min Typ Max Units — 160 — 600 mV Conditions — Min 2.0 Typ — Max — Units V — — — — 2.5 — — — — 0.8 — 0.6 V V V Power Off — — 1.8 A Conditions — Min 1.0 Typ — Max — Units V — — — 0.6 1.9 V V RLOAD = 50 Ω ≤ 165 MHz TMDS clock Single-ended HIGH-level Output Voltage > 165 MHz TMDS clock ≤ 165 MHz TMDS clock Single-ended LOW-level Output Voltage > 165 MHz TMDS clock Table 3.7. Single Mode Audio Return Channel DC Specifications Symbol VIS_ARC Parameter Input Swing Amplitude Table 3.8. CEC DC Specifications Symbol VTH+CEC Parameter LOW-to-HIGH Threshold VTH-CEC VOH_CEC VOL_CEC HIGH-to-LOW Threshold HIGH-level Output Voltage LOW-level Output Voltage IIL_CEC Input Leakage Current Table 3.9. CBUS DC Specifications Symbol VIH_CBUS Parameter High-level Input Voltage VIL_CBUS VOH_CBUS Low-level Input Voltage High-level Output Voltage IOH = 100 A — 1.5 VOL_CBUS Low-level Output Voltage IOL = –100 A — — 0.2 V ZDSC_CBUS ZON_CBUS Pull-down Resistance – Discovery Pull-down Resistance – Active — — 800 90 1000 100 1200 110 Ω kΩ IIL_CBUS Input Leakage Current High-impedance — — 1 CCBUS Capacitance Power On — — 80 A pF © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 3.3.1. DC Power Supply Pin Specifications Table 3.10. Total Power Dissipation Symbol Parameter Conditions Min Typ Max Units IIO_VDD33 I IO_APVDD33 Supply Current for IO_VDD33 Supply Current for IO_APVDD33 — — — — — — 6 5 mA mA IRX_AVDD10 IRX_AVDD33 ITX_AVDD10 Supply Current for RX_AVDD10 Supply Current for RX_AVDD33 Supply Current for TX_AVDD10 — — — — — — — — — 56 61 34 mA mA mA ITX_PVDD10 IVP_AVDD10 Supply Current for TX_PVDD10 Supply Current for VP_AVDD10 — — — — — — 8 12 mA mA IAP_AVDD10 IDVDD10 IIO_VDD5 Supply Current for AP_AVDD10 Supply Current for DVDD10 Supply Current for IO_VDD5 — — — — — — — — — 3 784 7 mA mA mA Total Total Power — — — 1.23 W Notes: Maximum power dissipation has been measured under the following operating conditions: 1. 70 C ambient temperature with device power supplies set to 5% over normal operating values. 2. Scaling 480p @ 60 Hz to 1080p @ 60 Hz with a pseudo random test pattern and video processing enabled. Table 3.11. Power-down Mode Power Dissipation Symbol Parameter Conditions Min Typ Max Units IPD_1V I PD_3.3V 1 V Power Supply Current 3.3 V Power Supply Current — — — — — — 220 7 mA mA IPD_5V Total 5 V Power Supply Current Total Power — — — — — — 7 292 mA mW Note: Maximum power dissipation has been measured at 70 C ambient temperature with supplies set to 5% over normal operating values, and no switching applied on the input and output ports. 3.4. AC Specifications Table 3.12. TMDS Input AC Timing Specifications – HDMI Mode Symbol TDPS Parameter Intrapair Differential Input Skew TCCS FRXC Channel-to-Channel Differential Input Skew Differential Input Clock Frequency TRXC TDIJIT Differential Input Clock Period Differential Input Clock Jitter Tolerance Conditions @300 MHz Min — Typ — Max 0.15TBIT + 112 Units ps — — — 25 — — 0.2TPIXEL + 1.78 300 ns Figure 4.3 MHz — — @300 MHz 3.33 — — — 40 0.3 Conditions — Min — Typ — Max 93 Units ps ns TBIT Figure — — — Table 3.13. TMDS Input AC Timing Specifications – MHL Mode Symbol TSKEW_DF Parameter Input Differential Intrapair Skew TSKEW_CM FRXC Input Common Mode Intrapair Skew Differential Input Clock Frequency — — — 25 — — 93 300 ps MHz TRXC TCLOCK_JIT TDATA_JIT Differential Input Clock Period Common Mode Clock Jitter Tolerance Differential Data Jitter Tolerance — @300 MHz @300 MHz 3.33 — — — — — 40 0.8TBIT 0.6TBIT ns ps Ps © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 29 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Table 3.14. TMDS Output AC Timing Specifications Mode Symbol Parameter Conditions Min Typ Max Units TTXDPS TTXRT TTXFT Intrapair Differential Output Skew Data/Clock Rise Time Data/Clock Fall Time — 20% – 80% 80% – 20% — 75 75 — — — 0.15 — — TBIT ps ps FTXC TTXC Differential Output Clock Frequency Differential Output Clock Period — — 25 3.33 — — 300 40 MHz ns TDCDUTY TDOJIT Differential Output Clock Duty Cycle Differential Output Clock Jitter — — 40% — — — 60% 0.25 TTXC TBIT Table 3.15. CEC AC Specifications Symbol TR_CEC Parameter Rise Time Conditions 10% – 90% Min — Typ — Max 250 Units TF_CEC Fall Time 90% – 10% — — 50 s Conditions 1 MHz clock Min 0.8 Typ — Max 1.2 Units — –1% — +1% s TBIT_CBUS s Table 3.16. CBUS AC Specifications Symbol TBIT_CBUS Parameter Bit Time TBJIT_CBUS Bit-to-Bit Jitter TDUTY_CBUS TR_CBUS Duty Cycle of 1 Bit Rise Time — 0.2 V – 1.5 V 40% 5 — — 60% 200 TBIT_CBUS ns TF_CBUS ΔTRF Fall Time Rise-to-Fall Time Difference 0.2 V – 1.5 V — 5 — — — 200 100 ns ns 2 Table 3.17. I S Audio Input Port Timing Specifications Symbol FS_I2S Parameter Sample Rate Conditions — Min 32 Typ — Max 192 Units kHz Figure — Notes — TSCKCYC TSCKIDUTY I S Cycle Time 2 I S Duty Cycle — — — 90% — — 1.0 110% UI UI Figure 4.4 Figure 4.4 1 1 TI2SSU I S Setup Time — 15 — — ns Figure 4.4 2 TI2SHD I S Hold Time — 5 — — ns Figure 4.4 Notes: 2 1. Proportional to unit time (UI) according to sample rate. Refer to the I S Specification. 2 2. Set up and hold minimum times are based on 13.388 MHz sampling, which is adapted from Figure 3 of the Philips I S Specification. 2 3. All parameters are applicable to the I S output port signals when reconfigured as inputs. 2 2 2 2 Table 3.18. S/PDIF Input Port Timing Specifications Symbol Parameter FS_SPDIF TSPICYC TSPIDUTY Sample Rate AI_SPDIF Cycle Time* AI_SPDIF Duty Cycle* Conditions Min Typ Max Units Figure — — — 32 — 90% — — — 192 1.0 110% kHz UI UI — Figure 4.5 Figure 4.5 *Note: Proportional to unit time (UI) according to sample rate. Refer to the IEC60958 Specification. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2 Table 3.19. I S Audio Output Port Timing Specifications Symbol Parameter Conditions Min Typ Max Units TTR THC TLC AO_SCK Clock Period AO_SCK Clock HIGH Time AO_SCK Clock LOW Time CL = 10 pF CL = 10 pF CL = 10 pF 1.00 0.35 0.35 — — — — — — Ttr Ttr Ttr TSU THD Setup Time, AO_SCK to AO_SD/WS Hold Time, AO_SCK to AO_SD/WS CL = 10 pF CL = 10 pF 0.4Ttr – 5 0.4Ttr – 5 — — — — ns ns TSCKODUTY TSCK2SD AO_SCK Duty Cycle AO_SCK to AO_SD or AO_WS Delay CL = 10 pF CL = 10 pF 40% –5 — — 60% +5 Ttr ns Figure Notes 1, 2 1, 2 1, 2 Figure 4.6 1, 2 1, 2 1, 2 1, 3 Notes: 1. Guaranteed by design. 2 2. Refer to Figure 4.6 on page 35. Meets timings in the Philips I S Specification. 3. Applies also to SDC-to-WS delay. Table 3.20. S/PDIF Output Port Timing Specifications Symbol TSPOCYC Parameter AO_SPDIF Cycle Time Conditions CL = 10 pF Min — Typ 1.0 Max — Units UI Figure Notes 1, 2 FSPDIF TSPODUTY TMCLKCYC AO_SPDIF Frequency AO_SPDIF Duty Cycle AO_MCLK Cycle Time — CL = 10 pF CL = 10 pF 4 90% 20 — — — 24 110% 250 MHz UI ns Figure 4.7 3 2 1 FMCLK TMCLKDUTY AO_MCLK Frequency AO_MCLK Duty Cycle CL = 10 pF CL = 10 pF 4 40% — — 50 60% MHz TMCLKCYC Figure 4.8 1 — Notes: 1. Guaranteed by design. 2. Proportional to unit time (UI), according to sample rate. 3. S/PDIF is not a true clock, but is generated from the internal 128 fS clock, for fS from 32 to 192 kHz. Table 3.21. Crystal Clock Timings Symbol FXTAL* Parameter External Crystal Freq. Conditions — Min 26 Typ 27 Max 28.5 Units MHz Figure Figure 3.1 *Note: The XTALIN/XTALOUT pin pair must be driven with a clock in all applications. 3.3 V 163 161 27 MHz 18 pF IO_APVDD33 XTALIN SiI9612 1 M 162 XTALOUT 18 pF Figure 3.1. Crystal Clock Schematic 3.5. Control Timing Specifications Table 3.22. Reset Timings Symbol Parameter TRESET RESET# Signal LOW Time for Valid Reset Conditions Min Typ Max Units — 10 — — µs Figure Figure 4.1, Figure 4.2 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 31 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 2 Table 3.23. I C Control Signal Timings Symbol Parameter Conditions Min Typ Max Units Figure Notes TI2CDVD FRXDDC FTXDDC SDA Data Valid Delay from SCL Falling Edge Clock Rate on Rx DDC Port Clock Rate on Tx DDC Port CL = 400 pF CL = 400 pF CL = 400 pF — — — — — — 700 100 100 ns kHz kHz Figure 4.9 — — — 1 1, 2 kHz — 3 Figure Figure 4.10, Figure 4.11 Figure 4.10, Figure 4.11 Figure 4.10, Figure 4.11 Figure 4.10, Figure 4.11 2 FI2C Clock Rate on Local I C Port CL = 400 pF — — 400 Notes: 2 1. DDC ports are limited to 100 kHz by the HDMI Specification, and meet I C standard mode timings. 2. The operating frequency of the HDMI transmitter DDC port is programmable. 2 2 3. Local I C port (CSCL/CSDA) meets standard mode I C timing requirements to 400 kHz. Table 3.24. SPI Control Signal Timings Symbol Parameter Conditions Min Typ Max Units tCSs SPI_CS# Setup Time to SPI_CLK — 6 — — ns tCSh SPI_CS# Hold Time to SPI_CLK — 6 — — ns tTXs SPI_TX Setup Time to SPI_CLK — 6 — — ns tTXh SPI_TX Hold Time to SPI_CLK — 6 — — ns tRXp SPI_RX Output Time from SPI_CLK Falling Edge — 1 — 7 ns Figure 4.11 Note: Signal names are from the perspective of the host. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 4. Timing Diagrams 4.1. Reset Timing Diagrams VCC must be stable between the limits shown in the Normal Operating Conditions section on page 26 for TRESET before RESET# goes HIGH, as shown in Figure 4.1. Before accessing registers, RESET# must be pulled LOW for TRESET. This can be done by holding RESET# LOW until TRESET after stable power, or by pulling RESET# LOW from a HIGH state for at least TRESET, as shown in Figure 4.2. VCCmax VCCmin VCC RESET# T RESET Figure 4.1. Conditions for Use of RESET# RESET# TRESET Figure 4.2. RESET# Minimum Timing 4.2. TMDS Input Timing Diagrams RX0 RX1 RX2 TCCS VDIFF = 0V Figure 4.3. TMDS Channel-to-Channel Skew Timing © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 33 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 4.3. Digital Audio Input Timing Diagrams TSCKCYC TSCKIDUTY SCK 50 % TI2SSU SD[0:3], WS 50 % TI2SHD no change allowed 50 % 50 % Figure 4.4. I2S Input Timings T SPICYC T SPIDUTY 50% SPDIF Figure 4.5. S/PDIF Input Timings © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 4.4. Digital Audio Output Timing Diagrams TTR TSCKODUTY SCK TSCK2SD_MAX WS SD TSU Data Valid TSCK2SD_MIN THD Data Valid Data Valid 2 Figure 4.6. I S Output Timings TSPOCYC TSPODUTY 50% SPDIF Figure 4.7. S/PDIF Output Timings TMCLKCYC MCLK 50% 50% TMCLKDUTY Figure 4.8. MCLK Timings © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 35 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 4.5. Control Signal Timing Diagrams 4.5.1. I2C Timing Diagram CSDA, DSDA TI2CDVD CSCL, DSCL 2 Figure 4.9. I C Data Valid Delay 4.5.2. SPI Timing Diagrams SPI_CLK tCSh tCSs SPI_CS# tTXs tTXh SPI_TX A14 A13 A0 0 D7 D6 D0 Figure 4.10. SPI Write Setup and Hold Times SPI_CLK tCSh tCSs SPI_CS# tTXs tTXh SPI_TX A14 A13 A0 1 tRXp SPI_RX D7 D6 D0 Figure 4.11. SPI Read Setup and Hold Times © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 4.6. Calculating Setup and Hold Times for I2S Audio Output Bus Valid serial data is available at TSCK2SD after the falling edge of the first AO_SCK cycle, and then captured downstream using the active rising edge of AO_SCK one clock period later. The setup time of data-to-AO_SCK (TSU) and hold time of AO_SCK-to-data (THD) are a function of the worst case AO_SCK-to-output data delay (TSCK2SD). Figure 4.6 on page 35 illustrates this timing relationship. Note that the active AO_SCK edge (rising edge) is shown with an arrowhead. For a falling edge sampling clock, the logic is reversed. Table 4.1 shows the setup and hold time calculation examples for various audio sample frequencies. The setup and hold times for other audio sampling frequencies can also be calculated with the formula used in these examples. 2 Table 4.1. I S Setup and Hold Time Calculations Symbol Parameter TSU Setup Time, SCK to SD/WS = TTR – ( TSCKDUTY_WORST + TSCK2SD_MAX) = TTR – (0.6TTR + 5 ns ) = 0.4TTR – 5 ns THD Hold Time, SCK to SD/WS = ( TSCKDUTY_WORST – TSCK2SD_MIN ) = 0.4TTR – 5 ns FWS (kHz) FSCK (MHz) TTR (ns) Min (ns) 32 2.048 488 190 44.1 2.822 354 136 48 3.072 326 125 96 6.144 163 60 192 12.288 81 27 32 2.048 488 190 44.1 2.822 354 136 48 3.072 326 125 96 6.144 163 60 192 12.288 81 27 Note: The sample calculations shown are based on WS = 64 SCK rising edges. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 37 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 5. Pin Diagram and Pin Descriptions 5.1. Pin Diagram RX_HPD/CBUS RX_DSCL RX_DSDA TX_DSDA TX_DSCL CDSENSE CEC RSVDL CSDA CSCL RSVDNC DVDD10 AP_AVDD10 IO_APVDD33 XTALOUT XTALIN IO_APGND VP_AVDD10 DVDD10 Figure 5.1 shows the pin assignments of the SiI9612 video processor. Individual pin functions are described in the Pin Descriptions section on page 38. The package is a 9 mm × 9 mm, 76-pin MQFN, 0.4 mm pitch, with ePad that must be connected to ground. 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 IO_VDD5 1 57 DVDD10 MCAP33 2 56 DVDD10 INT 3 55 DVDD10 RX_AVDD10 4 54 DVDD10 RX_AVDD33 5 53 TX2+ RXC– 6 52 TX2– RXC+ 7 51 TX_AVDD10 RX0– 8 50 TX1+ RX0+ 9 49 TX1– RX1– 10 48 TX0+ RX1+ 11 47 TX0– RX2– 12 46 TX_AVDD10 RX2+ 13 45 TXC+ SiI9612 Top View ePad (GND) ARC IO_VDD33 19 39 HPD_TX 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 DVDD10 40 AO_SPDIF/DL2(OUT) 18 AO_MUTE DVDD10 AO_MCLK DVDD10 AO_WS/DR0 41 AO_SCK 17 AO_SD0/DL0 DVDD10 AO_SD2/DL1 TX_GND AO_SD1/DR1 42 AO_SD3/DR2 16 AI_SPDIF/DL2(IN) RESET# AI_SCK TX_PVDD10 AI_WS 43 AI_SD 15 SPI_RX/GPIO3 DVDD10 SPI_TX/GPIO2 TXC– SPI_CLK/GPIO1 44 SPI_CS#/GPIO0 14 DVDD10 RX_AVDD10 Figure 5.1. Pin Diagram © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 38 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 5.2. Pin Descriptions 5.2.1. HDMI Receiver Control Signal Pins Pin Name RX_DSCL Pin 75 Type Schmitt Open-drain 5 V tolerant Dir Input Description 2 DDC I C Clock for HDMI Receiver Port. 2 HDCP KSV, An, and Ri values are exchanged over an I C port during authentication. This pin does not present a current path to GND when the device is not powered. This pin requires an external 47 kΩ pull-up resistor as defined in the HDMI Specification. RX_DSDA 74 Schmitt Open-drain 5 V tolerant Input DDC I C Data for HDMI Receiver Port. 2 Output HDCP KSV, An, and Ri values are exchanged over an I C port during authentication. This pin does not present a current path to GND when the device is not powered. RX_HPD/CBUS 76 LVTTL/ CBUS 5 V tolerant CEC 70 CEC compliant 5 V tolerant CDSENSE 71 LVTTL Schmitt 5 V tolerant Input Hotplug Output Signal to HDMI Connector. Output In HDMI mode, this is a 5 V signal with 1 kΩ output impedance. It indicates that EDID is readable. In MHL mode, this pin serves as the CBUS signal. Input HDMI Compliant CEC I/O used to interface to CEC Devices. Output This pin connects to the CEC signal of all HDMI connectors in the system. This pin has an internal pull-up resistor. Input MHL Cable Detect Sense. 2 5.2.2. HDMI Receiver Differential Signal Data Pins Pin Name RX0+ Pin 9 RX0– RX1+ RX1– 8 11 10 RX2+ RX2– 13 12 RXC+ RXC– 7 6 Type TMDS Analog Dir Input Description HDMI Port TMDS Input Data Pairs. TMDS Analog Input HDMI Port TMDS Input Clock Pair. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 39 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 5.2.3. Digital Audio Output Pins Pin Name Pin Type AO_MCLK 35 AO_SCK* 33 AO_SD3/DR2* AO_SD2/DL1* 29 30 AO_SD1/DR1* AO_SD0/DL0* 31 32 LVTTL 5 V tolerant 6 mA LVTTL Schmitt 5 V tolerant 6 mA LVTTL Schmitt 5 V tolerant 6 mA AO_WS/ DR0* 34 AO_SPDIF/ DL2(OUT) 37 LVTTL Schmitt 5 V tolerant 6 mA LVTTL Schmitt 5 V tolerant 6 mA Dir Description Output Audio Master Clock Output. This pin has a weak internal pull-down resistor. Output I2S Serial Clock Output or DSD Clock Output. Input This pin has a weak internal pull-down resistor. Output I2S Serial Ch3 Data Output/DSD Serial Right Ch2 Data Output. Input I2S Serial Ch2 Data Output/DSD Serial Left Ch1 Data Output. 2 I S Serial Ch1 Data Output/DSD Serial Right Ch1 Data Output. 2 I S Serial Ch0 Data Output/DSD Serial Left Ch0 Data Output. AO_SD[3:0] pins have a weak internal pull-down resistor. Output I2S Word Select Output/DSD Serial Right Ch0 Data Output. Input This pin has a weak internal pull-down resistor. Input SPI/GPIO Mode Strapping. This pin is an input when the RESET# pin is asserted. On the rising edge of RESET#, the level on this pin is latched and sets the operational mode of the SPI/GPIO pins. LOW – SPI/GPIO pins are used as SPI signals. HIGH – SPI/GPIO pins are used as GPIO signals. This pin has a weak internal pull-down resistor. Output S/PDIF audio output when the device is not in reset. DSD Serial Left Channel 2 data output when device is not in reset. AO_MUTE 36 LVTTL Schmitt 5 V tolerant 6 mA Input 2 Local I C Slave Address Strapping. This pin is an input when the RESET# pin is asserted. On the rising edge of RESET#, the level on this pin is latched and used to set the address of the local 2 I C interface. LOW – Address 0x30 HIGH – Address 0x32 This pin has a weak internal pull-down resistor. Output Mute Audio Output. This pin becomes the audio mute output when RESET# is inactive. It is used as a signal to the external downstream audio device, audio DAC, etc. to mute audio output. 2 *Note: These I S audio output signals can be reconfigured by software as inputs to support multichannel audio input. 5.2.4. HDMI Transmitter TMDS Output Pins Pin Name TX0+ TX0– Pin 48 47 TX1+ TX1– 50 49 TX2+ TX2– TXC+ 53 52 45 TXC– 44 Type TMDS Analog Dir Description Output HDMI Transmitter Output Port Data. TMDS LOW voltage differential signal output data pairs. TMDS Analog Output HDMI Transmitter Output Port Clock. TMDS LOW voltage differential signal output clock pair. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 40 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 5.2.5. HDMI Transmitter Control Signal Pins Pin Name Pin HPD_TX 39 Type LVTTL Schmitt 5 V tolerant Dir TX_DSCL 72 Schmitt Open-drain 5 V tolerant Input DDC I C Clock for HDMI Transmitter Port. 2 Output HDCP KSV, An, and Ri values are exchanged over this I C port during authentication. This is a true open-drain, so it does not pull to GND if power is not applied. This pin requires an external pull-up resistor between 1.5 to 2.0 kΩ as defined in the HDMI Specification. TX_DSDA 73 Schmitt Open-drain 5 V tolerant Input DDC I C Data for HDMI Transmitter Port. 2 Output HDCP KSV, An, and Ri values are exchanged over this I C port during authentication. This is a true open-drain, so it does not pull to GND if power is not applied. This pin requires an external pull-up resistor between 1.5 to 2.0 kΩ as defined in the HDMI Specification. Input Description Hot Plug Detect. This pin has a weak internal pull-down resistor. 2 2 5.2.6. Audio Input Pins Pin Name AI_SCK Pin 27 AI_WS 26 AI_SD 25 AI_SPDIF/ DL2(IN) 28 ARC 40 Type LVTTL Schmitt 5 V tolerant LVTTL Schmitt 5 V tolerant LVTTL Schmitt 5 V tolerant LVTTL Schmitt 5 V tolerant Analog Dir Input Description 2 I S Serial Clock Input. This pin has a weak internal pull-down resistor. Input I S Word Select Input. This pin has a weak internal pull-down resistor. Input I S Data Input. This pin has a weak internal pull-down resistor. Input S/PDIF Input/DSD Serial Left Channel 2 data input. This pin has a weak internal pull-down resistor. Input Audio Return Channel Input from HDMI. This pin can be left unconnected when not used. 2 2 © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 41 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 5.2.7. Configuration/Programming Pins Pin Name Pin Type LVTTL Open-drain 5 V tolerant 8 mA LVTTL Schmitt 5 V tolerant LVTTL Schmitt Open-drain 5 V tolerant INT 3 RESET# 16 CSCL 67 CSDA 68 LVTTL Schmitt Open-drain 5 V tolerant 8 mA SPI_CS#/GPIO0 21 LVTTL Schmitt 5 V tolerant 8mA SPI_CLK/ GPIO1 22 LVTTL Schmitt 5 V tolerant 8mA SPI_TX/GPIO2 23 LVTTL Schmitt 5 V tolerant 8mA SPI_RX/GPIO3 24 LVTTL Schmitt 5 V tolerant 8mA Dir Description Output Interrupt Output. The INT pin can be programmed to be an open drain output (default) or a push-pull LVTTL output. The polarity of the INT pin can be set to negative (default) or positive asserted. Input Input Reset Pin. Active LOW. This pin has a weak internal pull-down resistor. 2 Configuration/Status I C Clock. 2 Chip configuration and status are accessed using this I C port. This pin requires an external pull-up resistor. A suggested value is 4.7 kΩ or stronger. This pin has a weak internal pull-down resistor. 2 Input Configuration/Status I C Data. 2 Output Chip configuration and status are accessed using this I C port. This pin requires an external pull-up resistor. A suggested value is 4.7 kΩ or stronger. This pin has a weak internal pull-down resistor. Input SPI Chip Select. Selected when the AO_SPDIF/DL2(OUT) pin is LOW during reset. Input GPIO 0. Output Selected when the AO_SPDIF/DL2(OUT) pin is HIGH during reset. This pin has a weak internal pull-down resistor. Input SPI Clock. Selected when the AO_SPDIF/DL2(OUT) pin is LOW during reset. Input GPIO 1. Output Selected when the AO_SPDIF/DL2(OUT) pin is HIGH during reset. This pin has a weak internal pull-down resistor. Output SPI Data Output. Selected when the AO_SPDIF/DL2(OUT) pin is LOW during reset. Input GPIO 2. Output Selected when the AO_SPDIF/DL2(OUT) pin is HIGH during reset. This pin has a weak internal pull-down resistor. Input SPI Data Input. Selected when the AO_SPDIF/DL2(OUT) pin is LOW during reset. Input GPIO 3. Output Selected when the AO_SPDIF/DL2(OUT) pin is HIGH during reset. This pin has a weak internal pull-down resistor. 5.2.8. Crystal Clock Pins Pin Name XTALIN Pin 61 Type 5 V tolerant LVTTL Dir Input Description Crystal Clock Input. Generates internal system clock and allows LVTTL input. Frequency required is 26 MHz through 28.5 MHz. 27 MHz frequency is recommended. The system clock is used as the reference clock for the audio PLL and scaler PLL. It is also used for register access and interrupt processing. XTALOUT 62 LVTTL Output Crystal Clock Output. Note: The XTALIN pin can be driven at LVTTL levels by a clock (leaving XTALOUT unconnected) or connected through a crystal to XTALOUT. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 42 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 5.2.9. Power and Ground Pins Pin Name Pin Type IO_VDD5 1 Power Description Power supply for CSCL, CSDA, CEC, CDSENSE, TX_DSCL, TX_DSDA, RX_DSDA, RX_DSCL and RX_HPD/CBUS pins. MCAP33 Supply 5.0 V 2 Power Capacitor for Internal Regulator. 3.3 V RX_AVDD10 RX_AVDD33 TX_PVDD10 4, 14 5 43 Power Power Power TMDS Rx Analog 1.0 V Power Supply. TMDS Rx Analog 3.3 V Power Supply. TMDS Tx PLL Analog 1.0 V Power Supply. 1.0 V 3.3 V 1.0 V TX_AVDD10 DVDD10 46, 51 15, 17, 18, 20, 38, 41, 54, 55, 56, 57, 58, 65 Power Power TMDS Tx Analog 1.0 V Power Supply. Digital Logic Power Supply. 1.0 V 1.0 V VP_AVDD10 59 Power Video PLL Power Supply. 1.0 V AP_AVDD10 IO_VDD33 IO_APVDD33 64 19 63 Power Power Power Audio PLL Power Supply. I/O Power Supply. Audio PLL I/O Power Supply. 1.0 V 3.3 V 3.3 V TX_GND IO_APGND 42 60 Ground Ground TMDS Tx Ground. Audio PLL I/O Ground. Ground Ground ePad (bottom of package) Ground Ground. The ePad must be soldered to ground. Ground Description Do not connect. Reserved. Must be tied to ground. Supply — Ground GND 5.2.10. Reserved Pins Pin Name RSVDNC RSVDL Pin 66 69 Type Reserved Reserved © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 43 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 6. Feature Information 6.1. I2C and SPI Interfaces 6.1.1. E-DDC/I2C Interface The HDCP protocol requires the video transmitter and video receiver to exchange values. The transmitter reads the EDID data in the receiver to ascertain its capabilities. These values are exchanged over the DDC channel of the HDMI 2 interface. The E-DDC channel follows the I C serial protocol. Both the HDMI receiver and transmitter ports of the SiI9612 device feature their own separate E-DDC buses. 6.1.1.1. HDMI Receiver E-DDC Interface S Register Address Stop DSDA Line Slave Address Start Bus Activity : Master Start The HDMI receiver port of the SiI9612 device has a connection to the E-DDC bus with the slave address of 0x74 for 2 HDCP authentication, and 0xA0 for EDID data retrieval by the upstream transmitter. The I C read operation is shown in Figure 6.1, and the write operation in Figure 6.2. Slave Address S P A C K A C K A C K No A C K Data DSDA Line S Slave Address Register Address Stop Bus Activity : Master Start Figure 6.1. DDC Byte Read Data P A C K A C K A C K Figure 6.2. DDC Byte Write Multiple bytes can be transferred in each transaction, regardless of whether they are reads or writes. The operations are similar to those in the two figures above, except that there is more than one data phase. An ACK follows each byte except the last byte in a read operation. Byte addresses increase with the least-significant byte transferred first, and 2 the most-significant byte last. See the I C Specification for more information. DSDA Line S Slave Address Ri Lsb Ri Msb Stop Bus Activity: Master Start There is also a Short Read format that can be performed during the third phase of HDCP authentication. It is designed to improve the efficiency of Ri register reads that must be done every two seconds while encryption is enabled. Figure 6.3 shows this transaction. There is no register address phase (only the slave address phase), because the register 2 address is reset to 0x08 (Ri) after a hardware or software reset, and after the STOP condition on any preceding I C transaction. P A C K A C K No A C K Figure 6.3. Short Read Sequence © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 44 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 6.1.1.2. HDMI Transmitter E-DDC Interface 2 The SiI9612 HDMI transmitter port interfaces with the E-DDC bus through an I C master controller. The DDC master 2 supports the I C transactions specified by the VESA Enhanced Display Data Channel Standard. The DDC master complies 2 with the 100 kHz standard mode timing of the I C Specification and supports slave clock stretching, as required by E-DDC. Figure 6.4 shows the supported transactions and timing sequences. Current Read S slv addr + R As data 0 Am data 1 Am Am data n P N/As Sequential Read S slv addr + W As device offset As Sr slv addr + R As data 0 Am Am data n N/As P Enhanced DDC Read S 0x60 segment N/As N/As* Sr slv addr + W As device offset As Sr slv addr + R data n N/As As data 0 Am Am data n N/As P Sequential Write S slv addr + W As device offset As data 0 S = start Sr = restart As = slave acknowledge Am = master acknowledge As As P N = no ack P = stop * Don't care for segment 0, ACK for segment 1 and above 2 Figure 6.4. DDC Master I C Supported Transactions 6.1.2. Local I2C Interface 2 The SiI9612 video processor has a third I C port accessible only to the controller in the display device. It is separate from the 2 E-DDC bus and is a slave device. The local I C interface on SiI9612 pins CSCL and CSDA is a slave interface that can run up to 400 kHz. This bus is used to configure and control the video processor by reading and writing to necessary registers. CSDA Line S Slave Address 0x30 Register Address High Byte Register Address Low Byte Stop Bus Activity : Master Start The device registers are accessed using 16-bit addresses. Figure 6.5 illustrates the bus activity on the CSDA line when writing to a device register, and Figure 6.6 illustrates the same when reading a device register. In both read and write cycles, after the master transmits the device address and receives an acknowledgment from the slave, it sends two bytes, which represent the address of the register it wants to read or write. These two bytes make up the high and low bytes of the register address. The rest of the bus cycle follows the same format as transactions using an 8-bit register address. For example, to write to register 0x1008 of the HDMI receiver, the master would transmit 0x10 for the high address byte and 0x08 for the low address byte. Data L S B M S B A C K A C K P A C K A C K 2 S Register Address High Byte Register Address Low Byte L S B M S B A C K A C K Stop CSDA Line Slave Address 0x30 Start Bus Activity : Master Start Figure 6.5. Register Write Cycle on Local I C Slave Address S P A C K A C K Data No A C K 2 Figure 6.6. Register Read Cycle on Local I C © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 45 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Multibyte transfers are supported. The operations are similar to those described above. The internal address pointer is advanced automatically after every transfer of a byte. 2 The device address of the local I C interface can be set to one of two values by strapping the AO_MUTE pin LOW or HIGH at reset. Table 6.1 shows the device address selected for each state of the AO_MUTE pin at reset. 2 Table 6.1. Control of Local I C Device Address with AO_MUTE Pin Device Address 2 Local I C AO_MUTE = LOW AO_MUTE = HIGH 0x30 0x32 6.1.3. Video Requirement for I2C Access The SiI9612 video processor does not require an active video clock to access its registers from either the E-DDC port or 2 the local I C port. Read/Write registers can be written and then read back. Read-only registers that provide values for an active video or audio stream return indeterminate values if there is no video clock and no active sync. Use the SCDT and CKDT register bits to determine when active video is being received by the chip. 6.1.4. Local SPI Serial Interface The SPI serial interface is a simple four-wire synchronous serial interface with unidirectional data lines. The host CPU drives clock, chip select, and serial transmit data to the SPI slave device. It also receives serial data from the SPI slave device. By using multiple chip-enables and tying the receive data lines together, it is possible to connect multiple SPI slave devices to a single host CPU as shown in Figure 6.7 and Figure 6.8. The maximum clock frequency is 10 MHz. Host CPU SPI_CLK SPI_CLK SPI_TX SPI_RX SPI_RX SPI_TX SPI_CS# SPI_CS# SiI9612 SPI Slave Device Figure 6.7. SPI Serial Connection Example: Host ↔ Single SPI Slave Device Host CPU SPI_CLK SPI_CLK SPI_TX SPI_RX SPI_RX SPI_TX SPI_CS1# SPI_CS1# SiI9612 SPI Slave Device 1 SPI_CS2# SPI_CLK SPI_RX SPI_TX SPI_CS2# SPI Slave Device 2 Figure 6.8. SPI Serial Connection Example: Host ↔ Dual SPI Slave Devices © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 46 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 6.1.4.1. Write Operation The following description of a write operation is from the perspective of the host controller as shown in Figure 6.9. First, the host CPU asserts the SPI_CS# line LOW to indicate the start of a transfer. Then it sends 15 address bits (MSB first) on the SPI_TX line, followed by a single R/W bit (0 = write). For a write operation, the host CPU sends N bytes of write data one byte at a time (MSB first). The order of bits on the SPI_TX line is 7–0, 15–8, 23–16, and so on. When more than one byte is written, the address is incremented automatically in the SPI slave device. The maximum number of bytes that may be written in a single transaction is not limited by the bus protocol, but may be limited by the slave device. At the end of the transaction, SPI_CS# is deasserted to indicate the end of the transfer. If SPI_CS# is deasserted too early, the slave device aborts the transfer, and the results may be undefined. SPI_CLK SPI_Cs# SPI_Tx A14 A13 A0 0 D7 D6 D0 SPI_Rx Figure 6.9: SPI Serial Write Operation Note: Signal names are as seen at the host side of the interface. 6.1.4.2. Read Operation The following description of a read operation is from the perspective of the host controller as shown in Figure 6.10 below. First, the host CPU asserts the SPI_CS# line LOW to indicate the start of a transfer. Then it sends 15 address bits (MSB first) on the SPI_TX line, followed by a single R/W bit (1 = read). For a read operation, the host CPU must poll the SPI_RX line while holding the clock pin HIGH, until the slave device drives the SPI_RX line HIGH to indicate data is ready. The host may then start reading N bytes of data one byte at a time (MSB first). The order of bits on the serial line is 7–0, 15–8, 23–16, and so on. Similar to the write operation, when more than one byte is read, the address is incremented automatically in the SPI slave device. The maximum number of bytes that may be read in a single transaction is not limited by the bus protocol, but may be limited by the slave device. Note that the serial clock does not toggle in the pause between sending the address and receiving read data. At the end of the transaction, SPI_CS# is deasserted to indicate the end of the transfer. If SPI_CS# is deasserted too early, the slave device aborts the transfer, and the results may be undefined. SPI_CLK SPI_Cs# SPI_Tx A14 A13 A0 1 D7 SPI_Rx D6 D0 Figure 6.10: SPI Serial Read Operation Note: Signal names are as seen at the host side of the interface. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 47 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 7. Package Information 7.1. ePad Requirements The SiI9612 video processor is packaged in a 76 pin, 9 mm × 9 mm MQFN package with ePad that is used for the electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are 5.38 mm × 5.38 mm ± 0.15 mm. Soldering the ePad to the ground plane of the PCB is required to meet package power dissipation requirements at full-speed operation, and to correctly connect the chip circuitry to electrical ground. To avoid the possibility of electrical shorts, a clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads. The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter. Package standoff when mounting the device also needs to be considered. For a nominal standoff of approximately 0.1 mm, the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal land. Figure 7.1 on the next page shows the package dimensions of the SiI9612 video processor. 7.2. PCB Layout Guidelines Refer to Lattice Semiconductor document PCB Layout Guidelines: Designing with Exposed Pads (Lattice Semiconductor Documents on page 51) for basic PCB design guidelines when designing with thermally enhanced packages using the exposed pad. This application note is intended for use by PCB layout designers. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 48 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 7.3. Package Dimensions This figure is not to scale. 0.10 C A D A 0.10 M C A B D2 1.41 0.10 C B 1.41 Laser Mark for Pin 1 ID E2 E Pin 1 ID 3 2 1 L 76 Top View e b B 0.10 M C A B 0.07 M C A B 0.05 M C A2 Bottom View Side View C 0.10 A1 A3 A 0.08 C Seating Plane JEDEC Package Code MO-220 (Dimensions in mm) Symbol Min Typ Max Symbol Min Typ Max A A1 0.80 0.00 0.85 0.02 0.90 0.05 D2 E 5.23 5.38 9.00 BSC 5.53 A2 A3 — 0.65 0.20 REF 0.70 E2 L 5.23 0.30 5.38 0.40 5.53 0.50 b D 0.15 0.20 9.00 BSC 0.25 e 0.40 BSC Figure 7.1. Package Diagram © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 49 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet 7.4. Marking Specification Figure 7.2 shows the markings of the SiI9612 package. Refer to Figure 7.1 on page 49 for specifics. Pin 1 location Logo SiI9612CNUC LLLLLL.LL-L YYWW XXXXXXX Silicon Image Part Number Lot # (= Job#) Date code Trace code SiIxxxxrpppp-sXXXX Product Designation Special Designation Revision Speed Package Type Figure 7.2. Marking Diagram 7.5. Ordering Information Production Part Numbers: TMDS Clock Range Part Number 25 MHz – 300 MHz SiI9612CNUC The universal package may be used in lead-free and ordinary process lines. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 50 SiI-DS-1120-B SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet References Standards Documents This is a list of standards abbreviations appearing in this document, and references to their respective specifications documents. Abbreviation Standards publication, organization, and date HDMI HCTS HDCP High Definition Multimedia Interface, Revision 1.4, HDMI Consortium; June 2009 HDMI Compliance Test Specification, Revision 1.3c, HDMI Consortium; July 2008 High-bandwidth Digital Content Protection, Revision 1.3, Digital-Content Protection, LLC; December 2006 E-EDID E-DID IG Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; February 2000 VESA EDID Implementation Guide, VESA; June 2001 CEA-861 CEA-861-B A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; January 2001 A DTV Profile for Uncompressed High Speed Digital Interfaces, Draft 020328, EIA/CEA; March 2002 CEA-861-D EDDC MHL A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; July 2006 Enhanced Display Data Channel Standard, Version 1.1, VESA; March 2004 MHL (Mobile High-definition Link) Specification, Version 2.0, MHL, LLC, February 2012 Standards Groups For information on the specifications that apply to this document, contact the responsible standards groups appearing on this list. Standards Group Web URL ANSI/EIA/CEA VESA DVI http://global.ihs.com http://www.vesa.org http://www.ddwg.org HDCP HDMI http://www.digital-cp.com http://www.hdmi.org MHL http://www.mhlconsortium.org Lattice Semiconductor Documents This is a list of the related documents that are available from your Lattice Semiconductor sales representative. The Programmer’s Reference requires an NDA with Lattice Semiconductor. Document Title SiI-PR-1069 SiI-PR-0041 SiI9616/SiI9612 Programmer’s Reference CEC Programming Interface (CPI) Programmer’s Reference SiI-AN-0129 PCB Layout Guidelines: Designing with Exposed Pads Technical Support For assistance, submit a technical support case at www.latticesemi.com/techsupport. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1120-B 51 SiI9612 4K Video Processor with Integrated 300 MHz Receiver and Transmitter Data Sheet Revision History Revision B, February 2016 Updated to latest template. Revision B, October 2013 Updated the Direct Stream Digital Input and the One-bit Audio Output sections. Revision A, February 2013 First production release. © 2012-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 52 SiI-DS-1120-B th th 7 Floor, 111 SW 5 Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com