Ordering number : ENN7349
CMOS IC
LC75010W
LC75010W Car Audio DSP
Package Dimensions
unit: mm
3181C-SQFP100
[LC75010W]
16.0
0.5
14.0
51
76
50
100
26
1
0.5
0.2
25
16.0
75
14.0
• Hardware Functions
— Analog source selector (BTL:1ch, OTL:3 ch)
— 20 bits A/D (2ch)
— 24 bits DSP (core, program memory, data memory)
— SIO (CCB I/F) (CCB is LSB first input.)
— 24 bits D/A (4ch)
— EVR (4ch)
• Software Functions* (See Note.)
— Bass/Mid/Treb
— Bal/Fad
— Fixed equalizer (Front/Rear/separately controlled)
— Loudness control
— Hybrid volume
— Anti-hard clip
— Dedekind (Speaton**)
Note *: Software specifications can be modified in
response to user requests.
• DSP Functions (24 fixed-point DSP)
— Program ROM — 8k words
— Data RAM — 896 words
0.145
(1.0)
(1.4)
Features
1.6max
The LC75010W is a car audio DSP IC that integrates the
signal processing required by car audio systems, A/D and
D/A converters, volume control, and other functions on a
single chip. It can implement a car audio system with a
minimal number of external components.
• Supply Voltage and Package Specifications
— DSP core, A/D converter (digital block), D/A
converter (digital block): 3.3 V
— A/D converter (analog block), D/A converter
(analog block), volume control, crystal oscillator:
5V
— Package: 100-pin SQFP (14×14 mm)
0.1
Overview
SANYO: SQFP100
• CCB is a registered trademark of Sanyo Electric Co., Ltd.
• CCB is Sanyo's original bus format. All bus addresses are managed by Sanyo for this format.
Note **: Speaton is a registered trademark of Dedekind R&D. Users who want to develop, manufacture,
or sell electronic equipment that uses Dedekind functions must enter a separate contract with
Dedekind R&D for the use of those functions.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2103TN (OT) No. 7349-1/12
LC75010W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Ratings
Parameter
Symbol
Pin name
Supply voltage
(A/D, D/A, volume, etc)
VDDmax1
AVDD1, AVDD2, AVDD5, AVDD6, AVDD7, AVDD8, AVDD9,
AVDD10, AVDD11, AVDD12
–0.3
+6.0
V
Supply voltage (crystal oscillator)
VDDmax2
min
typ
max
Unit
XVDD
–0.3
+6.0
V
Supply voltage
(DSP core block)(I/O I/F, PLL block) VDDmax3
DVDD1, DVDD2, DVDD3, DVDD4, DVDD5, DVDD6, AVDD4
–0.3
+4.0
V
Maximum input voltage
(A/D, D/A, volume, etc)
VIN1
AINRP1, AINRN1, AINLP1, AINLN1, AINRP2,AINLP2,
AINRP3, AINLP3, AINRP4, AINLP4,
VFLI, VFRI, VRLI, VRRI
–0.3
VDDmax1
+ 0.3
V
Maximum input voltage
(DSP core block)
(I/O I/F block)
VIN2
TEST0, TEST1, TEST2, TEST3, TEST4, TEST5,
TEST6, TEST7, TEST8, TEST9, TEST10,
TEST13, TEST14, PWDB
–0.3
CL, CE, DI, RSTB, INTB
–0.3
VIN3
Allowable power dissipation
Maximum output current
Pdmax
Io
(max +6.0 V)
VDDmax3
+ 0.3
V
(max +4.0 V)
(Conditions: Audio disabled operating state, Std. Board
installation ; See note)
DO
+6.0
V
830
mW
0
6.0
mA
Operating temperature
Topr
–40
85
°C
Storage temperature
Tstg
–55
125
°C
Note Std. board : 114.3 mm × 76.2 mm × 1.5 mm, material ; glass epoxy resin
Allowable Operating Ranges at Ta = –40 to +85°C, VSSD = VSSA = 0 V
Parameter
Ratings
Symbol
Pin name
Supply voltage
(analog block)
AVDD5
AVDD1, AVDD2, AVDD5, AVDD6, AVDD7, AVDD8, AVDD9,
AVDD10, AVDD11, AVDD12
+4.75
+5.25
V
Supply voltage (crystal oscillator)
XVDD5
XVDD
+4.75
+5.25
V
+3.0
+3.6
V
Supply voltage
(digital block, PLL)
High-level input voltage
Low-level input voltage
min
typ
max
Unit
DVDD3.3
DVDD1, DVDD2, DVDD3, DVDD4, DVDD5, DVDD6, AVDD4
VIHD
PWDB, INITB, TEST0, TEST1, TEST2, TEST3, TEST4,
TEST5, TEST6, TEST7, TEST8, TEST9, TEST10,
TEST13, TEST14
0.7 × DVDD3.3
DVDD3.3
V
VIHD1
CL, CE, DI, RSTB
0.7 × AVDD5
AVDD5
V
VILD
PWDB, INITB, TEST0, TEST1, TEST2, TEST3, TEST4,
TEST5, TEST6, TEST7, TEST8, TEST9, TEST10,
TEST13, TEST14
VSS
0.3 × DVDD3.3
V
CL, CE, DI, RSTB
VSS
0.3 × AVDD5
V
0.4 × AVDD5
Vp-p
VILD1
Full-scale input level
AINRP1, AINRN1, AINLP1, AINLN1, AINRP2,
AINLP2, AINRP3, AINLP3, AINRP4, AINLP4
Crystal oscillator frequency *
XIN, XOUT
16.9344
MHz
Note*: Consult with the manufacturer of the crystal oscillator element used to verify that the circuit constant values are appropriate for that crystal
oscillator element before using this circuit.
No. N7349-2/12
LC75010W
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Symbol
Pin name
High-level input current
IIH
PWDB, RSTB, INTB, CE, CL, DI, TEST0,
TEST1, TEST2, TEST3, TEST4, TEST5, TEST6,
TEST7, TEST8, TEST9, TEST10, TEST13, TEST14
Low-level input current
IIL
PWDB, RSTB, INTB, CE, CL, DI, TEST0,
TEST1, TEST2, TEST3, TEST4, TEST5, TEST6,
TEST7, TEST8, TEST9, TEST10, TEST13, TEST14
High-level output voltage
Low-level output voltage
VOH
Ratings
min
typ
Unit
max
5
µA
–5
µA
BUSY, DO, TEST11, TEST12 (Microcontroller: 5 V)
4.5
5.5
V
BUSY, DO, TEST11, TEST12 (Microcontroller: 3.3 V)
3.0
3.6
V
VOL
BUSY, DO, TEST11, TEST12
Analog output level
VOUT
AOUT1, AOUT2, AOUT3, AOUT4
Reference voltage output
Vref1
Vref2
Vref3
Vref1, Vref2, Vref3
IAVDD5
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V
55
72
mA
IXVDD5
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V
5
7
mA
IDVDD3.3
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V
65
85
mA
Pd
(Conditions: Audio disabled operating state, Std. board
installed ; See note)
AVDD5 = XVDD5 = 5V, DVDD3.3 = 3.3 V
515
680
mW
Current drain
Power dissipation
0.5
0.6 × AVDD5
2.35
2.5
V
VP-P
2.65
V
Note Std. board : 114.3 mm × 76.2 mm × 1.5 mm, material : glass epoxy resin
LC75010W Analog Characteristics
Conditions: Analog system: 5 V, digital system: 3.3 V, fs: 44.1 kHz, signal frequency: 1 kHz, from the analog source selector input to the
volume control circuit output.
Measurement band: 10 Hz to 20 kHz, using the SANYO-specified DSP evaluation board.
Test circuit: LC75010W external circuit structure with the DSP operating in through mode (4-bit shiftup), room temperature
Test equipment: Audio analyzer (Rohde & Schwarz UPD)
Parameter
Conditions
Ratings
min
typ
max
Unit
S/N
A-weighted, Input conditions: 2 Vp-p
85
90
—
dB
Dynamic range
A-weighted
85
90
—
dB
THD+N
Input conditions: 1.5 Vp-p. See note.
—
–86
–80
dB
Note: THD+N shows the optimal characteristics for an input (1.5 Vp-p) that is 3 dB lower than the full-scale input level.
CCB Timing
Parameter
Symbol
Pin name
Ratings
min
typ
max
Unit
Data setup time
tSU
DI, CL
0.75
µs
Data hold time
tHD
DI, CL
0.75
µs
Clock low-level time
tCL
CL
0.75
µs
Clock high-level time
tCH
CL
0.75
µs
CE wait time
tEL
CE, CL
0.75
µs
CE setup time
tES
CE, CL
0.75
µs
CE hold time
tEH
CE, CL
0.75
Data latch change time
tLC
Data output time
tDC
tDH
DO, CL
DO, CE
µs
0.75
µs
0.35
µs
No. N7349-3/12
LC75010W
LC75010W
(Top view)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AVDD8
VFLO
VFLI
AOUT1
VFRO
VFRI
AOUT2
AVSS7
AVDD7
Vref2
AVB2
NC
NC
AVSS6
AVDD6
AOUT3
VRLI
VRLO
AOUT4
VRRI
VRRO
AVSS5
AVDD5
XVDD
XVSS
AVDD4
VCO
PDO
AVSS4
DVDD4
DVSS4
DVB2
BUSY
PWDB
RSTB
CE
CL
DI
DO
INTB
TEST11
DVSS5
DVDD5
TEST12
TEST13
TEST14
DVSS6
DVDD6
XIN
XOUT
AVSS0
AVSS1
AVDD1
AVDD2
AVSS2
AVSS3
AVB1
DVSS1
DVDD1
TEST0
TEST1
TEST2
TEST3
TEST4
DVSS2
DVDD2
TEST5
TEST6
TEST7
TEST8
TEST9
TEST10
DVB1
DVSS3
DVDD3
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
Vref1
AVSS12
AVDD12
AINRP1
Ars4
Ars3
AINRN1
AINRP4
AINRP3
AVSS11
AVDD11
AINRP2
AVDD9
AVSS9
Vref3
AINLP2
AVDD10
AVSS10
AINLP3
AINLP4
AINLN1
Als3
Als4
AINLP1
AVSS8
Pin Assignments
No. N7349-4/12
LC75010W
Pin Functions
Pin No.
Pin name
Input/Output (I/O)
97
AINRP1
I
Analog BTL input (Rch +)
Function
94
AINRN1
I
Analog BTL input (Rch -)
77
AINLP1
I
Analog BTL input (Lch +)
80
AINLN1
I
Analog BTL input (Lch -)
89
AINRP2
I
Analog OTL input1 (Rch +)
85
AINLP2
I
Analog OTL input1 (Lch +)
92
AINRP3
I
Analog OTL input2 (Rch +)
82
AINLP3
I
Analog OTL input2 (Lch +)
93
AINRP4
I
Analog OTL input3 (Rch +)
81
AINLP4
I
Analog OTL input3 (Lch +)
34
PWDB
I
Standby mode (active low)
Setting the PWDB pin to the low level sets the LC75010W to standby mode (also know as "power
down mode").
In standby mode, the DSP system clock and the crystal oscillator are stopped and the whole
LC75010W goes to the stopped state. This pin must be held at the high level during normal
operation.
35
RSTB
I
Reset (active low)
A reset is normally applied at power on, after recovering from a temporary power outage, and after
returning from standby mode ("power down mode").
40
INTB
I
Interrupt (active low) (Software clip input (0/1))
Provides feedback control to the DSP to prevent clipping when an overflow occurs in the amplifier
output.
10
TEST0
I/O
Test pin
11
TEST1
I/O
Test pin
12
TEST2
I/O
Test pin
13
TEST3
I/O
Test pin
14
TEST4
I/O
Test pin
17
TEST5
I/O
Test pin
18
TEST6
I/O
Test pin
19
TEST7
I/O
Test pin
20
TEST8
I/O
Test pin
21
TEST9
I/O
Test pin
22
TEST10
I/O
Test pin
41
TEST11
I/O
Test pin
44
TEST12
I/O
Test pin
45
TEST13
I/O
Test pin
46
TEST14
I/O
Test pin
49
XIN
I
Crystal input (384 fs = 16.9344 MHz) (fs = 44.1 kHz)
50
XOUT
O
Crystal output
27
VCO
I
VCO control
28
PDO
O
Charge pump output
36
CE
I
CCB enable
37
CL
I
CCB clock
38
DI
I
Data in
39
DO
O
Data out
CCB ready monitor
Outputs the state of the DSP CCB receive buffer.
A low-level output from the BUSY pin indicates that the buffer is empty.
A high-level output indicates that command data is present in the receive buffer.
33
BUSY
O
74
VFLO
O
Volume front Lch output
73
VFLI
I
Volume front Lch input
71
VFRO
O
Volume front Rch output
70
VFRI
I
Volume front Rch input
58
VRLO
O
Volume rear Lch output
59
VRLI
I
Volume rear Lch input
55
VRRO
O
Volume rear Rch output
56
VRRI
I
Volume rear Rch input
Continued on next page.
No. N7349-5/12
LC75010W
Continued from preceding page.
Pin No.
Pin name
100
Vref1
Input/Output (I/O)
Reference voltage
Function
66
Vref2
Reference voltage
86
Vref3
72
AOUT1
Reference voltage
O
Analog out 1
69
AOUT2
O
Analog out 2
60
AOUT3
O
Analog out 3
57
AOUT4
O
Analog out 4
9
DVDD1
Digital VDD (3.3 V)
16
DVDD2
Digital VDD (3.3 V)
25
DVDD3
Digital VDD (3.3 V)
30
DVDD4
Digital VDD (3.3 V)
43
DVDD5
Digital VDD (3.3 V)
48
DVDD6
Digital VDD (3.3 V)
8
DVSS1
Digital VSS
15
DVSS2
Digital VSS
24
DVSS3
Digital VSS
31
DVSS4
Digital VSS
42
DVSS5
Digital VSS
47
DVSS6
Digital VSS
29
AVSS4
Digital VSS
23
DVB1
Digital board GND
32
DVB2
Digital board GND
3
AVDD1
Analog VDD (5 V)
4
AVDD2
Analog VDD (5 V)
53
AVDD5
Analog VDD (5 V)
61
AVDD6
Analog VDD (5 V)
67
AVDD7
Analog VDD (5 V)
75
AVDD8
Analog VDD (5 V)
88
AVDD9
Analog VDD (5 V)
84
AVDD10
Analog VDD (5 V)
90
AVDD11
Analog VDD (5 V)
98
AVDD12
Analog VDD (5 V)
26
AVDD4
Digital VDD (3.3 V)
1
AVSS0
Analog VSS
2
AVSS1
Analog VSS
5
AVSS2
Analog VSS
6
AVSS3
Analog VSS
54
AVSS5
Analog VSS
62
AVSS6
Analog VSS
68
AVSS7
Analog VSS
76
AVSS8
Analog VSS
87
AVSS9
Analog VSS
83
AVSS10
Analog VSS
91
AVSS11
Analog VSS
99
AVSS12
7
AVB1
Analog Board GND
65
AVB2
Analog Board GND
52
XVDD
OSC VDD (5 V)
51
XVSS
OSC VSS
95
Ars3
Analog Rch source control
96
Ars4
Analog Rch source control
79
Als3
Analog Lch source control
78
Als4
Analog Lch source control
Analog VSS
No. N7349-6/12
LC75010W
Block Diagram
VFLO
(C ≥ 1µF)
R
Als3
DAC
(24 bits)
DSP
CORE
(24 bits)
Als4
VFLI
L.P.F.
Vref
AOUT1
VFRO
(C ≥ 1µF)
AINLP1
AINLN1
AINLP2
AINRP2
AINLP3
AINRP3
AINLP4
AINRP4
Analog source selector
AINRP1
AINRN1
DAC
(24 bits)
ADC
(20 bits)
R
VFRI
L.P.F.
AOUT2
Vref
VRLO
(C ≥ 1µF)
ADC
(20 bits)
Program ROM
(8 kw)
DAC
(24 bits)
R
VRLI
L.P.F.
AOUT3
Vref
VRRO
(C ≥ 1µF)
Ars3
DAC
(24 bits)
Ars4
R
VRRI
L.P.F.
AOUT4
Vref
Data RAM
(896W)
DVDD
3.3 V
DVSS
AVDD
5V
AVSS
PLL
VCO
VREF
RESB
PWDB
INTB
TEST14-0
CE
CL
CCB
XOUT
XIN
PDO
DI
DO
BUSY
VCO
No. N7349-7/12
LC75010W
CCB Control System Timing and Data Format
The LC75010W uses a CCB (Computer Control Bus) serial bus, which is a SANYO-developed bus format.
The input serial data consists of a total of (8 + DI + C) bits. Here, the first 8 bits are the CCB address, the next DI bits are
the data bits, and the last C bits are control bits. The output serial data consists of (8 + DO) bits. Here, the first 8 bits are
the CCB address and the next DO bits are the output data bits. Serial data can be input or output after power has been
applied, the crystal oscillator and PLL circuits have stabilized, and a reset has been applied.
• Serial Data Input
CL: Normally high
t LC < 0.75 µs
tSU, tHD, t EL , t ES , t EH ≥ 0.75µs
t EL
t ES
t EH
CE
CL
t SU
DI
tHD
B0 B1
B2
B3
A0
A1
A2
A3
DI1 DI2 DI3 DI4
DI24
C1
…
C24
t LC
Internal
Data
tEL
CL: Normally low
tES
tEH
CE
CL
tSU
B0
DI
tHD
B1
B2
B3
A0
A1
A2
A3
D11
D12 D13 D14
Internal
Data
tEL
C2
...
C24
t LC
tDC, t DH < 0.35 µs
tSU, tHD, t EL , t ES , t EH ≥ 0.75µs
• Serial Data Output
CL: Normally high
DI168
tES
tEH
CE
CL
tSU
DI
tHD
B0 B1
B2
B3
A0
A1
A2
A3
t DC
DO
t DC
S1
CL: Normally low
t EL
...
tt DH
S8
DO1
t ES
DO45 DO46 DO47 DO48
t EH
CE
CL
tSU
DI
DO
B0
tHD
B1
B2
B3
A0
A1
A2
A3
tDC
tDC
S1
…
tDH
S8
DO
DO45 DO46 DO47 DO48
Note: Since the DO pin is an n-channel open-drain output, the data transition times (tDC and tDH) differ depending on the value of the pull-up resistor used.
No. N7349-8/12
LC75010W
≈
• Serial Data Timing
CL: Normally high
VIH
VIH
VIL
VIH
VIH
VIH
VIL
≈
VIH
t EL
≈
CL
VIL
≈
t CL
t ES
t EH
≈
t CH
≈
CE
≈
t HD
VIL
t DC
t DH
≈
t SU
≈
VIL
≈
DI
≈
New
≈
≈
Internal
data latch
t LC
Old
≈
≈
≈
DO
When CL is stopped at the high level
≈
CL: Normally low
VIH
VIH
≈
VIH
VIH
VIL
t EL
VIL
t ES
VIH
≈
VIH
VIL
CL
VIL
≈
t CL
≈
t CH
≈
CE
t EH
t HD VIL
t DC
t DC
≈
≈
t SU
≈
VIL
≈
DI
t DH
≈
≈
≈
≈
DO
New
≈
≈
Internal
data latch
t LC
Old
When CL is stopped at the low level
Reset Timing
After power has been applied, and after crystal oscillator operation and PLL circuit operation have stabilized, a reset must
be applied at the point that the Vref voltages (Vref1, Vref2, and Vref3) exceed the minimum level of 2.35 V. The reset
period must be set up to include a period of at least 0.5 µs during which the reset signal is held fixed at the low level.
Audio processing (audio input/audio output) cannot be performed during the A/D converter calibration period (100 ms),
which directly follows the reset.
Note on Changes to the DSP Core Main Clock
The LC75010W DSP core main clock can be switched by setting the TEST8 pin either low or high as shown below.
TEST8
DSP core main clock (Crystal oscillator: 16.9344 MHz)
Low (DVSS)
38.1024 MHz
High (DVDD 3.3)
40.2192 MHz
No. N7349-9/12
LC75010W
Notes on Filter Coefficient Settings (precision of calculations)
The IIR filter calculations are performed using 24-bit coefficients, 24-bit delay functions, 24 × 24 = 48-bit
multiplications, and 48 + 48 = 48-bit additions.
For certain values of the filter coefficients, the precision can become inadequate during the process of the filter
calculation. Such errors can result in switching noise occurring when changing between different steps in the volume
control.
*: This problem can occur when setting the second-order IIR with filter coefficients having low characteristic
frequencies (for example, the cutoff frequency or the center frequency). For example, switching noise will occur if
the coefficients for a high-pass filter with a cutoff frequency of 25 Hz and a Q of 0.7 are set with FixEQ.)
The following workaround can be effective if switching noise occurs due to second-order IIR filter coefficient
settings.
• Increase the characteristic frequency without changing the second-order characteristics, for example, increase the
cutoff frequency from 25 Hz to 100 Hz.
• Use the second-order characteristics as the first-order characteristics and define the coefficients for first-order
characteristics.
• Serial Input Data Format Examples
Example 1: Data format for the volume function
CCB Address
volume function data
(8 bits)
bit 0
control data
(24 bits)
(24 bits)
78
31 32
LSB(B0, B1, … , A3, DI1, DI2,
…
…
55
DI23, DI24, C1, C2,
…
, C23, C24)MSB
…
Example 2: Data format for 24-bit coefficient data (Total: 200 bits maximum)
CCB Address
(8 bits)
bit 0
Coefficient data0
Coefficient data1
(24 bits)
78
LSB( B0, B1,…
55 56
…
control data
(24 bits)
31 32
, A3, DI1, DI2,
Coefficient address
(24 bits)
…
150151
…
(16 bits)
175176
DI168, C1, C2, …
…
(8 bits)
191192 199
… C23, C24)MSB
• Serial Output Data Format Example
Example 1: CCB status register format (Total: 64 bits)
CCB Address CCB status
(8 bits)
bit0
78
Monitor data1
(8 bits)
Monitor data2
(24 bits)
(24 bits)
15 16
LSB( B0, B1, … , A3, S1, S2, S8,
39 40
DO1, DO2,
…
…
63
…
…
, DO47, DO48)MSB
No. N7349-10/12
VDD(3.3 V)
VSS
47µH
+
+
DVDD(3.3 V)
AVSS
DVSS
Input high level (5 V)
Input high level (3.3 V)
+
AVDD(5 V)
XVDD(5 V)
AVSS0
AVSS1
AVDD1
AVDD2
AVSS2
AVSS3
AVB1
DVSS1
DVDD1
TEST0
TEST1
TEST2
TEST3
TEST4
DVSS2
DVDD2
TEST5
TEST6
TEST7
TEST8
TEST9
TEST10
DVB1
DVSS3
DVDD3
+
1.5 nF
+ + +
+
OTL1R
BTL1R-OTL3R
OTL2R
+
+
OTL1L
+ + +
1.5nF
+
BTL1L+
OTL2L
OTL3L
BTL1L--
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Top view
LC75010W
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Vref1
AVSS12
AVDD12
AINRP1
Ars4
Ars3
AINRN1
AINRP4
AINRP3
AVSS11
AVDD11
AINRP2
AVDD9
AVSS9
Vref3
AINLP2
AVDD10
AVSS10
AINLP3
AINLP4
AINLN1
Als3
Als4
AINLP1
AVSS8
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
220 Ω
0.1 µF
10 kΩ
Microcontroller(5 V)
Microcontroller supply
voltage(5 V)
AVDD8
VFLO
VFLI
AOUT1
VFRO
VFRI
AOUT2
AVSS7
AVDD7
Vref2
AVB2
NC
NC
AVSS6
AVDD6
AOUT3
VRLI
VRLO
AOUT4
VRRI
VRRO
AVSS5
AVDD5
XVDD
XVSS
16.9344
MHz
+ R:1 kΩ
+ R:1 kΩ
+
R:1 kΩ
+ R:1 kΩ
22 pF
+
+
+
+
+
: 10µF
C:1500 pF
C:1500 pF
C:1500 pF
LPF
C:1500 pF
22 pF
: 0.1µF
AMP
AVSS
AVDD(5 V)
XVDD(5 V)
DVDD(3.3 V)
DVSS
RR
RL
FR
FL
Unless indicated otherwise, capacitors shown as
Note: The component values shown here are provided for reference only, and are not
guaranteed for use in mass-produced end products.
: Consult the manufacturer of the crystal element used to determine the values
of the components used in the crystal oscillator circuit.
10 kΩ
10 kΩ
AVDD4
VCO
PDO
AVSS4
DVDD4
DVSS4
DVB2
BUSY
PWDB
RSTB
CE
CL
DI
DO
INTB
TEST11
DVSS5
DVDD5
TEST12
TEST13
TEST14
DV 6
SS
DVDD6
XIN
XOUT
VDD(5 V)
+
BTL1R+
LC75010W
Peripheral Circuit Example
No. N7349-11/12
LC75010W
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 2003. Specifications and information herein are
subject to change without notice.
PS No. N7349-12/12