16-Bit, Isolated Sigma-Delta Modulator AD7403 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD1 BUF VDD2 CLK DECODER CLK ENCODER DATA ENCODER DATA DECODER REF VIN+ MCLKIN (5MHz TO 20MHz) Σ-Δ ADC VIN– MDAT AD7403 GND1 GND2 12196-001 5 MHz to 20 MHz external clock input rate 16 bits, no missing codes Signal-to-noise ratio (SNR): 88 dB typical Effective number of bits (ENOB): 14.2 bits typical Offset drift vs. temperature AD7403: 1.6 µV/°C typical AD7403-8: 2 µV/°C typical On-board digital isolator On-board reference Full-scale analog input range: ±320 mV Operating range AD7403: −40°C to + 125°C AD7403-8: −40°C to + 105°C High common-mode transient immunity: >25 kV/µs Wide-body SOIC with increased creepage package Slew rate limited output for low EMI Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 1250 VPEAK Figure 1. APPLICATIONS Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Data acquisition systems Analog-to-digital and optoisolator replacements GENERAL DESCRIPTION The AD7403 is a high performance, second-order, Σ-Δ modulator that converts an analog input signal into a high speed, single-bit data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The device operates from a 5 V (VDD1) power supply and accepts a differential input signal of ±250 mV (±320 mV full-scale). The differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required. 1 The analog input is continuously sampled by a high performance analog modulator, and converted to a ones density digital output stream with a data rate of up to 20 MHz. The original 1 information can be reconstructed with an appropriate digital filter to achieve 88 dB signal to noise ratio (SNR) at 78.1 kSPS. The serial input/output can use a 5 V or a 3 V supply (VDD2). The serial interface is digitally isolated. High speed complementary metal oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The AD7403 device is offered in a 16-lead, wide-body SOIC package and has an operating temperature range of −40°C to +125°C. The AD7403-8 device is offered in an 8-lead, wide-body SOIC package and has an operating temperature range of −40°C to +105°C. Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com AD7403 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 15 Applications ....................................................................................... 1 Circuit Information.................................................................... 15 Functional Block Diagram .............................................................. 1 Analog Input ............................................................................... 15 General Description ......................................................................... 1 Differential Inputs ...................................................................... 16 Revision History ............................................................................... 2 Digital Output ............................................................................. 16 Specifications..................................................................................... 3 Applications Information .............................................................. 17 AD7403 .......................................................................................... 3 Current Sensing Applications ................................................... 17 AD7403-8 ...................................................................................... 4 Voltage Sensing Applications .................................................... 17 Timing Specifications .................................................................. 5 Input Filter................................................................................... 18 Package Characteristics ............................................................... 6 Digital Filter ................................................................................ 18 Insulation and Safety Related Specifications ............................ 6 Interfacing to ADSP-CM4xx .................................................... 21 Regulatory Information ............................................................... 6 Power Supply Considerations ................................................... 21 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation Characteristics .............................................................................. 7 Grounding and Layout .............................................................. 21 Absolute Maximum Ratings............................................................ 8 Outline Dimensions ....................................................................... 23 ESD Caution .................................................................................. 8 Ordering Guide .......................................................................... 24 Insulation Lifetime ..................................................................... 21 Pin Configurations and Function Descriptions ........................... 9 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 14 REVISION HISTORY 5/15—Rev. A to Rev. B Added AD7403-8 ................................................................ Universal Added Endnote 3, Table 1 ............................................................... 4 Added Table 2; Renumbered Sequentially .................................... 4 Added Figure 4 .................................................................................. 7 Added Figure 6 and Table 11........................................................... 9 Added Figure 8 ................................................................................ 10 Added Figure 14 and Figure 18..................................................... 11 Added Figure 20.............................................................................. 12 Added Power Supply Considerations Section, Figure 41, and Figure 42 .......................................................................................... 21 Added Figure 47, Outline Dimensions ........................................ 23 Changes to Ordering Guide .......................................................... 24 11/14—Rev. 0 to Rev. A Change to Figure 1 ............................................................................1 Changes to Regulatory Information Section and Table 5 ............5 Changes to Table 7.............................................................................7 Changes to Ordering Guide .......................................................... 20 4/14—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD7403 SPECIFICATIONS AD7403 VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +125°C, fMCLKIN1 = 5 MHz to 20 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 1. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Offset Error2 Offset Drift vs. Temperature3 Min Noise Free Code Resolution2 ISOLATION TRANSIENT IMMUNITY2 LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) ±12 ±0.99 ±0.75 3.8 3.1 −320 −250 Input Common-Mode Voltage Range Dynamic Input Current Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Effective Number of Bits (ENOB)2 ±2 ±0.2 1.6 1.3 50 ±0.2 ±0.2 ±0.2 65 40 ±0.6 Gain Error Drift vs. Temperature3 DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-Noise-and-Distortion Ratio (SINAD)2 Max 16 Offset Drift vs. VDD13 Gain Error2 Gain Error Drift vs. VDD13 ANALOG INPUT Input Voltage Range Typ ±0.8 ±0.8 ±1.2 95 60 +320 +250 −200 to +300 ±45 0.05 ±0.01 14 ±50 ±0.6 Unit Test Conditions/Comments Bits LSB LSB mV µV/°C µV/°C µV/V % FSR % FSR % FSR ppm/°C µV/°C mV/V Filter output truncated to 16 bits mV mV mV µA µA µA pF Guaranteed no missed codes to 16 bits 0°C to 85°C fMCLKIN = 16 MHz fMCLKIN = 20 MHz, TA = −40°C to +85°C fMCLKIN = 20 MHz Full-scale range For specified performance VIN+ = ±250 mV, VIN− = 0 V VIN+ = 0 V, VIN− = 0 V VIN+ = 1 kHz 81 83 86 13.1 13.4 14 25 87 87 88 −96 −97 14.2 14.2 dB dB dB dB dB Bits Bits Bits kV/µs 30 −40°C to +85°C −40°C to +85°C CMOS with Schmitt trigger 0.8 × VDD2 0.2 × VDD2 ±0.6 10 V V µA pF 0.4 V V VDD2 − 0.1 Rev. B | Page 3 of 24 IO = −200 µA IO = +200 µA AD7403 Parameter POWER REQUIREMENTS VDD1 VDD2 IDD1 IDD2 Data Sheet Min 2 3 Max Unit Test Conditions/Comments 30 12 6 231 185 5.5 5.5 36 18 10 297 231 V V mA mA mA mW mW VDD1 = 5.5 V VDD2 = 5.5 V VDD2 = 3.3 V VDD1 = VDD2 = 5.5 V VDD1 = 5.5 V, VDD2 = 3.3 V 4.5 3 Power Dissipation 1 Typ For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, VDD1 = 5 V ± 5%. See the Terminology section. Not production tested. Sample tested during initial release to ensure compliance. AD7403-8 VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +105°C, fMCLKIN1 = 5 MHz to 20 MHz, tested with sinc3 filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground. Table 2. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 Offset Error2 Offset Drift vs. Temperature3 Offset Drift vs. VDD13 Gain Error2 Min ±2 ±6.5 ±0.99 ±1.7 6.8 ±1 2 425 ±0.2 ±0.2 32 20 ±0.2 −320 −250 Input Common-Mode Voltage Range Dynamic Input Current DC Leakage Current Input Capacitance DYNAMIC SPECIFICATIONS Signal-to-Noise-and-Distortion Ratio (SINAD)2 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Effective Number of Bits (ENOB)2 ISOLATION TRANSIENT IMMUNITY2 LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Max 16 Gain Error Drift vs. Temperature3 Gain Error Drift vs. VDD13 ANALOG INPUT Input Voltage Range Typ ±0.8 ±1.4 80 51 +320 +250 −200 to +300 ±45 0.05 ±0.01 14 ±50 ±0.6 Unit Test Conditions/Comments Bits LSB LSB mV µV/°C µV/V % FSR % FSR ppm/°C µV/°C mV/V Filter output truncated to 16 bits mV mV mV µA µA µA pF Guaranteed no missed codes to 16 bits fMCLKIN = 16 MHz fMCLKIN = 20 MHz Full-scale range For specified performance VIN+ = ±250 mV, VIN− = 0 V VIN+ = 0 V, VIN− = 0 V VIN+ = 1 kHz 82 86 13.3 25 87 88 −94 −94 14.2 30 dB dB dB dB Bits kV/µs CMOS with Schmitt trigger 0.8 × VDD2 0.2 × VDD2 ±0.6 10 V V µA pF 0.4 V V VDD2 − 0.1 Rev. B | Page 4 of 24 IO = −200 µA IO = +200 µA Data Sheet AD7403 Parameter POWER REQUIREMENTS VDD1 VDD2 IDD1 IDD2 Min 2 3 Max Unit Test Conditions/Comments 30 13 6.5 237 187 5.5 5.5 33.5 16 8 272 211 V V mA mA mA mW mW VDD1 = 5.5 V VDD2 = 5.5 V VDD2 = 3.3 V VDD1 = VDD2 = 5.5 V VDD1 = 5.5 V, VDD2 = 3.3 V 4.5 3 Power Dissipation 1 Typ For fMCLKIN > 16 MHz, mark space ratio is 48/52 to 52/48, VDD1 = 5 V ± 5%. See the Terminology section. Not production tested. Sample tested during initial release to ensure compliance. TIMING SPECIFICATIONS VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +105°C (AD7403-8) or −40°C to +125°C (AD7403), unless otherwise noted. Sample tested during initial release to ensure compliance. It is recommended to read MDAT on the MCLKIN rising edge. Table 3. Parameter fMCLKIN Limit at TMIN, TMAX Typ Max 20 Unit MHz MHz 40 45 42 ns ns ns 1 1 Data access time after MCLKIN rising edge VDD2 = 4.5 V to 5.5 V VDD2 = 3 V to 3.6 V, AD7403 VDD2 = 3 V to 3.6 V, AD7403-8 Data hold time after MCLKIN rising edge VDD2 = 4.5 V to 5.5 V VDD2 = 3 V to 3.6 V Master clock low time fMCLKIN ≤ 16 MHz 16 MHz < fMCLKIN ≤ 20 MHz Master clock high time fMCLKIN ≤ 16 MHz 16 MHz < fMCLKIN ≤ 20 MHz t21 12 17 ns ns 0.45 × tMCLKIN 0.48 × tMCLKIN ns ns 0.45 × tMCLKIN 0.48 × tMCLKIN ns ns t3 t4 1 Description Master clock input frequency Defined as the time required from an 80% MCLKIN input level to when the output crosses 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V as outlined in Figure 2. Measured with a ±200 μA load and a 25 pF load capacitance. t4 80% MCLKIN t1 t2 t3 2.0V OR 0.7 × VDD2 1 MDAT 0.8V 1SEE NOTE 1 OF TABLE 3 FOR FURTHER DETAILS. Figure 2. Data Timing Rev. B | Page 5 of 24 12196-002 t Min 5 AD7403 Data Sheet PACKAGE CHARACTERISTICS Table 4. Parameter Resistance (Input to Output)1 Capacitance (Input to Output)1 IC Junction to Ambient Thermal Resistance 1 Symbol RI-O CI-O θJA Min Typ 1012 2.2 45 Max Unit Ω pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces The device is considered a 2-terminal device. For AD7403, Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together. For AD7403-8, Pin 1 to Pin 4 are shorted together, Pin 5 to Pin 8 are shorted together. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 5. Parameter Input to Output Momentary Withstand Voltage Minimum External Air Gap (Clearance) AD7403 AD7403-8 Minimum External Tracking (Creepage) AD7403 AD7403-8 Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group 1 2 3 Symbol VISO Value 5000 min Unit V Test Conditions/Comments 1 minute duration L(I01) 8.3 min1, 2 mm L(I01) 8.1 min1, 2 mm Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance through air L(I02) 8.3 min1 mm L(I02) 8.1 min1 mm CTI 0.034 min >400 II mm V Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 13 Material Group (DIN VDE 0110, 1/89, Table I)3 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 m. Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. CSA CTI rating for the AD7403 is >600 V and a Material Group I isolation group. AD7403-8 is >400 and a Material Group II isolation group. REGULATORY INFORMATION Table 6. UL1 Recognized under 1577 Component Recognition Program1 5000 V rms Isolation Voltage Single Protection File E214100 CSA Approved under CSA Component Acceptance Notice 5A VDE2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Basic insulation per CSA 60950-1-07 and IEC 60950-1, AD7403: 830 V rms (1173 VPEAK), AD7403-8: 810 Vrms (1145 VPEAK) maximum working voltage3 Reinforced insulation per CSA 60950-1-07 and IEC 60950-1. AD7403: 415 V rms (586 VPEAK), AD7403-8: 405 V rms (583 VPEAK) maximum working voltage3 Reinforced insulation per IEC 60601-1, 250 V rms (353 VPEAK) maximum working voltage File 205078 Reinforced insulation per DIN V VDE V 0884-10 (VDE V 0884-10):2006-12, 1250 VPEAK File 2471900-4880-0001 In accordance with UL 1577, each AD7403 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA). In accordance with DIN V VDE V 0884-10, each AD7403 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC). 3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7403 RI-16-2 package material is rated by CSA to a CTI of >600 V and therefore Material Group I. The AD7403-8 RI-8-1 package material is rated by CSA to a CTI of >400 V and therefore Material Group II. 1 2 Rev. B | Page 6 of 24 Data Sheet AD7403 DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. Table 7. Description INSTALLATION CLASSIFICATION PER DIN VDE 0110 For Rated Mains Voltage ≤300 V rms For Rated Mains Voltage ≤450 V rms For Rated Mains Voltage ≤600 V rms For Rated Mains Voltage ≤1000 V rms CLIMATIC CLASSIFICATION POLLUTION DEGREE (DIN VDE 0110, TABLE 1) MAXIMUM WORKING INSULATION VOLTAGE INPUT TO OUTPUT TEST VOLTAGE, METHOD B1 VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC INPUT TO OUTPUT TEST VOLTAGE, METHOD A After Environmental Test Subgroup 1 VIORM × 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC After Input and/or Safety Test Subgroup 2/ Safety Test Subgroup 3 VIORM × 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 Seconds) SURGE ISOLATION VOLTAGE 1.2 µs Rise Time, 50 μs, 50% Fall Time SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3 AND Figure 4) Case Temperature Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation AD7403 AD7403-8 INSULATION RESISTANCE AT TS, VIO = 500 V Characteristic Unit VIORM I to IV I to IV I to IV I to IV 40/105/21 2 1250 VPEAK 2344 VPEAK 2000 VPEAK 1500 8000 12000 VPEAK VPEAK VPEAK VPEAK 150 °C 2.78 1.19 >109 W W Ω VPD(M) VPR(M) VIOTM VIOSM TS PSO RIO 3 2 1 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 1 0 0 Figure 3. AD7403 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 50 100 150 AMBIENT TEMPERATURE (°C) 200 12196-041 SAFE OPERATING POWER (W) 2 12196-003 SAFE OPERATING POWER (W) 4 Symbol Figure 4. AD7403-8 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. B | Page 7 of 24 AD7403 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground. Table 8. Parameter VDD1 to GND1 VDD2 to GND2 Analog Input Voltage to GND1 Digital Input Voltage to GND2 Output Voltage to GND2 Input Current to Any Pin Except Supplies1 Operating Temperature Range AD7403 AD7403-8 Storage Temperature Range Junction Temperature Pb-Free Temperature, Soldering Reflow ESD FICDM2 HBM3 Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −1 V to VDD1 + 0.3 V −0.3 V to VDD2 + 0.5 V −0.3 V to VDD2 + 0.3 V ±10 mA Table 9. Maximum Continuous Working Voltage1 Parameter AC Voltage Bipolar Waveform Max Unit Constraint 1250 VPEAK Unipolar Waveform 1250 VPEAK 1250 VPEAK 20-year minimum lifetime (VDE approved working voltage) 20-year minimum lifetime 20-year minimum lifetime DC Voltage 1 −40°C to +125°C −40°C to +105°C −65°C to +150°C 150°C Refers to continuous voltage magnitude imposed across the isolation barrier. ESD CAUTION 260°C 2 kV ±1250 V ±4000 V Transient currents of up to 100 mA do not cause SCR to latch up. JESD22-C101; RC network: 1 Ω, Cpkg; Class: IV. 3 ESDA/JEDEC JS-001-2011; RC network: 1.5 kΩ, 100 pF; Class: 3A. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 8 of 24 Data Sheet AD7403 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 GND2 15 NIC2 VIN+ 2 VIN– 3 AD7403 14 VDD2 GND1 4 TOP VIEW 13 MCLKIN NIC1 5 (Not to Scale) 12 NIC2 NIC1 6 11 MDAT VDD1 7 10 NIC2 9 GND2 1NIC = NOT INTERNALLY CONNECTED. CONNECT TO V DD1 , GND1, OR LEAVE FLOATING. 2NIC = NOT INTERNALLY CONNECTED. CONNECT TO V DD2 , GND2, OR LEAVE FLOATING. 12196-004 GND1 8 Figure 5. AD7403 Pin Configuration Table 10. AD7403 Pin Function Descriptions Mnemonic VDD1 2 3 4, 8 5, 6 9, 16 10, 12, 15 11 VIN+ VIN− GND1 NIC GND2 NIC MDAT 13 MCLKIN 14 VDD2 Description Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7403 and is relative to GND1. For device operation, connect the supply voltage to both Pin 1 and Pin 7. Decouple each supply pin to GND1 with a 10 µF capacitor in parallel with a 1 nF capacitor. Positive Analog Input. Negative Analog Input. Normally connected to GND1. Ground 1. This pin is the ground reference point for all circuitry on the isolated side. Not Internally Connected. These pins are not internally connected. Connect to VDD1, GND1, or leave floating. Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side. Not Internally Connected. These pins are not internally connected. Connect to VDD2, GND2, or leave floating. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge. Master Clock Logic Input. 5 MHz to 20 MHz frequency range. The bit stream from the modulator is propagated on the rising edge of the MCLKIN. Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Decouple this supply to GND2 with a 100 nF capacitor. VDD1 1 VIN+ 2 AD7403-8 8 VDD2 7 MCLKIN TOP VIEW 6 MDAT (Not to Scale) 5 GND2 GND1 4 VIN– 3 12196-038 Pin No. 1, 7 Figure 6. AD7403-8 Pin Configuration Table 11. AD7403-8 Pin Function Descriptions Pin No. 1 Mnemonic VDD1 2 3 4 5 6 VIN+ VIN− GND1 GND2 MDAT 7 MCLKIN 8 VDD2 Description Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7403-8 and is relative to GND1. For device operation, connect the supply voltage to both Pin 1 and Pin 7. Decouple each supply pin to GND1 with a 10 µF capacitor in parallel with a 1 nF capacitor. Positive Analog Input. Negative Analog Input. Normally connected to GND1. Ground 1. This pin is the ground reference point for all circuitry on the isolated side. Ground 2. This pin is the ground reference point for all circuitry on the nonisolated side. Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are clocked out on the rising edge of the MCLKIN input and are valid on the following MCLKIN rising edge. Master Clock Logic Input. 5 MHz to 20 MHz frequency range. The bit stream from the modulator is propagated on the rising edge of the MCLKIN. Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2. Decouple this supply to GND2 with a 100 nF capacitor. Rev. B | Page 9 of 24 AD7403 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, fMCLKIN = 20 MHz, using a sinc3 filter with a 256 oversampling ratio (OSR), unless otherwise noted. 0 90 200mV p-p SINE WAVE ON VDD1 1nF DECOUPLING 88 –20 86 84 SINAD (dB) PSRR (dB) –40 –60 MCLKIN = 20MHz MCLKIN = 10MHz –80 82 16MHz MCLKIN, 16MHz MCLKIN, 16MHz MCLKIN, 20MHz MCLKIN, 20MHz MCLKIN, 20MHz MCLKIN, 80 78 76 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 = 4.5V = 5.0V = 5.5V = 4.5V = 5.0V = 5.5V 74 –100 1M 70 100 12196-005 800k 400k 600k 200k SUPPLY RIPPLE FREQUENCY (Hz) 0 Figure 7. AD7403 PSRR vs. Supply Ripple Frequency 10k Figure 10. SINAD vs. Analog Input Frequency 0 0 –20 –20 200mV p-p SINE WAVE ON VDD1 1nF DECOUPLING fIN = 1kHz SNR = 88.6dB SINAD = 88.3dB THD = –100.5dB –40 MAGNITUDE (dB) –40 –60 –80 MCLKIN = 20MHz MCLKIN = 10MHz –100 –60 –80 –100 –120 –120 –140 200k 400k 600k 800k SUPPLY RIPPLE FREQUENCY (Hz) 0 1M 12196-042 –140 –160 0 5 10 15 20 25 30 FREQUENCY (kHz) Figure 8. AD7403-8 PSRR vs. Supply Ripple Frequency 12196-008 PSRR (dB) 1k ANALOG INPUT FREQUENCY (Hz) 12196-007 72 –120 Figure 11. Typical Fast Fourier Transform (FFT) 0 1.0 SHORTED INPUTS 200mV p-p SINE WAVE ON INPUTS –20 0.8 0.6 DNL ERROR (LSB) MCLKIN = 20MHz, SINC3 DECIMATION RATE = 256 MCLKIN = 10MHz, SINC3 DECIMATION RATE = 256 MCLKIN = 20MHz, UNFILTERED MCLKIN = 10MHz, UNFILTERED –60 –80 0.4 0.2 0 –0.2 –0.4 –100 –0.6 –120 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M Figure 9. CMRR vs. Common-Mode Ripple Frequency –1.0 0 10 20 30 40 CODE (k) Figure 12. Typical DNL Error Rev. B | Page 10 of 24 50 60 12196-009 –0.8 –140 100 12196-006 CMRR (dB) –40 Data Sheet AD7403 100 1.0 fIN = 1kHz 0.8 0.6 SNR AND SINAD (dB) INL ERROR (LSB) 90 0.4 0.2 0 –0.2 –0.4 SNR SINAD 80 70 –0.6 0 10 20 30 40 50 60 CODE (k) 60 –50 12196-010 –1.0 –25 0 25 50 75 100 125 150 125 150 TEMPERATURE (°C) Figure 13. AD7403 Typical INL Error 12196-012 –0.8 Figure 16. SNR and SINAD vs. Temperature –60 1.0 fIN = 1kHz –70 THD AND SFDR (dB) 0 –0.5 –1.0 –80 –100 10 20 30 CODE (k) 40 50 60 –120 –50 12196-043 0 –25 0 25 50 75 100 TEMPERATURE (°C) Figure 14. AD7403-8 Typical INL Error 12196-013 –110 –1.5 Figure 17. AD7403 THD and SFDR vs. Temperature –60 800 692381 700 –70 THD AND SFDR (dB) 500 400 300 200 THD SFDR fIN = 1kHz MCLKIN = 10MHz VIN+ = VIN– = 0V 1M SAMPLES 600 –80 –90 –100 160941 144470 –110 100 0 0 1147 32764 32765 32766 32767 32768 1061 0 32769 32770 CODE –120 –50 12196-011 HITS PER CODE (k) THD SFDR –90 –25 0 25 50 TEMPERATURE (°C) 75 100 Figure 18. AD7403-8 THD and SFDR vs. Temperature Figure 15. Histogram of Codes at Code Center Rev. B | Page 11 of 24 125 12196-044 INL ERROR (LSB) 0.5 AD7403 Data Sheet 35 200 MCLKIN = 20MHz 150 30 100 25 0 20 MCLKIN = 20MHz, –40°C MCLKIN = 20MHz, +25°C MCLKIN = 20MHz, +85°C MCLKIN = 20MHz, +125°C MCLKIN = 10MHz, –40°C MCLKIN = 10MHz, +25°C MCLKIN = 10MHz, +85°C MCLKIN = 10MHz, +125°C 15 –50 10 –100 5 –150 0 –25 25 50 75 100 125 150 TEMPERATURE (°C) 0 4.50 12196-014 –200 –50 5.00 4.75 5.25 5.50 VDD1 (V) 12196-016 IDD1 (mA) OFFSET (µV) 50 Figure 22. IDD1 vs. VDD1 at Various Temperatures and Clock Rates Figure 19. AD7403 Offset vs. Temperature 32 800 TA = –40°C TA = 0°C TA = +25°C TA = +85°C TA = +125°C 31 600 DC INPUT 30 IDD1 (mA) OFFSET (µV) 400 200 29 28 0 27 MCLKIN = 10MHz MCLKIN = 16MHz MCLKIN = 20MHz –25 0 25 50 TEMPERATURE (°C) 75 100 125 25 –250 –125 0 125 250 VIN+ DC INPUT (mV) 12196-017 –400 –50 26 12196-045 –200 Figure 23. IDD1 vs. VIN+ DC Input at Various Temperatures Figure 20. AD7403-8 Offset vs. Temperature 10 14 MCLKIN = 10MHz MCLKIN = 20MHz 8 12 10 IDD2 (mA) 2 0 –2 –4 8 6 MCLKIN = 20MHz, –40°C MCLKIN = 20MHz, +25°C MCLKIN = 20MHz, +85°C MCLKIN = 20MHz, +125°C MCLKIN = 10MHz, –40°C MCLKIN = 10MHz, +25°C MCLKIN = 10MHz, +85°C MCLKIN = 10MHz, +125°C 4 –6 2 –8 –10 –50 –25 0 25 50 75 100 TEMPERATURE (°C) 125 150 0 3.0 3.5 4.0 4.5 5.0 5.5 VDD2 (V) Figure 24. IDD2 vs. VDD2 at Various Temperatures and Clock Rates Figure 21. Gain Error vs. Temperature Rev. B | Page 12 of 24 12196-018 4 12196-015 GAIN ERROR (mV) 6 Data Sheet AD7403 60 14 TA = –40°C TA = 0°C TA = +25°C TA = +85°C TA = +125°C 13 DC INPUT DC INPUT 40 IIN+ (µA) 12 0 MCLKIN = 5MHz MCLKIN = 10MHz MCLKIN = 20MHz –20 11 10 –250 –125 0 125 VIN+ DC INPUT (mV) 250 –60 –320 –240 –160 –80 0 80 160 240 VIN+ DC INPUT (mV) Figure 26. IIN+ vs. VIN+ DC Input at Various Clock Rates Figure 25. IDD2 vs. VIN+ DC Input at Various Temperatures Rev. B | Page 13 of 24 320 12196-020 –40 12196-019 IDD2 (mA) 20 AD7403 Data Sheet TERMINOLOGY Total Harmonic Distortion (THD) THD is the ratio of the rms sum of harmonics to the fundamental. It is defined as Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are specified negative full scale, −250 mV (VIN+ − VIN−), Code 7168 for the 16-bit level, and specified positive full scale, +250 mV (VIN+ − VIN−), Code 58,368 for the 16-bit level. THD(dB) = 20 log V2 2 + V3 2 + V4 2 + V5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error Offset error is the deviation of the midscale code (32,768 for the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V). Gain Error The gain error includes both positive full-scale gain error and negative full-scale gain error. Positive full-scale gain error is the deviation of the specified positive full-scale code (58,368 for the 16-bit level) from the ideal VIN+ − VIN− (250 mV) after the offset error is adjusted out. Negative full-scale gain error is the deviation of the specified negative full-scale code (7168 for the 16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the offset error is adjusted out. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD is the measured ratio of signal to noise and distortion at the output of the ADC. The signal is the rms value of the sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), including harmonics, but excluding dc. Signal-to-Noise Ratio (SNR) SNR is the measured ratio of signal to noise at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. The theoretical signal-to-noise ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-Noise Ratio = (6.02N + 1.76) dB Therefore, for a 12-bit converter, the SNR is 74 dB. Isolation Transient Immunity The isolation transient immunity specifies the rate of rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. The AD7403 was tested using a transient pulse frequency of 100 kHz. Peak Harmonic or Spurious Noise (SFDR) Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Effective Number of Bits (ENOB) ENOB is defined by ENOB = (SINAD − 1.76)/6.02 bits Noise Free Code Resolution Noise free code resolution represents the resolution in bits for which there is no code flicker. The noise free code resolution for an N-bit converter is defined as Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise) The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V. Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at ±250 mV frequency, f, to the power of a +250 mV peak-to-peak sine wave applied to the common-mode voltage of VIN+ and VIN− of frequency, fS, as CMRR (dB) = 10 log(Pf/PfS) where: Pf is the power at frequency, f, in the ADC output. PfS is the power at frequency, fS, in the ADC output. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSRR is the maximum change in the specified full-scale (±250 mV) transition point due to a change in power supply voltage from the nominal value. Rev. B | Page 14 of 24 Data Sheet AD7403 THEORY OF OPERATION A differential signal of 0 V ideally results in a stream of alternating 1s and 0s at the MDAT output pin. This output is high 50% of the time and low 50% of the time. A differential input of 250 mV produces a stream of 1s and 0s that are high 89.06% of the time. A differential input of −250 mV produces a stream of 1s and 0s that are high 10.94% of the time. CIRCUIT INFORMATION The AD7403 isolated Σ-Δ modulator converts an analog input signal into a high speed (20 MHz maximum), single-bit data stream; the time average single-bit data from the modulator is directly proportional to the input signal. Figure 27 shows a typical application circuit where the AD7403 is used to provide isolation between the analog input, a current sensing resistor or shunt, and the digital output, which is then processed by a digital filter to provide an N-bit word. A differential input of 320 mV ideally results in a stream of all 1s. A differential input of −320 mV ideally results in a stream of all 0s. The absolute full-scale range is ±320 mV and the specified full-scale performance range is ±250 mV, as shown in Table 12. ANALOG INPUT Table 12. Analog Input Range The differential analog input of the AD7403 is implemented with a switched capacitor circuit. This circuit implements a second-order modulator stage that digitizes the input signal into a single-bit output stream. The sample clock (MCLKIN) provides the clock signal for the conversion process as well as the output data framing clock. This clock source is externally supplied to the AD7403. The analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. A digital stream that accurately represents the analog input over time appears at the output of the converter (see Figure 28). Analog Input Positive Full-Scale Value Positive Specified Performance Input Zero Negative Specified Performance Input Negative Full-Scale Value Voltage Input (mV) +320 +250 0 −250 −320 FLOATING POWER SUPPLY +400V NONISOLATED 5V/3V GATED DRIVE CIRCUIT 10µF 1nF VDD1 220pF 10Ω VIN+ 10Ω RSHUNT FLOATING POWER SUPPLY 220pF VDD2 Σ-Δ MOD/ ENCODER MDAT MDAT MCLKIN MCLK VDD GND1 5.1V SINC3 FILTER* CS DECODER SCLK VIN– 10µF 1nF VDD1 DECODER GND2 GND1 GATED DRIVE CIRCUIT SDAT 100nF ENCODER GND 12196-022 *THIS FILTER IS IMPLEMENTED WITH AN FPGA OR DSP –400V Figure 27. Typical Application Circuit MODULATOR OUTPUT +FS ANALOG INPUT –FS ANALOG INPUT ANALOG INPUT Figure 28. Analog Input vs. Modulator Output Rev. B | Page 15 of 24 12196-021 MOTOR AD7403 AD7403 Data Sheet To reconstruct the original information, this output must be digitally filtered and decimated. A sinc3 filter is recommended because it is one order higher than that of the AD7403 modulator, which is a second-order modulator. If a 256 decimation rate is used, the resulting 16-bit word rate is 78.1 kSPS, assuming a 20 MHz external clock frequency. See the Digital Filter section for more detailed information on the sinc filter implementation. Figure 29 shows the transfer function of the AD7403 relative to the 16-bit output. DIFFERENTIAL INPUTS The analog input to the modulator is a switched capacitor design. The analog signal is converted into charge by highly linear sampling capacitors. A simplified equivalent circuit diagram of the analog input is shown in Figure 30. A signal source driving the analog input must provide the charge onto the sampling capacitors every half MCLKIN cycle and settle to the required accuracy within the next half cycle. φA VIN+ 65535 300Ω 58368 VIN– 300Ω φB 1.9pF φA 1.9pF φB MCLKIN φA φB φA φB 12196-024 ADC CODE SPECIFIED RANGE Figure 30. Analog Input Equivalent Circuit 7168 Because the AD7403 samples the differential voltage across its analog inputs, low noise performance is attained with an input circuit that provides low common-mode noise at each input. DIGITAL OUTPUT –320mV –250mV +250mV +320mV ANALOG INPUT Figure 29. Filtered and Decimated 16-Bit Transfer Function 12196-023 0 The AD7403 MDAT output driver is a slew rate limited driver. This driver lowers electromagnetic emissions, thus minimizing electromagnetic interference (EMI), both conducted and radiated. Rev. B | Page 16 of 24 Data Sheet AD7403 APPLICATIONS INFORMATION 90 CURRENT SENSING APPLICATIONS AD7403 20MHz AD7403-8 20MHz The AD7403 is ideally suited for current sensing applications where the voltage across a shunt resistor (RSHUNT) is monitored. The load current flowing through an external shunt resistor produces a voltage at the input terminals of the AD7403. The AD7403 provides isolation between the analog input from the current sensing resistor and the digital outputs. By selecting the appropriate shunt resistor value, a variety of current ranges can be monitored. 85 SINAD (dB) 80 75 13-BIT ENOB 70 65 The shunt resistor (RSHUNT) values used in conjunction with the AD7403 are determined by the specific application requirements in terms of voltage, current, and power. Small resistors minimize power dissipation, whereas low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. The final values chosen are a compromise between low power dissipation and accuracy. Higher value resistors use the full performance input range of the ADC, thus achieving maximum SNR performance. Low value resistors dissipate less power but do not use the full performance input range. The AD7403, however, delivers excellent performance, even with lower input signal levels, allowing low value shunt resistors to be used while maintaining system performance. 11-BIT ENOB 60 0 50 100 150 VIN+ (mV) 200 250 Figure 31. SINAD vs. VIN+ AC Input Signal Amplitude 1.6 DC INPUT 100k SAMPLES PER DATA POINT 1.4 RMS NOISE (LSB) 1.2 MCLKIN = 5MHz MCLKIN = 10MHz MCLKIN = 20MHz 1.0 0.8 0.6 0.4 To choose a suitable shunt resistor, first determine the current through the shunt. The shunt current for a 3-phase induction motor can be expressed as 0 –320 –240 –160 –80 0 80 160 240 320 12196-026 0.2 VIN+ DC INPUT SIGNAL AMPLITUDE (mV) PW 1.73 × V × EF × PF 12196-046 fIN = 1kHz MCLKIN = 20MHz VDD1 = 5V VDD2 = 5V TA = 25°C 12-BIT ENOB Choosing RSHUNT I RMS = 14-BIT ENOB Figure 32. RMS Noise vs. VIN+ DC Input Signal Amplitude where: IRMS is the motor phase current (A rms). PW is the motor power (Watts). V is the motor supply voltage (V ac). EF is the motor efficiency (%). PF is the power efficiency (%). To determine the shunt peak sense current, ISENSE, consider the motor phase current and any overload that may be possible in the system. When the peak sense current is known, divide the voltage range of the AD7403 (±250 mV) by the peak sense current to yield a maximum shunt value. If the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced and less of the ADC input range can be used. Figure 31 shows the SINAD performance characteristics and the ENOB of resolution for the AD7403 for different input signal amplitudes. Figure 32 shows the rms noise performance for dc input signal amplitudes. The performance of the AD7403 at lower input signal ranges allows smaller shunt values to be used while still maintaining a high level of performance and overall system efficiency. RSHUNT must be able to dissipate the I2R power losses. If the power dissipation rating of the resistor is exceeded, its value may drift or the resistor may be damaged, resulting in an open circuit. This open circuit can result in a differential voltage across the terminals of the AD7403, in excess of the absolute maximum ratings. If ISENSE has a large high frequency component, choose a resistor with low inductance. VOLTAGE SENSING APPLICATIONS The AD7403 can also be used for isolated voltage monitoring. For example, in motor control applications, it can be used to sense the bus voltage. In applications where the voltage being monitored exceeds the specified analog input range of the AD7403, a voltage divider network can be used to reduce the voltage being monitored to the required range. Rev. B | Page 17 of 24 AD7403 Data Sheet INPUT FILTER DIGITAL FILTER In a typical use case for directly measuring the voltage across a shunt resistor, the AD7403 can be connected directly across the shunt resistor with a simple RC low-pass filter on each input. The output of the AD7403 is a continuous digital bit stream. To reconstruct the original input signal information, this output bit stream needs to be digitally filtered and decimated. A sinc filter is recommended due to its simplicity. A sinc3 filter is recommended because it is one order higher than that of the AD7403 modulator, which is a second-order modulator. The type of filter selected, the decimation rate, and the modulator clock used determines the overall system resolution and throughput rate. The higher the decimation rate, the greater the system accuracy, as illustrated in Figure 36. However, there is a trade-off between accuracy and throughput rate and, therefore, higher decimation rates result in lower throughput solutions. Note that for a given bandwidth requirement, a higher MCLKIN frequency can allow higher decimation rates to be used, resulting in higher SNR performance. The recommended circuit configuration for driving the differential inputs to achieve best performance is shown in Figure 33. An RC low-pass filter is placed on both the analog input pins. Recommended values for the resistors and capacitors are 10 Ω and 220 pF, respectively. If possible, equalize the source impedance on each analog input to minimize offset. C R VIN+ AD7403 R 12196-027 VIN– 100 90 Figure 33. RC Low-Pass Filter Input Network 80 70 SNR (dB) The input filter configuration for the AD7403 is not limited to the low-pass structure shown in Figure 33. The differential RC filter configuration shown in Figure 34 also achieves excellent performance. Recommended values for the resistors and capacitor are 22 Ω and 47 pF, respectively. 40 SINC1 SINC2 SINC3 SINC4 20 10 12196-028 R VIN– 0 10 Figure 34. Differential RC Filter Network 100 1000 DECIMATION RATE Figure 35 compares the typical performance for the input filter structures outlined in Figure 33 and Figure 34 for different resistor and capacitor values. 95 fIN = 1kHz Figure 36. SNR vs. Decimation Rate for Different Sincx Filter Orders A sinc3 filter is recommended for the AD7403. This filter can be implemented on a field programmable gate array (FPGA) or a digital signal processor (DSP). Equation 1 describes the transfer function of a sinc filter. 90 85 1 (1 − Z − DR ) H ( z ) = −1 DR (1 − Z ) 80 SNR (dB) 50 AD7403 C 75 65 LOW PASS, 10Ω, 220pF DIFFERENTIAL, 22Ω, 47pF DIFFERENTIAL, 22Ω, 10nF 1000 Throughput = 12196-029 DECIMATION RATE (1) The throughput rate of the sinc filter is determined by the modulator clock and the decimation rate selected. 55 100 N where: DR is the decimation rate. N is the sinc filter order. 70 50 10 60 30 R VIN+ 60 fIN = 1kHz 12196-030 C Figure 35. SNR vs. Decimation Rate for Different Filter Structures for Different Resistor and Capacitor Values MCLK DR (2) where MCLK is the modulator clock frequency As the decimation rate increases, the data output size from the sinc filter increases. The output data size is expressed in Equation 3. The 16 most significant bits are used to return a 16-bit result. Data size = N × log2 DR Rev. B | Page 18 of 24 (3) Data Sheet AD7403 Z = one sample delay MCLKOUT = modulators conversion bit rate */ MCLKIN Throughput Rate (kHz) 625 312.5 156.2 78.1 39.1 Output Data Size (Bits) 15 18 21 24 27 Filter Response (kHz) 163.7 81.8 40.9 20.4 10.2 The following Verilog code provides an example of a sinc3 filter implementation on a Xilinx® Spartan®-6 FPGA. Note that the data is read on the positive clock edge. It is recommended to read in the data on the positive clock edge. The code is configurable to accommodate decimation rates from 32 to 4096. module dec256sinc24b ( input mclk1, /* used to clk filter */ input reset, /* used to reset filter */ input mdata1, /* input data to be filtered */ output reg [15:0] DATA, /* filtered output */ output reg data_en, input [15:0] dec_rate ); [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] [36:0] + Z ACC3+ + always @ (negedge mclk1, posedge reset) begin if (reset) begin /* initialize acc registers on reset */ acc1 <= 37'd0; acc2 <= 37'd0; acc3 <= 37'd0; end else begin /*perform accumulation process */ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end end /*decimation stage (MCLKOUT/WORD_CLK) */ always @ (posedge mclk1, posedge reset) begin if (reset) word_count <= 16'd0; else begin ip_data1; acc1; acc2; acc3; acc3_d2; diff1; diff2; diff3; diff1_d; diff2_d; if ( word_count == dec_rate - 1 ) word_count <= 16'd0; else word_count <= word_count + 16'b1; end end always @ ( posedge mclk1, posedge reset ) begin if ( reset ) word_clk <= 1'b0; else begin if ( word_count == dec_rate/2 1 ) word_clk <= 1'b1; else if ( word_count == dec_rate - 1 ) word_clk <= 1'b0; end end reg [15:0] word_count; reg word_clk; reg enable; /*Perform the Sinc always @ (mdata1) if(mdata1==0) ip_data1 <= /* change 0 complement */ else ip_data1 <= Z Figure 37. Accumulator /* Data is read on positive clk edge */ reg reg reg reg reg reg reg reg reg reg Z + Table 13. Sinc3 Filter Characteristics for 20 MHz MCLKIN Decimation Ratio (DR) 32 64 128 256 512 ACC2+ ACC1+ IP_DATA1 12196-031 For a sinc3 filter, the −3 dB filter response point can be derived from the filter transfer function, Equation 1, and is 0.262 times the throughput rate. The filter characteristics for a third-order sinc filter are summarized in Table 13. action*/ 37'd0; to a -1 for twos 37'd1; /*Accumulator (Integrator) Perform the accumulation (IIR) at the speed of the modulator. /*Differentiator (including decimation stage) Perform the differentiation stage (FIR) at a lower speed. Rev. B | Page 19 of 24 AD7403 Data Sheet Z = one sample delay WORD_CLK = output word rate */ + ACC3 DIFF1 + – DIFF2 + – Z–1 Z–1 12196-032 Z–1 DIFF3 – WORD_CLK Figure 38. Differentiator always @ (posedge word_clk, posedge reset) begin if(reset) begin acc3_d2 <= 37'd0; diff1_d <= 37'd0; diff2_d <= 37'd0; diff1 <= 37'd0; diff2 <= 37'd0; diff3 <= 37'd0; end else begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end 16'd512:begin DATA <= (diff3[27:11] == 17'h10000) ? 16'hFFFF : diff3[26:11]; end 16'd1024:begin DATA <= (diff3[30:14] == 17'h10000) ? 16'hFFFF : diff3[29:14]; end 16'd2048:begin DATA <= (diff3[33:17] == 17'h10000) ? 16'hFFFF : diff3[32:17]; end 16'd4096:begin DATA <= (diff3[36:20] == 17'h10000) ? 16'hFFFF : diff3[35:20]; end default:begin DATA <= (diff3[24:8] == 17'h10000) ? 16'hFFFF : diff3[23:8]; end endcase end diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; /* Synchronize Data Output*/ always@ ( posedge mclk1, posedge reset ) begin if ( reset ) begin data_en <= 1'b0; enable <= 1'b1; end else begin if ( (word_count == dec_rate/2 - 1) && enable ) begin data_en <= 1'b1; enable <= 1'b0; end else if ( (word_count == dec_rate - 1) && ~enable ) begin data_en <= 1'b0; enable <= 1'b1; end else data_en <= 1'b0; end end /* Clock the Sinc output into an output register WORD_CLK = output word rate */ DIFF3 DATA 12196-033 WORD_CLK Figure 39. Clocking Sinc3 Output into an Output Register always @ ( posedge word_clk ) begin case ( dec_rate ) 16'd32:begin DATA <= (diff3[15:0] == 16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0}; end 16'd64:begin DATA <= (diff3[18:2] == 17'h10000) ? 16'hFFFF : diff3[17:2]; end 16'd128:begin DATA <= (diff3[21:5] == 17'h10000) ? 16'hFFFF : diff3[20:5]; end 16'd256:begin end end endmodule Rev. B | Page 20 of 24 Data Sheet AD7403 Figure 40 shows the typical interface between the AD7403 and the ADSP-CM4xx. Additional information on the configuration of the sinc filter modules in the ADSP-CM4xx can be found in the AN-1265 Application Note. SINC PAIR n SINC0_D0 MDAT PRIMARY LIMIT SECONDARY CONTROL FOR GROUP n MCLKIN AD74031 MODULATOR CLOCK n 12196-034 SINC0_CLK0 ADSP-CM4xx1 1ADDITIONAL PINS OMITTED FOR CLARITY Figure 40. Interfacing the AD7403 to the ADSP-CM4xx ISOLATION BARRIER 4.5V TO 36V ADP2441 DC-TO-DC SWITCHING REGULATOR 5V VDD1 VDD2 5V DIGITAL 12196-040 The ADSP-CM4xx family of mixed-signal control processors contains on-chip sinc filter and clock generation modules for direct connection to the AD7403 MCLKIN and MDAT pins. The ADSP-CM4xx can process bit streams from four AD7403 devices using a pair of configurable sinc filters for each bit stream. The primary sinc filter of each pair produces the filtered and decimated output for the pair. The output can be decimated to any integer rate between 8 and 256 times lower than the input rate. The four secondary sinc filters are low latency filters with programmable positive and negative overrange detection comparators that can be used to detect system fault conditions Another method is to regulate a dc supply on the high voltage side of the isolation barrier using a step-down dc-to-dc regulator, such as the ADP2441. AD7403 INTERFACING TO ADSP-CM4xx Figure 42. ADP2441 Step-Down DC-to-DC Regulator Example GROUNDING AND LAYOUT It is recommended to decouple the VDD1 supply with a 10 μF capacitor in parallel with a 1 nF capacitor to GND1. Decouple Pin 1 and Pin 7 individually. Decouple the VDD2 supply with a 100 nF value to GND2. In applications involving high commonmode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout so that any coupling that occurs equally affects all pins on a given component side. Failure to ensure equal coupling can cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. Place any decoupling used as close to the supply pins as possible. Minimize series resistance in the analog inputs to avoid any distortion effects, especially at high temperatures. If possible, equalize the source impedance on each analog input to minimize offset. Check for mismatch and thermocouple effects on the analog input printed circuit board (PCB) tracks to reduce offset drift. POWER SUPPLY CONSIDERATIONS INSULATION LIFETIME The AD7403 requires a 5 V VDD1 supply, and there are various means of achieving this. One method is to use an isolated dc-todc converter such as the ADuM6000. This method provides a 5 V regulated dc supply across the isolation barrier. Note that the inherent isolation of the ADuM6000 is lower than the AD7403. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the AD7403. DC-TO-DC CONVERTER 5V DIGITAL VDD2 12196-039 VDD1 AD7403 5V ISO ADuM6000 ISOLATION BARRIER Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 9 summarize the peak voltage for 20 years of service life for a bipolar, ac operating condition and the maximum VDE approved working voltages. Figure 41. ADuM6000 Isolated 5 V DC-to-DC Regulator Example Rev. B | Page 21 of 24 AD7403 Data Sheet • The value that ensures at least a 20-year lifetime of continuous use. The maximum VDE approved working voltage. 12196-035 RATED PEAK VOLTAGE 0V Figure 43. Bipolar AC Waveform, 50 Hz or 60 Hz RATED PEAK VOLTAGE 0V Figure 44. Unipolar AC Waveform, 50 Hz or 60 Hz Note that the lifetime of the AD7403 varies according to the waveform type imposed across the isolation barrier. The iCoupler insulation structure is stressed differently, depending on whether the waveform is bipolar ac, unipolar ac, or dc. RATED PEAK VOLTAGE 12196-037 • Figure 43, Figure 44, and Figure 45 illustrate the different isolation voltage waveforms. 12196-036 These tests subjected the AD7403 to continuous cross isolation voltages. To accelerate the occurrence of failures, the selected test voltages were values exceeding those of normal use. The time to failure values of these units were recorded and used to calculate the acceleration factors. These factors were then used to calculate the time to failure under the normal operating conditions. The values shown in Table 9 are the lesser of the following two values: 0V Figure 45. DC Waveform Rev. B | Page 22 of 24 Data Sheet AD7403 OUTLINE DIMENSIONS 12.85 12.75 12.65 1.93 REF 16 9 7.60 7.50 7.40 1 10.51 10.31 10.11 8 PIN 1 MARK 2.44 2.24 45° 0.32 0.23 SEATING PLANE 1.27 BSC 8° 0° 1.01 0.76 0.51 0.46 0.36 11-15-2011-A 0.30 0.20 0.10 COPLANARITY 0.1 0.71 0.50 0.31 0.25 BSC GAGE PLANE 2.64 2.54 2.44 COMPLIANT TO JEDEC STANDARDS MS-013-AC Figure 46. 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-16-2) Dimensions shown in millimeters 6.05 5.85 5.65 8 5 7.60 7.50 7.40 1 10.51 10.31 10.11 4 2.45 2.35 2.25 0.30 0.20 0.10 COPLANARITY 0.10 2.65 2.50 2.35 1.27 BSC 0.51 0.41 0.31 SEATING PLANE 0.75 0.50 0.25 1.04 BSC 0.75 0.58 0.40 45° 8° 0° 0.33 0.27 0.20 Figure 47. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-8-1) Dimensions shown in millimeters Rev. B | Page 23 of 24 09-17-2014-B PIN 1 MARK AD7403 Data Sheet ORDERING GUIDE Model1 AD7403-8BRIZ AD7403-8BRIZ-RL AD7403-8BRIZ-RL7 AD7403BRIZ AD7403BRIZ-RL AD7403BRIZ-RL7 EVAL-AD7403-8FMCZ EVAL-AD7403FMCZ EVAL-SDP-CH1Z 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] 16-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] AD7403-8 Evaluation Board AD7403 Evaluation Board System Demonstration Platform Z = RoHS Compliant Part. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12196-0-5/15(B) Rev. B | Page 24 of 24 Package Option RI-8-1 RI-8-1 RI-8-1 RI-16-2 RI-16-2 RI-16-2