FEATURES APPLICATIONS General-purpose, low power, multichannel isolation 1 MHz low power serial peripheral interface (SPI) 4 mA to 20 mA loop process control GENERAL DESCRIPTION VDD1 1 20 VDD2 GND1 2 19 GND2 NIC 3 18 NIC NIC 4 17 NIC ADuM124x VIA/VOA 5 ENCODE DECODE 16 VOA/VIA VIB 6 ENCODE DECODE 15 VOB EN1 7 14 EN2 NIC 8 13 NIC NIC 9 12 NIC GND1 10 11 GND2 11925-002 FUNCTIONAL BLOCK DIAGRAMS Ultralow power operation 3.3 V operation 5.6 µA per channel quiescent current, refresh enabled 0.3 µA per channel quiescent current, refresh disabled 148 µA/Mbps per channel typical dynamic current 2.5 V operation 3.1 µA per channel quiescent current, refresh enabled 0.1 µA per channel quiescent current, refresh disabled 116 µA/Mbps per channel typical dynamic current Small, 20-lead SSOP package and small 8-lead SOIC package Bidirectional communication Up to 2 Mbps data rate nonreturn to zero (NRZ) High temperature operation: 125°C High common-mode transient immunity: >25 kV/µs Safety and Regulatory Approvals UL 1577 component recognition program (pending) 3750 V rms for 1 minute per UL 1577 (20-lead SSOP) 3000 V rms for 1 minute per UL 1577 (8-lead SOIC) CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 849 V peak (20-lead SSOP) VIORM = 560 V peak (8-lead SOIC) Figure 1. 20-Lead SSOP Package Functional Block Diagram VDD1 1 8 VDD2 ADuM124x VIA/VOA 2 ENCODE DECODE 7 VOA/VIA VIB 3 ENCODE DECODE 6 VOB 5 GND2 GND1 4 11925-102 Data Sheet Micropower, Dual-Channel Digital Isolators ADuM1240/ADuM1241/ADuM1245/ADuM1246 Figure 2. 8-Lead SOIC Package Functional Block Diagram The ADuM1240/ADuM1241/ADuM1245/ADuM1246 are packaged in either a 20-lead SSOP for 3.75 kV reinforced isolation or an 8-lead SOIC for 3 kV basic isolation. The devices meet regulatory requirements, such as UL and CSA standards. In addition to the space saving package options, the ADuM1240/ ADuM1241/ADuM1245/ADuM1246 operate with supplies as low as 2.25 V. All models provide low, pulse width distortion at <8 ns. In addition, every model has an input glitch filter to protect against extraneous noise disturbances. 1000 The ADuM1240/ADuM1241/ADuM1245/ADuM1246 are micropower, 2-channel, digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed, complementary metal oxide semiconductor (CMOS) and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to the alternatives, such as optocoupler devices. The 20-lead SSOP version of the ADuM1240/ADuM1241/ ADuM1245/ADuM1246 allows control of the internal refresh functions. As shown in Figure 3, in standard operating mode, when ENx = 0 (internal refresh enabled), the current per channel is less than 10 µA. 1 100 10 ENx = 0 ENx = 1 1 0.1 0.1 1 10 100 DATA RATE (kbps) 1000 10000 11925-001 When ENx = 1 (internal refresh disabled), the current per channel drops to less than 1 µA. TYPICAL TOTAL SUPPLY CURRENT PER CHANNEL (µA) 1 Figure 3. Typical Total Supply Current (IDD1 + IDD2) per Channel (VDDx = 3.3 V) as a Function of Data Rate Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ..................................................... 10 Applications ....................................................................................... 1 Continuous Working Voltage ................................................... 10 General Description ......................................................................... 1 ESD Caution................................................................................ 10 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 11 Revision History ............................................................................... 2 Truth Tables................................................................................. 13 Specifications..................................................................................... 3 Typical Performance Characteristics ........................................... 14 Electrical Characteristics—3.3 V Operation ............................ 3 Applications Information .............................................................. 17 Electrical Characteristics—2.5 V Operation ............................ 4 PCB Layout ................................................................................. 17 Electrical Characteristics—VDD1 = 3.3 V, VDD2 = 2.5 V Operation....................................................................................... 6 Propagation Delay Related Parameters ................................... 17 Electrical Characteristics—VDD1 = 2.5 V, VDD2 = 3.3 V Operation....................................................................................... 6 Magnetic Field Immunity ......................................................... 18 Package Characteristics ............................................................... 7 Regulatory Information ............................................................... 7 Insulation and Safety Related Specifications ............................ 8 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics ............................................................ 8 DC Correctness and Low Power Operation ........................... 17 Power Consumption .................................................................. 19 Insulation Lifetime ..................................................................... 19 Packaging and Ordering Information ......................................... 20 Outline Dimensions ................................................................... 20 Ordering Guide .......................................................................... 21 Recommended Operating Conditions ...................................... 9 REVISION HISTORY 3/14—Rev. 0 to Rev. A Added 8-lead SOIC Package ............................................. Universal Changes to Features Section, General Description Section, and Figure 3 .............................................................................................. 1 Deleted Product Highlights Section............................................... 1 Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Table 12 .......................................................................... 7 Changes to Table 13 .......................................................................... 8 Added Table 14; Renumbered Sequentially .................................. 8 Changed Case Temperature to Ambient Temperature, Figure 4 Caption ............................................................................... 9 Added Figure 5................................................................................ 11 Changes to Table 19 ....................................................................... 11 Added Figure 7 ............................................................................... 12 Changes to Table 20 ....................................................................... 12 Changes to Table 22 and Table 23 ....................................................... 13 Changes to PCB Layout Section ............................................................. 17 Added Figure 28 ......................................................................................... 17 Changes to Recommended Input Voltage for Low Power Operation Section........................................................................... 18 Added Figure 35, Outline Dimensions ........................................ 20 Changes to Ordering Guide .......................................................... 21 12/13—Revision 0: Initial Version Rev. A | Page 2 of 24 Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 1. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Change vs. Temperature Minimum Pulse Width Pulse Width Distortion Propagation Delay Skew 1 Channel Matching Codirectional Opposing Direction 1 Symbol Min Typ tPHL, tPLH 80 200 PW PWD tPSK Max Unit Test Conditions/Comments 2 180 Within pulse width distortion (PWD) limit 50% input to 50% output 8 10 Mbps ns ps/°C ns ns ns 10 15 ns ns 500 tPSKCD tPSKOD Within PWD limit |tPLH − tPHL| tPSK is the magnitude of the worst case difference in tPHL and tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 2. Parameter SUPPLY CURRENT ADuM1240/ADuM1245 ADuM1241/ADuM1246 Symbol Min IDD1 IDD2 IDD1 IDD2 Typ Max Unit 366 246 306 306 600 375 450 450 µA µA µA µA Test Conditions/Comments 2 Mbps, no load Table 3. Parameter DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Input Switching Thresholds Positive Threshold Voltage Negative Going Threshold Input Hysteresis Undervoltage Lockout, VDD1 or VDD2 Supply Current per Channel Quiescent Current Input Supply Output Supply Input (Refresh Off ) Output (Refresh Off ) Symbol Min VIH VIL 0.7 VDDx 1 VOH VDDx1 − 0.1 VDDx1 − 0.4 VOL II −1 Typ 3.3 3.1 0.0 0.2 +0.01 VT+ VT− ΔVT UVLO 1.8 1.2 0.6 1.5 IDDI (Q) IDDO (Q) IDDI (Q) IDDO (Q) 4.8 0.8 0.12 0.13 Rev. A | Page 3 of 24 Max Unit 0.3 VDDx1 V V 0.1 0.4 +1 V V V V µA Test Conditions/Comments IOUTx = −20 µA, VIx = VIxH IOUTx = −4 mA, VIx = VIxH IOUTx = 20 µA, VIx = VIxL IOUTx = 4 mA, VIx = VIxL 0 V ≤ VIx ≤ VDDx1 V V V V 10 6 µA µA µA µA ENX low ENX low ENX high ENX high ADuM1240/ADuM1241/ADuM1245/ADuM1246 Parameter Dynamic Supply Current Input Output AC SPECIFICATIONS Output Rise Time/Fall Time Common-Mode Transient Immunity 2 Symbol Min Typ IDDI (D) IDDO (D) tR/tF |CM| Refresh Rate Data Sheet 25 fr Max Unit Test Conditions/Comments 88 60 µA/Mbps µA/Mbps 2 40 ns kV/µs 14 kbps 10% to 90% VIx = VDDx1, VCM = 1000 V, transient magnitude = 800 V 1 VDDx = VDD1 or VDD2. 2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. ELECTRICAL CHARACTERISTICS—2.5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire recommended operation range of 2.25 V ≤ VDD1 ≤ 2.75 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 4. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Change vs. Temperature Pulse Width Distortion Minimum Pulse Width Propagation Delay Skew 1 Channel Matching Codirectional Opposing Direction 1 Symbol Min tPHL, tPLH PWD PW tPSK Typ 112 280 Max Unit Test Conditions/Comments 2 180 Within PWD limit 50% input to 50% output 10 Mbps ns ps/°C ns ns ns 10 30 ns ns 12 500 tPSKCD tPSKOD |tPLH − tPHL| Within PWD limit tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 5. Parameter SUPPLY CURRENT ADuM1240/ADuM1245 ADuM1241/ADuM1246 Symbol IDD1 IDD2 IDD1 IDD2 Min Typ Max Unit 312 168 240 240 400 250 375 375 µA µA µA µA Rev. A | Page 4 of 24 Test Conditions/Comments 2 Mbps, no load Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 Table 6. Parameter DC SPECIFICATIONS Input Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Input Switching Thresholds Positive Threshold Voltage Negative Going Threshold Input Hysteresis Undervoltage Lockout, VDD1 or VDD2 Supply Current per Channel Quiescent Current Input Supply Output Supply Input (Refresh Off ) Output (Refresh Off ) Dynamic Supply Current Input Output AC SPECIFICATIONS Output Rise Time/Fall Time Common-Mode Transient Immunity 2 Refresh Rate 1 2 Symbol Min VIH VIL 0.7 VDDx 1 VOH VDDx1 − 0.1 VDDx1 − 0.4 VOL II −1 Typ 2.5 2.35 0.0 0.1 +0.01 Max Unit 0.3 VDDx1 V V 0.1 0.4 +1 V V V V µA VT+ VT− ΔVT UVLO 1.5 1.0 0.5 1.5 IDDI (Q) IDDO (Q) IDDI (Q) IDDO (Q) 2.6 0.5 0.05 0.05 IDDI (D) IDDO (D) 76 41 µA/Mbps µA/Mbps 2 40 ns kV/µs 14 kbps tR/tF |CM| fr 25 Test Conditions/Comments IOx = −20 µA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VIx ≤ VDDx1 V V V V 3.75 3.75 µA µA µA µA ENX low ENX low ENX high ENX high 10% to 90% VIx = VDDx1, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A | Page 5 of 24 ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet ELECTRICAL CHARACTERISTICS—VDD1 = 3.3 V, VDD2 = 2.5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and VDD2 = 2.5 V. Minimum and maximum specifications apply over the entire recommended operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 2.25 V ≤ VDD2 ≤ 2.75 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. For dc specifications and ac specifications, see Table 3 for parameters related to Side 1 operation, and see Table 6 for parameters related to Side 2 operation. Table 7. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Side 1 to Side 2 Side 2 to Side 1 Change vs. Temperature Pulse Width Distortion Pulse Width Propagation Delay Skew 1 Channel Matching Codirectional Opposing Direction 1 Symbol Min tPHL, tPLH tPHL, tPLH PWD PW tPSK Typ 84 120 280 Max Unit Test Conditions/Comments 2 Mbps Within PWD limit 180 180 50% input to 50% output 50% input to 50% output 10 ns ns ps/°C ns ns ns 10 60 ns ns 12 500 tPSKCD tPSKOD |tPLH − tPHL| Within PWD limit tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Table 8. Parameter SUPPLY CURRENT ADuM1240/ADuM1245 ADuM1241/ADuM1246 Symbol Min IDD1 IDD2 IDD1 IDD2 Typ Max Unit 366 168 306 240 500 375 400 375 µA µA µA µA Test Conditions/Comments 2 Mbps, no load ELECTRICAL CHARACTERISTICS—VDD1 = 2.5 V, VDD2 = 3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = 2.5 V, and VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range of 2.25 V ≤ VDD1 ≤ 2.75 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. For dc specifications and ac specifications, see Table 6 for parameters related to Side 1 operation, and see Table 3 for parameters related to Side 2 operation. Table 9. Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Side 1 to Side 2 Side 2 to Side 1 Change vs. Temperature Pulse Width Distortion Pulse Width Propagation Delay Skew 1 Channel Matching Codirectional Opposing Direction 1 Symbol Min tPHL, tPLH tPHL, tPLH PWD PW tPSK tPSKCD tPSKOD Typ 120 84 200 Max Unit Test Conditions/Comments 2 Mbps Within PWD limit 180 180 50% input to 50% output 50% input to 50% output 10 ns ns ps/°C ns ns ns 10 60 ns ns 12 500 |tPLH − tPHL| Within PWD limit tPSK is the magnitude of the worst case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Rev. A | Page 6 of 24 Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 Table 10. Parameter SUPPLY CURRENT ADuM1240/ADuM1245 ADuM1241/ADuM1246 Symbol Min IDD1 IDD2 IDD1 IDD2 Typ Max Unit 306 248 240 306 500 375 375 450 µA µA µA µA Test Conditions/Comments 2 Mbps, no load PACKAGE CHARACTERISTICS Table 11. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction to Ambient Thermal Resistance 1 2 Symbol RI-O CI-O CI θJA Min Typ 1013 2 4.0 85 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION Approvals of the ADuM1240/ADuM1241/ADuM1245/ADuM1246 by the organizations listed in Table 12 are pending. See Table 18 and the Absolute Maximum Ratings section for recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 12. UL (Pending) Recognized under 1577 component recognition program 1 Single protection, 8-lead SOIC package, 3000 V rms isolation voltage Single protection, 20-lead SSOP package, 3750 V rms isolation voltage File E214100 CSA (Pending) Approved under CSA Component Acceptance Notice 5A 8-lead SOIC package, basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage 20-lead SSOP package, basic insulation per CSA 60950-1-03 and IEC 60950-1, 530 V rms (700 V peak) maximum working voltage 20-lead SSOP package, reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 265 V rms (374 V peak) maximum working voltage File 205078 VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 8-lead SOIC package, reinforced insulation, 560 VPEAK 20-lead SSOP package, reinforced insulation, 849 VPEAK File 2471900-4880-0001 In accordance with UL1577, each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 µA). 2 In accordance with DIN V VDE V 0884-10, each ADuM1240/ADuM1241/ADuM1245/ADuM1246 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. 1 Rev. A | Page 7 of 24 ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet INSULATION AND SAFETY RELATED SPECIFICATIONS Table 13. Parameter Rated Dielectric Insulation Voltage (8-Lead SOIC) Rated Dielectric Insulation Voltage (20-Lead SSOP) Minimum External Tracking and Air Gap, 8-Lead SOIC (Creepage and Clearance) Minimum Clearance in the Plane of the Printed Circuit Board, 8-Lead SOIC (PCB Clearance) Minimum Clearance in the Plane of the Printed Circuit Board, 20-Lead SSOP (PCB Clearance) Minimum Clearance in the Plane of the Printed Circuit Board, 20-Lead SSOP (PCB Clearance) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol Value 3000 Unit V rms Test Conditions/Comments 1 minute duration 3750 V rms 1 minute duration L(I02) 4 mm min L(I01) 4.5 mm min Measured from input terminals to output terminals, shortest distance path along package body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane L(I01) 5.1 mm min Measured from input terminals to output terminals, shortest distance path along package body L(I02) 5.1 mm min Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane 0.017 mm min Insulation distance through insulation >400 V DIN IEC 112/VDE 0303 Part 1 CTI II Material Group (DIN VDE 0110, 1/89, Table 1) DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval. Table 14. 8-Lead SOIC (R-8) Parameter Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method b1 Symbol VIORM Vpd(m) Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1 Vpd(m) After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Vpd(m) Case Temperature Total Power Dissipation at 25°C Insulation Resistance at TS TS IS1 RS VIOTM VIOSM Test Conditions/Comments VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = one second, partial discharge < 5 pC VIORM × 1.5 = Vpd(m), tini = 60 seconds, tm = 10 seconds, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 seconds, tm = 10 seconds, partial discharge < 5 pC VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 4) VIO = 500 V Rev. A | Page 8 of 24 Characteristic Unit I to IV I to III I to II 40/105/21 2 560 1050 VPEAK VPEAK 840 VPEAK 672 VPEAK 3500 4000 VPEAK VPEAK 150 1.64 >109 °C W Ω Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 Table 15. 20-Lead SSOP (RS-20) Parameter Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method b1 Symbol VIORM Vpd(m) Input to Output Test Voltage, Method a After Environmental Tests Subgroup 1 Vpd(m) After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Vpd(m) VIOTM VIOSM TS IS1 RS VIORM × 1.5 = Vpd(m), tini =60 seconds, tm = 10 seconds, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 seconds, tm = 10 seconds, partial discharge < 5 pC VIO = 500 V Unit I to IV I to III I to II 40/105/21 2 849 1592 VPEAK VPEAK 1273 VPEAK 1018 VPEAK 5335 6000 VPEAK VPEAK 150 2.5 >109 °C W Ω Table 16. 2.5 Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times 2.0 1.5 Symbol TA VDD1, VDD2 Min −40 2.25 Max +125 3.6 1.0 1 See the DC Correctness and Low Power Operation section for more information. 1.0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 11925-003 0.5 0 Characteristic RECOMMENDED OPERATING CONDITIONS 3.0 SAFE LIMITING POWER (W) VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = one second, partial discharge < 5 pC VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 4) Safety Limiting Values Case Temperature Side 1 IDD1 Current Insulation Resistance at TS Test Conditions/Comments Figure 4. Thermal Derating Curve, Dependent on Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. A | Page 9 of 24 Unit °C V ms ADuM1240/ADuM1241/ADuM1245/ADuM1246 ABSOLUTE MAXIMUM RATINGS Data Sheet TA = 25°C, unless otherwise noted. CONTINUOUS WORKING VOLTAGE Table 17. Table 18. Maximum Continuous Working Voltage1 Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2) Input Voltages (VIA, VIB ) Output Voltages (VOA, VOB) Average Output Current per Pin1 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients2 1 2 Parameter AC Voltage Bipolar Waveform Rating −65°C to +150°C −40°C to +125°C Unipolar Waveform −0.5 V to +5 V −0.5 V to VDDI + 0.5 V −0.5 V to VDD2 + 0.5 V DC Voltage −10 mA to +10 mA −10 mA to +10 mA −100 kV/μs to +100 kV/μs See Figure 4 for maximum rated current values for various temperatures. Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. 1 Max Unit Constraint 565 V peak 1131 V peak 1131 V peak 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 10 of 24 Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 20 VDD2 GND1 2 19 GND2 18 NIC NIC 4 VIA 5 VIB 6 EN1 7 VIA 2 VIB 3 GND1 4 ADuM1240/ ADuM1245 TOP VIEW (Not to Scale) NIC 8 8 VDD2 7 VOA NIC 9 6 VOB GND1 10 5 GND2 11925-104 VDD1 1 ADuM1240/ ADuM1245 TOP VIEW (Not to Scale) 17 NIC 16 VOA 15 VOB 14 EN2 13 NIC 12 NIC 11 GND2 NIC = NOT INTERNALLY CONNECTED. Figure 5. ADuM1240/ADuM1245 8-Lead SOIC (R-8) Pin Configuration 11925-004 NIC 3 Figure 6. ADuM1240/ADuM1245 20-Lead SSOP (RS-20) Pin Configuration Table 19. ADuM1240/ADuM1245 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions 1 8-Lead SOIC Pin No. 2 1 20-Lead SSOP Pin No. 1 Mnemonic VDD1 N/A 2 GND1 N/A N/A 2 3 N/A 3 4 5 6 7 NIC NIC VIA VIB EN1 N/A N/A 4 8 9 10 NIC NIC GND1 5 11 GND2 N/A N/A N/A 12 13 14 NIC NIC EN2 6 7 N/A N/A N/A 15 16 17 18 19 VOB VOA NIC NIC GND2 8 20 VDD2 1 2 Description Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF between VDD1 and GND1. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is recommended. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Logic Input A. Logic Input B. Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND1 enables the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables the refresh and watchdog functionality for the lowest power operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is recommended. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND2 enables the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 14 to VDD2 disables the refresh and watchdog functionality for lowest power operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. Logic Output B. Logic Output A. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is recommended. Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF between VDD2 and GND2. Reference AN-1109 for specific layout guidelines. N/A = not applicable. Rev. A | Page 11 of 24 Data Sheet VDD1 1 20 VDD2 GND1 2 19 GND2 NIC 3 18 NIC NIC 4 17 NIC 16 VIA VOA 5 VIB 6 EN1 7 VOA 2 VIB 3 GND1 4 ADuM1241/ ADuM1246 TOP VIEW (Not to Scale) TOP VIEW (Not to Scale) 15 VOB 14 EN2 8 VDD2 NIC 8 13 NIC 7 VIA NIC 9 12 NIC 6 VOB GND1 10 11 GND2 5 GND2 11925-105 VDD1 1 ADuM1241/ ADuM1246 NIC = NOT INTERNALLY CONNECTED. Figure 7. ADuM1241/ADuM1246 8-Lead SOIC (R-8) Pin Configuration 11925-005 ADuM1240/ADuM1241/ADuM1245/ADuM1246 Figure 8. ADuM1241/ADuM1246 20-Lead SSOP (RS-20) Pin Configuration Table 20. ADuM1241/ADuM1246 8-Lead SOIC (R-8) and 20-Lead SSOP (RS-20) Pin Function Descriptions 1 8-Lead SOIC Pin No. 2 1 20-Lead SSOP Pin No. 1 Mnemonic VDD1 N/A 2 GND1 N/A N/A 2 3 N/A 3 4 5 6 7 NIC NIC VOA VIB EN1 N/A N/A 4 8 9 10 NIC NIC GND1 5 11 GND2 N/A N/A N/A 12 13 14 NIC NIC EN2 6 7 N/A N/A N/A 15 16 17 18 19 VOB VIA NIC NIC GND2 8 20 VDD2 1 2 Description Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF between VDD1 and GND1. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is recommended. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Logic Output A. Logic Input B. Refresh and Watchdog Enable 1. In the 20-lead SSOP package, connecting Pin 7 to GND1 enables the input/output refresh and watchdog functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables the refresh and watchdog functionality for the lowest power operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Ground 1. Ground reference for Isolator Side 1. In the 20-lead SSOP package, Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is recommended. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Refresh and Watchdog Enable 2. In the 20-lead SSOP package, connecting Pin 14 to GND2 enables the input/output refresh and watchdog functionality for Side 2, supporting standard iCoupler operation. Tying Pin 14 to VDD2 disables the refresh and watchdog functionality for lowest power operation. See the DC Correctness and Low Power Operation section for a description of this mode. EN1 and EN2 must be set to the same logic state. Logic Output B. Logic Input A. Not Internally Connected. Leave this pin floating. Not Internally Connected. Leave this pin floating. Ground 2. Ground reference for Isolator Side 2. In the 20-lead SSOP package, Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is recommended. Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to 0.1 µF between VDD2 and GND2. Reference AN-1109 for specific layout guidelines. N/A = not applicable. Rev. A | Page 12 of 24 Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 TRUTH TABLES Table 22 provides the truth table (positive logic) for the ADuM1240 and the ADuM1241, and Table 23 provides the truth table (positive logic) for the ADuM1245 and the ADuM1246. For a description of the abbreviations used in the truth tables, see Table 21. Table 21. Truth Table Abbreviations Letter H L ↑ ↓ X QO Z Description High level Low level Rising data transition Falling data transition Irrelevant Level of VOX prior to levels being established High impedance Table 22. ADuM1240/ADuM1241 Truth Table (Positive Logic) 1, 2, 3 VIx Input H L X VDDI State Powered Powered Unpowered VDDO State Powered Powered Powered ENx State L L L VOx Output H L H X Unpowered Powered H QO ↑ ↓ X Powered Powered Powered Powered Powered Unpowered H H X H L Z 1 2 3 Description Normal operation; data is high and refresh is enabled. Normal operation; data is low and refresh is enabled. Input unpowered. Outputs are in the default high state. Outputs return to the input state within 150 µs of VDDI power restoration. See the pin function descriptions (Table 19 and Table 20) for details. Input unpowered. Outputs are static at the level that was last sent from the input or at the power-up level. See the pin function descriptions (Table 19 and Table 20) for details. Output is high after propagation delay, refresh is disabled. Output is low after propagation delay, refresh is disabled. Output unpowered. Output pins are in high impedance state. Outputs return to the input state within 150 µs of VDDO power restoration. See the pin function descriptions (Table 19 and Table 20) for details. VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). Table 23. ADuM1245/ADuM1246 Truth Table (Positive Logic) 1, 2, 3 VIx Input H L X VDDI State Powered Powered Unpowered VDDO State Powered Powered Powered ENx State L L L VOx Output H L L X Unpowered Powered H QO ↑ ↓ X Powered Powered Powered Powered Powered Unpowered H H X H L Z Description Normal operation; data is high and refresh is enabled. Normal operation; data is low and refresh is enabled. Input unpowered. Outputs are in the default low state. Outputs return to the input state within 150 µs of VDDI power restoration. See the pin function descriptions (Table 19 and Table 20) for details. Input unpowered. Outputs are static at the level that was last sent from the input or at the power-up level. See the pin function descriptions (Table 19 and Table 20) for details. Output is high, refresh is disabled. Output is low, refresh is disabled. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 150 µs of VDDO power restoration. See the pin function descriptions (Table 19 and Table 20) for details. VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 3 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D). 1 2 Rev. A | Page 13 of 24 ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 15 10 250 5 0 200 0 20 40 150 100 50 VDDx INPUT CURRENT 0 500 1500 1000 2000 DATA RATE (kbps) 0 20 40 60 40 20 VDDx OUTPUT CURRENT 0 500 1000 1500 2000 Figure 12. Current Consumption per Output vs. Data Rate for 3.3 V, ENx = Low Operation CURRENT CONSUMPTION PER INPUT (µA) 160 80 4 2 60 0 50 0 20 40 40 30 20 10 0 500 1000 1500 2000 DATA RATE (kbps) 1.0 120 0.5 100 0 0 5 10 80 60 40 20 VDDx INPUT CURRENT VDDx OUTPUT CURRENT 0 140 0 0 500 1500 1000 2000 DATA RATE (kbps) Figure 10. Current Consumption per Output vs. Data Rate for 2.5 V, ENx = Low Operation 11925-010 70 11925-007 CURRENT CONSUMPTION PER OUTPUT (µA) 0 80 DATA RATE (kbps) 90 Figure 13. Current Consumption per Input vs. Data Rate for 2.5 V, ENx = High Operation 90 350 CURRENT CONSUMPTION PER OUTPUT (µA) 400 15 10 300 5 0 250 0 20 40 200 150 100 50 VDDx INPUT CURRENT 0 500 1000 1500 2000 DATA RATE (kbps) 11925-008 CURRENT CONSUMPTION PER INPUT (µA) 2 100 0 Figure 9. Current Consumption per Input vs. Data Rate for 2.5 V, ENx = Low Operation 0 4 Figure 11. Current Consumption per Input vs. Data Rate for 3.3 V, ENx = Low Operation 80 1.0 70 0.5 60 0 0 5 10 50 40 30 20 10 VDDx OUTPUT CURRENT 0 0 500 1000 1500 2000 DATA RATE (kbps) Figure 14. Current Consumption per Output vs. Data Rate for 2.5 V, ENx = High Operation Rev. A | Page 14 of 24 11925-011 0 120 11925-009 300 CURRENT CONSUMPTION PER OUTPUT (µA) 140 11925-006 CURRENT CONSUMPTION PER INPUT (µA) 350 Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 300 FALLING RISING 180 1.0 250 160 0.5 0 120 0 5 IDDx CURRENT (µA) 140 10 100 80 60 40 150 100 50 500 1000 1500 2000 DATA RATE (kbps) 0 Figure 15. Current Consumption per Input vs. Data Rate for VDDx = 3.3 V, ENx = High Operation 1.0 1.5 2.0 2.5 3.0 Figure 18. IDDx Current per Input vs. Data Input Voltage for VDDx = 2.5 V 1.0 0.5 100 0 0 5 10 80 60 40 20 9 8 7 6 5 4 3 2 1 OUTPUT INPUT VDDx OUTPUT CURRENT 500 1000 1500 2000 DATA RATE (kbps) 0 –40 11925-013 0 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 16. Current Consumption per Output vs. Data Rate for VDDx = 3.3 V, ENx = High Operation Figure 19. Typical Input and Output Supply Current per Channel vs. Temperature for VDDx = 2.5 V, Data Rate = 100 kbps 600 10 SUPPLY CURRENT PER CHANNEL (µA) FALLING RISING 500 400 300 200 0 1 2 3 4 DATA INPUT VOLTAGE (V) 11925-014 100 0 –20 11925-016 SUPPLY CURRENT PER CHANNE L (µA) 10 120 IDDx CURRENT (µA) 0.5 DATA INPUT VOLTAGE (V) 140 0 0 11925-015 VDDx INPUT CURRENT 0 9 8 7 6 5 4 3 2 1 0 –40 OUTPUT INPUT –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 11925-017 0 CURRENT CONSUMPTION PER OUTPUT (µA) 200 20 11925-012 CURRENT CONSUMPTION PER INPUT (µA) 200 Figure 20. Typical Input and Output Supply Current per Channel vs. Temperature for VDDx = 3.3 V, Data Rate = 100 kbps Figure 17. Typical IDDx Current per Input vs. Data Input Voltage for VDDx = 3.3 V Rev. A | Page 15 of 24 ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet 120 90 100 GLITCH FILTER WIDTH (ns) 80 70 60 50 40 30 80 60 40 20 0 –40 OUTPUT INPUT –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0 2.0 4.0 Figure 24. Typical Glitch Filter Operation Threshold 140 100 90 120 REFRESH PERIOD (µs) 80 70 60 50 40 30 100 80 60 40 20 20 0 –40 VDDx = 2.5V VDDx = 3.3V OUTPUT INPUT –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 0 –40 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) Figure 22. Typical Input and Output Supply Current per Channel vs. Temperature for VDDX = 3.3 V, Data Rate = 1000 kbps 11925-022 10 11925-019 Figure 25. Typical Refresh Period vs. Temperature for 3.3 V and 2.5 V Operation 140 120 120 100 REFRESH PERIOD (µs) 100 80 60 40 80 60 40 20 20 –20 0 20 40 60 80 100 120 140 TEMPERATURE (°C) 11925-020 0 –40 VDDx = 2.5V VDDx = 3.3V Figure 23. Typical Propagation Delay vs. Temperature for VDDx = 3.3 V or VDDx = 2.5 V 0 2.0 2.5 3.0 3.5 VDDx VOLTAGE (V) Figure 26. Typical Refresh Period vs. VDDx Voltage Rev. A | Page 16 of 24 4.0 11925-023 SUPPLY CURRENT PER CHANNE L (µA) 3.5 3.0 TRANSMITTER VDDx (V) Figure 21. Typical Input and Output Supply Current per Channel vs. Temperature for VDDX = 2.5 V, Data Rate = 1000 kbps PROPAGATION DELAY (ns) 2.5 11925-021 20 10 11925-018 SUPPLY CURRENT PER CHANNEL (µA) 100 Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 APPLICATIONS INFORMATION PCB LAYOUT The ADuM1240/ADuM1241/ADuM1245/ADuM1246 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at both the input and output supply pins: VDD1 and VDD2 (see Figure 27). Maintain the capacitor value between 0.01 µF and 0.1 µF and for best results, ensure that the total lead length between both ends of the capacitor and the input power supply does not exceed 20 mm. VDD2 GND2 NIC NIC VOA/VIA VOB EN2 NIC NIC GND2 VDD1 GND1 NIC NIC VIA/VOA VIB EN1 NIC NIC GND1 NIC = NOT INTERNALLY CONNECTED. 11925-024 With proper PCB design choices, these digital isolators readily meet CISPR 22 Class A (and FCC Class A) emissions standards, as well as the more stringent CISPR 22 Class B (and FCC Class B) standards in an unshielded environment. Refer to AN-1109 for PCB related electromagnetic interference (EMI) mitigation techniques, including board layout and stack up issues. Figure 27. Recommended PCB Layout, 20-Lead SSOP (RS-20) Figure 28. Recommended PCB Layout, 8-Lead SOIC (R-8) For applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this equal capacitive coupling of pins can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. PROPAGATION DELAY RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. INPUT (VIx) 50% OUTPUT (VOx) tPHL 11925-025 tPLH Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM1240/ ADuM1241/ADuM1245/ADuM1246 components operating under the same conditions. DC CORRECTNESS AND LOW POWER OPERATION Standard Operating Mode Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. When refresh and watchdog functions are enabled, by pulling EN1 and EN2 low, in the absence of logic transitions at the input for more than ~140 µs, a periodic set of refresh pulses, indicative of the correct input state, is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 200 µs, the device assumes that the input side is unpowered or nonfunctional, in which case, the isolator watchdog circuit forces the output to a default state. The default state is either high, as in the ADuM1240 and ADuM1241 versions, or low, as in the ADuM1245 and ADuM1246 versions. Low Power Operating Mode 11925-124 VDD2 VOA/VIA VOB GND2 VDD1 VIA/VOA VIB GND1 Channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single component of the ADuM1240/ADuM1241/ADuM1245/ ADuM1246. 50% For the lowest power consumption, disable the refresh and watchdog functions of the ADuM1240/ADuM1241/ADuM1245/ ADuM1246 by pulling EN1 and EN2 to logic high. These control pins must be set to the same value on each side of the component for proper operation. In this mode, the current consumption of the chip drops to the microampere range. However, be careful when using this mode, because dc correctness is no longer guaranteed at startup. For example, if the following sequence of events occurs: 1. 2. 3. Power is applied to Side 1. A high level is asserted on the VIA input. Power is applied to Side 2. The high on VIA is not automatically transferred to the Side 2 VOA, and there can be a level mismatch that is not corrected until a transition occurs at VIA. When power is stable on each side, and a transition occurs on the input of the channel, the input and output state of that channel is correctly matched. This contingency can be resolved in several ways, such as sending dummy data, or toggling refresh on for a short period to force synchronization after turn on. Figure 29. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values, and an indication of how accurately the timing of the input signal is preserved. Rev. A | Page 17 of 24 The ADuM1240/ADuM1241/ADuM1245/ADuM1246 implement Schmitt trigger input buffers so that the devices operate cleanly in low data rate, or in noisy environments. Schmitt triggers allow a small amount of shoot through current when their input voltage is not approximate to either VDDx or GNDx levels. Shoot through is possible because the two transistors are both slightly on when input voltages are in the middle of the supply range. For many digital devices, this leakage is not a large portion of the total supply current and may not be noticed; however, in the ultralow power ADuM1240/ADuM1241/ADuM1245/ADuM1246, this leakage can be larger than the total operating current of the device and must not be ignored. 1000 100 10 1 0.1 0.01 0.001 1k 10k 10M 100k 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 11925-026 Recommended Input Voltage for Low Power Operation Data Sheet MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss) ADuM1240/ADuM1241/ADuM1245/ADuM1246 Figure 30. Maximum Allowable External Magnetic Flux Density To achieve optimum power consumption with the ADuM1240/ ADuM1241/ADuM1245/ADuM1246, always drive the inputs as near to VDDx or GNDx levels as possible. Figure 17 and Figure 18 illustrate the shoot through leakage of an input; therefore, whereas the logic thresholds of the input are standard CMOS levels, optimum power performance is achieved when the input logic levels are driven within 0.5 V of either VDDx or GNDx levels. For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs, with the worst case polarity, during a transmitted pulse, it would reduce the received pulse from >1.0 V to 0.75 V. This is still higher than the 0.5 V sensing threshold of the decoder. MAGNETIC FIELD IMMUNITY The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1240 transformers. Figure 31 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM1240 is very insensitive to external fields. Only extremely large, high frequency currents, very close to the component, could potentially be a concern. For the 1 MHz example noted, the user would have to place a 1.2 kA current 5 mm away from the ADuM1240 to affect component operation. V = (−dβ/dt)∑πrn2; n = 1, 2, …, N where: β is the magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM1240, and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 30. 1000 DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 10M 100k 1M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 31. Maximum Allowable Current for Various Currents to ADuM1240 Spacings Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Avoid PCB structures that form loops. Rev. A | Page 18 of 24 11925-027 The pulses at the transformer output have an amplitude greater than 1.5 V. The decoder has a sensing threshold of about 1.0 V, therefore establishing a 0.5 V margin in which induced voltages are tolerated. The voltage induced across the receiving coil is given by MAXIMUM ALLOWABLE CURRENT (kA) The limitation on the magnetic field immunity of the device is set by the condition in which, induced voltage in the transformer receiving coil is sufficiently large, to either falsely set or reset the decoder. The following analysis defines such conditions. The ADuM1240 is examined in a 3 V operating condition, because it represents the typical mode of operation for these products. ADuM1240/ADuM1241/ADuM1245/ADuM1246 For each input channel, the supply current is given by IDDI = IDDI (Q) f ≤ 0.5 fr IDDI = IDDI (D) × (2f − fr) + IDDI (Q) f > 0.5 fr For each output channel, the supply current is given by IDDO = IDDO (Q) f ≤ 0.5 fr IDDO = (IDDO (D) + (0.5 × 10−3) × CL × VDDO) × (2f − fr) + IDDO (Q) f > 0.5 fr where: IDDI (D) and IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half the input data rate, expressed in units of Mbps. fr is the input stage refresh rate (Mbps) = 1/Tr (µs). IDDI (Q) and IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 9 through Figure 16 show per channel supply currents as a function of data rate for an unloaded output condition. The insulation lifetime of the ADuM1240/ADuM1241/ ADuM1245/ADuM1246 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 19, Figure 20, and Figure 21 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime, under the ac bipolar condition, determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages, while still achieving a 50-year service life. The working voltages listed in Table 18 can be applied while maintaining the 50-year minimum lifetime, provided the voltages conform to either the unipolar ac or dc voltage case. Treat any crossinsulation voltage waveform that does not conform to Figure 33 or Figure 34 as a bipolar ac waveform, and limit its peak voltage to the 50-year lifetime voltage value listed in Table 18. Note that the voltage presented in Figure 33 is shown as sinusoidal for illustration purposes only. It represents any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage must not cross 0 V. INSULATION LIFETIME All insulation structures eventually degrade, when subjected to voltage stress for a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM1240/ADuM1241/ADuM1245/ADuM1246. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 18 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE Rev. A | Page 19 of 24 RATED PEAK VOLTAGE 11925-028 The supply current with refresh enabled at a given channel of the ADuM1240/ADuM1241/ADuM1245/ADuM1246 isolators, is a function of the supply voltage, the data rate of the channel, and the output load of the channel. approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life, in some cases. 0V Figure 32. Bipolar AC Waveform RATED PEAK VOLTAGE 11925-029 POWER CONSUMPTION 0V Figure 33. Unipolar AC Waveform RATED PEAK VOLTAGE 11925-030 Data Sheet 0V Figure 34. DC Waveform ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 35. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° COMPLIANT TO JEDEC STANDARDS MO-150-AE Figure 36. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters Rev. A | Page 20 of 24 0.95 0.75 0.55 060106-A 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 ORDERING GUIDE Model 1, 2 ADuM1240ARZ ADuM1240ARZ-RL7 ADuM1240ARSZ ADuM1240ARSZ-RL7 ADuM1241ARZ ADuM1241ARZ-RL7 ADuM1241ARSZ ADuM1241ARSZ-RL7 ADuM1245ARZ ADuM1245ARZ-RL7 ADuM1245ARSZ ADuM1245ARSZ-RL7 ADuM1246ARZ ADuM1246ARZ-RL7 ADuM1246ARSZ ADuM1246ARSZ-RL7 1 2 No. of Inputs, VDD1 Side 2 2 2 2 1 1 1 1 2 2 2 2 1 1 1 1 No. of Inputs, VDD2 Side 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Maximum Data Rate (Mbps) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Maximum Propagation Delay, 3.3 V 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 180 Output Default State High High High High High High High High Low Low Low Low Low Low Low Low Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. Tape and reel is available. The addition of the -RL7 suffix indicates that the product is shipped on 7” tape and reel. Rev. A | Page 21 of 24 Package Description 8-Lead SOIC_N 8-Lead SOIC_N 20-Lead SSOP 20-Lead SSOP 8-Lead SOIC_N 8-Lead SOIC_N 20-Lead SSOP 20-Lead SSOP 8-Lead SOIC_N 8-Lead SOIC_N 20-Lead SSOP 20-Lead SSOP 8-Lead SOIC_N 8-Lead SOIC_N 20-Lead SSOP 20-Lead SSOP Package Option R-8 R-8 RS-20 RS-20 R-8 R-8 RS-20 RS-20 R-8 R-8 RS-20 RS-20 R-8 R-8 RS-20 RS-20 ADuM1240/ADuM1241/ADuM1245/ADuM1246 NOTES Rev. A | Page 22 of 24 Data Sheet Data Sheet ADuM1240/ADuM1241/ADuM1245/ADuM1246 NOTES Rev. A | Page 23 of 24 ADuM1240/ADuM1241/ADuM1245/ADuM1246 Data Sheet NOTES ©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11925-0-4/14(A) www.analog.com/ADuM1240/ADuM1241/ADuM1245/ADuM1246 Rev. A | Page 24 of 24