FUNCTIONAL BLOCK DIAGRAMS Up to 25 Mbps data rate (NRZ) Low propagation delay: 25 ns typical Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C High common-mode transient immunity: >25 kV/µs Output default select 20-lead, RoHS-compliant, SSOP package Safety and regulatory approvals: UL recognition: 3750 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak ADuM3480 VDDL1 1 20 VDDL2 GND1 2 19 GND2 VIA 3 ENCODE DECODE 18 VOA VIB 4 ENCODE DECODE 17 VOB VIC 5 ENCODE DECODE 16 VOC VID 6 ENCODE DECODE 15 VOD NC 7 VDD1 8 14 CTRL2 REG REG 13 VDD2 VDDC1 9 12 VDDC2 GND1 10 11 GND2 Figure 1. ADuM3480 APPLICATIONS VDDL1 1 20 VDDL2 GND1 2 19 GND2 VIA 3 ENCODE DECODE 18 VOA GENERAL DESCRIPTION VIB 4 ENCODE DECODE 17 VOB The ADuM3480/ADuM3481/ADuM34821 are quad-channel digital isolators based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices and other integrated couplers. With typical propagation delay reduced to 25 ns, pulse width distortion is also halved. VIC 5 ENCODE DECODE 16 VOC VOD 6 DECODE ENCODE 15 VID The four channels of the ADuM3480/ADuM3481/ADuM3482 are available in a variety of channel configurations with two data rate grades up to 25 Mbps (see the Ordering Guide section). All models use separate core and I/O power supplies. The core operates between 3.0 V and 5.5 V, whereas the I/O supply can range from 1.8 V to 5.5 V. If I/O operation is required within the range of the core supply, the two supplies can be tied together to allow single-supply operation. When the I/O must interface with logic levels that are different from the core supply voltage, the I/O supply operates independently of the core supply over its wider range. The minimum I/O supply voltage is 1.8 V, which allows compatibility with low voltage logic. Both core and I/O supplies are required for proper operation. CTRL1 7 VDD1 8 REG REG 14 CTRL2 13 VDD2 VDDC1 9 12 VDDC2 GND1 10 11 GND2 20 VDDL2 10459-002 ADuM3481 General-purpose multichannel isolation SPI interface/data converter isolation Industrial field bus isolation 1 10459-001 FEATURES Figure 2. ADuM3481 ADuM3482 VDDL1 1 19 GND2 VIA 3 ENCODE DECODE 18 VOA VIB 4 ENCODE DECODE 17 VOB VOC 5 DECODE ENCODE 16 VIC VOD 6 DECODE ENCODE GND1 2 CTRL1 7 VDD1 8 REG REG 15 VID 14 CTRL2 13 VDD2 VDDC1 9 12 VDDC2 GND1 10 11 GND2 10459-003 Data Sheet Small, 3.75 kV RMS Quad Digital Isolators ADuM3480/ADuM3481/ADuM3482 Figure 3. ADuM3482 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM3480/ADuM3481/ADuM3482 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 10 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 11 General Description ......................................................................... 1 ESD Caution................................................................................ 11 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 12 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 15 Specifications..................................................................................... 3 Applications Information .............................................................. 17 Electrical Characteristics—5 V Operation................................ 3 Supply Voltages ........................................................................... 17 Electrical Characteristics—3 V Operation................................ 5 Printed Circuit Board Layout ................................................... 17 Electrical Characteristics—1.8 V Operation ............................ 7 Propagation Delay Related Parameters ................................... 17 Package Characteristics ............................................................... 9 DC Correctness and Magnetic Field Immunity ..................... 17 Regulatory Information ............................................................... 9 Power Consumption .................................................................. 18 Regulatory Approvals................................................................... 9 Insulation Lifetime ..................................................................... 19 Insulation and Safety Related Specifications ............................ 9 Outline Dimensions ....................................................................... 20 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 10 Ordering Guide .......................................................................... 20 REVISION HISTORY 6/14—Rev. 0 to Rev. A Changed Safety Certification Status from Pending to Approved (Throughout) .................................................................................... 1 Changes to Table 12 .......................................................................... 9 Changed Highest Allowable Overvoltage from 5300 VPEAK to 4000 VPEAK ........................................................................................ 10 Changes to DC Correctness and Magnetic Field Immunity Section .............................................................................................. 17 Changes to Ordering Guide .......................................................... 20 7/12—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at TA = 25°C, VDDL1 = VDD1 = VDDL2 = VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended operation range: 4.5 V ≤ VDDL1, VDD1 ≤ 5.5 V, 4.5 V ≤ VDDL2, VDD2 ≤ 5.5 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF, and CMOS signal levels, unless otherwise noted. Table 1. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol Min PW 1000 tPHL, tPLH PWD A Grade Typ Max Min B Grade Typ Max 40 65 1 90 6 25 7 25 33 3 3 tPSK 50 17 tPSKCD tPSKOD 19 25 5 7 2 2 Unit Test Conditions/Comments ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| Between any two units ns ns ns Table 2. Parameter SUPPLY CURRENT ADuM3480 ADuM3481 ADuM3482 Symbol IDD1 IDDL1 IDD2 IDDL2 IDD1 IDDL1 IDD2 IDDL2 IDD1 IDDL1 IDD2 IDDL2 1 Mbps—A, B Grades Min Typ Max 2.0 0.11 5.1 0.2 2.8 0.14 4.3 0.18 3.5 0.16 3.5 0.16 25 Mbps—B Grade Min Typ Max 2.9 0.4 6.9 0.7 3.0 0.5 5.7 0.6 4.1 0.5 4.7 0.65 Rev. A | Page 3 of 20 8.6 0.2 6.0 2.1 7.9 0.7 6.7 1.6 7.3 1.2 7.3 1.2 12 0.6 7.5 4.8 10 1.4 7.8 3.2 8.8 2.4 8.8 2.4 Unit mA mA mA mA mA mA mA mA mA mA mA mA Test Conditions/Comments CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF ADuM3480/ADuM3481/ADuM3482 Data Sheet Table 3. Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Supply Current per Channel Quiescent Supply Current Regulator Input Side I/O Input Regulator Output Side I/O Output Dynamic Supply Current Regulator Input Side I/O Input Regulator Output Side I/O Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Period 1 Symbol Min VIH VIL 0.7 VDDLx VOH VDDLx − 0.1 VDDLx − 0.4 Max Unit 0.3 VDDLx V V 5.0 4.8 0.0 0.2 +0.01 0.1 0.4 +10 V V V V µA IDDI (Q) IDDIL (Q) IDDO (Q) IDDOL (Q) 0.50 0.027 1.26 0.031 0.60 0.05 1.7 0.10 mA mA mA mA IDDI (D) IDDIL (D) IDDO (D) IDDOL (D) 0.070 0.90 0.010 0.020 mA/Mbps µA/Mbps mA/Mbps mA/Mbps 2.5 35 ns kV/µs 1.66 µs VOL II tR/tF |CM| tr −10 25 Typ Test Conditions/Comments IOx = −20 µA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VIx ≤ VDDLx, 0 V ≤ VCTRLx ≤ VDDLx 10% to 90% VIx = VDDLx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A | Page 4 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 ELECTRICAL CHARACTERISTICS—3 V OPERATION All typical specifications are at TA = 25°C, VDDL1 = VDD1 = VDDL2 = VDD2 = 3.0 V. Minimum/maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDDL1,VDD1 ≤ 3.6 V, 3.0 V ≤ VDDL2, VDD2 ≤ 3.6 V, −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 4. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol Min PW 1000 tPHL, tPLH PWD A Grade Typ Max Min B Grade Typ Max 40 71 2 7 1 99 12 28 3 3 25 38 5 tPSK 58 20 tPSKCD tPSKOD 20 26 6 9 4 3 Unit Test Conditions/Comments ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| Between any two units ns ns ns Table 5. Parameter SUPPLY CURRENT ADuM3480 ADuM3481 ADuM3482 Symbol IDD1 IDDL1 IDD2 IDDL2 IDD1 IDDL1 IDD2 IDDL2 IDD1 IDDL1 IDD2 IDDL2 1 Mbps—A, B Grades Min Typ Max 25 Mbps—B Grade Min Typ Max Unit 1.4 0.08 4.9 0.14 2.3 0.09 4.0 0.12 3.2 0.11 3.2 0.11 8.1 0.13 5.8 1.4 7.5 0.46 6.4 1.1 7.0 0.78 7.0 0.78 mA mA mA mA mA mA mA mA mA mA mA mA 2.9 0.4 6.7 0.40 3.0 0.4 5.7 0.5 4.2 0.5 4.2 0. 5 Rev. A | Page 5 of 20 11 0.5 7.2 2.5 9.8 1.4 7.5 2.7 8.8 1.7 8.8 1.7 Test Conditions/Comments CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF ADuM3480/ADuM3481/ADuM3482 Data Sheet Table 6. Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Supply Current per Channel Quiescent Supply Current Regulator Input Side I/O Input Regulator Output Side I/O Output Dynamic Supply Current Regulator Input Side I/O Input Regulator Output Side I/O Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Period 1 Symbol Min Max Unit VIH VIL 0.7 VDDLx 0.3 VDDLx V V VOH VDDLx − 0.1 VDDLx − 0.4 3.0 2.8 0.0 0.2 +0.01 0.1 0.4 +10 V V V V µA IDDI (Q) IDDIL (Q) IDDO (Q) IDDOL (Q) 0.36 0.019 1.21 0.021 0.5 0.050 1.7 0.050 mA mA mA mA IDDI (D) IDDIL (D) IDDO (D) IDDOL (D) 0.070 0.53 0.010 0.013 mA/Mbps µA/Mbps mA/Mbps mA/Mbps 3 35 ns kV/µs 1.66 µs VOL II tR/tF |CM| tr −10 25 Typ Test Conditions/Comments IOx = −20 µA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 4 mA, VIx = VIxL 0 V ≤ VIx ≤ VDDLx, 0 V ≤ VCTRLx ≤ VDDLx 10% to 90% VIx = VDDLx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A | Page 6 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 ELECTRICAL CHARACTERISTICS—1.8 V OPERATION All typical specifications are at TA = 25°C, VDDL1 = 1.8 V, VDD1 = 3.0 V, VDDL2 = 1.8 V, VDD2 = 3.0 V. Minimum/maximum specifications apply over the entire recommended operation range: VDDL1 = 1.8 V, 3.0 V ≤ VDD1 ≤ 3.6 V, VDDL2 = 1.8 V, 3.0 V ≤ VDD2 ≤ 3.6 V,−40°C ≤ TA ≤ +125°C; unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 7. Parameter SWITCHING SPECIFICATIONS Pulse Width Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Propagation Delay Skew Channel Matching Codirectional Opposing Direction Jitter Symbol Min PW 1000 tPHL, tPLH PWD A Grade Typ Max Min B Grade Typ Max 40 86 6 7 1 145 32 43 6 3 25 85 30 tPSK 93 60 tPSKCD tPSKOD 40 55 34 37 4 3 Unit Test Conditions/Comments ns Mbps ns ns ps/°C ns Within PWD limit Within PWD limit 50% input to 50% output |tPLH − tPHL| Between any two units ns ns ns Table 8. Parameter SUPPLY CURRENT ADuM3480 ADuM3481 ADuM3482 Symbol IDD1 IDDL1 IDD2 IDDL2 IDD1 IDDL1 IDD2 IDDL2 IDD1 IDDL1 IDD2 IDDL2 1 Mbps—A, B Grades Min Typ Max 25 Mbps—B Grade Min Typ Max Unit 1.4 0.04 4.7 0.08 2.3 0.05 3.9 0.07 3.1 0.06 3.1 0.06 8.1 0.07 5.7 0.82 7.5 0.25 6.3 0.63 6.9 0.44 6.9 0.44 mA mA mA mA mA mA mA mA mA mA mA mA 1.9 0.3 6.5 0.5 2.8 0.35 5.7 0.4 3.8 0.4 4.5 0.40 Rev. A | Page 7 of 20 11 0.4 7.3 1.5 10 0.7 8.0 1.3 8.7 1.1 8.8 1.1 Test Conditions/Comments CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF CL = 0 pF ADuM3480/ADuM3481/ADuM3482 Data Sheet Table 9. Parameter DC SPECIFICATIONS Input Voltage Threshold Logic High Logic Low Output Voltages Logic High Logic Low Input Current per Channel Supply Current per Channel Quiescent Supply Current Regulator Input Side I/O Input Regulator Output Side I/O Output Dynamic Supply Current Regulator Input Side I/O Input Regulator Output Side I/O Output AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 1 Refresh Period 1 Symbol Min VIH VIL 0.7 VDDLx VOH VDDLx − 0.1 VDDLx − 0.4 Max Unit 0.3 VDDLx V V 1.8 1.6 0.0 0.2 +0.01 0.1 0.4 +10 V V V V µA IDDI (Q) IDDIL (Q) IDDO (Q) IDDOL (Q) 0.39 0.010 1.17 0.012 0.45 0.025 1.5 0.038 mA mA mA mA IDDI (D) IDDIL (D) IDDO (D) IDDOL (D) 0.071 0.25 0.010 0.0077 mA/Mbps µA/Mbps mA/Mbps mA/Mbps 3 35 ns kV/µs 1.66 µs VOL II tR/tF |CM| tr −10 25 Typ Test Conditions/Comments IOx = −20 µA, VIx = VIxH IOx = −2 mA, VIx = VIxH IOx = 20 µA, VIx = VIxL IOx = 2 mA, VIx = VIxL 0 V ≤ VIx ≤ VDDLx, 0 V ≤ VCTRLx ≤ VDDLx 10% to 90% VIx = VDDLx, VCM = 1000 V, transient magnitude = 800 V |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOL < 0.8 × VDDLx or VOH > 0.7 × VDDIx. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. Rev. A | Page 8 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 PACKAGE CHARACTERISTICS Table 10. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance 1 2 Symbol RI-O CI-O CI θJC Min Typ 1012 2.2 4.0 50.5 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together; Pin 11 to Pin 20 are shorted together. Input capacitance is from any input data pin to ground. REGULATORY INFORMATION The ADuM3480/ADuM3481/ADuM3482 are approved by the organizations listed in Table 11. See Table 16 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. REGULATORY APPROVALS Table 11. UL Recognized under the UL 1577 component recognition program 1 Single protection, 3750 V rms isolation voltage File E214100 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM3480/ADuM3481/ADuM3482 is proof tested by applying an insulation test voltage of ≥4500 V rms for 1 second (current leakage detection limit = 10 µA). 2 In accordance with DIN V VDE V 0884-10, each of the ADuM348x is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. 1 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 12. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 3750 >5.1 Unit V rms mm Minimum External Tracking (Creepage) L(I02) >5.1 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min mm >400 V II Rev. A | Page 9 of 20 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air, in the plane of the PCB Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM3480/ADuM3481/ADuM3482 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 13. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Withstand Isolation Voltage Surge Isolation Voltage Safety Limiting Values SAFETY-LIMITING POWER (W) Case Temperature Total Power Dissipation Insulation Resistance at TS Test Conditions/Comments VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC 1 minute withstand rating VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 4) VIO = 500 V Symbol Characteristic Unit VIORM Vpd(m) I to IV I to III I to II 40/105/21 2 560 1050 VPEAK VPEAK Vpd(m) 840 VPEAK Vpd(m) 672 VPEAK VIOTM VISO 4000 3750 VPEAK VRMS VIOSM 6000 VPEAK TS IS1 RS 150 2.47 >109 °C W Ω 3.0 RECOMMENDED OPERATING CONDITIONS 2.5 Table 14. Parameter Operating Temperature Supply Voltages 1 2.0 1.5 Input Signal Rise and Fall Times 1.0 1 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 Min −40 1.8 3.0 Max +125 5.5 5.5 1.0 Unit °C V V ms See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. 10459-004 0.5 Symbol TA VDDL1, VDDL2 VDD1, VDD2 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 Rev. A | Page 10 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 ABSOLUTE MAXIMUM RATINGS Table 16. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 TA = 25°C, unless otherwise noted. Table 15. Parameter Supply Voltages (VDD1, VDD2, VDDL1, VDDL2, VDDC1, VDDC2) Input Voltages (VIA, VIB, VIC, VID, VCTRL1, VCTRL2) Output Voltages (VOA, VOB, VOC, VOD) Average Output Current per Pin1 Common-Mode Transients2 Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range 1 2 Rating −0.5 V to +7.0 V −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −10 mA to +10 mA −100 kV/μs to +100 kV/μs −65°C to +150°C −40°C to +125°C Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 Max 565 Unit V peak 848 V peak 848 V peak Applicable Certification All certifications Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. ESD CAUTION See Figure 4 for maximum rated current values for various temperatures. Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 11 of 20 ADuM3480/ADuM3481/ADuM3482 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDDL1 20 VDDL2 1 19 GND2* GND1* 2 18 VOA VIA 3 VIB 4 ADuM3480 17 VOB VIC 5 TOP VIEW (Not to Scale) 16 VOC VID 6 NC 7 15 VOD 14 CTRL2 VDD1 8 13 VDD2 VDDC1 9 12 VDDC2 GND1* 10 11 GND2* *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO PCB SIDE 2 GROUND IS RECOMMENDED. 10459-005 NOTES 1. NC = NO CONNECTION. THIS PIN IS NOT CONNECTED INTERNALLY AND CAN BE LEFT FLOATING OR CONNECTED TO VDD1 OR GND1. Figure 5. ADuM3480 Pin Configuration Table 17. ADuM3480 Pin Function Descriptions Pin No. 1 Mnemonic VDDL1 2 GND1 3 4 5 6 7 8 9 VIA VIB VIC VID NC VDD1 VDDC1 10 GND1 11 GND2 12 VDDC2 13 14 15 16 17 18 19 VDD2 CTRL2 VOD VOC VOB VOA GND2 20 VDDL2 Description 1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Input D. No Connection. This pin is not connected internally and can be left floating or connected to VDD1 or GND1. 3.0 V to 5.5 V Supply Voltage for Isolator Side 1. Output Pin of an Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not use this pin to power external circuits. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Output Pin of an Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not use this pin to power external circuits. 3.0 V to 5.5 V Supply Voltage for Isolator Side 2. Select Side 2 Output Default Level. Low = default output low. High = default output high. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. 1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2. Rev. A | Page 12 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 20 VDDL2 1 19 GND2* 18 VOA VIA 3 VIB 4 ADuM3481 17 VOB VIC 5 TOP VIEW (Not to Scale) 16 VOC VOD 6 CTRL1 7 15 VID 14 CTRL2 VDD1 8 13 VDD2 VDDC1 9 12 VDDC2 GND1* 10 11 GND2* *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO PCB SIDE 2 GROUND IS RECOMMENDED. 10459-006 VDDL1 GND1* 2 Figure 6. ADuM3481 Pin Configuration Table 18. ADuM3481 Pin Function Descriptions Pin No. 1 Mnemonic VDDL1 2 GND1 3 4 5 6 7 8 9 VIA VIB VIC VOD CTRL1 VDD1 VDDC1 10 GND1 11 GND2 12 VDDC2 13 14 15 16 17 18 19 VDD2 CTRL2 VID VOC VOB VOA GND2 20 VDDL2 Description 1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Select Side 1 Output Default Level. Low = default output low. High = default output high. 3.0 V to 5.5 V Supply Voltage for Isolator Side 1. Output Pin of an Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not use this pin to power external circuits. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Output Pin of an Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not use this pin to power external circuits. 3.0 V to 5.5 V Supply Voltage for Isolator Side 2. Select Side 2 Output Default Level. Low = default output low. High = default output high. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. 1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2. Rev. A | Page 13 of 20 ADuM3480/ADuM3481/ADuM3482 Data Sheet 20 VDDL2 1 19 GND2* 18 VOA VIA 3 VIB 4 ADuM3482 17 VOB VOC 5 TOP VIEW (Not to Scale) 16 VIC VOD 6 CTRL1 7 15 VID 14 CTRL2 VDD1 8 13 VDD2 VDDC1 9 12 VDDC2 GND1* 10 11 GND2* *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO PCB SIDE 1 GROUND IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO PCB SIDE 2 GROUND IS RECOMMENDED. 10459-007 VDDL1 GND1* 2 Figure 7. ADuM3482 Pin Configuration Table 19. ADuM3482 Pin Function Descriptions Pin No. 1 Mnemonic VDDL1 2 GND1 3 4 5 6 7 8 9 VIA VIB VOC VOD CTRL1 VDD1 VDDC1 10 GND1 11 GND2 12 VDDC2 13 14 15 16 17 18 19 VDD2 CTRL2 VID VIC VOB VOA GND2 20 VDDL2 Description 1.8 V to 5.5 V Supply Voltage for Isolator Side 1 Input/Output Circuits. Bypass VDDL1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL1 can be connected directly to VDD1. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Select Side 1 Output Default Level. Low = default output low. High = default output high. 3.0 V to 5.5 V Supply Voltage for Isolator Side 1. Output Pin of Internal Regulator for Side 1. Bypass VDDC1 to GND1 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not use this pin to power external circuits. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. Output Pin of Internal Regulator for Side 2. Bypass VDDC2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. Do not use this pin to power external circuits. 3.0 V to 5.5 V Supply Voltage for Isolator Side 2. Select Side 2 Output Default Level. Low = default output low. High = default output high. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to the PCB ground plane as close to the part as possible is recommended. 1.8 V to 5.5 V Supply Voltage for Isolator Side 2 Input/Output Circuits. Bypass VDDL2 to GND2 with a 0.01 µF to 0.1 µF ceramic capacitor. For 3.0 V to 5.5 V input/output operation, VDDL2 can be connected directly to VDD2. Rev. A | Page 14 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 TYPICAL PERFORMANCE CHARACTERISTICS 1.6 2.5 IDDO CURRENT/CHANNEL (mA) IDDI CURRENT/CHANNEL (mA) 1.4 2.0 1.5 VDD = 5V/VDDL = 1.8V VDD = 5V/VDDL = 5V 1.0 0.5 VDD = 3.3V/VDDL = 1.8V 1.2 VDD = 3.3V/VDDL = 3.3V 1.0 0.8 0.6 0.4 0 5 10 15 DATA RATE (Mbps) 20 25 0 10459-008 0 Figure 8. Typical VDDI = 5 V Supply Current per Input Channel vs. Data Rate for 5 V and 1.8 V I/O Operation 0 10 15 DATA RATE (Mbps) 20 25 Figure 11. Typical VDDO = 3.3 V Supply Current per Output Channel vs. Data Rate for 3.3 V and 1.8 V I/O Operation 0.06 2.0 1.5 VDD = 3.3V/VDDL = 1.8V 1.0 0.5 VDD = 3.3V/VDDL = 3.3V 0 5 10 15 DATA RATE (Mbps) 20 25 Figure 9. Typical VDDI = 3.3 V Supply Current per Input Channel vs. Data Rate for 3.3 V, and 1.8 V I/O Operation 0.04 VDDL = 5V 0.03 VDDL = 3.3V 0.02 VDDL = 1.8V 0.01 0 10459-009 0 0.05 0 5 10 15 DATA RATE (Mbps) 20 25 10459-012 VDDIL CURRENT/CHANNEL (mA) 2.5 IDDI CURRENT/CHANNEL (mA) 5 10459-011 0.2 Figure 12. Typical VDDIL Input Supply Current vs. Data Rate for 5 V, 3.3 V, and 1.8 V Operation 1.6 0.6 VDD = 5V/VDDL = 1.8V IDDOL CURRENT/CHANNEL (mA) VDD = 5V/VDDL = 5V 1.2 1.0 0.8 0.6 0.4 0.5 0.4 VDDL = 5V 0.3 VDDL = 3.3V 0.2 0.1 0.2 0 0 5 10 15 DATA RATE (Mbps) 20 25 10459-010 VDDL = 1.8V Figure 10. Typical VDDO = 5 V Supply Current per Output Channel vs. Data Rate for 5 V and 1.8 V I/O Operation Rev. A | Page 15 of 20 0 0 5 10 15 DATA RATE (Mbps) 20 25 Figure 13. Typical VDDOL Output Supply Current vs. Data Rate for 5 V, 3.3 V, and 1.8 V, CL = 0 pF Operation 10459-013 IDDO CURRENT/CHANNEL (mA) 1.4 ADuM3480/ADuM3481/ADuM3482 Data Sheet 1.6 1.2 VDDL = 5V 1.0 0.8 VDDL = 3.3V 0.6 VDDL = 1.8V 0.4 0.2 0 0 5 10 15 DATA RATE (Mbps) 20 25 10459-014 IDDOL CURRENT/CHANNEL (mA) 1.4 Figure 14. Typical VDDOL Output Supply Current vs. Data Rate for 5 V, 3.3 V, and 1.8 V, CL = 15 pF Operation Rev. A | Page 16 of 20 Data Sheet ADuM3480/ADuM3481/ADuM3482 APPLICATIONS INFORMATION The ADuM3480/ADuM3481/ADuM3482 devices are built around a fixed voltage internal data transfer core. The core voltage is 2.7 V, which is generated by regulating the VDD1 and VDD2 voltages with an internal LDO. To ensure proper headroom for the LDO, the VDD1 and VDD2 inputs must be in the 3.0 V to 5.5 V range. Additional pins, VDDC1 and VDDC2, are provided for direct bypass of the LDO output, ensuring clean stable core operation. Bypass capacitors to ground of between 0.01 μF and 0.1 μF are required for each of these supply or dedicated bypass pins. The ADuM3480/ADuM3481/ADuM3482 provide independent supplies for the I/O buffers, VDDL1 and VDDL2, which have wider operating ranges than that required for the core. This allows the I/O supply voltage to range between 1.8 V and 5.5 V. The VDDLx supplies must also be bypassed with between 0.01 μF and 0.1 μF capacitors. Having independent power supplies for the I/O and core allows several power configurations depending on the I/O voltage required and the available power supply rails. If one power supply is available, the VDDx and VDDLx pins can be connected together and operate between 3.0 V and 5.5 V. If lower I/O supply voltage is required, to interface with low voltage logic, two supply rails are required. For example, if the I/O is 1.8 V logic, the VDDLx pin can be connected to a 1.8 V supply rail. The core supply voltage for VDDx requires an input of between 3.0 V and 5.5 V, so an available 3.3 V or 5 V supply rail can be used. The I/O and core supply voltage on each side are independent and different configurations can be used on each side of the device. PRINTED CIRCUIT BOARD LAYOUT The ADuM3480/ADuM3481/ADuM3482 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing to the local ground is required at all four power supply pins, VDD1, VDDL1, VDD2, and VDDL2, as well as at the two internal regulator bypass pins: VDDC1 and VDDC2 (see Figure 15). Placement of the recommended bypass capacitors is shown in Figure 15. The capacitor value should be between 0.01 μF and 0.1 μF. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. VDDL2 GND2 VOA VOB VOC/VIC VOD/VID CTRL2 VDD2 VDDC2 GND2 PROPAGATION DELAY RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. INPUT (VIx) 50% tPLH tPHL OUTPUT (VOx) 50% Figure 16. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved. Channel to channel matching refers to the maximum amount of time that the propagation delay differs between channels within a single ADuM3480/ADuM3481/ADuM3482 component. Propagation delay skew refers to the maximum amount of time that the propagation delay differs between multiple ADuM3480/ ADuM3481/ADuM3482 components operating under the same conditions. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1.7 μs, the current dc state is sent to the output to ensure dc correctness at the output. If the decoder receives no pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 17, Table 18, or Table 19) by the watchdog timer circuit. 10459-016 VDDL1 GND1 VIA VIB VIC/VOC VID/VOD CTRL1 VDD1 VDDC1 GND1 In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to follow this design guideline can allow voltage differentials between pins that exceed the absolute maximum ratings of the device during high voltage transients, which can lead to latch-up or permanent damage. 10459-017 SUPPLY VOLTAGES Figure 15. Recommended Printed Circuit Board (PCB) Layout Rev. A | Page 17 of 20 ADuM3480/ADuM3481/ADuM3482 Data Sheet The limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines such conditions. The ADuM3480/ADuM3481/ADuM3482 are examined in a 3 V operating condition because it represents the most susceptible mode of operation of these products. The pulses at the transformer output have an amplitude of greater than 1.5 V. The decoder has a sensing threshold of approximately = 1.0 V, thereby establishing a 0.5 V margin within which induced voltages can be tolerated. The voltage induced across the receiving coil is given by Given the geometry of the receiving coil in the ADuM3480/ ADuM3481/ADuM3482 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 17. 100 DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10M 10k 100k 1M MAGNETIC FIELD FREQUENCY (Hz) 100M 10459-019 where: β is the magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. MAXIMUM ALLOWABLE CURRENT (kA) 1000 V = (−dβ / dt)∑πrn2; n = 1, 2, …, N Figure 18. Maximum Allowable Current for Various Current to ADuM3480 Spacings Note that at combinations of strong magnetic field and high frequency, or any loops formed by PCB traces, can induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Take care to avoid PCB structures that form loops. 10 1 0.1 POWER CONSUMPTION 0.01 0.001 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) 10459-018 MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM3480/ADuM3481/ADuM3482 transformers. Figure 18 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM3480/ADuM3481/ ADuM3482 are very insensitive to external fields. Only extremely large, high frequency currents that are very close to the component are a concern. For the 1 MHz example noted, a 1.2 kA current would need to be placed 5 mm away from the ADuM3480/ADuM3481/ ADuM3482 to affect component operation. Figure 17. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs, with the worst-case polarity, during a transmitted pulse, it reduces the received pulse from >1.0 V to 0.75 V. This is still well above the 0.5 V sensing threshold of the decoder. The supply current at a given channel of the ADuM3480/ ADuM3481/ADuM3482 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. Calculating IDD1 or IDD2 For each input channel, assuming worst case I/O voltage, the supply current is given by IDDI = IDDI (Q) RD ≤ 2.5 × RR IDDI = IDDI (D) × (RD−RR) + IDDI (Q) RD > 2.5 × RR For each output channel, the supply current is given by Rev. A | Page 18 of 20 IDDO = IDDO (D) × RD + IDDO (Q) Data Sheet ADuM3480/ADuM3481/ADuM3482 For each output channel, the supply current is given by C × V DDOL × 10 −3 I DDOL = I DDOL ( D ) + L 2 R D + I DDOL ( Q ) where: CL is the output load capacitance (pF). VDDOL is the output supply voltage (V). RD is the input logic signal data rate (Mbps); it is twice the input frequency, expressed in units of MHz. RR is the input stage refresh rate (Mbps) = 1/tr (µs) IDDI (Q), IDDIL (Q), IDDO (Q), IDDOL (Q) are the specified input and output quiescent supply currents (mA). IDDI (D), IDDIL (D), IDDO (D), and IDDOL(D) are the input and output dynamic supply currents per channel (mA/Mbps). As inputs and outputs can be present on each side of the device, the calculations refer to the current drawn from the local supply. For example, if an output is on Side 2 of a part, the IDDOL current is drawn from the VDDL2 pin of the part. The IDDL1 and IDDL2 currents are dependent on VDDL1 and VDDL2, the data rate, and the capacitive load. It is nearly independent of the value of the core supplies. To calculate the total IDD1, IDDL1, IDD2, and IDDL2 supply current, the supply currents for each input and output channel corresponding to VDD1, VDDL1, VDD2, and VDDL2 are calculated and totaled, or read from Figure 8 through Figure 14. The input current for the regulated core power supplies is nearly independent of the I/O voltage, and scales with data rate. The IDDI current is not linear down to dc, but goes to a minimum value between about 2.5 × RR and dc. This is due to the refresh circuit establishing a minimum data rate; the values in Figure 8 and Figure 9 and the quiescent currents in Table 3, Table 6, and Table 9 approximate the current in this region. VDDI, VDDO, VDDIL, and VDDOL represent the voltages on the core and I/O power supply pins for the input and output of a given channel. I represents an input, O is an output, and L denotes an I/O supply. The insulation lifetime of the ADuM3480/ADuM3481/ADuM3482 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 19, Figure 20,and Figure 21 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by Analog Devices. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 16 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the unipolar ac or dc voltage case. Treat any cross-insulation voltage waveform that does not conform to Figure 19, Figure 20, or Figure 21 as a bipolar ac waveform, and limit its peak voltage to the 50-year lifetime voltage value listed in Table 16. Note that the voltage presented in Figure 20 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. INSULATION LIFETIME All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation depends on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM3480/ADuM3481/ADuM3482. Analog Devices performs accelerated life testing using voltage levels that are higher than the rated continuous working voltage. Rev. A | Page 19 of 20 RATED PEAK VOLTAGE 10459-020 IDDIL = IDDIL (D) × RD + IDDIL (Q) 0V Figure 19. Bipolar AC Waveform RATED PEAK VOLTAGE 10459-021 For each input channel, the supply current is given by Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 16 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than the 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. 0V Figure 20. Unipolar AC Waveform RATED PEAK VOLTAGE 10459-023 Calculating IDDL1 or IDDL2 0V Figure 21. DC Waveform ADuM3480/ADuM3481/ADuM3482 Data Sheet OUTLINE DIMENSIONS 7.50 7.20 6.90 11 20 5.60 5.30 5.00 8.20 7.80 7.40 1 10 0.25 0.09 0.38 0.22 0.05 MIN COPLANARITY 0.10 0.65 BSC SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150-AE 060106-A 1.85 1.75 1.65 2.00 MAX Figure 22. 20-Lead Standard Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model1 ADuM3480ARSZ ADuM3480ARSZ-RL7 ADuM3480BRSZ ADuM3480BRSZ-RL7 ADuM3481ARSZ ADuM3481ARSZ-RL7 ADuM3481BRSZ ADuM3481BRSZ-RL7 EVAL-ADuM3481EBZ ADuM3482ARSZ ADuM3482ARSZ-RL7 ADuM3482BRSZ ADuM3482BRSZ-RL7 1 No. of Inputs, VDD1 Side 4 4 4 4 3 3 3 3 No. of Inputs, VDD2 Side 0 0 0 0 1 1 1 1 Maximum Data Rate 1 Mbps 1 Mbps 25 Mbps 25 Mbps 1 Mbps 1 Mbps 25 Mbps 25 Mbps Max Prop Delay, 5 V 90 ns 90 ns 33 ns 33 ns 90 ns 90 ns 33 ns 33 ns Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C 2 2 2 2 2 2 2 2 1 Mbps 1 Mbps 25 Mbps 25 Mbps 90 ns 90 ns 33 ns 33 ns −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Z = RoHS Compliant Part. ©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10459-0-6/14(A) Rev. A | Page 20 of 20 Package Description 20-Lead SSOP 20-Lead SSOP, 7” Reel 20-Lead SSOP 20-Lead SSOP, 7” Reel 20-Lead SSOP 20-Lead SSOP, 7” Reel 20-Lead SSOP 20-Lead SSOP, 7” Reel Evaluation Board 20-Lead SSOP 20-Lead SSOP, 7” Reel 20-Lead SSOP 20-Lead SSOP, 7” Reel Package Option RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20