PRELIMINARY Data Sheet No. PD60256 revA IRS2130D/IRS21303D/IRS2132D 3-PHASE BRIDGE DRIVER Features • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Three Independent half-bridge drivers Matched propagation delay for all channels 2.5 V logic compatible Outputs out of phase with inputs Cross-conduction prevention logic All parts are LEAD-FREE Integrated bootstrap diode function Description Product Summary VOFFSET 600 V max. IO+/- (min.) 200 mA / 420 mA VOUT 10 V – 20 V (IRS213(0,2)D) 13 V – 20 V (IRS21303D) 500 ns ton/off (typ.) Deadtime (typ.) 2.0 µs (IRS2130D) 0.7 µs (IRS213(2,03)D) Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Packages The IRS213(0, 03, 2)D are high voltage, high speed power MOSFET and IGBT drivers with three independent high and low side referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are compatible with CMOS or LSTTL outputs, down to 2.5 V logic. A ground-referenced operational amplifier provides analog feedback of bridge 28-Lead SOIC 28-Lead PDIP current via an external current sense resistor. A current trip function which terminates all six outputs is also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The 44-Lead PLCC w/o 12 Leads floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V. Typical Connection www.irf.com 1 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSO. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Zener clamps are included between VCC & VSO (25 V), VCC & VSS (20V), and VBx & VSx (20 V). Symbol Definition Min. Max. VB1,2,3 High side floating supply voltage -0.3 625 VS1,2,3 High side floating offset voltage VB1,2,3 - 20 VB1,2,3 + 0.3 VHO1,2,3 High side floating output voltage VS1,2,3 - 0.3 VB1,2,3 + 0.3 -0.3 25 VCC Low side and logic fixed supply voltage VSS Logic ground VLO1,2,3 VCC - 20 VCC + 0.3 -0.3 VFLT VCAO FAULT output voltage Operational amplifier output voltage VSS -0.3 VSS -0.3 VCC + 0.3 (VSS + 15) or (VCC + 0.3), whichever is lower VCC +0.3 VCC +0.3 VCA- Operational amplifier inverting input voltage VSS -0.3 VCC +0.3 — 50 (28 lead PDIP) — 1.5 (28 lead SOIC) — 1.6 VIN dVS/dt PD Rth,JA Low side output voltage Logic input voltage ( HIN1,2,3, LIN1,2,3 & ITRIP) Allowable offset supply voltage transient Package power dissipation @ TA ≤ +25 °C Thermal resistance, junction to ambient VSS -0.3 (44 lead PLCC) — 2.0 (28 lead PDIP) — 83 (28 lead SOIC) — 78 (44 lead PLCC) — 63 TJ Junction temperature — 150 TS Storage temperature -55 150 TL Lead temperature (soldering, 10 seconds) — 300 www.irf.com Units V V/ns W °C/W °C 2 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Recommended Operating Conditions The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the recommended conditions. All voltage parameters are absolute voltage referenced to VSO. The VS offset rating is tested with all supplies biased at a 15 V differential. Symbol Definition VB1,2,3 High side floating supply voltage VS1,2,3 High side floating offset voltage VHO1,2,3 High side floating output voltage VCC Low side and logic fixed supply voltage VSS Logic ground VLO1,2,3 Min. IRS213(0,2)D IRS21303D IRS213(0,2)D IRS21303D VS1,2,3 +10 VS1,2,3 +13 Note 1 VS1,2,3 10 13 -5 Max. VS1,2,3 +20 600 VB1,2,3 20 5 Low side output voltage Logic input voltage (HIN1,2,3, LIN1,2,3 & ITRIP) 0 VCC VIN VSS VSS + 5 VFLT FAULT output voltage VSS VCC VCAO Operational amplifier output voltage VSS VSS + 5 VCA- Operational amplifier inverting input voltage VSS VSS + 5 Ambient temperature -40 125 TA Units V °C Note 1: Logic operational for VS of (VSO - 8 V) to (VSO + 600 V). Logic state held for VS of (VSO - 8 V) to (VSO – VBS). (Please refer to the Design Tip DT97-3 for more details). Note 2: The CAO pin and all input pins (except CA-) are internally clamped with a 5.2 V zener diode. www.irf.com 3 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Static Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition Min. Typ. Max. Units Test Conditions VIH Logic “0” input voltage (OUT = LO) 2.2 — — VIL VIT,TH+ Logic “1” input voltage (OUT = HI) ITRIP input positive going threshold — 400 — 490 0.8 580 mV VOH High level output voltage, VBIAS - VO — — 1 V VIN = 0 V, Io= 20 mA VOL Low level output voltage, VO — — 400 mV VIN = 5 V, Io= 20 mA V ILK Offset supply leakage current — — 50 IQBS Quiescent VBS supply current — 30 70 IQCC Quiescent VCC supply current — 4 6 IIN+ IIN- Logic “1” input bias current (OUT = HI) Logic “0” input bias current (OUT = LO) “High” ITRIP bias current “Low” ITRIP bias current IRS213(0,2)D VBS supply undervoltage positive going threshold IRS21303D IRS213(0,2)D VBS supply undervoltage negative going threshold IRS21303D IRS213(0,2)D VCC supply undervoltage positive going threshold IRS21303D IRS213(0,2)D VCC supply undervoltage negative going threshold IRS21303D IRS213(0,2)D Hysteresis IRS21303D IRS213(0,2)D Hysteresis IRS21303D FAULT low on-resistance — — — — 7.5 11 7.1 9 8.3 11 8 9 — — — 400 300 100 10 9.2 13 8.8 11 9.7 13 9.4 11 — — — — 300 220 5 — 8.35 — 7.95 — 9 — 8.7 — 0.3 2 0.4 2 55 IO+ Output high short circuit pulsed current 200 250 — IO- Output low short circuit pulsed current 420 500 — — — — 200 — — — 10 50 TBD 80 — TBD 75 — 4.9 5.2 5.4 V VCA- = 0 V, VSO =1 V — — 30 mV VCA- = 1 V, VSO =0 V IITRIP+ IITRIPVBSUV+ VBSUVVCCUV+ VCCUVVCCUVH VBSUVH Ron, FLT RBS VOS ICACMRR PSRR VOH,AMP VOL,AMP 75 µA mA VIN = 0 V µA VIN = 5 V ITRIP = 5 V ITRIP = 0 V nA V Ω mA Integrated bootstrap diode resistance Operational amplifier input offset voltage CA- input bias current Operational amplifier common mode rejection ratio Operational amplifier power supply rejection ratio Operational amplifier high level output voltage Operational amplifier low level output voltage VB = VS = 600 V Ω mV nA dB VO = 0 V, VIN = 0 V PW ≤ 10 µs VO = 15 V, VIN = 5 V PW ≤ 10 µs VSO = VCA- = 0.2 V VCA- = 2.5 V VSO = VCA- = 0.1 V & 1.1 V VSO = VCA- = 0.2 V VCC = 10 V & 20 V Note: Please refer to Feature Description section for integrated bootstrap functionality information. www.irf.com 4 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Static Electrical Characteristics - (Continued) VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and TA = 25 °C unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respective output leads: HO1,2,3 or LO1,2,3. Symbol Definition Min. Typ. Max. Units Test Conditions ISRC,AMP Operational amplifier output source current 4 7 — ISNK,AMP Operational amplifier output sink current 1 2.1 — — 10 — — 4 — IO+,AMP IO-,AMP Operational amplifier output high short circuit current Operational amplifier output low short circuit current mA VCA- = 0 V, VSO =1 V VCAO = 4 V VCA- = 1 V, VSO =0 V VCAO = 2 V VCA- = 0 V, VSO =5 V VCAO = 0 V VCA- = 5 V, VSO =0 V VCAO = 5 V Dynamic Electrical Characteristics VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS , CL = 1000 pF, TA = 25 °C unless otherwise specified. Symbol Definition Min. Typ. Max. Units Test Conditions ton Turn-on propagation delay 400 500 700 toff Turn-off propagation delay 400 500 700 tr Turn-on rise time — 80 125 tf Turn-off fall time — 35 55 400 660 920 — 400 — 350 550 870 titrip ITRIP to output shutdown propagation delay tbl ITRIP blanking time ITRIP to FAULT indication delay tflt tflt, in tfltclr DT SR+ SR- Input filter time (all six inputs) — 325 — LIN1,2,3 to FAULT clear time IRS213(0,2)D 5300 8500 13700 LIN1,2,3 & HIN1,2,3 to FAULT clear time IRS21303D IRS2130D 1300 2000 3100 Deadtime IRS213(2,03)D 500 700 1100 Operational amplifier slew rate (+) 5 10 — Operational amplifier slew rate (-) 2.4 3.2 — VS1,2,3 = 0 V to 600 V ns V/µs 1 V input step NOTE: For high side PWM, HIN pulse width must be > 1.5 µs. www.irf.com 5 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Fig. 1. Input/Output Timing Diagram Fig. 2. Deadtime Waveform Definitions Fig. 3. Input/Output Switching Time Waveform Definitions www.irf.com 6 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Fig. 4. Overcurrent Shutdown Switching Time Waveform Definitions Fig. 5. Input Filter Function Fig. 6. Diagnostic Feedback Operational Amplifier Circuit www.irf.com 7 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Lead Definitions Symbol Description HIN1,2,3 Logic input for high side gate driver outputs (HO1,2,3), out of phase LIN1,2,3 Logic input for low side gate driver output (LO1,2,3), out of phase FAULT VCC Indicates over-current or undervoltage lockout (low side) has occurred, negative logic Low side and logic fixed supply ITRIP Input for over-current shutdown CAO Output of current amplifier CA- Negative input of current amplifier VSS VB1,2,3 HO1,2,3 VS1,2,3 Logic ground High side floating supply High side gate drive output High side floating supply return LO1,2,3 Low side gate drive output VSO Low side return and positive input of current amplifier Lead Assignments www.irf.com 8 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 9 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 10 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY - 1 Features Description 1.1 Integrated Bootstrap Functionality The IRS213(0,03,2)D family embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of applications. There is one bootstrap FET for each channel and it is connected between each of the floating supply (VB1, VB2, VB3) and VCC (see Fig. 7). The bootstrap FET of each channel follows the state of the respective low side output stage (i.e., bootFet is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 1.1(VCC). In that case the bootstrap FET stays off until the VB voltage returns below that threshold (see Fig. 8). at a very high PWM duty cycle due to the bootstrap FET equivalent resistance (RBS, see page 4). In these cases, better performances can be achieved by using the IRS213(0,03,2) non D version with an external bootstrap network. 2 PCB Layout Tips 2.1 Distance from H to L Voltage The IRS213(0,03,2)J package lacks some pins (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. It’s strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (VB1,2,3, VS1,2,3) side. 2.2 Ground Plane To minimize noise coupling ground plane must not be placed under or near the high voltage floating side. 2.3 Gate Drive Loops Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 9). In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-togate parasitic capacitance. The parasitic autoinductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. IGC VBX (V CC ) Fig. 7. Simplified BootFet Connection gate resistance CGC HO X ( LOX ) Vth~17V Vcc=15V Gate Drive Loop Phase voltage VGE VSX ( Vs0 ) LO Bootstrap FET state BootFet ON BootFet OFF BootFet ON Fig. 9. Antenna Loops Fig. 8. State Diagram Bootstrap FET is suitable for most PWM modulation schemes and can be used either in parallel with the external bootstrap network (diode + resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: when used in non-complementary PWM schemes (typically 6-step modulations) www.irf.com 2.4 Supply Capacitors Supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance. 11 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 2.5 Routing and Placement Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In particular it’s recommended to limit phase voltage negative transients. www.irf.com In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray inductance. See DT04-4 at www.irf.com for more detailed information. 12 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 1500 Turn-off Propagation Delay (ns) Turn-on Propagation Delay (ns) Figures 10-40 provide information on the experimental performance of the IRS2132DS HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 1200 900 600 Exp. 300 0 -50 -25 0 25 50 75 100 1000 125 800 600 Exp. 400 200 0 -50 -25 0 75 100 125 Temperature ( C) Fig. 11. Turn-Off Propagation Delay vs. Temperature Fig. 10. Turn-On Propagation Delay vs. Temperature 250 Turn-Off fall Time (ns) Turn-On Rise Time (ns) 50 o Temperature (oC) 200 150 100 25 Exp. 125 100 75 50 Exp. 50 25 0 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 12. Turn-On Rise Time vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 13. Turn-Off Fall Time vs. Temperature 13 125 IRS2130D/IRS21303D/IRS2132D (J&S)PbF 1500 1500 1200 1200 Exp. 900 600 300 0 -50 -25 0 25 50 75 100 125 TiTRIP Propagation Delay (ns) DT Propagation Delay (ns) PRELIMINARY 900 Exp. 600 300 0 -50 -25 0 Temperature (oC) 900 Exp. 600 300 0 25 50 75 100 125 FAULT Low On Resistance ( Ohm) ITRIP to FAULT Propagation Delay (ns) 1200 0 100 50 Exp. 0 -50 -25 0 8 Exp. 4 2 0 25 50 75 100 Temperature (oC) Fig. 18. VCC Quiescent Current vs. Temperature www.irf.com 50 75 100 125 Fig.17. FAULT Low On Resistance vs. Temperature 10 0 25 Temperature ( C) 125 VBS Quiescent Supply Current (uA) VCC Quiescent Supply Current (mA) 150 o Fig. 16. ITRIP to FAULT Propagation Delay vs. Temperature -25 125 200 Temperature ( C) -50 100 250 o 6 75 Fig. 15. TITRIP Propagation Delay vs. Temperature 1500 -25 50 o Fig. 14. DT Propagation Delay vs. Temperature -50 25 Temperature ( C) 100 80 60 Exp. 40 20 0 -50 -25 0 25 50 75 100 125 Temperature (oC) Fig. 19. VBS Quiescent Current vs. Temperature 14 IRS2130D/IRS21303D/IRS2132D (J&S)PbF 11 11 10 10 VCCUV- Threshold (V) VCCUV+ Threshold (V) PRELIMINARY Exp. 9 8 7 6 9 Exp. 8 7 6 -50 -25 0 25 50 75 100 125 -50 -25 0 25 o 125 Fig. 21. VCCUV- Threshold vs. Temperature 11 11 10 10 VBSUV- Threshold (V) VBSUV+ Threshold (V) 100 Temperature ( C) Fig. 20. VCCUV+ Threshold vs. Temperature 9 Exp. 7 6 9 Exp. 8 7 6 -50 -25 0 25 50 75 100 125 -50 -25 0 25 o 250 0 0 25 50 75 100 125 Temperature (oC) Fig. 24. ITRIP Positive Going Threshold vs. Temperature www.irf.com ITRIP Negative Going Threshold (mV) EXP. -25 100 125 Fig. 23. VBSUV- Threshold vs. Temperature 750 -50 75 Temperature ( C) Fig. 22. VBSUV+ Threshold vs. Temperature 500 50 o Temperature ( C) ITRIP Positive Going Threshold (mV) 75 o Temperature ( C) 8 50 750 500 Exp. 250 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 25. ITRIP Negative Going Threshold vs. Temperature 15 125 IRS2130D/IRS21303D/IRS2132D (J&S)PbF Output High Short Circuit Pulsed Current (mA) 500 400 300 Exp. 200 100 0 -50 -25 0 25 50 75 100 125 Output Low Short Circuit Current (mA) PRELIMINARY 750 600 Exp. 450 300 150 0 -50 -25 0 75 100 125 Fig. 27. Output Low Short Circuit Current vs. Temperature Fig. 26. Output High Short Circuit Pulsed Current vs. Temperature 25 "LOW" ITRIP Bias Current (nA) "HIGH" ITRIP Bias Current (uA) 50 Temperature ( C) Temperature ( C) 20 15 10 5 Exp. 0 25 20 15 10 Exp. 5 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 25 50 75 100 125 Temperature (oC) Fig. 29. "Low" ITRIP Bias Current vs. Temperature Fig. 28. "High" ITRIP Bias Current vs. Temperature 8 25 20 6 Exp. Exp. VOL,AMP (mV) VOH,AMP (V) 25 o o 4 2 0 15 10 5 0 -50 -25 0 25 50 75 o Temperature ( C) Fig. 30. VOH,AMP vs. Temperature www.irf.com 100 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 31. VOL,AMP vs. Temperature 16 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 5 4 15 SR-,AMP (V/us) SR+,AMP (V/us) 20 Exp. 10 5 0 Exp. 3 2 1 0 -50 -25 0 25 50 75 100 125 -50 -25 0 25 o 75 100 125 100 125 100 125 o Temperature ( C) Temperature ( C) Fig. 32. SR+,AMP vs. Temperature Fig. 33. SR-,AMP vs. Temperature 12 5 10 3 ISRC,AMP (mA) 4 ISNK,AMP (mA) 50 Exp. 2 1 Exp. 8 6 4 2 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 o Temperature (oC) Temperature ( C) Fig. 34. ISNK,AMP vs. Temperature Fig. 35. ISRC,AMP vs. Temperature 15 20 12 16 9 IO+,AMP (mA) IO-,AMP (mA) Exp. 6 3 0 12 8 Exp. 4 0 -50 -25 0 25 50 75 o Temperature ( C) Fig. 36. IO-,AMP vs. Temperature www.irf.com 100 125 -50 -25 0 25 50 75 o Temperature ( C) Fig. 37. IO+,AMP vs. Temperature 17 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY 90 125 70 100 PSRR (dB) 50 30 75 50 25 10 Exp. 0 -10 -50 -25 0 25 50 75 100 -50 125 -25 0 25 50 75 100 o o Temperature ( C) Temperature ( C) Fig. 39. PSRR vs. Temperature Fig. 38. VOS,AMP vs. Temperature 150 125 100 CMRR (dB) VOS,AMP (mV) Exp. 75 Exp. 50 25 0 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 40. CMRR vs. Temperature www.irf.com 18 125 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Case Outlines www.irf.com 19 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY Case Outlines www.irf.com 20 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 11.90 12.10 B 3.90 4.10 C 23.70 24.30 D 11.40 11.60 E 10.80 11.00 F 18.20 18.40 G 1.50 n/a H 1.50 1.60 28SOICW Imperial Min Max 0.468 0.476 0.153 0.161 0.933 0.956 0.448 0.456 0.425 0.433 0.716 0.724 0.059 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 28SOICW Metric Imperial Code Min Max Min Max A 329.60 330.25 12.976 13.001 B 20.95 21.45 0.824 0.844 C 12.80 13.20 0.503 0.519 D 1.95 2.45 0.767 0.096 E 98.00 102.00 3.858 4.015 F n/a 30.40 n/a 1.196 G 26.50 29.10 1.04 1.145 H 24.40 26.40 0.96 1.039 www.irf.com 21 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 23.90 24.10 B 3.90 4.10 C 31.70 32.30 D 14.10 14.30 E 17.90 18.10 F 17.90 18.10 G 2.00 n/a H 1.50 1.60 44PLCC Imperial Min Max 0.94 0.948 0.153 0.161 1.248 1.271 0.555 0.562 0.704 0.712 0.704 0.712 0.078 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 44PLCC Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 38.4 G 34.7 35.8 H 32.6 33.1 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 1.511 1.366 1.409 1.283 1.303 22 IRS2130D/IRS21303D/IRS2132D (J&S)PbF PRELIMINARY ORDER INFORMATION 28-Lead PDIP IRS2130DPbF 28-Lead PDIP IRS21303DPbF 28-Lead PDIP IRS2132DPbF 28-Lead SOIC IRS2130DSPbF 28-Lead SOIC IRS21303DSPbF 28-Lead SOIC IRS2132DSPbF 44-Lead PLCC IRS2132DJPbF 44-Lead PLCC IRS21303DJPbF 44-Lead PLCC IRS2132DJPbF 28-Lead SOIC Tape & Reel IRS2130DSTRPbF 28-Lead SOIC Tape & Reel IRS21303DSTRPbF 28-Lead SOIC Tape & Reel IRS2132DSTRPbF 44-Lead PLCC Tape & Reel IRS2130DJTRPbF 44-Lead PLCC Tape & Reel IRS21303DJTRPbF 44-Lead PLCC Tape & Reel IRS2132DJTRPbF WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105 This part has been qualified per industrial level http://www.irf.com Data and specifications subject to change without notice.5/19/2006 www.irf.com 23