Data Sheet No. PD60247revD PRELIMINARY IRS2136D/IRS21362D/IRS21363D/IRS21365D/ IRS21366D/IRS21367D/IRS21368D (J&S) PBF 3-PHASE BRIDGE DRIVER Packages Features • • • • • • • • • • • • • • • Floating channel designed for bootstrap operation Fully operational to +600 V Tolerant to negative transient voltage, dV/dt immune Gate drive supply range from 10 V to 20 V (IRS2136D/ IRS21368D), 11.5 V to 20 V (IRS21362D), or 12 V to 20 V (IRS21363D/IRS21365D/IRS21366D/IRS21367D Undervoltage lockout for all channels Over-current shutdown turns off all six drivers Independent 3 half-bridge drivers Matched propagation delay for all channels Cross-conduction prevention logic Integrated bootstrap diode function Low side output out of phase with inputs. High side outputs out of phase (IRS213(6,63, 65, 66, 67, 68)D), or in phase (IRS21362D) with inputs 3.3 V logic compatible Lower di/dt gate drive for better noise immunity Externally programmable delay for automatic fault clear All parts are LEAD-FREE 28-Lead SOIC 28-Lead PDIP 44-Lead PLCC w/o 12 Leads Applications: *Motor Control *Air Conditioners/ Washing Machines *General Purpose Inverters *Micro/Mini Inverter Drives Description The IRS2136xD (J&S) are high voltage, high Feature Comparison: IRS2136xD speed power MOSFET and IGBT driver with three independent high side and low side Part IRS2136D IRS21362D IRS21363D IRS21365D IRS21366D IRS21367D IRS21368D referenced output channels for 3-phase ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ Input Logic HIN, LIN HIN, LIN HIN, LIN HIN, LIN HIN, LIN HIN, LIN HIN, LIN applications. Proprietary HVIC technology t (typ.) 530 ns 530 ns 530 ns 530 ns 200 ns 200 ns 530 ns enables ruggedized monolithic construction. t (typ.) 530 ns 530 ns 530 ns 530 ns 200 ns 200 ns 530 ns Logic inputs are compatible with CMOS or V (min.) 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V LSTTL outputs, down to 3.3 V logic. A V (max.) 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V current trip function which terminates all six V 0.46 V 0.46 V 0.46 V 4.3 V 0.46 V 4.3 V 4.3 V outputs can be derived from an external V / 8.9 V 10.4 V 11.1 V 11.1 V 11.1 V 11.1 V 8.9 V V current sense resistor. An enable function is V / 8.2 V 9.4 V 10.9 V 10.9 V 10.9 V 10.9 V 8.2 V available to terminate all six outputs V simultaneously. An open-drain FAULT signal is provided to indicate that an overcurrent or undervoltage shutdown has occurred. Overcurrent fault conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration which operates up to 600 V. on off IH IL ITRIP+ CCUV+ BSUV+ CCUV- BSUV- Typical Connection www.irf.com 1 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage Symbol Definition VS High side offset voltage VB High side floating supply voltage VHO1,2,3 High side floating output voltage Min. Max. VB 1,2,3 - 20 VB 1,2,3 + 0.3 -0.3 620 VS1,2,3 - 0.3 VB 1,2,3 + 0.3 VCC Low side and logic fixed supply voltage -0.3 20 VSS Logic ground VCC - 20 VCC + 0.3 Low side output voltage Input voltage LIN, HIN, ITRIP, EN, RCIN FAULT output voltage -0.3 VSS -0.3 VSS -0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 — 50 (28 lead PDIP) — 1.5 (28 lead SOIC) — 1.6 (44 lead PLCC) — 2.0 (28 lead PDIP) — 83 (28 lead SOIC) — 78 VLO1,2,3 VIN VFLT dV/dt PD RthJA Allowable offset voltage slew rate Package power dissipation @ TA ≤ +25 °C Thermal resistance, junction to ambient Units (44 lead PLCC) V V/ns W °C/W — 63 TJ Junction temperature — 150 TS Storage temperature -55 150 °C TL Lead temperature (soldering, 10 seconds) — 300 parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Recommended Operating Conditions The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The VS & VSS offset ratings are tested with all supplies biased at a 15 V differential. Symbol Definition Min. IRS213(6,68)D VB1,2,3 High side floating supply voltage IRS21362D VS 1,2,3 High side floating supply voltage IRS213(6,63,65,66,67)D IRS213(6,68)D VCC Low side supply voltage IRS21362D IRS213(6,63,65,66,67)D VHO 1,2,3 VLO1,2,3 VSS High side output voltage Low side output voltage Max. VS1,2,3 +10 VS1,2,3 + 20 VS1,2,3 +11.5 VS1,2,3 + 20 VS1,2,3 +12 VS1,2,3 + 20 Note 1 600 10 20 11.5 20 12 20 VS1,2,3 0 VB1,2,3 VCC Logic ground FAULT output voltage -5 5 VFLT VSS VCC VRCIN RCIN input voltage VSS VCC Units V Note 1: Logic operational for VS of (COM - 8 V) to (COM + 600 V). Logic state held for VS of (COM - 8 V) to (COM – VBS). (Please refer to the Design Tip DT97-3 for more details). www.irf.com 2 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Recommended Operating Conditions - (Continued) The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute referenced to COM. The VS & VSS offset ratings are tested with all supplies biased at a 15 V differential. Definition Symbol Min. VITRIP ITRIP input voltage Logic input voltage LIN, HIN (IRS213(6,63,65,66,67,68)D), VIN LIN, HIN (IRS21362D), EN TA Ambient temperature Note 1: HIN, LIN, EN and the ITRIP pin are internally clamped with a 5.2 V zener diode. Max. Units VSS VSS + 5 VSS VSS + 5 -40 125 V °C Static Electrical Characteristics VBIAS (VCC,VBS1,2,3) = 15 V unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six channels (HIN1,2,3/HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Symbol Definition Min. Typ. Max. Units Test Conditions Logic “0” input voltage LIN1,2,3, HIN1,2,3 IRS213(6,63,65)D 2.5 — — VIH Logic “1” input voltage HIN1,2,3 IRS21362D Logic “0” input voltage LIN1,2,3, HIN1,2,3 2.5 — — IRS213(66,67,68)D Logic “1” input voltage LIN1,2,3, HIN1,2,3 IRS213(6,63,65)D Logic “0” input voltage HIN1,2,3 IRS21362D VIL — — 0.8 Logic “0” input voltage LIN1,2,3, HIN1,2,3 IRS213(66,67,68)D VIN,TH+ Input positive going threshold — 1.9 — VIN,TH- Input negative going threshold — 1 — VEN,TH+ Enable positive going threshold — — 2.5 VEN,TH- Enable negative going threshold 0.8 — — ITRIP positive going threshold 0.37 0.46 VIT,TH+ (6,62,63,66) VIT,HYS (6,62,63,66) ITRIP hysteresis VIT,TH+ (65,67,68) ITRIP positive going threshold VIT,HYS (65,67,68) 0.55 — 0.07 — 3.85 4.3 4.75 ITRIP hysteresis — 0.15 — VRCIN, TH+ RCIN positive going threshold — 8 — VRCIN, HYS RCIN hysteresis — 3 — VOH High level output voltage, VBIAS - VO — 0.9 1.4 VOL Low level output voltage, VO VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage hysteresis VBS supply undervoltage positive going threshold — 0.4 0.6 8 8.9 9.8 7.4 8.2 9 0.3 0.7 — 8 8.9 9.8 VCCUV+ (6,68) VCCUV- (6,68) VCCUVHY (6,68) VBSUV+ (6,68) www.irf.com V Io = 20 mA 3 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Static Electrical Characteristics - (Continued) VBIAS (VCC,VBS1,2,3) = 15 V unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six channels (HIN1,2,3/ HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Symbol VBSUV- (6,68) VBSUVHY (6,68) VCCUV+ (62) VCCUV- (62) VCCUVHY (62) VBSUV+ (62) VBSUV- (62) VBSUVHY (62) VCCUV+ (63,65,66,67) VCCUV(63,65,66,67) VCCUVHY (63,65,66,67) VBSUV+ (63,65,66,67) VBSUV(63,65,66,67) VBSUVHY (63,65,66,67) ILK Definition VBS supply undervoltage negative going threshold VBS supply undervoltage hysteresis VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage hysteresis VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold VBS supply undervoltage hysteresis VCC supply undervoltage positive going threshold VCC supply undervoltage negative going threshold VCC supply undervoltage hysteresis VBS supply undervoltage positive going threshold VBS supply undervoltage negative going threshold Min. Typ. Max. Units 7.4 8.2 9 0.3 0.7 — 9.6 10.4 11.2 8.6 9.4 10.2 0.5 1 — 9.6 10.4 11.2 8.6 9.4 10.2 0.5 1 — 10.4 11.1 11.6 10.2 10.9 11.4 — 0.2 Test Conditions V — 10.4 11.1 11.6 10.2 10.9 11.4 VBS supply undervoltage hysteresis — 0.2 — Offset supply leakage current — — 50 IQBS Quiescent VBS supply current — 70 120 IQCC Quiescent VCC supply current — 3 4 mA all inputs @ logic 0 value Input clamp voltage (HIN, LIN, ITRIP and EN) 4.8 5.2 5.65 V IIN=100 µA ILIN+ (6,62,63,65) Input bias current (LOUT = HI) — 110 150 VIN=4 V ILIN- (6,62,63,65) Input bias current (LOUT = LO) — 150 200 VIN=0 V ILIN+ (66,67,68) Input bias current (LOUT = HI) — — 3 VIN=4 V VIN,CLAMP µA VB=VS= 600 V ILIN- (66,67,68) Input bias current (LOUT = LO) — — 3 VIN=0 V IHIN+ (6,63,65) Input bias current (HOUT = HI) — 110 150 VIN=4 V IHIN- (6,63,65) Input bias current (HOUT = LO) — 150 200 VIN=0 V IHIN+ (62) Input bias current (HOUT = HI) — 5 20 IHIN- (62) Input bias current (HOUT = LO) — — 3 IHIN+ (66,67,68) Input bias current (HOUT = HI) — — 3 VIN=4 V IHIN- (66,67,68) Input bias current (HOUT = LO) — — 3 VIN=0 V IITRIP+ “High” ITRIP input bias current — 5 40 VIN=4 V IITRIP- “Low” ITRIP input bias current — — 1 VIN=0 V IEN+ “High” ENABLE input bias current — 5 40 VIN=4 V IEN- “Low” ENABLE input bias current — — 1 VIN=0 V www.irf.com µA VIN=4 V VIN=0 V 4 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Static Electrical Characteristics - (Continued) VBIAS (VCC,VBS1,2,3) = 15 V unless otherwise specified. The VIN, VTH, and IIN parameters are referenced to VSS and are applicable to all six channels (HIN1,2,3/HIN1,2,3 and LIN1,2,3). The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads: LO1,2,3 and HO1,2,3. Symbol IRCIN Definition RCIN input bias current Min. Typ. Max. Units — — 1 IO+ Output high short circuit pulsed current 120 200 — IO- Output low short circuit pulsed current 250 350 — RCIN low on resistance FAULT low on resistance — 50 100 — 50 100 Internal BS diode RON — 200 — Ron_RCIN Ron_FAULT RBS µA mA Ω Test Conditions VRCIN= 0 V or 15 V Vo =0 V, PW ≤10 µs Vo =15 V, PW ≤10 µs I= 1.5 mA Note 1: Please refer to Feature Description section for integrated bootstrap functionality information. Dynamic Electrical Characteristics Dynamic Electrical Characteristics VCC = VBS = VBIAS = 15 V, VS1,2,3 = VSS = COM, TA = 25 °C and CL = 1000 pF unless otherwise specified. Symbol Definition Min. Typ. Max. Units ton Turn-on propagation delay 400 530 750 toff Turn-off propagation delay 400 530 750 ton (66,67) Turn-on propagation delay — 200 — toff(66,67) Turn-off propagation delay — 200 — Test Conditions VIN = 0 V & 5 V tr Turn-on rise time — 125 190 tf Turn-off fall time ENABLE low to output shutdown propagation delay ENABLE low to output shutdown propagation delay ITRIP to output shutdown propagation delay — 50 75 350 460 650 — 300 — 500 750 1200 — 400 — 400 600 950 VIN = 0 V or 5 V VITRIP = 5 V 200 350 510 VIN = 0 V & 5 V 100 200 — 190 290 420 tEN tEN (66,67) tITRIP tbl tFLT tFILIN tfilterEN ITRIP blanking time ITRIP to FAULT propagation delay Input filter time (HIN, LIN) (IRS213(6,62,63,65,68)D only) Enable input filter time (IRS213(6,62,63,65,68)D only) DT Deadtime MT ton, toff matching time (on all six channels) — — 50 DT matching (Hi->Lo & Lo->Hi on all channels) — — 60 Pulse width distortion (pwin-pwout) FAULT clear time RCIN: R = 2 MΩ, C = 1 nF — — 75 1.3 1.65 2 MDT PM tFLTCLR VIN, VEN = 0 V or 5 V VITRIP =5 V ns ms VIN = 0 V & 5 V external dead time External dead time >420 ns External dead time 0 s PW input=10 µs VIN = 0 V or 5 V VITRIP = 0 V Note 2: For high side PWM, HIN pulse width must be ≥ 500 ns. www.irf.com 5 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY HIN1,2,3 HIN1,2,3 LIN1,2,3 EN ITRIP FAULT RCIN HO1,2,3 LO1,2,3 Fig. 1. Input/Output Timing Diagram LIN1,2,3 50% 50% 50% HIN1,2,3 EN PW IN ten LIN1,2,3 HIN1,2,3 50% ton HO1,2,3 LO1,2,3 50% tr PW OUT 90% 10% HO1,2,3 LO1,2,3 toff tf 90% 10% Fig. 2. Switching Time Waveforms www.irf.com 90% Fig. 3. Output Enable Timing Waveform 6 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY L IN 1 ,2 ,3 50% 50% H IN 1 ,2 ,3 L IN 1 ,2 ,3 H IN 1 ,2 ,3 50% 50% 50% 50% L O 1 ,2 ,3 D T H O 1 ,2 ,3 D T 50% 50% Fig. 4. Internal Deadtime Timing Waveforms R C IN 50% IT R IP FAULT tflt 50% 50% 50% 90% Any O uput tfltc lr titrip Fig. 5. ITRIP/RCIN Timing Waveforms t in,fil t in,fil H IN /LIN H O /LO o ff on on off on n o ff h ig h lo w Fig. 6. Input Filter Function www.irf.com 7 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Lead Definitions Symbol VCC VSS HIN1,2,3 HIN1,2,3 LIN1,2,3 FAULT EN ITRIP RCIN COM VB1,2,3 HO1,2,3 VS1,2,3 LO1,2,3 Description Low side supply voltage Logic ground Logic inputs for high side gate driver outputs (HO1,2,3), out of phase [IRS213(6,63,65,66,67,68)D] Logic inputs for high side gate driver outputs (HO1,2,3), in phase (IRS21362D) Logic input for low side gate driver outputs (LO1,2,3), out of phase Indicates over-current (ITRIP) or low-side undervoltage lockout has occurred. Negative logic, opendrain output Logic input to enable I/O functionality. I/O logic functions when ENABLE is high (i.e., positive logic) No effect on FAULT and not latched Analog input for overcurrent shutdown. When active, ITRIP shuts down outputs and activates FAULT and RCIN low. When ITRIP becomes inactive, FAULT stays active low for an externally set time TFLTCLR, then automatically becomes inactive (open-drain high impedance). External RC network input used to define FAULT CLEAR delay, TFLTCLR, approximately equal to R*C When RCIN>8 V, the FAULT pin goes back into open-drain high-impedance Low side gate drivers return High side floating supply High side gate driver outputs High voltage floating supply return Low side driver sourcing outputs Note: LIN, HIN, EN, and ITRIP are internally clamped with a 5.2 V zener diode. www.irf.com 8 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Lead Assignments www.irf.com 9 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 10 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 11 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Functional Block Diagram www.irf.com 12 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Functional Block Diagram VCC <UVCC 15 V 15 V 15 V 15 V VBS X <UVBS 15 V 15 V 15 V ITRIP X 0V 0V >VITRIP 0V ENABLE X 5V 5V 5V 0V FAULT 0 (note 1) high imp high imp 0 (note 3) high imp LO1,2,3 0 LIN1,2,3 LIN1,2,3 0 0 HO1,2,3 0 0 (note 2) HIN1,2,3 0 0 Note 1: A shoot-through prevention logic prevents LO1,2,3 and HO1,2,3 for each channel from turning on simultaneously. Note 2: UVCC is not latched, when VCC > UVCC, FAULT returns to high impedance. Note 3: When VBS < UVBS, HO goes low. After VBS goes higher than UVBS, HO stays low until a new falling IRS213(6,63,65,66,67,68)D or rising IRS21362D transition of HIN. Note 4: When ITRIP < VITRIP, FAULT returns to high-impedance after RCIN pin becomes greater than 8 V (@ VCC = 15 V). www.irf.com 13 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY 1 Features Description 1.1 Integrated Bootstrap Functionality The IRS2136xD family embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of applications. - at a very high PWM duty cycle due to the bootstrap FET equivalent resistance (RBS, see page 5). In these cases, better performances can be achieved by using the IRS2136x non D version with an external bootstrap network. There is one bootstrap FET for each channel and it is connected between each of the floating supply (VB1, VB2, VB3) and VCC (see Fig. 7). 2 PCB Layout Tips The bootstrap FET of each channel follows the state of the respective low side output stage (i.e., bootFet is ON when LO is high, it is OFF when LO is low), unless the VB voltage is higher than approximately 1.1(VCC). In that case the bootstrap FET stays off until the VB voltage returns below that threshold (see Fig. 8). The IRS2136xDJ package lacks some pins (see page 8) in order to maximizing the distance between the high voltage and low voltage pins. It’s strongly recommended to place the components tied to the floating voltage in the respective high voltage portions of the device (VB1,2,3, VS1,2,3) side. 2.1 Distance from H to L Voltage 2.2 Ground Plane To minimize noise coupling ground plane must not be placed under or near the high voltage floating side. 2.3 Gate Drive Loops Current loops behave like an antenna able to receive and transmit EM noise (see Fig. 9). In order to reduce EM coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-togate parasitic capacitance. The parasitic autoinductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. Fig. 7. Simplified BootFet Connection Vth~17V Vcc=15V Phase voltage LO Bootstrap FET state BootFet ON BootFet OFF BootFet ON Fig. 8. State Diagram Bootstrap FET is suitable for most PWM modulation schemes and can be used either in parallel with the external bootstrap network (diode+resistor) or as a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some limitations in the following situations: when used in non-complementary PWM schemes (typically 6-step modulations) www.irf.com Fig. 9. Antenna Loops 2.4 Supply Capacitors Supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic inductance/resistance. 14 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY 2.5 Routing and Placement Power stage PCB parasitic may generate dangerous voltage transients for the gate driver and the control logic. In particular it’s recommended to limit phase voltage negative transients. www.irf.com In order to avoid such undervoltage it is highly recommended to minimize high side emitter to low side collector distance and low side emitter to negative bus rail stray inductance. See DT04-4 at www.irf.com for more detailed information. 15 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY 1000 Turn-off Propagation Delay (ns) Turn-on Propagation Delay (ns) Figures 10-30 provide information on the experimental performance of the IRS2136DS HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood trend. The individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 800 600 Exp. 400 200 0 -50 -25 0 25 50 75 100 1000 800 600 Exp. 400 200 0 -50 125 -25 0 Fig. 10. Turn-On Propagation Delay vs. Temperature 75 100 125 Fig. 11. Turn-Off Propagation Delay vs. Temperature Turn-Off Fall Time (ns) 300 Turn-On Rise Time (ns) 50 Temperature ( C) Temperature ( C) 225 150 Exp. 75 25 o o 100 75 50 Exp. 25 0 0 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 12. Turn-On Rise Time vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 13. Turn-Off Fall Time vs. Temperature 16 IRS213(6,62,63,65,66,67,68)D(J&S)PbF 600 TITRIP Propagation Delay (ns) DT Propagation Delay (ns) PRELIMINARY 450 Exp. 300 150 1500 1200 900 Exp. 600 300 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 1200 1000 Exp. 600 400 200 0 -25 0 25 50 75 100 600 Exp. 400 200 0 -50 -25 0 20 0 75 100 125 o Temperature ( C) Fig. 18. RCIN Low On Resistance vs. Temperature www.irf.com FAULT Low On Resistance ( Ohm) RCIN Low On Resistance ( Ohm) Exp. 50 75 100 125 Fig. 17. TEN SD Propagation Delay vs. Temperature 60 25 50 Temperature ( C) 80 0 25 o 100 -25 125 800 125 Fig. 16. ITRIP to FAULT Propagation Delay vs. Temperature -50 100 1000 Temperature (oC) 40 75 Fig. 15. TITRIP Propagation Delay vs. Temperature TEN SD Propagation Delay (ns) ITRIP to FAULT Propagation Delay (ns) Fig. 14. DT Propagation Delay vs. Temperature -50 50 Temperature ( C) Temperature ( C) 800 25 o o 100 80 60 40 Exp. 20 0 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 19. FAULT Low On Resistance vs. Temperature 17 IRS213(6,62,63,65,66,67,68)D(J&S)PbF 5 VBS Quiescent Current (uA) VCC Quiescent Current (mA) PRELIMINARY 4 3 Exp. 2 1 120 100 80 60 Exp. 40 20 0 0 -50 -25 0 25 50 75 100 -50 125 -25 0 75 100 125 Fig. 21. VBS Quiescent Current vs. Temperature Fig. 20. VCC Quiescent Current vs. Temperature 12 12 10 10 Exp. VCCUV- Threshold (V) VCCUV+ Threshold (V) 50 Temperature ( C) Temperature ( C) 8 6 4 2 0 8 Exp. 6 4 2 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 25 50 75 100 125 o Temperature ( C) Fig. 22. VCCUV+ Threshold vs. Temperature Fig. 23. VCCUV- Threshold vs. Temperature 10 10 9 9 VBSUV+ Threshold (V) VBSUV+ Threshold (V) 25 o o Exp. 8 7 6 5 Exp. 8 7 6 5 -50 -25 0 25 50 75 100 o Temperature ( C) Fig. 24. VBSUV+ Threshold vs. Temperature www.irf.com 125 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 25. VBSUV- Threshold vs. Temperature 18 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY 800 600 600 ITRIP TH- (mV) ITRIP TH+ (mV) 800 EXP. 400 200 Exp. 400 200 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (oC) 75 100 125 100 125 Temperature ( C) Fig. 27. ITRIP TH- vs. Temperature 0.30 IO- L1 SC Current (A) IO+ L1 SC Pulsed Currentt (A) 50 o Fig. 26. ITRIP TH+ vs. Temperature 0.25 Exp. 0.20 25 0.15 0.10 0.50 0.45 0.40 Exp. 0.35 0.30 0.25 0.05 0.20 0.15 0.00 -50 -25 0 25 50 75 100 -50 125 -25 25 50 75 Temperature ( C) Temperature ( C) Fig. 29. IO- L1 SC Pulsed Current vs. Temperature Fig. 28. IO+ L1 SC Pulsed Current vs. Temperature ITRIP Input Bias Current (uA) 0 o o 16 12 8 4 Exp. 0 -50 -25 0 25 50 75 100 125 o Temperature ( C) Fig. 30. ITRIP Input Bias Current vs. Temperature www.irf.com 19 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Case Outlines www.irf.com 20 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY Case Outlines www.irf.com 21 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY LOADED TAPE FEED DIRECTION A B H D F C NOTE : CONTROLLING DIM ENSION IN M M E G CARRIER TAPE DIMENSION FOR Metric Code Min Max A 23.90 24.10 B 3.90 4.10 C 31.70 32.30 D 14.10 14.30 E 17.90 18.10 F 17.90 18.10 G 2.00 n/a H 1.50 1.60 44PLCC Imperial Min Max 0.94 0.948 0.153 0.161 1.248 1.271 0.555 0.562 0.704 0.712 0.704 0.712 0.078 n/a 0.059 0.062 F D C B A E G H REEL DIMENSIONS FOR 44PLCC Metric Code Min Max A 329.60 330.25 B 20.95 21.45 C 12.80 13.20 D 1.95 2.45 E 98.00 102.00 F n/a 38.4 G 34.7 35.8 H 32.6 33.1 www.irf.com Imperial Min Max 12.976 13.001 0.824 0.844 0.503 0.519 0.767 0.096 3.858 4.015 n/a 1.511 1.366 1.409 1.283 1.303 22 IRS213(6,62,63,65,66,67,68)D(J&S)PbF PRELIMINARY ORDER INFORMATION 28-Lead PDIP IRS2136DPbF 28-Lead PDIP IRS21362DPbF 28-Lead PDIP IRS21363DPbF 28-Lead PDIP IRS21365DPbF 28-Lead PDIP IRS21366DPbF 28-Lead PDIP IRS21367DPbF 28-Lead PDIP IRS21368DPbF 28-Lead SOIC IRS2136DSPbF 28-Lead SOIC IRS21362DSPbF 28-Lead SOIC IRS21363DSPbF 28-Lead SOIC IRS21365DSPbF 28-Lead SOIC IRS21366DSPbF 28-Lead SOIC IRS21367DSPbF 28-Lead SOIC IRS21368DSPbF 44-Lead PLCC IRS2136DJPbF 44-Lead PLCC IRS21362DJPbF 44-Lead PLCC IRS21363DJPbF 44-Lead PLCC IRS21365DJPbF 44-Lead PLCC IRS21366DJPbF 44-Lead PLCC IRS21367DJPbF 44-Lead PLCC IRS21368DJPbF 28-Lead SOIC Tape & Reel IRS2136DSTRPbF 28-Lead SOIC Tape & Reel IRS21362DSTRPbF 28-Lead SOIC Tape & Reel IRS21363DSTRPbF 28-Lead SOIC Tape & Reel IRS21365DSTRPbF 28-Lead SOIC Tape & Reel IRS21366DSTRPbF 28-Lead SOIC Tape & Reel IRS21367DSTRPbF 28-Lead SOIC Tape & Reel IRS21368DSTRPbF 44-Lead PLCC Tape & Reel IRS2136DJTRPbF 44-Lead PLCC Tape & Reel IRS21362DJTRPbF 44-Lead PLCC Tape & Reel IRS21363DJTRPbF 44-Lead PLCC Tape & Reel IRS21365DJTRPbF 44-Lead PLCC Tape & Reel IRS21366DJTRPbF 44-Lead PLCC Tape & Reel IRS21367DJTRPbF 44-Lead PLCC Tape & Reel IRS21368DJTRPbF WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: (310) 252-7105 This part has been qualified per industrial level http://www.irf.com Data and specifications subject to change without notice. 5/19/2006 www.irf.com 23