IRF IR3088M

NOT RECOMMENDED FOR NEW
DESIGNS. REPLACE WITH IR3088A
Data Sheet No. PD94712
IR3088
XPHASETM PHASE IC WITH FAULT AND OVERTEMP DETECT
DESCRIPTION
The IR3088 Phase IC combined with an IR XPhaseTM Control IC provides a full featured and flexible way to
implement power solutions for the latest high performance CPUs and ASICs. The “Control” IC provides
overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single
phase of a multiphase converter. The XPhaseTM architecture results in a power supply that is smaller, less
expensive, and easier to design while providing higher efficiency than conventional approaches.
The IR3088 is intended for the following application conditions:
•
Excessive impedance between converter and load
•
Output voltage exceeding the control IC reference/VID voltage
FEATURES
•
2.5A Average Gate Drive Current
•
Loss-Less Inductor Current Sense
•
Internal Inductor DCR Temperature Compensation
•
Programmable Phase Delay
•
Programmable Feed-Forward Voltage Mode PWM Ramp
•
Sub 100ns Minimum Pulse Width supports 1MHz per-phase operation
•
Current Sense Amplifier drives a single wire Average Current Share Bus
•
Current Share Amplifier reduces PWM Ramp slope to ensure sharing between phases
•
Body BrakingTM disables Synchronous MOSFET for improved transient response and prevents negative
output voltage at converter turn-off
•
Phase Fault Detection
•
Programmable Phase Over-Temperature Detection
•
Control FET driver’s 25V input voltage capability simplifies boot-strap supply design
•
Small thermally enhanced 20L MLPQ package
CSIN-
16
17
18
PHSFLT
CSIN+
GATEH
PGND
GATEL
14
13
12
11
VCC
LGND
VCCL
15
10
6
Page 1 of 34
PWMRMP
ISHARE
9
VRHOT
SCOMP
5
HOTSET
EAIN
4
IR3088
PHASE
IC
RMPIN-
8
3
DACIN
20
BIASIN
2
VCCH
RMPIN+
7
1
19
PACKAGE PINOUT
9/30/04
IR3088
ORDERING INFORAMATION
Device
Order Quantity
IR3088MTR
3000 per reel
* IR3088M
100 piece strips
* Samples only
ABSOLUTE MAXIMUM RATINGS
Operating Junction Temperature……………..150oC
Storage Temperature Range………………….-65oC to 150oC
ESD Rating………………………………………HBM Class 1C JEDEC standard
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1
2
3
4
5
6
RMPIN+
RMPINHOTSET
VRHOT
ISHARE
SCOMP
20V
20V
20V
20V
20V
20V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
1mA
1mA
1mA
1mA
5mA
1mA
1mA
1mA
1mA
30mA
5mA
1mA
7
8
9
10
11
EAIN
PWMRMP
LGND
VCC
VCCL
20V
20V
n/a
24V
27V
-0.3V
-0.3V
n/a
-0.3V
-0.3V
1mA
1mA
50mA
n/a
n/a
1mA
20mA
n/a
50mA
3A for 100ns,
200mA DC
12
GATEL
27V
-0.3V DC, -2V for
100ns
3A for 100ns,
200mA DC
3A for 100ns,
200mA DC
13
PGND
0.3V
-0.3V
n/a
14
GATEH
27V
-0.3V DC, -2V for
100ns
3A for 100ns,
200mA DC
3A for 100ns,
200mA DC
15
VCCH
27V
-0.3V
n/a
16
17
CSIN+
CSIN-
20V
20V
-0.3V
-0.3V
1mA
1mA
3A for 100ns,
200mA DC
1mA
1mA
18
19
20
PHSFLT
DACIN
BIASIN
20V
20V
20V
-0.3V
-0.3V
-0.3V
1mA
1mA
1mA
20mA
1mA
1mA
Page 2 of 34
3A for 100ns,
200mA DC
9/30/04
IR3088
ELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over: 8.4V ≤ VCC ≤ 14V, 6V ≤ VCCH ≤ 25V, 6V ≤
VCCL ≤ 14V, 0 oC ≤ TJ ≤ 125 oC, CGATEH = 3.3nF, CGATEL = 6.8nF
PARAMETER
Gate Drivers
GATEH Rise Time
GATEH Fall Time
GATEL Rise Time
GATEL Fall Time
GATEL low to GATEH high
delay
GATEH low to GATEL high
delay
Disable Pull-Down Current
Current Sense Amplifier
CSIN+ Bias Current
CSIN- Bias Current
Input Offset Voltage
Gain at TJ = 25 oC
Gain at TJ = 125 oC
Slew Rate
Differential Input Range
Common Mode Input Range
Rout at TJ = 25 oC
Rout at TJ = 125 oC
Ramp Discharge Clamp
Clamp Voltage
Clamp Discharge Current
Page 3 of 34
TEST CONDITION
VCCH = 12V, Measure 2V to 9V
transition time
VCCH = 12V, Measure 9V to 2V
transition time
VCCL = 12V, Measure 2V to 9V
transition time
VCCL = 12V, Measure 9V to 2V
transition time
VCCH = VCCL = 12V, Measure the time
from GATEL falling to 1V to GATEH
rising to 1V
VCCH = VCCL = 12V, Measure the time
from GATEH falling to 1V to GATEL
rising to 1V
Force GATEH or GATEL = 2V with
BIASIN = 0V
CSIN+ = CSIN- = DACIN. Measure input
referred offset from DACIN
MIN
TYP
MAX
UNIT
22
50
ns
22
50
ns
50
75
ns
50
75
ns
10
25
50
ns
10
25
50
ns
15
25
40
µA
-0.5
-0.5
-3
-0.25
-0.25
0.5
0
0
5
µA
µA
mV
32
27
34
29
12.5
36
31
V/V
V/V
Current Sense Amplifier output is an
internal node. Slew rate at the ISHARE
pin will be set by the internal 10kΩ
resistor and any stray external
capacitance
Force I(PWMRMP) = 500µA. Measure
V(PWMRMP) – V(DACIN)
-20
0
7.9
9.3
V/µs
10.5
12.4
100
4
13.1
15.5
mV
V
kΩ
kΩ
-10
5
20
mV
4
8
mA
9/30/04
IR3088
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Ramp Comparator
Input Offset Voltage
20
40
80
Hysteresis
Note 1
-10
0
10
RMPIN+, RMPIN- Bias Current
-1
-0.5
1
Propagation Delay
VCCH = 12V. Measure time from RMPIN
100
150
240
input (50mV overdrive) to GATEL
transition to <11V.
PWM Comparator
PWM Comparator Input Offset
-5
5
15
Voltage
EAIN & PWMRMP Bias
Clamp and Current Share Adjust OFF
-1
-0.4
1
Current
Propagation Delay
VCCH = 12V. Measure time from
70
150
PWMRMP input (50mV overdrive) to
GATEH transition to < 11V.
Common Mode Input Range
Exceeding the Common Mode input
5
range results in 100% duty cycle
Share Adjust Error Amplifier
Input Offset Voltage
10
20
30
Input Voltage Range
EAIN – PWMRMP, Note 1
-3.5
3.5
PWMRMP Adjust Current
4
8
Transconductance
I(PWMRMP) = 3.5mA, Note 1
0.9
1.6
2.3
SCOMP Source/Sink Current
Note 1
20
30
40
SCOMP Activation Voltage
Amount SCOMP must increase from its
60
150
300
minimum voltage until the Ramp Slope
Adjust current equals = 10µA
PWMRMP Min Voltage
150
225
350
I(PWMRMP) = 500µA
0% Duty Cycle Comparator
Threshold Voltage
Compare to V(DACIN)
88
91
94
Propagation Delay
VCCL = 12V. Measure time from EAIN <
100
150
0.9 x V(DACIN) (200mV overdrive) to
GATEL transition to < 11V. Note 1.
Phase Fault Comparator
Threshold Voltage
Compare to V(DACIN)
88
91
94
Output Voltage
I(PHSFLT) = 4mA
300
400
PHSFLT Leakage Current
V(PHSFLT) = 5.5V
0
10
VRHOT Comparator
HOTSET Bias Current
-2
-0.5
1
Output Voltage
I(VRHOT) = 29mA
150
400
VRHOT Leakage Current
V(VRHOT) = 5.5V
0
10
o
Threshold Hysteresis
TJ ≥ 85 C
3.0
7.0
9.0
MIN
TYP
MAX
Threshold Voltage
TJ ≥ 85 oC
4.73mV/ oC x TJ + 4.73mV/ oC x TJ + 4.73mV/ oC x TJ +
1.176V
1.241V
1.356V
Page 4 of 34
9/30/04
UNIT
mV
mV
µA
ns
mV
µA
ns
V
mV
V
mA
A/V
µA
mV
mV
%
ns
%
mV
µA
µA
mV
µA
o
C
V
IR3088
PARAMETER
General
VCC Supply Current
VCCL Supply Current
VCCH Supply Current
TEST CONDITION
MIN
TYP
MAX
UNIT
-5
-2
10
2.5
5.5
6.5
-2.5
-0.5
14
5
8
10
2
1
mA
mA
mA
mA
µA
µA
6V ≤ VCCH ≤ 14V
14V ≤ VCCH ≤ 25V
BIASIN Bias Current
DACIN Bias Current
Note 1: Guaranteed by design, but not tested in production
PIN DESCRIPTION
PIN#
1
2
3
PIN SYMBOL
RMPIN+
RMPINHOTSET
4
VRHOT
5
ISHARE
6
SCOMP
7
EAIN
8
PWMRMP
9
10
11
12
13
14
15
16
17
18
LGND
VCC
VCCL
GATEL
PGND
GATEH
VCCH
CSIN+
CSINPHSFLT
19
DACIN
20
BIASIN
Page 5 of 34
PIN DESCRIPTION
Non-inverting input to Ramp Comparator
Inverting input to Ramp Comparator
Inverting input to VRHOT comparator. Connect resistor divider from VBIAS to LGND
to program VRHOT threshold. Diode or thermistor may be substituted for lower
resistor for enhanced/remote temperature sensing.
Open Collector output of the VRHOT comparator which drives low if IC junction
temperature exceeds the user programmable limit. Connect external pull-up.
Output of the Current Sense Amplifier and input to the Share Adjust Error Amplifier.
Voltage on this pin is equal to V(DACIN) + 34 * [V(CSIN+) – V(CSIN-)]. Connecting
ISHARE pins together creates a Share Bus enabling current sharing between Phase
ICs. The Share bus is also used by the Control IC for voltage positioning and OverCurrent protection.
Compensation for the Current Share control loop. Connect a capacitor to ground to se
the control loop’s bandwidth.
PWM comparator input from the error amplifier output of Control IC. Both Gate Driver
outputs drive low if the voltage on this pin is less than 91% of V(DACIN).
PWM comparator ramp input. Connect a resistor from this pin to the converter input
voltage and a capacitor to LGND to program the PWM ramp.
Signal ground and IC substrate connection
Power for internal circuitry
Power for Low-Side Gate Driver
Low-Side Gate Driver Output and input to GATEH non-overlap comparator
Return for Gate Drivers
High-Side Gate Driver Output and input to GATEL non-overlap comparator
Power for High-Side Gate Driver
Non-inverting input to the Current Sense Amplifier
Inverting input to the Current Sense
Open Collector output of the Phase Fault comparator. Drives low if Phase current is
unable to match the level of the SHARE bus due to an external fault. Connect externa
pull-up.
Reference voltage input from the Control IC. Current sensing and PWM operation
referenced to this pin.
System reference voltage for internal circuitry
9/30/04
IR3088
SYSTEM THEORY OF OPERATION
XPhaseTM Architecture
The XPhaseTM architecture is designed for multiphase interleaved buck converters which are used in applications
requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can
control converters of any phase number flexibility facilitates the design trade-off of multiphase converters. The
scalable architecture can be applied to other applications which require high current or multiple output voltages.
As shown in Figure 1, the XPhaseTM architecture consists of a Control IC and a scalable array of phase converters
each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e.
bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all
the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The
Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator
and latch, over-voltage protection, and current sensing and sharing.
There is no unused or redundant silicon with the XPhaseTM architecture compared to others such as a 4 phase
controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus
eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and
current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the
parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.
POWER GOOD
PHASE FAULT
VR HOT
12V
ENABLE
VID5
VID0
VID1
IR3081
CONTROL
IC
PHASE FAULT
CIN
>> BIAS VOLTAGE
VOUT SENSE+
>> PHASE TIMING
VID2
<< CURRENT SENSE
VID3
>> PWM CONTROL
VID4
>> VID VOLTAGE
CURRENT SHARE
IR3088
PHASE
IC
VOUT+
0.1uF
COUT
VOUT-
PHASE HOT
CCS
RCS
VOUT SENSE-
PHASE FAULT
CURRENT SHARE
IR3088
PHASE
IC
0.1uF
PHASE HOT
CCS
CONTROL BUS
RCS
ADDITIONAL PHASES
INPUT/OUTPUT
Figure 1. System Block Diagram
Page 6 of 34
9/30/04
IR3088
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 2. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes
in load current.
VIN
CONTROL IC
VPEAK
RAMPIN+
RMPOUT
RPHS1
VVALLEY
PWM
LATCH
CLOCK
PULSE
GENERATOR
RAMPIN-
-
EAIN
VBIAS
+
-
+
+
-
RVFB
X
0.91
+
ISHARE
FB
10K
CURRENT
SENSE
AMPLIFIER
20mV
IROSC
X34
RDRP
VDRP
AMP
CSIN+
+
IFB
VOSNS-
CSCOMP
-
SHARE
ADJUST
ERROR
AMPLIFIER
BODY
BRAKING
COMPARATOR
+
RAMP
DISCHARGE
CLAMP
SCOMP
+
ERROR
AMP
GND
-
CPWMRMP
EAOUT
GATEL
ENABLE
PWMRMP
VOSNSVDAC
VOUT
COUT
R
+
-
RPWMRMP
VOSNS+
RESET
DOMINANT
+
RPHS2
VDAC
VBIAS
REGULATOR
GATEH
S
PWM
COMPARATOR
-
RAMP GENERATOR
+
50%
DUTY
CYCLE
PHASE IC
SYSTEM
REFERENCE
VOLTAGE
BIASIN
CCS
RCS
CCS
RCS
CSIN-
DACIN
VDRP
+
-
IIN
RAMPIN+
PWM
LATCH
CLOCK
PULSE
GENERATOR
+
RPHS1
PHASE IC
SYSTEM
REFERENCE
VOLTAGE
BIASIN
-
RAMPIN-
GATEH
S
PWM
COMPARATOR
-
EAIN
RESET
DOMINANT
R
GATEL
+
RPHS2
ENABLE
PWMRMP
+
RPWMRMP
-
X
0.91
-
+
SHARE
ADJUST
ERROR
AMPLIFIER
+
ISHARE
10K
20mV
CURRENT
SENSE
AMPLIFIER
-
CSIN+
+
X34
-
CSCOMP
-
CPWMRMP
BODY
BRAKING
COMPARATOR
+
RAMP
DISCHARGE
CLAMP
SCOMP
CSIN-
DACIN
Figure 2. PWM Block Diagram
Frequency and Phase Timing Control
An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty
cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used
to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by
resistor divider RPHS1 and RPHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A
comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the
resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS
voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note
that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins,
as shown in Figure 2.
Page 7 of 34
9/30/04
IR3088
50% RAMP
DUTY CYCLE
RAMP (FROM
CONTROL IC)
SLOPE = 80mV / % DC
VPEAK (5.0V)
VPHASE4&5 (4.5V)
SLOPE = 1.6mV / ns @ 200kHz
SLOPE = 8.0mV / ns @ 1MHz
VPHASE3&6 (3.5V)
VPHASE2&7 (2.5V)
VPHASE1&8 (1.5V)
VVALLEY (1.00V)
CLK1
PHASE IC CLOCK PULSES
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
Figure 3. 8 Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP
voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the nonoverlap time. When the PWMRMP voltage exceeds the Error Amplifier’s output voltage, the PWM latch is reset.
This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the
Ramp Discharge Clamp, which quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC
until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode
input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required.
It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of
most systems. The inductor current will increase much more rapidly than decrease in response to load transients.
This control method is designed to provide “single cycle transient response” where the inductor current changes in
response to load transients within a single switching cycle maximizing the effectiveness of the power train and
minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in
ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.
Figure 4 depicts PWM operating waveforms under various conditions.
Page 8 of 34
9/30/04
IR3088
PHASE IC
CLOCK
PULSE
EAIN
PWMRMP
VDAC
91% VDAC
GATEH
GATEL
STEADY-STATE
OPERATION
DUTY CYCLE INCREASE
DUE TO LOAD
INCREASE
DUTY CYCLE DECREASE
DUE TO VIN INCREASE
(FEED-FORWARD)
DUTY CYCLE DECREASE DUE TO LOAD
DECREASE (BODY BRAKING) OR FAULT
(VCC UV, VCCVID UV, OCP, VID=11111X)
STEADY-STATE
OPERATION
Figure 4. PWM Operating Waveforms
Body BrakingTM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
TSLEW =
L * ( I MAX − I MIN )
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in
response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the
synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +
VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient
decrease is now;
TSLEW =
L * ( I MAX − I MIN )
VO + VBODYDIODE
Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished
through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amplifier’s output voltage drops below
91% of the VDAC voltage this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a resistor and a capacitor in parallel with the inductor and measuring
the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is,
vC ( s) = vL ( s)
1
RL + sL
= iL ( s)
1 + sRCS CCS
1 + sRCS CCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of
inductor DC current, but affects the AC component of the inductor current.
Page 9 of 34
9/30/04
IR3088
vL
iL
Current
Sense Amp
L
RL
RCS
CCS
VO
CO
vCc S
CSOUT
Figure 5. Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current
being delivered to the load is obtained rather than peak or sampled information about the switch currents. The
output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in
series with inductor, this is the only sense method that can support a single cycle transient response. Other
methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer
from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency
variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and
the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier
bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional
sources of peak-to-average errors.
Current Sense Amplifier
This is a high speed differential current sense amplifier, as shown in Figure 5. Its gain decreases with increasing
temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain tends to
compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is hotter than
the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is
required.
The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before
clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and
other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases
are tied together and the voltage on the share bus represents the average current being delivered to the load and is
used by the Control IC for voltage positioning and current limit protection.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC.
The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is
smaller than the average current, the share adjust error amplifier of the phase will activate a current source that
reduces the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of
the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not
interact with the output voltage loop.
Page 10 of 34
9/30/04
IR3088
IR3088 THEORY OF OPERATION
Block Diagram
The Block diagram of the IR3088 is shown in Figure 6, and specific features are discussed in the following sections.
PWM
LATCH
RAMP
COMPARATOR
S
PWM
COMPARATOR
-
EAIN
-
-
R
+
SYSTEM
REFERENCE
VOLTAGE
BIASIN
GATEH
RESET
DOMINANT
+
GATE
NON-OVERLAP
COMPARATORS
ENABLE
+
+
PWMRMP
-
RAMP
DISCHARGE
CLAMP
-
RAMP
SLOPE
ADJUST
2V
-
+
RMPIN-
VCCH
+
RMPIN+
CLOCK
PULSE
GENERATOR
VCCL
GATEL
+
SCOMP
-
X
0.91
-
+
SHARE
ADJUST
ERROR
AMP
ISHARE
PGND
INTERNAL
CIRCUIT
BIAS
VCC
+
+
X34
VRHOT
COMPARATOR
VOLTAGE
PROPORTIONAL
TO ABSOLUTE
TEMPERATURE
-
-
CSINPHSFLT
+
+
-
HOTSET
+
CSIN+
-
-
LGND
DACIN
CURRENT
SENSE
AMP
+
+
20mV
10K
VRHOT
0% DUTY
CYCLE
COMPARATOR
FAULT
COMPARATOR
Figure 6. IR3088 Block Diagram
Tri-State Gate Drivers
The gate drivers can deliver up to 3A peak current. An adaptive non-overlap circuit monitors the voltage on the
GATEH and GATEL pins to prevent MOSFET shoot-through current while minimizing body diode conduction.
An Enable signal is provided by the Control IC to the Phase IC without the addition of a dedicated signal line. The
Error Amplifier output of the Control IC drives low in response to any fault condition such as input under voltage or
output overload. The IR3088 0% duty cycle comparator detects this and drives both gate outputs low. This tri-state
operation prevents negative inductor current and negative output voltage during power-down.
The Gate Drivers revert to a high impedance “off” state if VCCL and VCCH supply voltages are below the normal
operating range. An 80kΩ resistor is connected across the GATEH/GATEL and PGND pins to prevent the
GATEH/GATEL voltage from rising due to leakage or other causes under these conditions.
Thermal Monitoring (VRHOT)
The IR3088 senses its own die temperature and produces a voltage at the input of the VRHOT comparator that is
proportional to temperature. An external resistor divider connected from VBIAS to the HOTSET pin and ground can
be used to program the thermal trip point of the VRHOT comparator. The VRHOT pin is an open-collector output
and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT output
drives low.
Page 11 of 34
9/30/04
IR3088
Phase Fault
It is possible for multiphase converters to appear to be working correctly with one or more phases not functioning.
The output voltage can still be regulated and the full load current may still be delivered. However, the remaining
phase(s) will be stressed far beyond their intended design limits and are likely to fail. Loss of a phase can occur due
to poor solder connections or mounting during the manufacturing process, or can occur in the field. The most
common failure mode of a buck converter is failure of the high side MOSFET. The IR3088 has the ability to detect if
a phase stops switching and can provide this information to the system through the PHSFLT output pin. If a phase
stops switching its output current will drop to zero and the output of its IR3088 current sense amplifier will be the
DACIN voltage. The Share Adjust Amplifier reacts to this by increasing the Ramp Slope Adjust current until it
exceeds the externally programmable PWM Ramp bias current. This will cause the voltage at the PWMRMP pin to
drop below its normal operating range. The Fault Comparator trips and drives the PHSFLT output to ground when
the voltage on the PWMRMP pin falls below 91% of the DACIN voltage. PHSFLT is an open-collector output and
should be pulled up to a voltage source through a resistor.
APPLICATIONS INFORMATION
POWERGOOD
VRHOT
PHASE FAULT
12V
RCSRVCC
10 ohm
RCP
CSIN+
18
19
16
20
17
CSIN-
DACIN
BIASIN
DBST
PGND
GATEL
VCCL
CIN
VOUT SENSE+
15
14
13
VOUT+
12
DISTRIBUTION
IMPEDANCE
11
COUT
VCC
VOUT10
LGND
SCOMP
6
CSCOMP
GATEH
CVCCL
RVCC
VOUT SENSE-
RPWMRMP
CVCC
CCP
RCS-
17
CCP1
CSIN+
16
18
19
17
CSIN-
DACIN
20
DBST
ISHARE
SCOMP
6
CSCOMP
PGND
GATEL
VCCL
CIN
15
14
13
12
11
VCC
VRHOT
GATEH
10
HOTSET
RPHASE22
RPHASE23
PHSFLT
BIASIN
4
LGND
RSHARE
5
CVDAC
RCS+
CBST
VCCH
IR3088
PHASE
IC
RMPIN-
PWMRMP
3
RVDAC
RMPIN+
EAIN
2
9
1
CCS+
CCS-
RBIASIN
7
VDAC
15
CPWMRMP 8
16
ROCSET
ROSC
ISHARE
RPHASE21
RPHASE31
19
14
ROSC
OCSET
TRM4
VID4
21
20
18
VRHOT
RPHASE21
25
23
LGND
RMPOUT
24
26
27
N/C
SS/DEL
PWRGD
22
FB
VDRP
IIN
8
RFB
VCC
EAOUT
VID3
13
7
VID2
12
VID4
ENABLE
28
6
VID1
TRM3
VID3
IR3081
CONTROL
IC
VID0
VOSNS-
5
TRM2
4
VID2
BBFB
TRM1
3
VID1
VBIAS
VID5
9
VID0
OSCDS
11
2
10
1
VID5
RFB1
HOTSET
PWMRMP
5
CFB
0.1uF
RCS+
CBST
VCCH
IR3088
PHASE
IC
RMPIN-
EAIN
4
1nF
ENABLE
RMPIN+
9
CSS/DEL
3
7
2
CPWMRMP 8
1
PHSFLT
RPHASE11
RSS/DEL
RFB22
CCS+
CCS-
RBIASIN
RFB21
CVCC
0.1uF
CVCCL
RVCC
RPWMRMP
CVCC
RCS-
RPHASE33
CSIN+
16
19
18
20
17
CSIN-
DACIN
BIASIN
DBST
GATEH
PGND
GATEL
CIN
15
14
13
12
11
VCC
VCCL
10
SCOMP
6
CSCOMP
EAIN
ISHARE
LGND
VRHOT
PWMRMP
HOTSET
RPHASE32
5
9
4
RCS+
CBST
VCCH
IR3088
PHASE
IC
RMPIN-
7
3
RMPIN+
CPWMRMP 8
2
PHSFLT
RPHASE31
1
CCS+
CCS-
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
Figure 7. IR3081/3088 12V to 2.5V 3 Phase Converter
Page 12 of 34
9/30/04
IR3088
POWERGOOD
VRHOT
PHASE FAULT
12V
RCS-
VGATE
RVCC
10 ohm
QGATE
CCS+
CCS-
19
RCP
18
16
CSIN+
19
17
CSIN-
20
18
DACIN
PHSFLT
CIN
PGND
GATEL
VOUT SENSE+
15
14
L
13
VOUT+
12
DISTRIBUTION
IMPEDANCE
11
COUT
VCC
VOUT10
LGND
VCCL
9
SCOMP
CSCOMP
GATEH
CVCCL
RVCC
VOUT SENSE-
RPWMRMP
CVCC
CCP
RCS-
17
CCS+
CCP1
16
CSIN+
17
CSIN-
19
CIN
GATEH
PGND
GATEL
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
DBST
CBST
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE23
CVDAC
HOTSET
RCS+
RCS+
VCCH
IR3088
PHASE
IC
RMPIN-
RPHASE22
5
18
20
4
DACIN
BIASIN
3
RSHARE
RMPIN+
PWMRMP
2
EAIN
1
PHSFLT
RDRP
RVDAC
CCS-
20k
7
RBIASIN
VDAC
15
CPWMRMP 8
RDRP1 CDRP
16
ROCSET
ROSC
ISHARE
6
RPHASE13
RBBDRP
14
ROSC
13
8
OCSET
21
20
VRHOT
RPHASE21
23
LGND
25
26
27
24
RMPOUT
SS/DEL
N/C
PWRGD
22
FB
VDRP
IIN
VID4
RFB
VCC
EAOUT
VID3
TRM4
VID4
7
VID2
12
6
BBFB
VID1
TRM3
VID3
VBIAS
IR3081
CONTROL
IC
VID0
RBBFB
RFB1
VID5
VOSNS-
5
TRM2
4
VID2
TRM1
3
VID1
9
VID0
OSCDS
11
2
10
1
ENABLE
28
0.1uF
HOTSET
RPHASE12
5
ENABLE
VID5
BIASIN
4
CFB
CBST
VCCH
IR3088
PHASE
IC
RMPIN-
PWMRMP
3
RMPIN+
EAIN
CSS/DEL
2
1nF
DBST
7
1
RCS+
20k
CPWMRMP 8
RBIASIN
DGATE
RPHASE11
RGATE
RSS/DEL
CVCC
0.1uF
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
CCSRBIASIN
RCS+
20k
16
CSIN+
17
CSIN-
19
18
PGND
GATEL
CIN
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
GATEH
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE33
DACIN
BIASIN
HOTSET
RPHASE32
5
PWMRMP
4
VCCH
IR3088
PHASE
IC
RMPIN-
EAIN
3
RMPIN+
7
2
CPWMRMP 8
1
PHSFLT
RPHASE31
20
DBST
CBST
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
CCS-
16
CSIN+
17
18
19
PGND
GATEL
CIN
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
GATEH
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE43
CSIN-
BIASIN
HOTSET
RPHASE42
5
CBST
VCCH
IR3088
PHASE
IC
RMPIN-
PWMRMP
4
RMPIN+
EAIN
3
7
2
DACIN
20
DBST
PHSFLT
RPHASE41
1
RCS+
20k
CPWMRMP 8
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
CCS-
16
CSIN+
17
18
19
CIN
PGND
GATEL
15
14
L
13
12
11
VCC
10
SCOMP
CSCOMP
GATEH
VCCL
LGND
ISHARE
9
VRHOT
6
RPHASE53
CSIN-
BIASIN
HOTSET
RPHASE52
5
PWMRMP
4
CBST
VCCH
IR3088
PHASE
IC
RMPIN-
EAIN
3
RMPIN+
7
2
DACIN
20
DBST
PHSFLT
RPHASE51
1
RCS+
20k
CPWMRMP 8
RBIASIN
CVCCL
RVCC
RPWMRMP
CVCC
RCSCCS+
RBIASIN
CCS-
20k
RCS+
RPHASE63
16
CSIN+
17
CSIN-
19
18
DACIN
BIASIN
PGND
GATEL
VCCL
15
14
L
13
12
11
VCC
SCOMP
6
CSCOMP
GATEH
10
ISHARE
LGND
VRHOT
9
HOTSET
RPHASE62
5
PWMRMP
4
CIN
VCCH
IR3088
PHASE
IC
RMPIN-
EAIN
3
RMPIN+
7
2
CPWMRMP 8
1
PHSFLT
RPHASE61
20
DBST
CBST
CVCCL
RVCC
RPWMRMP
CVCC
Figure 8. IR3081/3088 Six Phase VRM/EVRD 10 Converter
Page 13 of 34
9/30/04
IR3088
DESIGN PROCEDURES - IR3081 AND IR3088 CHIPSET
IR3081 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR3081 generates a triangle waveform to synchronize the phase ICs, and the switching frequency
of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC according to
the curve in Figure 13 of IR3081 Data Sheet.
Soft Start Capacitor CSS/DEL and Resistor RSS/DEL
Because the capacitor CSS/DEL programs four different time parameters, i.e. soft start delay time, soft start time,
over-current latch delay time, and power good delay time, they should be considered together while choosing
CSS/DEL.
The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10 of IR3081
Data Sheet. After the ENABLE pin voltage rises above 0.6V, there is a soft-start delay time tSSDEL, after which the
error amplifier output is released to allow the soft start. The soft start time tSS represents the time during which
converter voltage rises from zero to VO. tSS can be programmed by an external capacitor, which is determined by
Equation (1).
I
*t
70 * 10 −6 * t SS
(1)
C SS / DEL = CHG SS =
VO
VO
Once CSS/DEL is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the
delay time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in Equations (2), (3)
and (4) respectively.
*1.3 CSS / DEL *1.3
C
(2)
=
tSSDEL = SS / DEL
I CHG
70 *10− 6
t OCDEL =
tVccPG =
C SS / DEL * 0.09 C SS / DEL * 0.09
=
I DISCHG
6 *10 −6
CSS / DEL * (3.91 − VO − 1.3) CSS / DEL * (3.91 − VO − 1.3)
=
I CHG
70 *10−6
(3)
(4)
If faster over-current protection is required, a resistor in series with the soft start capacitor CSS/DEL can be used to
reduce the over-current fault latch delay time tOCDEL, and the resistor RSS/DEL is determined by Equation (5).
Equation (1) for soft start capacitor CSS/DEL and Equation (4) for power good delay time tVccPG are unchanged,
while the equation for soft start delay time tSS/DEL (Equation 2) is changed to Equation (6). Considering the worst
case values of charge and discharge current, RSS/DEL should be no grater than 10kΩ.
0.09 −
RSS / DEL =
tSSDEL =
tOCDEL * I DISCHG
t
∗ 6 *10−6
0.09 − OCDEL
CSS / DEL
CSS / DEL
=
I DISCHG
6 *10−6
(5)
CSS / DEL * (1.3 − RSS / DEL ∗ I CHG ) CSS / DEL * (1.3 − RSS / DEL * 70 *10−6 )
(6)
=
I CHG
70 *10−6
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in
Equation (7), where ISINK is the sink current of VDAC pin as shown in Figure 15 of IR3081 Data Sheet. The resistor
RVDAC is used to compensate VDAC circuit and is determined by Equation (8). The slew rate of VDAC up-slope
Page 14 of 34
9/30/04
IR3088
SRUP is proportional to that of VDAC down-slope and is given by Equation (9), where ISOURCE is the source current
of VDAC pin as shown in Figure15 of IR3081 Data Sheet.
CVDAC =
I SINK
SR DOWN
RVDAC = 0.5 +
SRUP =
3.2 ∗ 10 −15
CVDAC 2
I SOURCE
CVDAC
(7)
(8)
(9)
Over Current Setting Resistor ROCSET
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from Equation
(10), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature
T_ROOM respectively.
R L _ MAX = R L _ ROOM ∗ [1 + 3850 * 10 −6 ∗ (T L _ MAX − TROOM )]
(10)
The current sense amplifier gain of IR3088 decreases with temperature at the rate of 1470 ppm/°C, which
compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius
higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense
amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (11).
GCS _ MIN = GCS _ ROOM ∗ [1 − 1470 * 10 −6 ∗ (TIC _ MAX − TROOM )]
(11)
The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset
(VCS_OFST) of the amplifier itself and that created by the amplifier input bias currents flowing through the current
sense resistors RCS+ and RCS-.
VCS _ TOFST = VCS _ OFST + I CSIN + ∗ RCS + − I CSIN − ∗ RCS −
(12)
The over current limit is set by the external resistor ROCSET as defined in Equation (13), where ILIMIT is the required
over current limit. IOCSET, the bias current of OCSET pin, changes with switching frequency setting resistor ROSC
and is determined by the curve in Figure 14 of IR3081 Data Sheet. KP is the ratio of inductor peak current over
average current in each phase and is calculated from Equation (14).
ROCSET = [
KP =
I LIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS _ MIN / I OCSET
n
(VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2)
IO / n
(13)
(14)
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP
A resistor between FB pin and the converter output is used to create output voltage offset VO_NLOFST, which is the
difference between VDAC voltage and output voltage at no load condition. Adaptive voltage positioning further
lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter.
RFB is not only determined by IFB, the current flowing out of FB pin as shown in Figure 14 of IR3081 Data Sheet, but
also affected by the adaptive voltage positioning resistor RDRP and total input offset voltage of current sense
amplifiers. RFB and RDRP are determined by (15) and (16) respectively.
Page 15 of 34
9/30/04
IR3088
R FB =
R L _ MAX ∗ VO _ NLOFST − VCS _ TOFST ∗ n ∗ RO
R DRP =
I FB ∗ R L _ MAX
R FB ∗ R L _ MAX ∗ GCS _ MIN
(15)
(16)
n ∗ RO
Body BrakingTM Related Resistors RBBFB and RBBDRP
The body brakingTM during Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is
enabled, Resistors RBBFB and RBBDRP are needed to restore the feedback voltage of the error amplifier after
Dynamic VID step down. Usually RBBFB and RBBDRP are chosen to match RFB and RDRP respectively.
IR3088 EXTERNAL COMPONENTS
PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP
PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well
as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VRAMP and
the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from Equation
(17). To achieve feed-forward voltage mode control, the resistor RRAMP should be connected to the input of the
converter.
RPWMRMP =
VIN * f SW * CPWMRMP * [ln(VIN
VO
− VDAC ) − ln(VIN − VDAC − VPWMRMP )]
(17)
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSThe DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor
CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage
across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC
component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch
does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well
as the output voltage during the load current transient if adaptive voltage positioning is adopted.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS+ and calculate RCS+ as
follows.
RCS + =
L RL
C CS +
(18)
The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across
RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of
converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage
positioning is adopted. To reduce the offset voltage, a resistor RCS- should be added between the amplifier inverting
input and the converter output.
RCS − = RCS +
(19)
If RCS- is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less
than 2 kΩ and therefore a larger CCS+ value is needed.
Page 16 of 34
9/30/04
IR3088
Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC. Determine
the relationship between the die temperature of phase IC and the temperature of the power converter according to
the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the
allowed maximum temperature from Equation (20).
V HOTSET = 4.73 * 10 −3 * T J + 1.241
(20)
There are two ways to set the over temperature threshold, central setting and local setting. In the central setting,
only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To
reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next
to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage
is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the
reference voltage. If RHOTSET1 is pre-selected, RHOTSET2 can be calculated as follows.
RHOTSET 2 =
RHOTSET 1 ∗ VHOTSET
VBIAS − VHOTSET
(21)
Phase Delay Timing Resistors RPHASE1 and RPHASE2
The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at
RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of
phase IC, as shown in Figure 3.
If the upslope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and
RMPIN- pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at
RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.
If down slope is used, RMPIN- pin of the phase IC should be connected to RMPOUT pin of the control IC and
RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at
RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.
Use VBIAS voltage as the reference for the resistor divider since the oscillator ramp magnitude from control IC
tracks VBIAS voltage. Try to avoid both edges of the oscillator ramp for better noise immunity. Determine the ratio
of the programming resistors corresponding to the desired switching frequencies and phase numbers. If the resistor
RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as:
R PHASEx 2 =
RAPHASEx ∗ R PHASEx1
1 − RAPHASEx
(22)
Combined Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3
The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one
resistor per phase.
Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from
Equation (20). If the over temperature setting voltage is lower than the phase delay setting voltage,
VBIAS*RAPHASEx, connect RMPIN+ or RMPIN- pin between RPHASEx1 and RPHASEx2, and connect HOTSET pin
between RPHASEx2 and RPHASEx3. Pre-select RPHASEx1,
Page 17 of 34
RPHASEx 2 =
( RAPHASEx ∗ VBIAS − VHOTSET ) * RPHASEx1
VBIAS ∗ (1 − RAPHASEx )
(23)
RPHASEx3 =
VHOTSET ∗ RPHASEx1
VBIAS * (1 − RAPHASEx )
(24)
9/30/04
IR3088
If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect
HOTSET pin between RPHASEx1 and RPHASEx2, and connect RMPIN+ or RMPIN- between RPHASEx2 and RPHASEx3.
Pre-select RPHASEx1,
R PHASEx 2 =
(V HOTSET − RAPHASEx ∗ V BIAS ) ∗ R PHASEx1
V BIAS − V HOTSET
(25)
RPHASEx3 =
RAPHASEx ∗ VBIAS * RPHASEx1
VBIAS − VHOTSET
(26)
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the
bootstrap circuit.
Decoupling Capacitors for Phase IC
0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.
VOLTAGE LOOP COMPENSATION
The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient
response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop
introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage
loop compensation much easier.
Resistors RFB and RDRP are chosen according to Equations (15) and (16), and the selection of compensation types
depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or ALPolymer capacitors and running at lower frequency, type II compensation shown in Figure 9(a) is usually enough.
While for the applications using only ceramic capacitors and running at higher frequency, type III compensation
shown in Figure 9(b) is preferred.
For applications where AVP is not required, the compensation is the same as for the regular voltage mode control.
For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency,
type III compensation is required as shown in Figure 9(b) with RDRP and CDRP removed.
CCP1
CCP1
RFB
VO+
RCP
VO+
RFB
FB
CCP
RDRP
VDAC
CFB
FB
-
EAOUT
EAOUT
VDRP
RFB1
CCP
RCP
+
(a) Type II compensation
EAOUT
VDRP
RDRP
VDAC
EAOUT
+
CDRP
(b) Type III compensation
Figure 9. Voltage loop compensation network
Type II Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10
and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the
output inductors matches that of the inductor, and determine RCP and CCP from Equations (27) and (28), where LE
and CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors
respectively.
Page 18 of 34
9/30/04
IR3088
(2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VPWMRMP
RCP =
VO * 1 + (2π * fC * C * RC ) 2
10 ∗ L E ∗ C E
C CP =
(27)
(28)
RCP
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A
ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for AVP Applications
Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and
capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the
voltage loop can be estimated by Equations (29) and (30), where RLE is the equivalent resistance of inductor DCR.
f C1 =
RDRP
2π * CE ∗ GCS * RFB ∗ RLE
θ C1 = 90 − A tan(0.5) ∗
(29)
180
(30)
π
Choose the desired crossover frequency fc around fc1 estimated by Equation (29) or choose fc between 1/10 and
1/5 of the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB
/Dec around the crossover frequency. Choose resistor RFB1 according to Equation (31), and determine CFB and
RDRP from Equations (32) and (33).
1
R FB
2
R FB1 =
CFB =
to
R FB1 =
2
R FB
3
1
4π ∗ fC ∗ RFB1
C DRP =
( R FB + R FB1 ) ∗ C FB
R DRP
(31)
(32)
(33)
RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency
and transient load response. Determine RCP and CCP from Equations (34) and (35).
RCP =
C CP =
(2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VPWMRMP
VO
10 ∗ L E ∗ C E
RCP
(34)
(35)
CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A
ceramic capacitor between 10pF and 220pF is usually enough.
Type III Compensation for Non-AVP Applications
Resistor RFB is chosen according to Equations (15), and resistor RDRP and capacitor CDRP are not needed. Choose
the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase
margin θc. Calculate K factor from Equation (36), and determine the component values based on Equations (37) to
(41),
π θ
(36)
K = tan[ ∗ ( C + 1.5)]
4 180
Page 19 of 34
9/30/04
IR3088
RCP = RFB ∗
( 2π ∗ LE ∗ CE ∗ fC ) 2 ∗ VPWMRMP
VO ∗ K
(37)
CCP =
K
2π ∗ fC ∗ RCP
(38)
CCP1 =
1
2π ∗ fC ∗ K ∗ RCP
(39)
CFB =
K
2π ∗ fC ∗ RFB
(40)
R FB1 =
1
2π ∗ f C ∗ K ∗ C FB
(41)
CURRENT SHARE LOOP COMPENSATION
The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop
in order to eliminate the interaction between the two loops. A capacitor from SCOMP to ground is usually enough
for the share loop compensation. Choose the crossover frequency of current share loop (fCI) based on the
crossover frequency of voltage loop (fC), and determine the CSCOMP,
CSCOMP =
0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI
VO ∗ 2π ∗ fCI *1.05 *106
(42)
Where FMI is the PWM gain in the current share loop,
FMI =
Page 20 of 34
RPWMRMP * CPWMRMP * f SW *V PWMRMP
(VI − VPWMRMP − VDAC ) * (VI − VDAC )
(43)
9/30/04
IR3088
DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.35 V
No Load Output Voltage Offset: VO_NLOFST=20 mV
Output Current: IO=105 ADC
Maximum Output Current: IOMAX=120 ADC
Output Impedance: RO=0.91 mΩ
VCC Ready to VCC Power Good Delay: tVccPG=0-10mS
Soft Start Time: tSS=2 mS
Over Current Delay: tOCDEL=0.5mS
Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Over Temperature Threshold: TPCB=115 ºC
POWER STAGE
Phase Number: n=6
Switching Frequency: fSW=400 kHz
Output Inductors: L=220 nH, RL=0.47 mΩ
Output Capacitors: AL-Polymer, C=560uF, RC= 7mΩ, Number Cn=10
IR3081 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13 of IR3081 Data
Sheet. For switching frequency of 400kHz per phase, choose ROSC=30.1kΩ
Soft Start Capacitor CSS/DEL and Resistor RSS/DEL
Because faster over-current protection is required, the soft start capacitor CSS/DEL in series with the resistor
RSS/DEL is used. Calculate the soft start capacitor from the required soft start time.
C SS / DEL =
I CHG ∗ t SS 70 * 10 −6 ∗ 2 * 10 −3
=
= 0.1uF
VO
1.35 − 20 * 10 −3
Calculate the soft start resistor from the required over current delay time tOCDEL,
0.09 −
RSS / DEL =
tOCDEL ∗ I DISCHG
0.5 *10−3 ∗ 6 *10−6
0.09 −
CSS / DEL
0.1 *10− 6
= 10kΩ
=
I DISCHG
6 *10− 6
The soft start delay time is
tSSDEL =
CSS / DEL ∗ (1.3 − RSS / DEL ∗ ICHG ) 0.1 *10−6 ∗ (1.3 − 10 *103 * 70 *10−6 )
=
= 0.86mS
I CHG
70 *10− 6
The power good delay time is
tVccPG =
CSS / DEL * (3.91 − VO − 1.3) 0.1*10−6 * (3.91 − 1.33 − 1.3)
=
= 1.8ms
I CHG
70 *10− 6
Page 21 of 34
9/30/04
IR3088
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
From Figure 15 of IR3081 Data Sheet, the sink current of VDAC pin corresponding to 400kHz (ROSC=30.1kΩ) is
76uA. Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
CVDAC =
I SINK
76 * 10 −6
=
= 30.4nF , Choose CVDAC=33nF
SR DOWN
2.5 * 10 −3 / 10 −6
Calculate the programming resistor.
RVDAC = 0.5 +
3.2 * 10 −15
CVDAC 2
= 0.5 +
3.2 * 10 −15
(33 * 10 −9 ) 2
= 3.5Ω
From Figure 15 of IR3081 Data Sheet, the source current of VDAC pin is 110uA. The VDAC up-slope slew rate is
SRUP =
I SOURCE 110 * 10 −6
=
= 3.3mV / uS
CVDAC
33 * 10 −9
Over Current Setting Resistor ROCSET
The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1
ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.
Calculate Inductor DC resistance at 100 ºC,
RL _ MAX = RL _ ROOM ∗ [1 + 3850*10−6 ∗ (TL _ MAX − TROOM )] = 0.47 *10−3 ∗ [1 + 3850*10−6 ∗ (100 − 25)] = 0.61mΩ
The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,
G CS _ MIN = G CS _ ROOM ∗ [1 − 1470 *10 −6 ∗ (T IC _ MAX − T ROOM )] = 34 ∗ [1 − 1470 *10 −6 ∗ (101 − 25)] = 30.2
Set the over current limit at 135A. From Figure 14 of IR3081 Data Sheet, the bias current of OCSET pin (IOCSET) is
41uA with ROSC=30.1kΩ. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset
created by the current sense amplifier input resistor mismatch.
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
KP =
(V I − VO ) ∗ VO /( L ∗ V I ∗ f SW ∗ 2) (12 − 1.33) ∗ 1.33 /( 220 *10 −9 ∗ 12 ∗ 400 * 10 3 ∗ 2)
=
= 0.3
135 / 6
I LIMIT / n
ROCSET = [
=(
RLIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS _ MIN / I OCSET
n
135
∗ 0.61 *10 −3 ∗ 1.3 + 0.55 *10 − 3 ) ∗ 30.2 /( 41 *10 − 6 ) = 13.3kΩ
6
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP
From Figure 14 of IR3081 Data, the bias current of FB pin is 41uA with ROSC=30.1kΩ.
R FB =
RDRP =
R L _ MAX ∗ V O _ NLOFST − V CS _ TOFST ∗ n ∗ R O
I FB ∗ R L _ MAX
RFB ∗ RL _ MAX ∗ GCS _ MIN
n ∗ RO
Page 22 of 34
=
=
0 .61 * 10 −3 ∗ 20 * 10 −3 − 0 .55 * 10 −3 ∗ 6 ∗ 0 .91 * 10 −3
41 * 10 − 6 ∗ 0 .61 * 10 − 3
= 365 Ω
365 ∗ 0.61*10−3 ∗ 30.2
= 1.21kΩ
6 ∗ 0.91*10−3
9/30/04
IR3088
Body Braking Related Resistors RBBFB and RBBDRP
N/A. The body braking during Dynamic VID is disabled.
IR3088 EXTERNAL COMPONENTS
PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP
Set PWM ramp magnitude VPWMRMP=0.8V. Choose 220pF for PWM ramp capacitor CPWMRMP, and calculate the
resistor RPWMRMP,
VO
RPWMRMP =
VIN ∗ f SW ∗ CPWMRMP ∗ [ln(VIN − VDAC ) − ln(VIN − VDAC − VPWMRMP )]
=
1.33
12 ∗ 400 *10 3 ∗ 220 *10 −12 ∗ [ln(12 − 1.35) − ln(12 − 1.35 − 0.8)]
= 16.1kΩ , choose RPWMRMP=16.2kΩ
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSChoose CCS+=47nF and calculate RCS+,
RCS + =
L RL 220 *10−9 /(0.47 *10−3 )
=
= 10.0kΩ
CCS +
47 *10−9
The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,
RCS − = RCS + = 10.0kΩ
Over Temperature Setting Resistors RHOTSET1 and RHOTSET2
Use central over-temperature setting and set the temperature threshold at 115 ºC, which corresponds to the IC die
temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 −3 * TJ + 1.241 = 4.73 * 10 −3 ∗ 116 + 1.241 = 1.79V
Pre-select RHOTSET1=10.0kΩ,
R HOTSET 2 =
R HOTSET 1 ∗ V HOTSET 10 *10 3 ∗1.79
= 3.57 kΩ
=
6.8 − 1.79
V BIAS − V HOTSET
Phase Delay Timing Resistors RPHASE1 and RPHASE2
Use central over-temperature setting and set the temperature threshold at 115 ºC, which corresponds to the IC die
temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.
The phase delay resistor ratios for phases 1 to 6 at 400kHz of switching frequencies are RAPHASE1=0.628,
RAPHASE2=0.415, RAPHASE3=0.202, RAPHASE4=0.246, RAPHASE5=0.441 and RAPHASE6=0.637 starting from downslope. Pre-select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51= RPHASE61=10kΩ,
RPHASE12 =
RAPHASE1
0.628
∗ RPHASE11 =
∗ 10 *103 = 16.9kΩ
1 − RAPHASE1
1 − 0.628
RPHASE22=7.15kΩ, RPHASE32=2.55kΩ, RPHASE42=3.24kΩ, PPHASE52=7.87kΩ, RPHASE62=17.4kΩ
Page 23 of 34
9/30/04
IR3088
Bootstrap Capacitor CBST
Choose CBST=0.1uF
Decoupling Capacitors for Phase IC and Power Stage
Choose CVCC=0.1uF, CVCCL=0.1uF
VOLTAGE LOOP COMPENSATION
Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the crossover frequency
fc=40kHz, which is 1/10 of the switching frequency per phase, and determine Rcp and CCP.
RCP =
CCP =
(2π ∗ fC )2 ∗ LE ∗ CE ∗ RFB ∗ VRAMP
VO * 1 + (2π * fC * C * RC )2
10 ∗ LE ∗ CE
RCP
=
=
(2π ∗ 40 ∗103 )2 ∗ (220 ∗10−9 / 6) ∗ (560 ∗10−6 ∗10) ∗ 365 ∗ 0.8
(1.35 − 20 ∗10−3 ) * 1 + (2π * 40 *103 * 560 *10−6 * 7 *10−3 )2
10 ∗ (220 ∗ 10−9 / 6) ∗ (560 ∗ 10−6 *10)
2.0 ∗103
= 2.0kΩ
= 71nF , Choose CCP=68nF
Choose CCP1=47pF to reduce high frequency noise.
CURRENT SHARE LOOP COMPENSATION
The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage
loop fC. Choose the crossover frequency of current share loop fCI=4kHz, and calculate CSCOMP,
FMI =
RPWMRMP * CPWMRMP * f SW *V PWMRMP 16.2 *103 * 220 *10−12 * 400 *103 * 0.8
=
= 0.011
(VI − VPWMRMP − VDAC ) * (VI − VDAC )
(12 − 0.8 − 1.35) * (12 − 1.35)
CSCOMP =
=
0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI
VO ∗ 2π ∗ fCI *1.05 *106
0.65 *16.2 *10 3 *12 *105 * 34 * (0.47 *10 −3 6) * [1 + 2π * 4 *10 3 * 560 *10 −6 *10 * (1.33 − 105 * 9.1*10 −4 ) 105] * 0.011
(1.33 − 105 * 9.1*10 − 4 ) ∗ 2π ∗ 4 *10 3 *1.05 *10 6
= 31.4nF
Choose CSCOMP=33nF.
Page 24 of 34
9/30/04
IR3088
DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER
SPECIFICATIONS
Input Voltage: VI=12 V
DAC Voltage: VDAC=1.3 V
No Load Output Voltage Offset: VO_NLOFST=20 mV
Output Current: IO=105 ADC
Maximum Output Current: IOMAX=120 ADC
Output Impedance: RO=0.91 mΩ
VCC Ready to VCC Power Good Delay: tVccPG=0-10mS
Soft Start Time: tSS=2.9mS
Over Current Delay: tOCDEL=2.1mS
Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS
Over Temperature Threshold: TPCB=115 ºC
POWER STAGE
Phase Number: n=6
Switching Frequency: fSW=800 kHz
Output Inductors: L=100 nH, RL=0.5 mΩ
Output Capacitors: Ceramic, C=22uF, RC= 2mΩ, Number Cn=62
IR3081 EXTERNAL COMPONENTS
Oscillator Resistor Rosc
Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13 of IR3081 Data
Sheet. For switching frequency of 800kHz per phase, choose ROSC=13.3kΩ
Soft Start Capacitor CSS/DEL and Resistor RSS/DEL
Because faster over-current protection is required, the soft start capacitor CSS/DEL in series with the resistor
RSS/DEL is used. Calculate the soft start capacitor from the required soft start time.
CSS / DEL =
I CHG ∗ tSS 70 *10−6 ∗ 2.9 *10−3
=
= 0.16uF , choose CSS/DEL=0.15uF
VO
1.3 − 20 *10−3
Calculate the soft start resistor from the required over current delay time tOCDEL,
0.09 −
RSS / DEL =
tOCDEL ∗ I DISCHG
2.1 *10−3 ∗ 6 *10−6
0.09 −
CSS / DEL
0.15 *10− 6
=
= 1kΩ
I DISCHG
6 *10− 6
The soft start delay time is
t SSDEL =
C SS / DEL ∗ (1.3 − R SS / DEL ∗ I CHG ) 0.15 * 10 −6 ∗ (1.3 − 1 * 10 3 * 70 * 10 −6 )
=
= 2.6mS
I CHG
70 * 10 −6
The power good delay time is
tVccPG =
C SS / DEL ∗ (3.91 − VO − 1.3) 0.15 * 10 −6 * (3.91 − 1.28 − 1.3)
=
= 2.85ms
I CHG
70 * 10 −6
Page 25 of 34
9/30/04
IR3088
VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC
From Figure 15 of IR3081 Data Sheet, the sink current of VDAC pin corresponding to 800kHz (ROSC=13.3kΩ) is
170uA. Calculate the VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.
CVDAC =
I SINK
170 * 10 −6
=
= 68nF
SR DOWN
2.5 * 10 −3 / 10 −6
Calculate the programming resistor.
RVDAC = 0.5 +
3.2 * 10 −15
CVDAC 2
= 0.5 +
3.2 * 10 −15
(68 * 10 −9 ) 2
= 1.2Ω
From Figure 15 of IR3081 Data Sheet, the source current of VDAC pin is 250uA. The VDAC up-slope slew rate is
SRUP =
I SOURCE 250 *10 −6
=
= 3.7 mV / uS
CVDAC
68 *10 −9
Over Current Setting Resistor ROCSET
The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1
ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.
Calculate Inductor DC resistance at 100 ºC,
RL _ MAX = RL _ ROOM ∗ [1 + 3850*10−6 ∗ (TL _ MAX − TROOM )] = 0.5 *10−3 ∗ [1 + 3850*10−6 ∗ (100 − 25)] = 0.64mΩ
The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,
G CS _ MIN = G CS _ ROOM ∗ [1 − 1470 *10 −6 ∗ (T IC _ MAX − T ROOM )] = 34 ∗ [1 − 1470 *10 −6 ∗ (101 − 25)] = 30.2
Set the over current limit at 135A. From Figure 14 of IR3081 Data Sheet, the bias current of OCSET pin (IOCSET) is
90uA with ROSC=13.3kΩ. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset
created by the current sense amplifier input resistor mismatch.
Calculate constant KP, the ratio of inductor peak current over average current in each phase,
KP =
(VI − VO ) ∗ VO /( L ∗ VI ∗ f SW ∗ 2) (12 − 1.28) ∗ 1.28 /(100 *10−9 ∗ 12 ∗ 800 *103 ∗ 2)
=
= 0.32
I LIMIT / n
135 / 6
ROCSET = [
=(
RLIMIT
∗ RL _ MAX ∗ (1 + K P ) + VCS _ TOFST ] ∗ GCS _ MIN / I OCSET
n
135
∗ 0.64 *10 − 3 ∗ 1.32 + 0.55 *10 −3 ) * 30.2 /(90 *10 − 6 ) = 6.34 kΩ
6
No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP
From Figure 14 of IR3081 Data Sheet, the bias current of FB pin is 90uA with ROSC=13.3kΩ.
RFB =
RL _ MAX ∗ VO _ NLOFST − VCS _ TOFST ∗ n ∗ RO
RDRP =
I FB ∗ RL _ MAX
RFB ∗ RL _ MAX ∗ GCS _ MIN
n ∗ RO
Page 26 of 34
=
=
0.64 *10−3 ∗ 20 *10−3 − 0.55 *10−3 ∗ 6 ∗ 0.91 *10−3
= 162Ω
90 *10−6 * 0.64 *10−3
162 ∗ 0.64 *10−3 * 30.2
= 576Ω
6 ∗ 0.91 *10−3
9/30/04
IR3088
Body Braking Related Resistors RBBFB and RBBDRP
N/A. The body braking during Dynamic VID is disabled.
IR3088 EXTERNAL COMPONENTS
PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP
Set PWM ramp magnitude VPWMRMP=0.75V. Choose 100pF for PWM ramp capacitor CPWMRMP, and calculate the
resistor RPWMRMP,
VO
RPWMRMP =
VIN * f SW * CPWMRMP * [ln(VIN − VDAC ) − ln(VIN − VDAC − VPWMRMP )]
=
1.28
12 ∗ 800 *103 ∗100 *10− 12 ∗ [ln(12 − 1.3) − ln(12 − 1.3 − 0.75)]
= 18.2kΩ
Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCSChoose 47nF for capacitor CCS+, and calculate RCS+,
RCS + =
L RL 100 *10−9 /(0.5 *10−3 )
=
= 4.22kΩ
CCS +
47 *10−9
The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,
RCS − = RCS + = 4.22kΩ
Combined Over Temperature and Phase Delay Setting Resistors RPHASEx1, RPHASEx2 and RPHASEx3
The over temperature setting resistor divider is combined with the phase delay resistor divider. Set the temperature
threshold at 115 ºC, which corresponds to the IC die temperature of 116 ºC, and calculate the HOTSET threshold
voltage corresponding to the temperature thresholds.
V HOTSET = 4.73 * 10 −3 ∗ TJ + 1.241 = 4.73 * 10 −3 ∗ 116 + 1.241 = 1.79V
The phase delay resistor ratios for phases 1 to 6 at 800kHz of switching frequencies are RAPHASE1=0.665,
RAPHASE2=0.432, RAPHASE3=0.198, RAPHASE4=0.206, RAPHASE5=0.401 and RAPHASE6=0.597 starting from downslope.
The over temperature setting voltage of phases 1, 2, 5, and 6 is lower than the phase delay setting voltage,
VBIAS*RAPHASEx. Pre-select RPHASE11=10kΩ,
RPHASEx 2 =
( RAPHASEx ∗ VBIAS − VHOTSET ) * RPHASEx1 (0.665 ∗ 6.8 − 1.79) ∗10 *103
= 12.1kΩ
=
6.8 ∗ (1 − 0.665)
VBIAS ∗ (1 − RAPHASEx )
RPHASEx3 =
VHOTSET ∗ RPHASEx1
1.79 ∗ 12.1 *103
=
= 7.87 kΩ
VBIAS * (1 − RAPHASEx ) 6.8 * (1 − 0.665)
RPHASE21=10kΩ, RPHASE22=2.94kΩ, RPHASE23=4.64kΩ
RPHASE51=10kΩ, RPHASE52=2.32kΩ, RPHASE53=4.42kΩ
RPHASE61=10kΩ, RPHASE62=8.25kΩ, RPHASE63=6.49kΩ
Page 27 of 34
9/30/04
IR3088
The over temperature setting voltage of Phases 3 and 4 is higher than the phase delay setting voltage,
VBIAS*RAPHASEx. Pre-select RPHASEX1=10kΩ,
R PHASE 32 =
(V HOTSET − RAPHASE 3 ∗ V BIAS ) ∗ R PHASE 31 (1.79 − 0.198 ∗ 6.8) ∗10 *10 3
= 887Ω
=
V BIAS − V HOTSET
6.8 − 1.79
RPHASE 33 =
RAPHASE 3 ∗ VBIAS * RPHASE 31 0.198 ∗ 6.8 ∗ 10 *103
= 2.67 kΩ
=
6.8 − 1.79
VBIAS − VHOTSET
RPHASE41=10kΩ, RPHASE42=768Ω, RPHASE43=2.80kΩ
Bootstrap Capacitor CBST
Choose CBST=0.1uF
Decoupling Capacitors for Phase IC and Power Stage
Choose CVCC=0.1uF, CVCCL=0.1uF
VOLTAGE LOOP COMPENSATION
Type III compensation is used for the converter with only ceramic output capacitors. The crossover frequency and
phase margin of the voltage loop can be estimated as follows.
f C1 =
R DRP
576
=
= 146 kHz
−6
2π ∗ C E ∗ G CS ∗ R FB ∗ R LE
2π ∗ (62 ∗ 22 * 10 ) ∗ 34 ∗ 162 ∗ (0.5 * 10 − 3 / 6)
θC1 = 90 − A tan(0.5) ∗
Choose RFB1 =
180
π
= 63°
2
2
∗ RFB = ∗ 162 = 110Ω
3
3
Choose the desired crossover frequency fc (=140kHz) around fc1 estimated above, and calculate
CFB =
1
4π ∗ fC ∗ RFB1
CDRP =
RCP =
CCP =
=
1
= 5.2nF , choose CFB=5.6nF
4π ∗ 140 *103 ∗ 110
( RFB + RFB1 ) ∗ CFB (162 + 110) ∗ 5.6 *10−9
=
= 2.7 nF
RDRP
576
( 2π ∗ fC ) 2 ∗ LE ∗ CE ∗ RFB ∗ VRAMP (2π ∗140 *103 ) 2 ∗ (100 *10−9 / 6) ∗ (22 *10−6 ∗ 62) ∗162 * 0.75
=
= 1.65kΩ
VO
1.3 − 20 *10−3
10 ∗ LE ∗ CE
RCP
=
10 ∗ (100 *10−9 / 6) ∗ ( 22 *10−6 * 62)
1.65 ∗ 103
= 27nF
Choose CCP1=47pF to reduce high frequency noise.
CURRENT SHARE LOOP COMPENSATION
The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage
loop fC. Choose the crossover frequency of current share loop fCI=3.5kHz, and calculate CSCOMP,
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IR3088
FMI =
RPWMRMP * CPWMRMP * f SW *V PWMRMP 18.2 *103 *100 *10−12 * 800 *103 * 0.75
=
= 0.011
(VI − VPWMRMP − VDAC ) * (VI − VDAC )
(12 − 0.75 − 1.3) * (12 − 1.3)
CSCOMP =
=
0.65 * RPWMRMP *VI * I O * GCS _ ROOM * RLE * [1 + 2π * fCI * CE * (VO I O )] * FMI
VO ∗ 2π ∗ fCI *1.05 *106
0.65 *18.2 *10 3 *12 *105 * 34 * (0.5 *10 −3 6) * [1 + 2π * 3500 * 22 *10 −6 * 62 * (1.33 − 105 * 9.1*10 −4 ) 105] * 0.011
(1.33 − 105 * 9.1*10 − 4 ) ∗ 2π ∗ 3500 *1.05 *10 6
= 20.6nF
Choose CSCOMP=22nF
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IR3088
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
power ground plane (PGND).
• Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
respectively through vias.
• In order to reduce the noise coupled to SCOMP pin of phase IC, use a dedicated wire to connect the capacitor
CSCOMP directly to LGND pin. However, connect PWM ramp capacitor CPWMRMP, phase delay programming
resistor RPHASE2 or RPHASE3, decoupling capacitor CVCC to LGND plane through vias.
• Place current sense resistors and capacitors (RCS+, RCS-, CCS+, and CCS-) close to phase IC. Use Kelvin
connection for the inductor current sense wires, but separate the two wires by ground polygon. The wire from
the inductor terminal to RCS- should not cross over the fast transition nodes, i.e. switching nodes, gate drive
outputs and bootstrap nodes.
• Place the decoupling capacitors CVCC and CVCCL as close as possible to VCC and VCCL pins of the phase IC
respectively.
• Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
• There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.
LGND
PLANE
To Signal Bus
To LGND
Plane
SCOMP
PHSFLT
LGND
PGND
PLANE
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To
Switching
Node
Ground
Polygon
CCS-
RCS-
CCS+
RCS+
VCCH
To Bottom To Top
MOSFET MOSFET
CBST
GATEH
CSIN+
PGND
VCC
GATEL
CVCCL
CSIN-
VCCL
To PGND
Plane
RBIASIN
DACIN
DBST
CSCOMP
EAIN
CVCC
To Gate
Drive
Voltage
BIASIN
PWMRMP
To LGND
Plane
RPHASE1
RMPIN+
RMPIN-
VRHOT
HOTSET
ISHARE
EAIN
RPWMRMP
RPHASE2
To LGND
Plane
CPWMRMP
To VIN
Ground
Polygon
To Inductor
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IR3088
PCB Metal and Component Placement
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥
0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
• Four 0.3mm diameter vias shall be placed in the pad land spaced at 1.2mm, and connected to ground to
minimize the noise effect on the IC, and to transfer heat to the PCB.
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IR3088
Solder Resist
• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder
Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is completely
removed from between the lead lands forming a single opening for each “group” of lead lands.
• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of ≥ 0.17mm remains.
• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the
copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have
the solder resist opening for the land pad to be smaller than the part pad.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect
ratio of the solder resist strip separating the lead lands from the pad land.
• The 4 vias in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the
diameter of the via.
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IR3088
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch
devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in
stencils < 0.25mm wide are difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately
50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float
and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening
minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands
when the part is pushed into the solder paste.
Metal and Solder Resist
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IR3088
PACKAGE INFORMATION
20L MLPQ (4 x 4 mm Body) – θJA = 32oC/W, θJC = 3oC/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
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