IR3521 DATA SHEET XPHASE3TM AMD SVID CONTROL IC DESCRIPTION The IR3521 Control IC combined with an xPHASE3TM Phase IC provides a full featured and flexible way to implement a complete AMD SVID power solution. It provides outputs for both the VDD core and VDDNB auxiliary planes required by the CPU. The IR3521 provides overall system control and interfaces with any number of Phase ICs each driving and monitoring a single phase. The xPHASE3TM architecture results in a power supply that is smaller, less expensive, and easier to design while providing higher efficiency than conventional approaches. FEATURES 2 converter outputs for the AMD processor VDD core and VDDNB auxiliary planes Supports High Speed (HS) I2C Serial communications PSI_L serial commands are communicated to a programmable number of phase ICs 0.5% overall system set point accuracy High speed error amplifiers with wide bandwidth of 20MHz and fast slew rate of 10V/us Remote sense amplifiers provide differential sensing and require less than 50uA bias current Programmable Dynamic VID Slew Rates Programmable VID Offset (VDD output only) Programmable output impedance (VDD output only) Programmable Dynamic OC for IDD_Spike Programmable per phase switching frequency of 250kHz to 1.5MHz Hiccup over current protection with delay during normal operation Central over voltage detection and communication to phase ICs through IIN (ISHARE) pin OVP disabled during dynamic VID down to prevent false triggering Over voltage signal to system with over voltage detection during powerup and normal operation Detection and protection of open remote sense lines Gate Drive and IC bias linear regulator control with programmable output voltage and UVLO Small thermally enhanced 32L MLPQ (5mm x 5mm) package ORDERING INFORMATION Device Package Order Quantity IR3521MTRPBF 32 Lead MLPQ (5 x 5 mm body) 3000 per reel IR3521MPBF (Samples Only) 32 Lead MLPQ (5 x 5 mm body) 100 piece strips Page 1 V3.03 IR3521 APPLICATION CIRCUIT 12V 12V Q3 To Converters To Phase IC VCCL & GATE DRIVE BIAS VCCL RVCCLFB1 CVCCL9 RVCCLFB2 PHSIN RVCCLDRV PGOOD Phase Clock Input to Last Phase IC of VDD 2 wire Digital Daisy Chain Bus to VDD & VDDNB Phase ICs CCP21 CCP22 25 CLKOUT 27 26 28 VCCL PHSIN 30 29 VCCLFB PHSOUT SS/DEL1 VDAC1 RFB22 RFB21 CFB2 PSI_L ROSC 23 Power Saving Indicator to VDD Phase ICs 22 21 ISHARE1 CSS/DEL1 20 RVDAC1 19 18 CVDAC1 ROCSET1 17 VDAC1 EAOUT1 CDRP1 3 Wire Analog Control Bus to VDD Phase ICs RDRP1 16 15 24 FB1 EAOUT1 VOUT1 OCSET1 EAOUT2 9 RCP2 IIN1 OCSET2 FB2 8 VDAC2 VOSNS1+ 7 SS/DEL2 VONSN1- 6 IIN2 14 ROCSET2 5 VDRP1 IR3521 CONTROL IC 13 RVDAC2 ROSC ENABLE VOSNS2- CSS/DEL2 CVDAC2 PWROK 12 4 EPAD PSI_L VOSNS2+ 3 CLKOUT SVD 11 ENABLE VCCLDRV 32 SVC PWROK 2 VOUT2 1 10 SVD PGOOD SVC 31 PHSOUT CFB1 RFB12 RFB11 RCP1 CCP11 CCP12 RFB13 RTHERMISTOR1 Load Line NTC Thermistor; Locate close to VDD Power Stage To VDD Remote Sense VDD SENSE + VDD SENSE EAOUT2 VDAC2 ISHARE2 3 Wire Analog Control Bus to VDDNB Phase ICs VDDNB SENSE VDDNB SENSE + To VDDNB Remote Sense Figure 1 – IR3521 Application Circuit Page 2 V3.03 IR3521 PIN DESCRIPTION PIN# 1 PIN SYMBOL SVD 2 PWROK 3 ENABLE 4 IIN2 5 SS/DEL2 6 VDAC2 7 OCSET2 8 9 10 11 12 13 14 15 16 EAOUT2 FB2 VOUT2 VOSEN2+ VOSEN2VOSEN1VOSEN1+ VOUT1 FB1 17 18 EAOUT1 OCSET1 19 VDAC1 PIN DESCRIPTION SVD (Serial VID Data) is a bidirectional signal that is an input and open drain output for both master (AMD processor) and slave (IR3521), requires an external bias voltage and should not be floated System wide Power Good signal and input to the IR3521. When asserted, the IR3521 output voltage is programmed through the SVID interface protocol. Connecting this pin to VCCL enables VFIX mode. Enable input. A logic low applied to this pin puts the IC into fault mode. A logic high on the pin enables the converter and causes the SVC and SVD input states to be decoded and stored, determining the 2-bit Boot VID. Do not float this pin as the logic state will be undefined. Output 2 average current input from the output 2 phase IC(s). This pin is also used to communicate over voltage condition to the output 2 phase ICs. Programs output 2 startup and over current protection delay timing. Connect an external capacitor to LGND to program. Output 2 reference voltage programmed by the SVID inputs and error amplifier noninverting input. Connect an external RC network to LGND to program dynamic VID slew rate and provide compensation for the internal buffer amplifier. Programs the output 2 constant converter output current limit and hiccup overcurrent threshold through an external resistor tied to VDAC2 and an internal current source from this pin. Over-current protection can be disabled by connecting a resistor from this pin to VDAC2 to program the threshold higher than the possible signal into the IIN2 pin from the phase ICs but no greater than 5V (do not float this pin as improper operation will occur). Output of the output 2 error amplifier. Inverting input to the Output 2 error amplifier. Output 2 remote sense amplifier output. Output 2 remote sense amplifier input. Connect to output at the load. Output 2 remote sense amplifier input. Connect to ground at the load. Output 1 remote sense amplifier input. Connect to ground at the load. Output 1 remote sense amplifier input. Connect to output at the load. Output 1 remote sense amplifier output. Inverting input to the output 1 error amplifier. Converter output voltage can be increased from the VDAC1 voltage with an external resistor connected between VOUT1 and this pin (there is an internal current sink at this pin). Output of the output 1 error amplifier. Programs the output 1 constant converter output current limit and hiccup overcurrent threshold through an external resistor tied to VDAC1 and an internal current source from this pin. Over-current protection can be disabled by connecting a resistor from this pin to VDAC1 to program the threshold higher than the possible signal into the IIN1 pin from the phase ICs but no greater than 5V (do not float this pin as improper operation will occur). Output 1 reference voltage programmed by the SVID inputs and error amplifier noninverting input. Connect an external RC network to LGND to program dynamic VID slew rate and provide compensation for the internal buffer amplifier. Page 3 V3.03 IR3521 PIN# 20 PIN SYMBOL SS/DEL1 21 IIN1 22 VDRP1 23 ROSC/OVP 24 25 PSI_L CLKOUT 26 PHSOUT 27 28 PHSIN VCCL 29 VCCLFB 30 VCCLDRV 31 PGOOD 32 SVC EPAD LGND PIN DESCRIPTION Programs output 1 startup and over current protection delay timing. Connect an external capacitor to LGND to program. Output 1 average current input from the output 1 phase IC(s). This pin is also used to communicate over voltage condition to phase ICs. Output 1 Buffered IIN1 signal. Connect an external RC network to FB1 to program converter output impedance. Connect a resistor to LGND to program oscillator frequency and OCSET1, OCSET2, FB1, FB2, VDAC1, and VDAC2 bias currents. Oscillator frequency equals switching frequency per phase. The pin voltage is 0.6V during normal operation and higher than 1.6V if over-voltage condition is detected. Digital output to communicate the systems power state to phase ICs PSI_L pin. Clock output at switching frequency multiplied by phase number. Connect to CLKIN pins of phase ICs. Phase clock output at switching frequency per phase. Connect to PHSIN pin of the first phase IC. Feedback input of phase clock. Connect to PHSOUT pin of the last phase IC. Output of the voltage regulator, and power input for clock oscillator circuitry. Connect a decoupling capacitor to LGND. No external power rail connection is allowed. Non-inverting input of the voltage regulator error amplifier. Output voltage of the regulator is programmed by the resistor divider connected to VCCL. Output of the VCCL regulator error amplifier to control external transistor. The pin senses 12V power supply through a resistor. Open collector output that drives low during startup and under any external fault condition. And it monitors output voltages, if any of the voltage planes fall out of spec, it will drive low. Connect external pull-up. ( Output voltage out of spec is defined as 350mV to 240mV below VDAC voltage ) SVC (Serial VID Clock) is an open drain output of the processor and input to IR3521, requires an external bias voltage and should not be floated Local ground for internal circuitry and IC substrate connection. Page 4 V3.03 IR3521 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed below may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. All voltages are absolute voltages referenced to the LGND pin. Operating Junction Temperature……………..0 to 150oC Storage Temperature Range………………….-65oC to 150oC ESD Rating………………………………………HBM Class 1C JEDEC Standard MSL Rating………………………………………2 Reflow Temperature…………………………….260oC PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EPAD PIN NAME SVD PWROK ENABLE IIN2 SS/DEL2 VDAC2 OCSET2 EAOUT2 FB2 VOUT2 VOSEN2+ VOSEN2VOSEN1VOSEN1+ VOUT1 FB1 EAOUT1 OCSET1 VDAC1 SS/DEL1 IIN1 VDRP1 ROSC/OVP PSI_L CLKOUT PHSOUT PHSIN VCCL VCCLFB VCCLDRV PGOOD SVC LGND VMIN -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.5V -0.5V -0.5V -0.5V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V -0.3V n/a VMAX 8V 8V 3.5V 8V 8V 3.5V 8V 8V 8V 8V 8V 1.0V 1.0V 8V 8V 8V 8V 8V 3.5V 8V 8V 8V 8V VCCL+ 0.3V 8V 8V 8V 8V 3.5V 10V VCCL + 0.3V 8V n/a Page 5 ISOURCE 1mA 1mA 1mA 5mA 1mA 1mA 1mA 25mA 1mA 5mA 5mA 5mA 5mA 5mA 5mA 1mA 25mA 1mA 1mA 1mA 5mA 35mA 1mA 1mA 100mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 20mA ISINK 10mA 1mA 1mA 1mA 1mA 1mA 1mA 10mA 1mA 25mA 1mA 1mA 1mA 1mA 25mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 20mA 100mA 10mA 1mA 20mA 1mA 50mA 20mA 1mA 1mA V3.03 IR3521 RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN 4.75V ≤ VCCL ≤ 7.5V, -0.3V ≤ VOSEN-x ≤ 0.3V, 0 oC ≤ TJ ≤ 100 oC, 7.75 kΩ ≤ ROSC ≤ 50 kΩ, CSS/DELx = 0.1uF ELECTRICAL CHARACTERISTICS The electrical characteristics table shows the spread of values guaranteed within the recommended operating conditions (unless otherwise specified). Typical values (TYP) represent the median values, which are related to 25°C. PARAMETER SVID Interface SVC & SVD Input Thresholds Bias Current SVD Low Voltage SVD Fall Time, CSVD=400 pF SVD Fall Time, CSVD=100 pF Pulse width input filter TEST CONDITION MIN TYP MAX UNIT Threshold Increasing Threshold Decreasing Threshold Hysteresis 0V ≤ V(x) ≤ 3.5V, SVD not asserted I(SVD)= 3mA 70-30% VDDIO, 1.425V ≤ VDDIO ≤ 1.9V, 1.7MHz operation, Note 1 3.4MHz operation Note 1 0.8025 570 150 -5 20 0.90 650 250 0 20 40 0.9975 750 400 5 300 160 V mV mV uA mV ns 10 20 20 80 20 <100 ns ns 6 150 10 300 20 mV kΩ See Figure 2 0.600 +10% kHz 0.630 1 V V 1 1 V V 1 70 V % 8 30 0.6 1 mV mA mA MHz V/s A PSI_L OUTPUT Output Voltage Pull-up Resistance (to VCCL) I(PSI_L) = 3mA Oscillator PHSOUT Frequency -10% ROSC Voltage CLKOUT High Voltage 0.57 CLKOUT Low Voltage PHSOUT High Voltage PHSOUT Low Voltage PHSIN Threshold Voltage I(CLKOUT)= -10 mA, measure V(VCCL) – V(CLKOUT). I(CLKOUT)= 10 mA I(PHSOUT)= -1 mA, measure V(VCCL) – V(PHSOUT) I(PHSOUT)= 1 mA Compare to V(VCCL) 30 50 -8 2 0.2 0 VDRP1 Buffer Amplifier Input Offset Voltage Source Current Sink Current Unity Gain Bandwidth Slew Rate IIN Bias Current V(VDRP1) – V(IIN1), 0.5V ≤ V(IIN) ≤ 3.3V 0.5V ≤ V(IIN1) ≤ 3.3V 0.5V ≤ V(IIN1) ≤ 3.3V Note 1 Note 1 -2 0.4 8 4.7 -0.2 3.0 -3 6.4 0 9.0 3 MHz mV 0.5 2 2 1 12 4 30 30 1.7 18 8 50 50 5.5 250 1 mA mA V/us uA uA V mV V Remote Sense Differential Amplifiers Unity Gain Bandwidth Input Offset Voltage Source Current Sink Current Slew Rate VOSEN+ Bias Current VOSEN- Bias Current VOSEN+ Input Voltage Range Low Voltage High Voltage Note 1 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V, Note 2 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V 0.5V≤ V(VOSENx+) - V(VOSENx-) ≤ 1.6V TBS V < V(VOSENx+) < 1.6V -0.3V ≤ VOSENx- ≤ 0.3V, All VID Codes V(VCCL)=7V V(VCCL) =7V V(VCCL) – V(VOUTx) Page 6 0.5 V3.03 IR3521 PARAMETER Soft Start and Delay Start Delay Start-up Time OC Delay Time SS/DELx to FBx Input Offset Voltage Charge Current OC Delay/VID Off Discharge Currents Fault Discharge Current Hiccup Duty Cycle Charge Voltage Delay Comparator Threshold Delay Comparator Threshold Delay Comparator Hysteresis Discharge Comp. Threshold Over-Current Comparators Input Offset Voltage TEST CONDITION Measure Enable to EAOUTx activation Measure Enable activation to PGOOD V(IINx) – V(OCSETx) = 500 mV With FBx = 0V, adjust V(SS/DELx) until EAOUTx drives high TYP MAX UNIT 1 3 85 0.7 2.9 8 170 1.4 3.5 13 325 1.9 ms ms us V -30 -50 47 -70 A A 2.5 7 3.5 4.5 10 3.9 80 6.5 12 4.2 A uA/uA V mV Note 1 I(Fault) / I(Charge) Relative to Charge Voltage, SS/DELx rising Note 1 Relative to Charge Voltage, SS/DELx falling Note 1 Note 1 120 150 1V ≤ V(OCSETx) ≤ 3.3V OCSET Bias Current 2048-4096 Count Threshold 1024-2048 Count Threshold MIN 40 200 mV 300 mV mV -35 0 35 mV -5% Vrosc(V)*100 0/Rosc(KΩ) +5% A Adjust ROSC value to find threshold Adjust ROSC value to find threshold 16 20 kΩ kΩ Error Amplifiers System Set-Point Accuracy (Deviation from Table 1, 2, and 3 per test circuit in Figures 2A & 2B) Input Offset Voltage FB1 Bias Current FB2 Bias Current DC Gain Bandwidth Slew Rate Sink Current Source Current Maximum Voltage Minimum Voltage Open Voltage Loop Detection Threshold Open Voltage Loop Detection Delay Enable Input Blanking Time VID ≥ 1V 0.8V ≤ VID < 1V 0.5V ≤ VID < 0.8V -0.5 -5 -8 Measure V(FBx) – V(VDACx)). Note 2 -1 -5% Note 1 Note 1 Note 1 Measure V(VCCL) – V(EAOUTx) -1 100 20 5.5 0.4 5.0 500 0 Vrosc(V)*1000 /Rosc(KΩ) 0 110 30 12 0.85 8.5 780 120 300 0.5 +5 +8 % mV mV 1 +5% mV A 1 135 40 20 1 12.0 950 250 600 A dB MHz V/s mA mA mV mV mV Measure V(VCCL) - V(EAOUT), Relative to Error Amplifier maximum voltage. Measure PHSOUT pulse numbers from V(EAOUTx) = V(VCCL) to PGOOD = low. 125 Noise Pulse < 100ns will not register an ENABLE state change. Note 1 75 250 400 ns 3050*Vrosc(V) / ROSC(kΩ) 2650*Vrosc(V) / ROSC(kΩ) +8% A +8% A -315 -265 mV 8 VDAC References Source Currents Includes I(OCSETx) -8% Sink Currents Includes I(OCSETx) -8% PGOOD Output Under Voltage Threshold Voutx Decreasing Reference to VDACx -365 Page 7 Pulses V3.03 IR3521 PARAMETER Under Voltage Threshold - Voutx Increasing Under Voltage Threshold Hysteresis Output Voltage Leakage Current VCCL Activation Threshold TEST CONDITION Reference to VDACx MIN TYP MAX UNIT -325 -275 -225 mV 5 53 150 0 1.73 110 300 10 3.5 mV mV A V I(PGOOD) = 4mA V(PGOOD) = 5.5V I(PGOOD) = 4mA, V(PGOOD) = 300mV Over Voltage Protection (OVP) Comparators Threshold at Power-up Voutx Threshold Voltage OVP Release Voltage during Normal Operation Threshold during Dynamic VID down Dynamic VID Detect Comparator Threshold Propagation Delay to IIN OVP High Voltage OVP Power-up High Voltage Propagation Delay to OVP Compare to V(VDACx) Compare to V(VDACx) Note 1 Measure time from V(Voutx) > V(VDACx) (250mV overdrive) to V(IINx) transition to > 0.9 * V(VCCL). Measure V(VCCL)-V(ROSC/OVP) V(VCCLDRV)=1.8V. Measure V(VCCL)-V(ROSC/OVP) Measure time from V(Voutx) > V(VDACx) (250mV overdrive) to V(ROSC/OVP) transition to >1V. 1.60 220 -20 1.73 260 3 1.83 285 25 V mV mV 1.8 25 1.85 50 90 1.9 75 180 V mV ns 1.2 0.2 V V 0 0 150 300 nS 5 15 Ω 150 200 250 mV 29 62.5 90 mV 86.5 89.0 91.5 % 0.36 0.40 0.44 V 200 500 700 uA 1.15 -1 10 89.0 81.0 7.0 1.2 0 40 93.5 85.0 8.25 1.25 1 1.3 0.8 470 -5 3.3 V 1.65 0.99 620 0 (VCCL +3.3)(V) / 2 3.5 10 IIN Pull-up Resistance Open Sense Line Detection Sense Line Detection Active Comparator Threshold Voltage Sense Line Detection Active Comparator Offset Voltage VOSEN+ Open Sense Line Comparator Threshold VOSEN- Open Sense Line Comparator Threshold Sense Line Detection Source Currents V(Voutx) < [V(VOSENx+) – V(LGND)] / 2 Compare to V(VCCL) V(Voutx) = 100mV VCCL Regulator Amplifier Reference Feedback Voltage VCCLFB Bias Current VCCLDRV Sink Current UVLO Start Threshold UVLO Stop Threshold Hysteresis Compare to V(VCCL) Compare to V(VCCL) Compare to V(VCCL) 97.0 89.0 9.5 V uA mA % % % ENABLE, PWROK Inputs Threshold Increasing Threshold Decreasing Threshold Hysteresis Bias Current PWROK VFIX Mode Threshold 0V ≤ V(x) ≤ 3.5V, SVC not asserted 1.9 1.2 770 5 VC CL V V mV uA V 15 mA General VCCL Supply Current Note 1: Guaranteed by design, but not tested in production Note 2: VDACx Outputs are trimmed to compensate for Error & Amp Remote Sense Amp input offset. Page 8 V3.03 IR3521 PHSOUT FREQUENCY VS RROSC CHART PHSOUT FREQUENCY vs. RROSC 1600 1500 1400 1300 Frequency (KHz) 1200 1100 1000 900 800 700 600 500 400 300 200 5 10 15 20 25 30 35 40 45 50 55 RROSC (KOhm) Figure 2 - Phout Frequency vs. RROSC chart System Fault Table Response Latch Reset Outputs Affected Disables EA SS/DELx Discharge Flags PGood Delays Additional Flagged Response Open Open Open UVLO Over Daisy Sense Voltage (VCCL) Voltage UV & EN Latch EN Fault Latch Recycle VCCL then Enable Recycle Enable Both Single Both Both Disable Both VID_OFF OC OC SVID Before After SS Latch SS discharge below 0.2V Single Single UVLO (Vout) No No Single Yes No Yes No Yes 32 Clock Pulses No 8 PHSOUT Pulses No No No 250ns Blanking Time Yes, IINx and Rosc pins pulled-up to VCCL * Pulse number range depends on Rosc value selected (See Specifications Table) Page 9 No PHSOUT Pulses* SS/DELx Discharge Threshold No V3.03 No IR3521 SYSTEM SET POINT TEST The converter output voltage is determined by the system set point voltage which is the voltage that appears at the FBx pins when the converter is in regulation. The set point voltage includes error terms for the VDAC digitalto-analog converters, Error Amp input offsets, and Remote Sense input offsets. The voltage appearing at the VDACx pins is not the system set point voltage. System set point voltage test circuits for Outputs 1 and 2 are shown in Figures 3A and 3B. IR3521 ERROR AMPLIFIER VDAC1 BUFFER AMPLIFIER EAOUT1 + FB1 + ISOURCE "FAST" VDAC VDAC1 OCSET1 ISINK ROCSET1 - IFB1 IOCSET1 IROSC IROSC RVDAC1 CVDAC1 ROSC BUFFER AMPLIFIER 1.2V LGND + CURRENT SOURCE GENERATOR IROSC ROSC RROSC VOUT1 EAOUT SYSTEM SET POINT VOSNSVOLTAGE REMOTE SENSE AMPLIFIER VOSEN1+ + VOSEN1- Figure 3A - Output 1 System Set Point Test Circuit IR3521 ERROR AMPLIFIER VDAC2 BUFFER AMPLIFIER EAOUT2 + FB2 + ISOURCE "FAST" VDAC VDAC2 OCSET2 ISINK ROCSET2 - IOCSET2 IROSC RVDAC2 CVDAC2 CURRENT SOURCE GENERATOR LGND + ROSC RROSC VOUT2 REMOTE SENSE AMPLIFIER VOSEN2+ + EAOUT SYSTEM SET POINT VOSNSVOLTAGE VOSEN2- IROSC ROSC BUFFER AMPLIFIER 1.2V Figure 3B - Output 2 System Set Point Test Circuit Page 10 V3.03 IR3521 SYSTEM THEORY OF OPERATION PWM Control Method The PWM block diagram of the xPHASE3TM architecture is shown in Figure 4. Feed-forward voltage mode control with trailing edge modulation is used to provide system control. A voltage type error amplifier with high-gain and wide-bandwidth, located in the Control IC, is used for the voltage control loop. The feed-forward control is performed by the phase ICs as a result of sensing the input voltage (FET’s drain voltage). The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. GATE DRIVE VOLTAGE VIN IR35121CONTROL IC PHSOUT CLOCK GENERATOR CLKOUT IR3505 PHASE IC VCC CLKIN VCCH CLK Q PWM LATCH D PHSOUT PHSIN PHSIN CBST VOSNS1+ SW RESET DOMINANT VOUT1 COUT - EAIN R VCCL + GND GATEL ENABLE + + VID6 - REMOTE SENSE AMPLIFIER GATEH S PWM COMPARATOR VOSNS1- - + - RAMP DISCHARGE CLAMP VOUT1 PGND BODY BRAKING COMPARATOR VDAC1 LGND - ISHARE + - RCP1 RFB12 CCP13 FB1 VID6 VID6 + RFB11 + CFB2 IROSC CDRP2 VDRP1 AMP CURRENT SENSE AMPLIFIER VID6 VID6 + VDRP1 CCS RCS CSIN- DACIN RDRP1 PHSOUT IR3505 PHASE IC VCC + - CLKIN VCCH CLK Q Output 1 Only CSIN+ + CCP14 IFB1 - 3K - + SHARE ADJUST ERROR AMPLIFIER EAOUT1 - VDAC + ERROR AMPLIFIER IIN1 PWM LATCH D PHSIN GATEH CBST S PWM COMPARATOR - EAIN SW RESET DOMINANT R VCCL + GATEL ENABLE + VID6 PGND BODY BRAKING COMPARATOR - + - RAMP DISCHARGE CLAMP SHARE ADJUST ERROR AMPLIFIER CURRENT SENSE AMPLIFIER + ISHARE - 3K - VID6 VID6 + CSIN+ + + CCS RCS - VID6 VID6 + CSIN- DACIN Figure 4 - PWM Block Diagram Frequency and Phase Timing Control The oscillator (system clock) is located in the Control IC and is programmable from 250 kHz to 9 MHZ by an external resistor. The control IC clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is controlled by the daisy chain loop. The control IC phase clock output (PHSOUT) is connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC, etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the loop. During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 5 shows the phase timing for a four phase converter. Page 11 V3.03 IR3521 Control IC CLKOUT (Phase IC CLKIN) Control IC PHSOUT (Phase IC1 PHSIN) Phase IC1 PWM Latch SET Phase IC 1 PHSOUT (Phase IC2 PHSIN) Phase IC 2 PHSOUT (Phase IC3 PHSIN) Phase IC 3 PHSOUT (Phase IC4 PHSIN) Phase IC4 PHSOUT (Control IC PHSIN) Figure 5 Four Phase Oscillator Waveforms PWM Operation The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock, the PWM latch is set and the PWM ramp amplitude begins to increase prompting the low side driver is turned off. After the non-overlap time (GATEL < 1.0V), the high side driver is turned on. When the PWM ramp voltage exceeds the error amplifier’s output voltage, the PWM latch is reset. This also turns off the high side driver, turns on the low side driver after the non-overlap time and the PWM ramp discharged current is clamped which quickly discharges the internal capacitor to the output voltage of share adjust amplifier, in phase IC, until the next clock pulse. The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The inductor current will increase much more rapidly than decrease in response to load transients. This control method is designed to provide “single cycle transient response” where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Figure 6 depicts PWM operating waveforms under various conditions. Page 12 V3.03 IR3521 PHASE IC CLOCK PULSE EAIN PWMRMP VDAC GATEH GATEL STEADY-STATE OPERATION DUTY CYCLE INCREASE DUE TO LOAD INCREASE DUTY CYCLE DECREASE DUE TO VIN INCREASE (FEED-FORWARD) DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, OCP, VID FAULT) STEADY-STATE OPERATION Figure 6 PWM Operating Waveforms Body BrakingTM In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in response to a load step decrease is; TSLEW L * ( I MAX I MIN ) VO The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is now; TSLEW L * ( I MAX I MIN ) VO VBODYDIODE Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through the “body braking comparator” located in the phase IC. If the error amplifier’s output voltage drops below the VDAC voltage or a programmable voltage, this comparator turns off the low side gate driver. Lossless Average Inductor Current Sensing Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor, as shown in Figure 7. The equation of the sensing network is, vC ( s) vL ( s) 1 RL sL iL ( s) 1 sRCS CCS 1 sRCS CCS Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor DC current, but affects the AC component of the inductor current. Page 13 V3.03 IR3521 vL iL L RL RCS CCS Current Sense Amp VO CO c vCS CSOUT Figure 7 Inductor Current Sensing and Current Sense Amplifier The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no information during either load increase (low side sensing) or load decrease (high side sensing). An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors. Current Sense Amplifier A high speed differential current sense amplifier is located in the phase IC, as shown in Figure 7. Its gain is nominally 34 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the voltage loop feedback path. The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the control IC and other phases through an on-chip 3KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on the share bus represents the average current through all the inductors and is used by the control IC for voltage positioning and current limit protection. Average Current Share Loop Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The output of the current sense amplifier is compared with average current at the share bus. If current in a phase is smaller than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output current. The current share amplifier is internally compensated so that the crossover frequency of the current share loop is much slower than that of the voltage loop and the two loops do not interact. Page 14 V3.03 IR3521 IR3521 THEORY OF OPERATION Block Diagram The Block diagram of the IR3521 is shown in Figure 8. The following discussions are applicable to either output plane unless otherwise specified. Serial VID Control The two Serial VID Interface (SVID) pins SVC and SVD are used to program the Boot VID voltage upon assertion of ENABLE while PWROK is de-asserted. See Table 1 for the 2-bit Boot VID codes. Both VDAC1 and VDAC2 voltages will be programmed to the Boot VID code until PWROK is asserted. The Boot VID code is stored by the IR3521 to be utilized again if PWROK is de-asserted. Serial VID communication from the processor is enabled after the PWROK is asserted. Addresses and data are serially transmitted in 8-bit words. The IR3521 has three fixed addresses to control VDAC1, VDAC2, or both VDAC1 and VDAC2 (See Table 6 for addresses). The first data bit of the SVID data word represents the PSI_L bit and if pulled low will force all phase ICs, connected to the PSI_L pin, in to a power-saving mode. The remaining data bits SVID[6:0] select the desired VDACx regulation voltage as defined in Table 3. SVID[6:0] are the inputs to the Digital-to-Analog Converter (DAC) which then provides an analog reference voltage to the transconductance type buffer amplifier. This VDACx buffer provides a system reference on the VDACx pin. The VDACx voltage along with error amplifier and remote sense differential amplifier input offsets are post-package trimmed to provide a 0.5% system set-point accuracy, as measured in Figures 3A and 3B. VDACx slew rates are programmable by properly selecting external series RC compensation networks located between the VDACx and the LGND pins. The VDACx source and sink currents are derived off the external oscillator frequency setting resistor, RROSC. The programmable slew rate enables the IR3521 to smoothly transition the regulated output voltage throughout VID transitions. This results in power supply input and output capacitor inrush currents along with output voltage overshoot to be well controlled. The two Serial VID Interface (SVID) pins SVC and SVD can also program the VFIX VID voltage upon assertion of ENABLE while PWROK is equal to VCCL. See Table 2 for the 2-bit VFIX VID codes. Both VDAC1 and VDAC2 voltages will be programmed to the VFIX code. The SVC and SVD pins require external pull-up biasing and should not be floated. Output 1 (VDD) Adaptive Voltage Positioning The IR3521 provides Adaptive Voltage Positioning (AVP) on the output1 plane only. AVP helps reduces the peak to peak output voltage excursions during load transients and reduces load power dissipation at heavy load. The circuitry related to the voltage positioning is shown in Figure 9. Resistor RFB1 is connected between the error amplifiers inverting input pin FB1 and the remote sense differential amplifier output, VOUT1. An internal current sink on the FB1 pin along with RFB1 provides programmability of a fixed offset voltage above the VDAC1 voltage. The offset voltage generated across RFB1 forces the converter’s output voltage higher to maintain a balance at the error amplifiers inputs. The FB1 sink current is derived by the external resistor RROSC that programs the oscillator frequency. The VDRP1 pin voltage is a buffered reproduction of the IIN1 pin which is connected to the current share bus ISHARE. The voltage on ISHARE represents the system average inductor current information. At each phase IC, an RC network across the inductor provides current information which is gained up 32.5X and then added to the VDACX voltage. This phase current information is provided on the ISHARE bus via a 3K resistor in the phase ICs. Page 15 V3.03 IR3521 S POR VDD VCCLDRV VCCL-UVLO VCCLFB D Q . Q SELECT MODE + 250nS BLANKING S Q SET DOMINANT DLY OUT2 VOUT2 VID OFF UV2 UV1 VOUT1 VID OFF DLY OUT1 VCCLDRV FLT1 + VCCL UVLO 400k - SS/DEL CLEARED FAULT LATCH2 SELECT MODE DISABLE VCCL UVLO OC2 AFTER VRRDY OC2 Bf VRRDY SSCL FS2 OPEN DAISY OPEN SENSE2 OPEN CONTROL2 SS/DEL CLEARED FAULT LATCH1 S Q SET DOMINANT Q S SET DOMINANT R UV CLEARED FAULT LATCH2 SELECT MODE DISABLE VCCL UVLO OC1 AFTER VRRDY OC1 Bf VRRDY SSCL FS1 R S Q SET DOMINANT Q S SET DOMINANT R + DLY OUT2 - ICHG 50uA DCHG2 AND2 PHSOUT DIS OC DELAY IROSC COUTER DIS DIS S Q RESET DOMINANT DISCHARGE COMPARATOR U? FLT2 POWER-UP OK LATCH R reset DIS OC DELAY COUTERDIS DIS 80mV DELAY COMPARATOR 120mV POWER-UP OK LATCH PHSOUT IROSC DLY OUT1 Q S RESET DOMINANT reset Q Q DISCHARGE COMPARATOR R - - + + DIS IDCHG 4.5uA DCHG2 PHSOUT IDCHG2 IDCHG1 47uA 47uA SS/DEL1 DCHG1 FLT1 IDCHG 4.5uA VCCL OV1 PHSOUT OV2 8 Pulse Delay DIS OC LIMIT COMPARATOR - IOCSET + VDRP AMPLIFIER IOCSET OPEN CONTROL LOOP COMPARATOR VCCL - FLT1 DISABLE2 DISABLE1 DLY OUT2 SOFT START CLAMP SOFT START CLAMP DLY OUT1 VDAC1 + - FB2 260mV 275mV VOUT2 UV COMPARATOR 315mV - VRRDY - + + OVLATCH 1.6V + - - U? 1.6V DYNAMIC VID1 DOWN DETECT COMPARATOR + + VDAC2 VDAC1 OVLATCH DYNAMIC VID2 DOWN DETECT COMPARATOR OV2 DETECTION PULSE2 25k 60mV 25k 60mV + 25k - REMOTE SENSE AMPLIFIER REMOTE SENSE AMPLIFIER + + IVOSEN2+ 25k 25k - VCCL - 200mV 200mV + EN + - 4 OPEN SENSE LINE DETECT COMPARATORS VCCL RESET VCCL*0.9 EN + OPEN SENSE LINE1 OPEN SENSE LINE2 0.4V EN EN + + + VCCL UVLO OPEN DAISY FAULT CHAIN SVID to SVID Vout1 VID SVID to Metal Metal to SVID On-The-Fly High to Low CURRENT SOURCE GENERATOR ROSC BUFFER AMPLIFIER IROSC DVID2 VID0 PHSIN + CLKOUT CLOCK MEMORY VDAC1 IROSC ISINK - VDAC BUFFER AMPLIFIER ISOURCE VOUT1 VID OFF VOUT2 VID OFF IROSC ISINK - ISOURCE VDAC BUFFER AMPLIFIER VID3 VDD READ & STORE PRE-PWROK 2 BIT VID VID7 SVID to SVID Vout2 VID SVID to Metal On-The-Fly Metal to SVID High to Low D/A CONVERTER VID3 SVID ENABLED Low to High VFIXVID3 Mode Connection to VCCL Back to PRE-PWROK VID3 2 BIT VID VID3 VID3 SVI (Seriel VID Interface) VID3 SVC VID3 SVD ROSC VCCL- 1.2V OV1_2 CLKOUT PHSIN VID7 VID3 PHSOUT PWROK High to Low PHSOUT - 0.6V + VDAC2 EPAD VCCL DETECTION PULSE1 + 4 OPEN SENSE LINE DETECT COMPARATORS VCCL RESET VCCL*0.9 0.4V IVOSENVCCL DETECTION PULSE2 - IVOSEN1+ VIDSEL VCCL IVOSEN1- VIDSEL - IVOSEN- VOSEN1- - IVOSEN2- VOSEN1+ + 25k VOSEN2- VOUT1 25k 25k VOSEN2+ OV1 DETECTION PULSE1 50mV 50mV AND2 UV1 - OVER VOLTAGE COMPARATOR FB1 IROSC IFB OVER VOLTAGE COMPARATOR 275mV VOUT1 UV 315mV COMPARATOR 260mV VRRDY EAOUT1 ERROR AMPLIFIER FLT2 + + + VDAC2 ERROR AMPLIFIER - EAOUT2 1.4V + 1.4V VOUT2 IIN1 1.08V + + UV2 VDRP1 + OCSET1 IROSC IROSC - 8 Pulse Delay DIS + + - OPEN CONTROL LOOP COMPARATOR - IIN2 OCSET2 DIS OC LIMIT COMPARATOR + DIS FLT1 DCHG1 DIS FLT2 VCCL DIS ICHG 50uA 0.2V 0.2V SS/DEL2 3.9V - DELAY COMPARATOR 3.9V VCCL OPEN DAISY OPEN SENSE1 OPEN CONTROL1 + 80mV 120mV INTERNAL DIS CIRCUIT BIAS UV CLEARED FAULT LATCH1 R VCCL PGOOD OV1 FAULT LATCH VCCL UVL COMPARATOR 1.08V 1.65V 1V SSCL FS1 R 0.94 0.86 ENABLE - ENABLE + COMPARATOR FLT2 SSCL FS2 OV1-2 DISABLE - 1.2V DISABLE OVLATCH OV FAULT LATCH R VCCL REGULATOR AMPLIFIER VID3 SVC SVD VCCL OV2 10k OV1 PSI_L Figure 8 Block Diagram Page 16 V3.03 IR3521 Control IC VDAC1 Phase IC VDAC1 Current Sense Amplifier ... ... RDRP1 Phase IC VDRP1 Current Sense Amplifier + ISHARE VOUT1 VDAC + VOSEN1+ - VOSEN1- 3k CSIN+ CSIN- Figure 9 Adaptive voltage positioning Control IC VDAC1 VDAC1 Error Amplifier + EAOUT1 RFB11 IFB FB1 VDRP Amplifier + RFB12 Rt RDRP1 VDRP1 IIN1 VOUT1 VOSEN1+ - Remote Sense Amplifier + Remote Sense Amplifier IIN1 - VDRP Amplifier CSIN- + + - RFB1 FB1 IFB CSIN+ - VDAC EAOUT1 3k + ISHARE Error Amplifier VOSEN1- Figure 10 Temperature compensation of Output1 inductor DCR Page 17 V3.03 IR3521 Output 1 (VDD) Adaptive Voltage Positioning (continued) The voltage difference between VDRP1 and FB1 represents the gained up average current information. Placing a resistor RDRP1 between VDRP1 and FB1 converts the gained up current information (in the form of a voltage) into a current forced onto the FB1 pin. This current, which can be calculated using (VDRP1-VDAC1) / RDRP1, will vary the offset voltage produced across RFB1. Since the error amplifier will force the loop to maintain FB1 to equal the VDAC1 reference voltage, the output regulation voltage will be varied. When the load current increases, the adaptive positioning voltage V(VDRP1) increases accordingly. (VDRP1-VDAC1) / RDRP1 increases the voltage drop across the feedback resistor RFB1, and makes the output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor RDRP1 so that the droop impedance produces the desired converter output impedance. The offset and slope of the converter output impedance are referenced to VDAC1 and are not affected by changes in the VDAC1 voltage. Output1 Inductor DCR Temperature Compensation A negative temperature coefficient (NTC) thermistor can be used for output1 inductor DCR temperature compensation. The thermistor should be placed close to the output1 inductors and connected in parallel with the feedback resistor, as shown in Figure 10. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. Remote Voltage Sensing VOSENX+ and VOSENX- are used for remote sensing and connected directly to the load. The remote sense differential amplifiers are high speed, have low input offset and low input bias currents to ensure accurate voltage sensing and fast transient response. Start-up Sequence The IR3521 has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DELX and LGND pins controls soft start timing, over-current protection delay and hiccup mode timing. Constant current sources and sinks control the charge and discharge rates of the SS/DELX. Figure 11 depicts the SVID start-up sequence. If the ENABLE input is asserted and there are no faults, the SS/DELX pin will begin charging, the pre-PWROK 2 bit Boot VID codes are read and stored, and both VDAC pins transition to the pre-PWROK Boot VID code. The error amplifier output EAOUTX is clamped low until SS/DELX reaches 1.4V. The error amplifier will then regulate the converter’s output voltage to match the V(SS/DELX)-1.4V offset until the converter output reaches the 2-bit Boot VID code. The SS/DELX voltage continues to increase until it rises above the threshold of Delay Comparator where the PGOOD output is allowed to go high. The SVID interface is activated upon PWROK assertion and the VDACX along with the converter output voltage will change in response to any SVID commands. VCCL under voltage, over current, or a low signal on the ENABLE input immediately sets the fault latch, which causes the EAOUT pin to drive low, thereby turning off the phase IC drivers. The PGOOD pin also drives low and SS/DELX discharges to 0.2V. If the fault has cleared, the fault latch will be reset by the SS/DELX discharge comparator allowing another soft start charge cycle to occur. Other fault conditions, such as output over voltage, open VOSNS sense lines, or an open phase timing daisy chain set a different group of fault latches that can only be reset by cycling VCCL power. These faults discharge SS/DELX, pull down EAOUTX and drive PGOOD low. SVID OFF codes turn off the converter by discharging SS/DELX and pulling down EAOUTx but do not drive PGOOD low. Upon receipt of a non-off SVID code the converter will re-soft start and transition to the voltage represented by the SVID code as shown in Figure 11. The converter can be disabled by pulling the SS/DELx pins below 0.6V. Page 18 V3.03 IR3521 VCC (12V) ENABLE SVC 2-Bit Boot VID READ & STORE 2-Bit Boot VID On-Hold SVID TRANSITION SVID OFF COMMAND SVID ON COMMAND SVD 2-Bit Boot VID READ & STORE 2-Bit Boot VID On-Hold SVID TRANSITION SVID OFF COMMAND SVID ON COMMAND 2-Bit Boot VID Voltage SVID set voltage 0.8V VDACx SVID programmed voltage 0.5V 4.0V 3.92V 1.4V 1.4V SS/DEL EAOUT VOUT PGOOD PWROK START DELAY STARTUP TIME VID ON NORMAL THE FLY OPERATION PROCESSION SVID OFF TRANSISTION SVID ON TRANSISTION Figure 11 SVID Start-up Sequence Transitions Page 19 V3.03 IR3521 Serial VID Interface Protocol and VID-on-the-fly Transition The IR3521 supports the AMD SVI bus protocol and the AMD Server and desktop SVI wire protocol which are based on High-Speed I2C. SVID commands from an AMD processor are communicated through SVID bus pins SVC and SVD. The SVC pin of the IR3521 does not have an open drain output since AMD SVID protocol does not support slave clock stretching. The IR3521 transitions from a 2-bit Boot VID mode to SVI mode upon assertion of PWROK. The SMBus send byte protocol is used by the IR3521 VID-on-the-fly transactions. The IR3521 will wait until it detects a start bit which is defined as an SVD falling edge while SVC is high. A 7bit address code plus one write bit (low) should then follow the start bit. This address code will be compared against an internal address table and the IR3521 will reply with an acknowledge ACK bit if the address is one of the three stored addresses otherwise the ACK bit will not be sent out. The SVD pin is pulled low by the IR3521 to generate the ACK bit. Table 4 has the list of addresses recognized by the IR3521. The processor should then transmit the 8-bit data word immediately following the ACK bit. The first data bit (bit 7), of the SVID data word, represents the Power State Indicator (PSI) bit which is passed on to the phase ICs via the IR3521 PSI_L pin. PSI_L is pulled high by an internal 10K resistor to VCCL when data bit 7 of an SVID command is high. A low, on this bit (bit 7), will pull the PSL_pin low and trigger all connected, predetermine, phase ICs to turn off. If transitioning from one phase to multiple phases, the last phase IC, or returning phase IC, should be left on to ensure the fastest possible clock frequency calibration. A shorter calibration time will help minimize droop at the VDD output when leaving PSI_L mode. The remaining data bits SVID[6:0] select the desired VDACx regulation voltage as defined in Table 3. The IR3521 replies again with an ACK bit once the data is received. If the received data is not a VID-OFF command, the IR3521 immediately changes the DAC analog outputs to the new target. VDAC1 and VDAC2 then slew to the new VID voltages. See Figure 12 for a send byte example. Table 1 – 2-bit Boot VID codes SVC 0 0 1 1 SVD 0 1 0 1 Table 2 – VFIX mode 2 bit VID Codes SVC 0 0 1 1 Output Voltage(V) 1.1 1.0 0.9 0.8 SVD 0 1 0 1 Output Voltage(V) 1.4 1.2 1.0 0.8 Figure 12 Send Byte Example Page 20 V3.03 IR3521 Table 3 - AMD 7 BIT SVID CODES SVID [6:0] Voltage (V) 000_0000 1.5500 000_0001 1.5375 000_0010 1.5250 000_0011 1.5125 000_0100 1.5000 000_0101 1.4875 000_0110 1.4750 000_0111 1.4625 000_1000 1.4500 000_1001 1.4375 000_1010 1.4250 000_1011 1.4125 000_1100 1.4000 000_1101 1.3875 000_1110 1.3750 000_1111 1.3625 001_0000 1.3500 001_0001 1.3375 001_0010 1.3250 001_0011 1.3125 001_0100 1.3000 001_0101 1.2875 001_0110 1.2750 001_0111 1.2625 001_1000 1.2500 001_1001 1.2375 001_1010 1.2250 001_1011 1.2125 001_1100 1.2000 001_1101 1.1875 001_1110 1.1750 001_1111 1.1625 SVID [6:0] Voltage (V) 010_0000 1.1500 010_0001 1.1375 010_0010 1.1250 010_0011 1.1125 010_0100 1.1000 010_0101 1.0875 010_0110 1.0750 010_0111 1.0625 010_1000 1.0500 010_1001 1.0375 010_1010 1.0250 010_1011 1.0125 010_1100 1.0000 010_1101 0.9875 010_1110 0.9750 010_1111 0.9625 011_0000 0.9500 011_0001 0.9375 011_0010 0.9250 011_0011 0.9125 011_0100 0.9000 011_0101 0.8875 011_0110 0.8750 011_0111 0.8625 011_1000 0.8500 011_1001 0.8375 011_1010 0.8250 011_1011 0.8125 011_1100 0.8000 011_1101 0.7875 011_1110 0.7750 011_1111 0.7625 SVID [6:0] Voltage (V) 100_0000 0.7500 100_0001 0.7375 100_0010 0.7250 100_0011 0.7125 100_0100 0.7000 100_0101 0.6875 100_0110 0.6750 100_0111 0.6625 100_1000 0.6500 100_1001 0.6375 100_1010 0.6250 100_1011 0.6125 100_1100 0.6000 100_1101 0.5875 100_1110 0.5750 100_1111 0.5625 101_0000 0.5500 101_0001 0.5375 101_0010 0.5250 101_0011 0.5125 101_0100 0.5000 101_0101 0.5000 101_0110 0.5000 101_0111 0.5000 101_1000 0.5000 101_1001 0.5000 101_1010 0.5000 101_1011 0.5000 101_1100 0.5000 101_1101 0.5000 101_1110 0.5000 101_1111 0.5000 SVID [6:0] 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0110 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 111_1101 111_1110 111_1111 Voltage (V) 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 0.5000 OFF OFF OFF OFF Table 4 - SVI Send Byte Address Table SVI Address [6:0] + Wr Description 110xx100b Set VID only on Output 1 110xx010b Set VID only on Output 2 110xx110b Set VID on both Output 1 and Output 2 Note: ‘x’ in the above Table 4 means the bit could be either ‘1’ or ‘0’. Page 21 V3.03 IR3521 Over-Current Hiccup Protection after Soft Start The over current limit threshold is set by a resistor connected between OCSETX and VDACX pins. Figure 13 shows the hiccup over-current protection with delay after PGOOD is asserted. The delay is required since over-current conditions can occur as part of normal operation due to load transients or VID transitions. If the IINX pin voltage, which is proportional to the average current plus VDACX voltage, exceeds the OCSETx voltage after PGOOD is asserted, it will initiate the discharge of the capacitor at SS/DELX through the discharge current 47uA. If the over-current condition persists long enough for the SS/DELX capacitor to discharge below the 120mV offset of the delay comparator, the fault latch will be set which will then pull the error amplifier’s output low to stop phase IC switching and will also de-asserting the PGOOD signal. The SS/DEL capacitor will then continue to be discharged by a 4.5 uA current until it reaches 200 mV where the fault latch will reset to allow another soft start cycle to occur. The output current is not controlled during the delay time. If an over-current condition is again encountered during the soft start cycle, the over-current action will repeat and the converter will be in hiccup mode. ENABLE INTERNAL OC DELAY SS/DEL 4.0V 3.92V 3.87V 1.4V EA VOUT PGOOD OCP THRESHOLD IOUT START-UP WITH OUTPUT SHORTED HICCUP OVER-CURRENT PROTECTION (OUTPUT SHORTED) NORMAL START-UP OCP DELAY OVER-CURRENT NORMAL NORMAL PROTECTION START-UP OPERATION POWER-DOWN (OUTPUT SHORTED) (OUTPUT NORMAL OPERATION SHORTED) Figure 13 Hiccup over-current waveforms Linear Regulator Output (VCCL) The IR3521 has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear regulator. The output voltage of the linear regulator can be programmed between 4.75V and 7.5V [?] by the resistor divider at VCCLFB pin. The regulator output powers the gate drivers and other circuits of the phase ICs along with circuits in the control IC, and the voltage is usually programmed to optimize the converter efficiency. The linear regulator can be compensated by a 4.7uF capacitor at the VCCL pin. As with any linear regulator, due to stability reasons, there is an upper limit to the maximum value of capacitor that can be used at this pin and it’s a function of the number of phases used in the multiphase architecture and their switching frequency. Figure 14 shows the stability plots for the linear regulator with 5 phases switching at 750 kHz. For powering the IR3521 and up to two phase ICs an NPN transistor in a SOT-23 package could be used. For a larger number of phase ICs an NPN transistor in DPAK package is recommended. . VCCL voltage must be regulated by a closed control loop based on the IR3521’s VCCL regulator controller in order to keep both VCCLDRV and VCCLFB voltages in the operating points that would support correct UVLO operation. No external power rail can be connected to VCCL pin.” Page 22 V3.03 IR3521 Figure 14 VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz VCCL Under Voltage Lockout (UVLO) The IR3521 does not directly monitor VCC for under voltage lockout but instead monitors the system VCCL supply voltage since this voltage is used for the gate drive. As VCC begins to rise during power up, the VCCLDRV pin will be high impedance therefore allowing VCCL to roughly follow VCC-NPNVBE until VCCL is above 94% of the voltage set by resistor divider at VCCLFB pin. At this point, the OVX and UV CLEARED fault latches will be released. If VCCL voltage drops below 86% of the set value, the SS/DEL CLEARED fault latch will be set. VID OFF Codes SVID OFF codes of 111_1100, 111_1101, 111_1110, and 111_1111 turn off the converter by pulling down EAOUTX voltage and discharging SS/DELX through the 50uA discharge current, but do not drive PGOOD low. Upon receipt of a non-off SVID code the converter will turn on and transition to the voltage represented by the SVID as shown in Figure 10. Power Good (PGOOD) The PGOOD pin is an open-collector output and should have an external pull-up resistor. During soft start, PGOOD remains low until the output voltage is in regulation and SS/DELX is above 3.9V. The PGOOD pin becomes low if ENABLE is low, VCCL is below 86% of target, an over current condition occurs for at least 1024 PHSOUT clocks prior to PGOOD, an over current condition occurs after PGOOD and SS/DELX discharges to the delay threshold, an open phase timing daisy chain condition occurs, VOSNS lines are detected open, VOUTX is 315mV below VDACX, or if the error amp is sensed as operating open loop for 8 PHSOUT cycles. A high level at the PGOOD pin indicates that the converter is in operation with no fault and ensures the output voltage is within the regulation. PGOOD monitors the output voltage. If any of the voltage planes fall out of regulation, PGOOD will become low, but the VR continues to regulate its output voltages. The PWROK input may or may not de-assert prior to the voltage planes falling out of specification. Output voltage out of spec is defined as 315mV to 275mV below nominal voltage. VID on-the-fly transition which is a voltage plane transitioning between one voltage associated with one VID code and a voltage associated with another VID code is not considered to be out of specification. A PWROK de-assert while ENABLE is high results in all planes regulating to the previously stored 2-bit Boot VID. If the 2-bit Boot VID is higher than the VID prior to PWROK de-assertion, this transition will NOT be treated as VID onthe-fly and if either of the two outputs is out of spec high, PGOOD will be pulled down. Page 23 V3.03 IR3521 Open Voltage Loop Detection The output voltage range of error amplifier is continuously monitored to ensure the voltage loop is in regulation. If any fault condition forces the error amplifier output above VCCL-1.08V for 8 PHSOUT switching cycles, the fault latch is set. The fault latch can only be cleared by cycling the power to VCCL. Load Current Indicator Output The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current information can be retrieved by using a differential amplifier to subtract VDAC1 voltage from the VDRP1 voltage. Enable Input Pulling the ENABLE pin below 0.8V sets the Fault Latch. Forcing ENABLE to a voltage above 1.94V results in the pre-PWROK 2 bit VID codes off the SVD and SVC pins to be read and stored. SS/DELX pins are also allowed to begin their power-up cycles. Over Voltage Protection (OVP) Output over-voltage might occur due to a high side MOSFET short or if the output voltage sense path is compromised. If the over-voltage protection comparators sense that either VOUTX pin voltage exceeds VDACX by 260mV, the over voltage fault latch is set which pulls the error amplifier output low to turn off the converter power stage. The IR3521 communicates an OVP condition to the system by raising the ROSC/OVP pin voltage to within V(VCCL) – 1.2 V. An OVP condition is also communicated to the phase ICs by forcing the IIN pin (which is tied to the ISHARE bus and ISHARE pins of the phase ICs) to VCCL as shown in Figure 15. In each phase IC, the OVP circuit overrides the normal PWM operation to ensure the low side MOSFET turn-on within approximately 150ns. The low side MOSFET will remain on until the ISHARE pins fall below V(VCCL) - 800mV. An over voltage fault condition is latched in the IR3521 and can only be cleared by cycling the power to VCCL. During dynamic VID down at light to no load, false OVP triggering is prevented by increasing the OVP threshold to a fixed 1.85V whenever a dynamic VID is detected and the difference between output voltage and the fast internal VDAC is more than 50mV, as shown in Figure 16. The over-voltage threshold is changed back to VDAC+125mV if the difference between output voltage and the fast internal VDAC is less than 50mV. The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-DC or DC-DC converter supplying the multiphase converter will be triggered thus providing effective protection without damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not possible, a fuse can be added in the input supply to the multiphase converter. Page 24 V3.03 IR3521 OUTPUT VOLTAGE (Vout) OVP THRESHOLD VCCL-800 mV IIN (PHASE IC ISHARE) GATEH (PHASE IC) GATEL (PHASE IC) FAULT LATCH ERROR AMPLIFIER OUTPUT (EAOUT) VDAC NORMAL OPERATION OVP CONDITION AFTER OVP Figure 15 - Over-voltage protection during normal operation VID VDAC 1.85V OV THRESHOLD VDAC + 260mV OUTPUT VOLTAGE (VO) VDAC 50mV 50mV NORMAL OPERATION VID DOWN LOW VID VID UP NORMAL OPERATION Figure 16 Over-voltage protection during dynamic VID Page 25 V3.03 IR3521 Open Remote Sense Line Protection If either remote sense line VOSENX+ or VOSENX- is open, the output of Remote Sense Amplifier (VOUTX) drops. The IR3521 continuously monitors the VOUTX pin and if VOUTX is lower than 200 mV, two separate pulse currents are applied to the VOSENX+ and VOSENX- pins to check if the sense lines are open. If VOSENX+ is open, a voltage higher than 90% of V(VCCL) will be present at VOSENX+ pin and the output of Open Line Detect Comparator will be high. If VOSENX- is open, a voltage higher than 400mV will be present at VOSENX- pin and the Open Line Detect Comparator output will be high. With either sense line open, the Open Sense Line Fault Latch will be set to force the error amplifier output low and immediately shut down the converter. SS/DELX will be discharged and the Open Sense Fault Latch can only be reset by cycling the power to VCCL. Open Daisy Chain Protection The IR3521 checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and detects the feedback at PHSIN pin. If no pulse comes back after 32 CLKOUT pulses, the pulse is restarted again. If the pulse fails to come back the second time, the Open Daisy Chain fault is registered, and SS/DELX is not allowed to charge. The fault latch can only be reset by cycling the power to VCCL. After powering up, the IR3521 monitors PHSIN pin for a phase input pulse equal or less than the number of phases detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an Open Daisy Chain fault is registered. Phase Number Determination After a daisy chain pulse is started, the IR3521 checks the timing of the input pulse at PHSIN pin to determine the phase number. Page 26 V3.03 IR3521 APPLICATIONS INFORMATION CVCC8 Q4 VGATE CSIN+ 19 16 VCC GATEL PGND VDDNB+ Q63 11 COUTNB VDDNB- 10 NC1 6 VDDNB SENSE+ 12 VDDNBSEN- VDDNB SENSE- CDRP1 VDD 5-PHASE CONVERTER CVCC12 CSS/DEL1 2 4 RFB11 5 17 18 19 16 Q16 SW U345 GATEH IR3507 BOOST PSI DACIN LGND VCCL PHSIN NC1 CFB1 CIN1 IOUT GATEL 1 PGND CCP11 VCC VDDEA RCP1 CSIN+ NC3 VDAC 17 EAIN ROCSET1 20 CVDAC1 CSIN- NC2 15 CCS8 RCS1 VDDSEN+ CBST2 13 L9 VDD+ COUT 11 Q15 VDD- 6 10 CVCCL14 CLOSE TO POWER STAGE VDD SENSE+ 14 12 RTHERM1 9 26 25 19 18 FB1 VOUT1 VOSNS1+ RDRP12 RVDAC1 16 15 14 20 VDDNBSEN+ L12 RDRP11 3 RFB13 NC2 14 CBST62 13 ROSC CCP12 RFB12 RFB21 PHSIN CIN6 CCS9 RCS6 CVCCL12 CCP21 CFB2 VCCL CLKIN PHSIN CLKOUT PHSOUT 29 27 30 28 VCCL VCCLFB 13 VONSN1- EAOUT1 VOSNS2- VDAC1 OCSET1 EAOUT2 VDDSEN- VDD SENSECVCC7 VDDSEN+ 16 VCC CSIN+ 17 19 20 NC3 EAIN SW U343 GATEH IR3507 BOOST PSI DACIN 10 6 9 PHSIN GATEL VCCL PGND LGND NC1 5 CIN2 IOUT CLKIN 4 PHSOUT 3 8 2 7 1 CSIN- VDDNBSENVDDNBSEN+ 18 VDDSEN- NC2 Q24 15 CCS7 RCS2 14 CBST9 13 L8 12 11 Q23 CVCCL15 16 VCC CSIN+ 17 19 20 NC3 CSIN- EAIN DACIN GATEH BOOST 10 6 9 PHSIN GATEL VCCL PGND LGND NC1 5 U105 IR3507 PSI CLKIN 4 PHSOUT 3 SW 8 2 CIN3 IOUT 7 1 18 CVCC11 NC2 U344 15 CCS12 RCS3 14 CBST7 13 L10 12 11 U318 CVCCL13 16 VCC CSIN+ 17 19 20 NC3 CSIN- EAIN DACIN GATEH BOOST NC2 Q43 15 CCS10 RCS4 14 13 CBST6 L11 12 11 Q44 10 6 9 PHSIN GATEL VCCL PGND LGND NC1 5 U346 IR3507 PSI CLKIN 4 PHSOUT 3 SW 8 2 CIN4 IOUT 7 1 18 CVCC10 CVCCL11 16 VCC 19 18 17 CSIN+ U341 SW U347 GATEH IR3507 BOOST PSI DACIN 10 9 6 GATEL VCCL PHSIN PGND LGND NC1 5 EAIN NC3 4 CIN5 IOUT CLKIN 3 PHSOUT 2 8 1 CSIN- 20 CVCC9 7 RFB22 LGND Q64 15 21 IIN1 OCSET2 CCP22 22 SS/DEL1 VDAC2 BOOST PHSOUT SS/DEL2 GATEH 24 23 VDRP1 IR3521 CONTROL IC IIN2 FB2 8 ENABLE 12 7 ROSC 9 RCP2 6 VRRDY 32 ROCSET2 V2EA VCCLDRV SVC 5 RVDAC2 PSI_L PWROK VOSNS2+ 4 CSS/DEL2 CVDAC2 5 DACIN EPAD SVD VOUT2 ENABLE 3 2 11 1 10 SVD PWROK 31 CLKOUT 4 U311 IR3507 PSI 9 PHSOUT 18 20 3 EAIN NC3 2 PHSIN SVC VDDNB CONVERTER SW CLKIN VDDPWRGD IOUT PHSOUT VDAC2 8 1 CSIN- ISHARE2 17 V2EA CVCCL10 7 RVCCLFB2 8 RVCCLFB1 RVCCLDRV 7 12V NC2 15 14 CCS11 RCS5 CBST8 L7 13 12 11 U342 CVCCL16 Figure 17 IR3521 \ IR3507 Five Phases – One Phase Dual Outputs AMD SVID Converter Page 27 V3.03 IR3521 DESIGN PROCEDURES - IR3521 AND IR3508 CHIPSET IR3521 EXTERNAL COMPONENTS All the output components are selected using one output but suitable for both unless otherwise specified. Oscillator Resistor RRosc The IR3521 generates square wave pulses to synchronize the phase ICs. The switching frequency of the each phase converter equals the PHSOUT frequency, which is set by the external resistor RROSC (use Figure 2 to determine the RROSC value). The CLKOUT frequency equals the switching frequency multiplied by the phase number. Soft Start Capacitor CSS/DEL The Soft Start capacitor CSS/DEL programs four different time parameters: soft start delay time, soft start time, PGOOD delay time and over-current fault latch delay time after PGOOD. SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 11. Once the ENABLE pin rises above 1.65V, there is a soft-start delay time TD1 during which SS/DEL pin is charged from zero to 1.4V. Once SS/DEL reaches 1.4V the error amplifier output is released to allow the soft start. The soft start time, TD2, represents the time during which converter voltage rises from zero to pre-PWROK VID voltage and the SS/DEL pin voltage rises from 1.4V to pre-PWROK VID voltage plus 1.4V. PGOOD delay time TD3 is the time period from VR reaching the pre-PWROK VID voltage to the PGOOD signal assertion. Calculate CSS/DEL based on the required soft start time TD2. C SS / DEL TD 2 * I CHG TD 2 * 50 * 10 6 V pre PWROK V pre PWROK (1) The soft start delay time TD1 and PGOOD delay time TD3 are determined by equation (2) and (3) respectively. TD1 TD 3 C SS / DEL * 1.4 C SS / DEL * 1.4 I CHG 50 * 10 6 C SS / DEL * (3.92 V pre PWROK 1.4) I CHG (2) C SS / DEL * (3.92 V pre PWROK 1.4) (3) 50 * 10 6 Once CSS/DEL is chosen, use equation (4) to calculate the maximum over-current fault latch delay time tOCDEL. t OCDEL C SS / DEL * 0.12 C SS / DEL * 0.12 I DISCHG 47 * 10 6 (4) VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in (5), where ISINK is the VDAC buffer sink current. The resistor RVDAC is used to compensate VDAC circuit and is determined by (6). The up and down slow are equal due to symmetrical sink and source capabilities of the VDAC buffer. Page 28 V3.03 IR3521 CVDAC I SINK SR DOWN RVDAC 0.5 (5) 3.2 10 15 CVDAC 2 (6) Over Current Setting Resistor ROCSET The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (7), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature, TL_MAX, and room temperature, TL_ROOM, respectively. RL _ MAX RL _ ROOM [1 3850 *106 (TL _ MAX TL _ ROOM )] (7) The total input offset voltage (VCS_TOFST), of the phase IC’s current sense amplifier, is the sum of input offset (VCS_OFST) of the amplifier itself and that created by the amplifier input bias current flowing through the current sense resistor RCS. VCS _ TOFST VCS _ OFST I CSIN RCS (8) The over-current limit is set by the external resistor ROCSET as defined in (9). ILIMIT is the required over-current limit. IOCSET is the bias current of OCSET pin and can be calculated with the equation located in the ELECTRICAL CHARACTERISTICS Table. GCS is the gain of the current sense amplifier. KP is the ratio of inductor peak current over the average current in each phase and can be calculated using equation (10). ROCSET [ KP I LIMIT RL _ MAX (1 K P ) VCS _ TOFST ] GCS / I OCSET n (VI VO ) VO /( L VI f SW 2) IO / n (9) (10) VCCL Programming Resistor RVCCLFB1 and RVCCLFB2 Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the MOSFET conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL linear regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor divider. Preselect RVCCLFB1, and calculate RVCCLFB2 from (11). RVCCLFB 2 RVCCLFB1 *1.23 VCCL 1.23 (11) No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor RDRP11 for Output1 Define RFB_R as the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the offset voltage VO_NLOFST (offset above the DAC voltage) and calculating the sink current from the FB1 pin IFB1, using the equation in the ELECTRICAL CHARACTERISTICS Table, the effective offset resistor value, RFB1, can be determined from equation (12). Page 29 V3.03 IR3521 RFB _ R VO _ NLOFST (12) I FB1 Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP, RDRP11 RFB _ R RL _ ROOM * GCS (13) n RO Calculate the desired effective feedback resistor at the maximum temperature RFB_M using (14) RFB _ M RDRP11 RO * n GCS RL _ MAX (14) A negative temperature constant (NTC) thermistor RTHERM1 is required to sense the temperature of the power stage for the inductor DCR thermal compensation. Pre-select the value of RTHERM. RTHERM must be bigger than RFB_R at room temperature but also bigger than RFB_M at the maximum allowed temperature. RTMAX1 is defined as the NTC thermistor resistance at maximum allowed temperature, TMAX. RTMAX1 is calculated from (15). RTMAX 1 RTHERM 1 * EXP[ BTHERM 1 * ( 1 T L _ MAX 1 T _ ROOM (15) )] Select the series resistor RFB13 by using equation (16). RFB13 is incorporated to linearize the NTC thermistor which has non-linear characteristics in the operational temperature range. R FB 13 ( RTHERM 1 RTMAX 1 ) 2 4 * ( RTHERM 1 * RTMAX 1 ( RTHERM 1 RTMAX 1 ) * R FB _ R * R FB _ M /( RFB _ R R FB _ M )) ( RTHERM 1 RTMAX 1 ) 2 Use equation (17) to determine RFB11. 1 1 1 RFB11 RFB _ R RFB13 RTHERM 1 Page 30 (17) V3.03 (16) IR3521 IDD Dynamic OC Limit Capacitor The latest AMD processors require two over current limits: one for normal thermal design current (TDC) operation and the other for system IDD_Spike. TDC over-current is set by following instructions outlined in the Over Current Setting Resistor Rocset section. IDD_Spike occur when the load current exceeds the TDC for a very short duration (10 ms). Figure 18 shows the boundaries of an event. The current over a moving average of 10 ms does not exceed the TDC limit. Higher IDD-Spike will last for a shorter duration. OCP-IDDSpike IDDSpike OCP-TDC Current (A) TDC 1 2 3 4 5 6 Time (ms) 7 8 9 10 Figure 18 Showing IDD_Spike Boundaries The IDD_Spike over current threshold can be implemented by incorporation a properly sized capacitor between the OCSET (18) and the IN1 (21) pins (see Figure 19). Phase IC 1 IOUT Phase IC 2 IOUT High-pass filter IIN CIDDSpike Phase IC 3 IOUT Control IC OCSET1 ROCSET VDAC OCSET comparator R VDAC Phase IC 4 IOUT C VDAC Figure 19 CIDDSpike and ROCSET form a High Pass Filter Page 31 V3.03 IR3521 When a step load is applied, the capacitor acts as a short-circuit, at that instant, and pushes the OCSET signal up by ∆V (i.e. change in IIN) instantaneously. After an increase in its level, the OCP signal starts decaying exponentially towards its original value. The rate of decay is determined by the RC time constant. The VR will enter hiccup mode when the OCSET signal falls below the IIN value. The following equation (18) is use to calculate the ideal capacitor value: t spike _ oc C IDD _ Spike ROC In I spike I OC , (18) I spike I TDC where, tspike_oc = IDD_Spike OC time (choose >1.5ms), Roc = OC resistor (TDC), Ispike = IDD_Spike Max, IOC = TDC OC Threshold, ITDC = Thermal Design Current. The following graph shows a dynamic OC response with tspike set for 1.5ms. tspike_oc IDD_Spike OC Threshold IDD_Spike Boundary OC Threshold TDC Figure X: Figure 20 Showing Dynamic OC Response Page 32 V3.03 IR3521 IR3508 EXTERNAL COMPONENTS Inductor Current Sensing Capacitor CCS and Resistor RCS The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as follows. L RL (19) RCS C CS Bootstrap Capacitor CBST Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is needed for the bootstrap circuit. Decoupling Capacitors for Phase IC 0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs. Page 33 V3.03 IR3521 VOLTAGE LOOP COMPENSATION The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage loop compensation much easier. Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. The selection of compensation types depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or AL-Polymer capacitors and running at lower frequency, type II compensation shown in Figure 21(a) is usually enough. While for the applications using only ceramic capacitors and running at higher frequency, type III compensation shown in Figure 21(b) is preferred. For applications where AVP is not required, the compensation is the same as for the regular voltage mode control. For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency, type III compensation is required as shown in Figure 18(b) with RDRP and CDRP removed. CCP1 CCP1 RFB VO+ RCP VO+ RFB CCP RDRP CFB FB CCP EAOUT FB EAOUT VDRP RFB1 RCP VDAC EAOUT VDRP RDRP VDAC EAOUT + CDRP + (a) Type II compensation (b) Type III compensation Figure 21 Voltage loop compensation network Type II Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, and determine RCP and CCP from (20) and (21), where LE and CE are the equivalent inductance of output inductors and the equivalent capacitance of output capacitors respectively. ( 2 fC ) 2 LE CE RFB 5 (20) RCP VI * 1 (2 * fC * C * RC ) 2 C CP 10 L E C E (21) RCP CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Page 34 V3.03 IR3521 Type III Compensation for AVP Applications Determine the compensation at no load, the worst case condition. Assume the RC, resistor and capacitor across the output inductors, and L/DCR time constant matches, the crossover frequency and phase margin of the voltage loop can be estimated by (22) and (23), where RLE is the equivalent resistance of inductor DCR. f C1 RDRP 2 * CE GCS * RFB RLE C1 90 A tan(0.5) (22) 180 (23) Choose the desired crossover frequency fc around fc1, estimated by (22), or choose fc between 1/10 and 1/5 of the switching frequency per phase. The components should be selected to ensure the close loop gain slope is -20dB /Dec around the crossover frequency. Choose resistor RFB1 according to (24), and determine CFB and CDRP from (25) and (26). 1 R FB 2 R FB1 CFB R FB1 to 2 R FB 3 1 4 fC RFB1 C DRP (24) (25) ( R FB R FB1 ) C FB R DRP (26) RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency and transient load response. Determine RCP and CCP from (27) and (28). RCP C CP ( 2 fC ) 2 LE CE RFB 5 VI (27) 10 L E C E (28) RCP CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic capacitor between 10pF and 220pF is usually enough. Type III Compensation for Non-AVP Applications Resistor RDRP and capacitor CDRP are not needed. Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase margin θc. Calculate K factor from (29), and determine the component values based on (30) to (34), K tan[ ( C 1.5)] 4 180 RCP RFB (29) ( 2 LE CE fC ) 2 5 VI K (30) CCP K 2 fC RCP (31) CCP1 1 2 fC K RCP (32) Page 35 V3.03 IR3521 CFB R FB1 K 2 fC RFB (33) 1 2 f C K C FB (34) CURRENT SHARE LOOP COMPENSATION The internal compensation of current share loop ensures that crossover frequency of the current share loop is at least one decade lower than that of the voltage loop so that the interaction between the two loops is eliminated. Page 36 V3.03 IR3521 DESIGN EXAMPLE – AMD FIVE + ONE PHASE DUAL OUTPUT CONVERTER (FIGURE 17) SPECIFICATIONS Input Voltage: VI=12 V DAC Voltage: VDAC=1.2 V No Load Output Voltage Offset for output1: VO_NLOFST=15 mV Output1 Current: IO1=95 ADC Output2 Current: IO1=20 ADC Output1 Over Current Limit: Ilimit1=115 ADC Output2 Over Current Limit: Ilimit2= 25 ADC Output Impedance: RO1=0.3 mΩ Dynamic VID Slew Rate: SR=3.25mV/uS Over Temperature Threshold: TMAX=110 ºC POWER STAGE Phase Number: n1=5, n2=1 Switching Frequency: fSW=520 kHz Output Inductors: L1=120 nH, L2=220 nH, RL1= 0.52mΩ, RL2= 0.47mΩ Output Capacitors: POSCAPs, C=470uF, RC= 8mΩ, Number Cn1=9, Cn2=5 IR3500 EXTERNAL COMPONENTS Oscillator Resistor RROSC Once the switching frequency is chosen, RROSC can be determined from Figure 2. For switching frequency of 520kHz per phase, choose ROSC=23.2kΩ. Soft Start Capacitor CSS/DEL Determine the soft start capacitor from the required soft start time. C SS / DEL TD 2 * I CHG 2 * 10 3 * 50 * 10 6 0.1uF Vboot 1. 0 The soft start delay time is TD1 C SS / DEL * 1.1 0.1 * 10 6 * 1.1 2.2mS I CHG 50 * 10 6 The PGOOD delay time is TD3 C SS / DEL * (3.92 Vboot 1.1) 0.1 * 10 6 * (3.92 1 1.1) 3.6mS I CHG 50 * 10 6 The maximum over current fault latch delay time is t OCDEL C SS / DEL * 0.12 0.1 * 10 6 * 0.12 0.638mS I DISCHG 47 * 10 6 Page 37 V3.03 IR3521 VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC I 45.2 10 6 CVDAC SINK 14.1nF , Choose CVDAC=22nF SRDOWN 3.2 * 103 RVDAC 0.5 3.2 10 15 CVDAC 2 7.1Ohm Over Current Setting Resistor ROCSET The output1 over current limit is 115A and the output2 over current limit is 25A. From the electrical characteristics table can get the bias current of OCSET pin (IOCSET) is 26uA with ROSC=23.2 kΩ. The total current sense amplifier input offset voltage is around 0mV, Calculate constant KP, the ratio of inductor peak current over average current in each phase, K P1 (VI VO ) VO /( L VI f SW 2) (12 1.2) 1.2 /(120 *109 12 520 *103 2) 0.38 115 / 5 I LIMIT / n (12 1.2) 1.2 /(220 *109 12 520 *103 2) 0.19 25 I ROCSET 1 [ LIMIT R L (1 K P ) VCS _ TOFST ] GCS / I OCSET n KP 2 115 0.52 *10 3 1.38) * 34 /( 26 *10 6 ) 21.6 k 5 I ROCSET 2 [ LIMIT RL (1 K P ) VCS _ TOFST ] GCS / IOCSET n ( ( 25 0.47 *10 3 1.19) * 34 /( 26 *10 6 ) 18.4k 1 VCCL Programming Resistor RVCCLFB1 and RVCCLFB2 Choose VCCL=7V to maximize the converter efficiency. Pre-select RVCCLFB1=20kΩ, and calculate RVCCLFB2. RVCCLFB 2 RVCCLFB1 *1.23 20 *103 *1.23 4.26k VCCL 1.23 7 1.23 No Load Offset Setting Resistor RFB11, RFB13, RTHERM1 and Adaptive Voltage Positioning Resistor RDRP11 for Output1 Define RFB_R is the effective offset resistor at room temperature equals to RFB11//(RFB13+RTHERM1). Given the offset voltage VO_NLOFST above the DAC voltage, calculate the sink current from the FB1 pin IFB1= 26uA using the equation in the ELECTRICAL CHARACTERISTICS Table, then the effective offset resistor value RFB_R1 can be determined by: R FB _ R 1 VO _ NLOFST I FB1 15 *10 3 26 *10 6 577Ohm Adaptive voltage positioning lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter. Pre-select feedback resistor RFB, and calculate the droop resistor RDRP, Page 38 V3.03 IR3521 RDRP1 RFB _ R RL _ ROOM * GCS n RO 577 * 0.52 *103 * 34 6.7 KOhm 5 * 0.3 *103 In the case of thermal compensation is required, use equation (14) to (17) to select the RFB network resistors. IR3508 EXTERNAL COMPONENTS Inductor Current Sensing Capacitor CCS and Resistor RCS Choose CCS1=Ccs2=0.1uF, and calculate RCS, RCS 1 L RL 120 *109 /(0.52 *103 ) 2.3k CCS 0.1*106 RCS 2 L RL 220 *109 /(0.47 *103 ) 4.7k CCS 0.1*10 6 Page 39 V3.03 IR3521 LAYOUT GUIDELINES The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB layout, therefore minimizing the noise coupled to the IC. Dedicate at least one middle layer for a ground plane LGND. Connect the ground tab under the control IC to LGND plane through a via. Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce the noise coupling. Place VCCL decoupling capacitor VCCL as close as possible to VCCL and LGND pins. Place the following critical components on the same layer as control IC and position them as close as possible to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, and CSS/DEL. Avoid using any via for the connection. Place the compensation components on the same layer as control IC and position them as close as possible to EAOUT, FB, VO and VDRP pins. Avoid using any via for the connection. Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes. Avoid analog control bus signals, VDAC, IIN, and especially EAOUT, crossing over the fast transition nodes. Separate digital bus, CLKOUT, PHSOUT and PHSIN from the analog control bus and other compensation components. Page 40 V3.03 IR3521 PCB METAL AND COMPONENT PLACEMENT Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥ 0.2mm to prevent shorting. Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. Center pad land length and width should be equal to maximum part pad length and width. However, the minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥ 0.23mm for 3 oz. Copper) Four 0.30mm diameter vias shall be placed in the center of the pad land and connected to ground to minimize the noise effect on the IC. No pcb traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can cause the IC to rise up from the pcb resulting in poor solder joints to the IC leads. Page 41 V3.03 IR3521 SOLDER RESIST The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads. The minimum solder resist width is 0.13mm. At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of ≥ 0.17mm remains. The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. Four vias in the land pad should be tented or plugged from bottom boardside with solder resist. Page 42 V3.03 IR3521 STENCIL DESIGN The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float and the lead lands will be open. The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. Page 43 V3.03 IR3521 PACKAGE INFORMATION 32L MLPQ (5 x 5 mm Body) θJA =24.4 oC/W, θJC =0.86 oC/W Page 44 V3.03 IR3521 Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. www.irf.com Page 45 V3.03