Revised June 2005
74VCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistors in Outputs
General Description
Features
The VCX162374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP) and output enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
■ 1.4V–3.6V VCC supply operation
The VCX162374 is also designed with 26: series resistors
in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and
bus transceivers/transmitters.
The 74VCX162374 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintaining low CMOS power dissipation.
■ 3.6V tolerant inputs and outputs
■ 26: series resistors in outputs
■ tPD (CLK to O n)
3.4 ns max for 3.0V to 3.6V VCC
■ Power-off high impedance inputs and outputs
■ Supports live insertion and withdrawal (Note 1)
■ Static Drive (IOH/IOL)
r12 mA @ 3.0V VCC
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model ! 2000V
Machine model ! 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74VCX162374MTD
Package
Package Descriptions
Number
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
Output Enable Input (Active LOW)
CPn
Clock Pulse Input
I0–I15
O0–O15
© 2005 Fairchild Semiconductor Corporation
DS500235
Description
Inputs
Outputs
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74VCX162374 Low Voltage 16-Bit D-Type Flip-Flop
January 2000
74VCX162374
Connection Diagram
Truth Tables
Inputs
Outputs
OE1
I0–I7
O0–O7
L
H
H
L
L
L
L
L
X
O0
X
H
X
Z
CP1
Inputs
OE2
I8–I15
O8–O15
L
H
H
L
L
L
L
L
X
O0
X
H
X
Z
CP2
H
L
X
Z
O0
Outputs
HIGH Voltage Level
LOW Voltage Level
Immaterial (HIGH or LOW, inputs may not float)
High Impedance
Previous O0 before HIGH-to-LOW of CP
Functional Description
flop will store the state of their individual I inputs that meet
the setup and hold time requirements on the LOW-to-HIGH
Clock (CPn) transition. With the Output Enable (OEn) LOW,
the contents of the flip-flops are available at the outputs.
When OEn is HIGH, the outputs go to the high impedance
state. Operations of the OEn input does not affect the state
of the flip-flops.
The 74VCX162374 consists of sixteen edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each clock has a buffered clock and buffered Output
Enable common to all flip-flops within that byte. The
description which follows applies to each byte. Each flip-
Logic Diagram
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions (Note 4)
0.5V to 4.6V
0.5V to 4.6V
Supply Voltage (VCC)
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
Outputs 3-STATED
Outputs Active (Note 3)
DC Input Diode Current (IIK) VI 0V
0.5V to 4.6V
0.5V to VCC 0.5V
50 mA
Output Voltage (VO)
Output in Active States
DC Output Diode Current (IOK)
50 mA
50 mA
VO ! VCC
r50 mA
(IOH/IOL)
0.0V to 3.6V
Output Current in IOH/IOL
DC Output Source/Sink Current
DC VCC or GND Current per
Storage Temperature Range (TSTG)
0V to VCC
Output in “OFF” State
VO 0V
Supply Pin (ICC or GND)
1.4V to 3.6V
0.3V to 3.6V
Input Voltage
r100 mA
65qC to 150qC
VCC
3.0V to 3.6V
VCC
2.3V to 2.7V
VCC
1.65V to 2.3V
VCC
1.4V to 1.6V
Free Air Operating Temperature (TA)
r12 mA
r8 mA
r3 mA
r1 mA
40qC to 85qC
Minimum Input Edge Rate ('t/'V)
VIN
0.8V to 2.0V, VCC
3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol
VIH
VIL
Parameter
Conditions
HIGH Level Input Voltage
VCC
(V)
2.7 - 3.6
LOW Level Input Voltage
Min
HIGH Level Output Voltage
1.6
1.65 - 2.3
0.65 x VCC
1.4 - 1.6
0.65 x VCC
2.7 - 3.6
IOH
100 PA
IOH
IOH
V
0.8
2.3 - 2.7
0.7
1.65 - 2.3
0.35 x VCC
V
0.35 x VCC
2.7 - 3.6
VCC - 0.2
6 mA
2.7
2.2
8 mA
3.0
2.4
IOH
12 mA
3.0
2.2
IOH
100 PA
2.3 - 2.7
VCC - 0.2
IOH
4 mA
2.3
2.0
IOH
6 mA
2.3
1.8
IOH
8 mA
IOH
100 PA
IOH
3 mA
IOH
100 PA
IOH
1 mA
3
Units
2.0
2.3 - 2.7
1.4 - 1.6
VOH
Max
2.3
1.7
1.65 - 2.3
VCC - 0.2
1.65
1.25
1.4 - 1.6
VCC - 0.2
1.4
1.05
V
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74VCX162374
Absolute Maximum Ratings(Note 2)
74VCX162374
DC Electrical Characteristics
Symbol
(Continued)
Parameter
VCC
Conditions
Min
Max
Units
(V)
VOL
LOW Level Output Voltage
IOL
100 PA
2.7 - 3.6
0.2
IOL
6 mA
2.7
0.4
IOL
8 mA
3.0
0.55
IOL
12 mA
3.0
0.8
IOL
100 PA
2.3 - 2.7
0.2
IOL
6 mA
2.3
0.4
IOL
8 mA
2.3
0.6
IOL
100 PA
IOL
3 mA
IOL
100 PA
IOL
1 mA
II
Input Leakage Current
0 d VI d 3.6V
IOZ
3-STATE Output Leakage
0 d VO d 3.6V, VI
IOFF
Power-OFF Leakage Current
0 d (VI, VO) d 3.6V
ICC
Quiescent Supply Current
VI
VIH or VIL
VCC or GND
VCC d (VI, VO) d 3.6V (Note 5)
'ICC
Increase in ICC per Input
VIH
VCC 0.6V
1.65 - 2.3
0.2
1.65
0.3
V
1.4 - 1.6
0.2
1.4
0.35
1.4 - 3.6
r5.0
1.4 - 3.6
r10.0
PA
0
10.0
PA
1.4 - 3.6
20.0
1.4 - 3.6
r20.0
2.7 - 3.6
750
PA
PA
PA
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Symbol
fMAX
Parameter
Maximum Clock Frequency
tPHL
Propagation Delay
tPLH
CPn to On
tPZL
Output Enable Time
(Note 6)
VCC
Conditions
CL
30 pF, RL
500:
Output Disable Time
tH
Setup Time
Hold Time
250
2.5 r 0.2
200
1.8 r 0.15
100
2k:
1.5 r 0.1
80
30 pF, RL
500:
3.3 r 0.3
0.8
3.4
2.5 r 0.2
1.0
4.8
1.8 r 0.15
1.5
9.6
1.5 r 0.1
1.0
19.2
CL
15 pF, RL
2k:
CL
30 pF, RL
500:
CL
15 pF, RL
2k:
CL
30 pF, RL
500:
3.3 r 0.3
0.8
3.9
2.5 r 0.2
1.0
5.4
1.8 r 0.15
1.5
9.8
1.5 r 0.1
1.0
19.6
3.3 r 0.3
0.8
4.0
2.5 r 0.2
1.0
4.4
1.8 r 0.15
1.5
7.9
CL
15 pF, RL
2k:
1.5 r 0.1
1.0
15.8
CL
30 pF, RL
500:
3.3 r 0.3
1.5
2.5 r 0.2
1.5
1.8 r 0.15
2.5
CL
15 pF, RL
2k:
1.5 r 0.1
3.0
CL
30 pF, RL
500:
3.3 r 0.3
1.0
15 pF, RL
2k:
4
2.5 r 0.2
1.0
1.8 r 0.15
1.0
1.5 r 0.1
2.0
Units
Figure
Number
ns
15 pF, RL
CL
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3.3 r 0.3
Max
CL
tPHZ
tS
40qC to 85qC
Min
CL
tPZH
tPLZ
TA
(V)
ns
Figures
1, 2
Figures
7, 8
ns
Figures
1, 3, 4
Figures
7, 9, 10
ns
Figures
1, 3, 4
Figures
7, 9, 10
ns
Figures
1, 6
Figures
6, 7
ns
Figures
1, 6
Figures
6, 7
Symbol
tW
Parameter
Pulse Width
Output to Output Skew
tOSLH
(Note 7)
30 pF, RL
500:
3.3 r 0.3
1.5
2.5 r 0.2
1.5
1.8 r 0.15
4.0
4.0
2k:
1.5 r 0.1
CL
30 pF, RL
500:
3.3 r 0.3
2k:
40qC to 85qC
Min
15 pF, RL
15 pF, RL
TA
(V)
CL
CL
Note 6: For CL
VCC
Conditions
CL
tOSHL
(Continued)
Units
Max
Figure
Number
ns
Figures
1, 5
Figures
5, 7
0.5
2.5 r 0.2
0.5
1.8 r 0.15
0.75
1.5 r 0.1
1.5
ns
50PF, add approximately 300 ps to the AC maximum specification.
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
VOLP
VOLV
VOHV
Parameter
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
Conditions
CL
CL
CL
30 pF, VIH
30 pF, VIH
30 pF, VIH
VCC, VIL
VCC, VIL
VCC, VIL
0V
0V
0V
V CC
TA 25qC
(V)
Typical
1.8
0.15
2.5
0.25
3.3
0.35
1.8
0.15
2.5
0.25
3.3
0.35
1.8
1.55
2.5
2.05
3.3
2.65
Units
V
V
V
Capacitance
Symbol
Parameter
Conditions
CIN
Input Capacitance
VCC
COUT
Output Capacitance
VI
0V or VCC, VCC
CPD
Power Dissipation Capacitance
VI
0V or VCC, f
VCC
1.8V, 2.5V or 3.3V, VI
TA 25qC
Typical
Units
0V or VCC
6.0
pF
1.8V, 2.5V or 3.3V
7.0
pF
20.0
pF
10 MHz,
1.8V, 2.5V or 3.3V
5
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74VCX162374
AC Electrical Characteristics
74VCX162374
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC 3.3 r 0.3V;
VCC x 2 at VCC 2.5 r 0.2V; 1.8V r 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 3. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
tREC Waveforms
Symbol
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VCC
3.3V r 0.3V
2.5V r 0.2V
1.8V r 0.15V
Vmi
1.5V
VCC/2
VCC/2
Vmo
1.5V
VCC/2
VCC/2
VX
VOL 0.3V
VOL 0.15V
VOL 0.15V
VY
VOH 0.3V
VOH 0.15V
VOH 0.15V
6
74VCX162374
AC Loading and Waveforms (VCC 1.5V r 0.1V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC
tPZH, tPHZ
1.5 r 0.1V
GND
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V r 0.1V
VCC/2
Vmi
Vmo
VCC/2
VX
VOL 0.1V
VY
VOH 0.1V
7
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74VCX162374 Low Voltage 16-Bit D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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