IRF IRL3714SPBF

PD - 95580
IRL3714PbF
IRL3714SPbF
IRL3714LPbF
SMPS MOSFET
Applications
High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l High Frequency Buck Converters for
Computer Processor Power
l Lead-Free
HEXFET® Power MOSFET
l
VDSS
RDS(on) max
ID
20V
20mΩ
36A
Benefits
l
l
l
Ultra-Low Gate Impedance
Very Low RDS(on) at 4.5V VGS
Fully Characterized Avalanche Voltage
and Current
TO-220AB
IRL3714
D2Pak
IRL3714S
TO-262
IRL3714L
Absolute Maximum Ratings
Symbol
VDS
VGS
ID @ TC
ID @ TC
I DM
PD @TC
PD @TC
= 25°C
= 70°C
= 25°C
= 70°C
TJ , TSTG
Parameter
Drain-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Maximum Power Dissipation ƒ
Maximum Power Dissipation ƒ
Linear Derating Factor
Junction and Storage Temperature Range
Max.
Units
20
± 20
36
31
140
47
33
0.31
-55 to + 175
V
V
A
W
W
W/°C
°C
Thermal Resistance
RθJC
RθCS
RθJA
RθJA
Parameter
Typ.
Max.
Junction-to-Case
Case-to-Sink, Flat, Greased Surface „
Junction-to-Ambient„
Junction-to-Ambient (PCB mount) …
–––
0.50
–––
–––
3.2
–––
62
40
Units
°C/W
Notes  through † are on page 11
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1
07/20/04
IRL3714/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
V(BR)DSS
RDS(on)
VGS(th)
IDSS
IGSS
Min.
20
–––
Static Drain-to-Source On-Resistance –––
–––
Gate Threshold Voltage
1.0
–––
Drain-to-Source Leakage Current
–––
Gate-to-Source Forward Leakage
–––
Gate-to-Source Reverse Leakage
–––
Typ. Max. Units
–––
––– V
0.022 ––– V/°C
15
20
mΩ
21
28
–––
3.0
V
–––
20
µA
–––
100
–––
200
nA
––– -200
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 18A ƒ
VGS = 4.5V, ID = 14A ƒ
VDS = VGS, ID = 250µA
VDS = 16V, VGS = 0V
VDS = 16V, VGS = 0V, TJ = 125°C
VGS = 16V
VGS = -16V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qoss
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Output Gate Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
17
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
6.5
1.8
2.9
7.1
8.7
78
10
4.5
670
470
68
Max. Units
Conditions
–––
S
VDS = 10V, ID = 14A
9.7
ID = 14A
–––
nC VDS = 10V
–––
VGS = 4.5V
–––
VGS = 0V, VDS = 10V
–––
VDD = 10V
–––
ID = 14A
ns
–––
RG = 1.8Ω
–––
VGS = 4.5V ƒ
–––
VGS = 0V
–––
VDS = 10V
–––
pF
ƒ = 1.0MHz
Avalanche Characteristics
Symbol
EAS
IAR
Parameter
Single Pulse Avalanche Energy‚
Avalanche Current
Typ.
Max.
Units
–––
–––
72
14
mJ
A
Diode Characteristics
Symbol
IS
I SM
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
VSD
Diode Forward Voltage
trr
Q rr
trr
Q rr
Reverse
Reverse
Reverse
Reverse
2
Recovery
Recovery
Recovery
Recovery
Time
Charge
Time
Charge
Min. Typ. Max. Units
–––
36
A
––– 140
–––
–––
–––
–––
–––
–––
––– 1.3
0.88 –––
35
53
34
51
35
53
35
53
V
ns
nC
ns
nC
Conditions
D
MOSFET symbol
showing the
G
integral reverse
S
p-n junction diode.
TJ = 25°C, IS = 18A, VGS = 0V ƒ
TJ = 125°C, IS = 18A, VGS = 0V ƒ
TJ = 25°C, IF = 18A, VR=10V
di/dt = 100A/µs ƒ
TJ = 125°C, IF = 18A, VR=10V
di/dt = 100A/µs ƒ
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IRL3714/S/LPbF
10000
1000
VGS
15V
10V
4.5V
3.0V
2.7V
2.5V
2.2V
BOTTOM 2.0V
VGS
15V
10V
4.5V
3.0V
2.7V
2.5V
2.2V
BOTTOM 2.0V
TOP
1000
100
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
10
1
2.0V
0.1
100
10
2.0V
1
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
0.1
0.01
0.1
1
10
0.1
100
1
100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.5
1000.00
I D = 36A
T J = 25°C
100.00
TJ = 175°C
10.00
VDS = 15V
20µs PULSE WIDTH
1.00
2.0
4.0
6.0
8.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10.0
(Normalized)
2.0
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α)
10
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL3714/S/LPbF
10000
15
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
VDS = 16V
VDS = 10V
12
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
Coss = Cds + Cgd
1000
Ciss
Coss
100
Crss
ID = 14
9
6
3
10
0
1
10
0
100
4
8
12
16
20
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000.00
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
T J = 175°C
100.00
100
10.00
T J = 25°C
1.00
100µsec
10
1msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.10
0.0
1.0
2.0
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
10msec
1
3.0
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL3714/S/LPbF
40
RD
V DS
I D , Drain Current (A)
V GS
D.U.T.
30
RG
20
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
+
-V DD
4.5V
Fig 10a. Switching Time Test Circuit
VDS
10
90%
0
25
50
75
100
TC , Case Temperature
125
150
( °C)
175
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC)
10
D = 0.50
1
Thermal Response
0.20
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P DM
0.1
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+TC
0.1
1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRL3714/S/LPbF
150
ID
15V
D.U.T
RG
+
V
- DD
IAS
20V
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
E AS , Single Pulse Avalanche Energy (mJ)
VDS
120
DRIVER
L
TOP
5.9A
BOTTOM
10A
14A
90
60
30
0
25
50
75
100
125
150
175
( °C)
Starting T , Junction
Temperature
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
4.5 V
50KΩ
12V
.2µF
.3µF
QGS
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRL3714/S/LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
V DD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
*
ISD
VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRL3714/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
4- DRAIN
14.09 (.555)
13.47 (.530)
1.40 (.055)
1.15 (.045)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2
DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- EMITTER
3- SOURCE
4 - DRAIN
HEXFET
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T H IS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T HE AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
RE CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
8
P AR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
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IRL3714/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IR F530S WITH
LOT CODE 8024
AS S E MBL ED ON WW 02, 2000
IN T HE AS S EMB LY LINE "L "
INT E RNATIONAL
RE CT IF IER
LOGO
Note: "P" in as s embly line
pos ition indicates "L ead-F ree"
PAR T NUMB ER
F 530S
AS S EMBL Y
L OT CODE
DAT E CODE
YEAR 0 = 2000
WEE K 02
L INE L
OR
INT ERNAT IONAL
RECT IF IE R
L OGO
AS S E MB LY
LOT CODE
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PART NUMB ER
F 530S
DAT E CODE
P = DES IGNAT ES L EAD-F REE
PRODUCT (OPT IONAL)
YEAR 0 = 2000
WEEK 02
A = AS S EMB LY S IT E CODE
9
IRL3714/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
E XAMPLE : T HIS IS AN IRL 3103L
LOT CODE 1789
AS S E MB LE D ON WW 19, 1997
IN T HE AS S E MBL Y L INE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RE CT IF IE R
L OGO
AS S E MBL Y
L OT CODE
PART NUMB ER
DAT E CODE
YEAR 7 = 1997
WE EK 19
L INE C
OR
INT E RNAT IONAL
RE CT IF IE R
L OGO
AS S E MBL Y
L OT CODE
10
PART NUMB ER
DAT E CODE
P = DE S IGNAT ES LE AD-F REE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WE EK 19
A = AS S E MBL Y S IT E CODE
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IRL3714/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 0.69 mH
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ This is only applied to TO-220AB package
RG = 25Ω, I AS = 14A.
… This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
These products have been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.07/04
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11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/