PD - 95380
IRL3715PbF
IRL3715SPbF
IRL3715LPbF
SMPS MOSFET
Applications
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l High Frequency Buck Converters for
Computer Processor Power
l Lead-Free
HEXFET® Power MOSFET
VDSS
RDS(on) max
ID
20V
14mΩ
54A
Benefits
l
l
l
Ultra-Low Gate Impedance
Very Low RDS(on) at 4.5V VGS
Fully Characterized Avalanche Voltage
and Current
TO-220AB
IRL3715
D2Pak
IRL3715S
TO-262
IRL3715L
Absolute Maximum Ratings
Symbol
VDS
VGS
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
PD @TA = 25°C
TJ , TSTG
Parameter
Drain-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Maximum Power Dissipation
Maximum Power Dissipation
Linear Derating Factor
Junction and Storage Temperature Range
Max.
Units
20
± 20
54
38
210
71
3.8
0.48
-55 to + 175
V
V
A
W
W
W/°C
°C
Thermal Resistance
RθJC
RθCS
RθJA
RθJA
Parameter
Typ.
Max.
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Junction-to-Ambient (PCB mount)
–––
0.50
–––
–––
2.1
–––
62
40
Units
°C/W
Notes through are on page 11
www.irf.com
1
06/07/04
IRL3715/S/LPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
V(BR)DSS
RDS(on)
VGS(th)
IDSS
IGSS
Min.
20
–––
–––
Static Drain-to-Source On-Resistance
–––
Gate Threshold Voltage
1.0
–––
Drain-to-Source Leakage Current
–––
Gate-to-Source Forward Leakage
–––
Gate-to-Source Reverse Leakage
–––
Typ.
–––
0.022
11
15
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
14
VGS = 10V, ID = 26A
mΩ
20
VGS = 4.5V, ID = 21A
3.0
V
VDS = VGS, ID = 250µA
20
VDS = 16V, VGS = 0V
µA
100
VDS = 16V, VGS = 0V, TJ = 125°C
200
VGS = 16V
nA
-200
VGS = -16V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qoss
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Output Gate Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
26
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
11
3.8
4.4
11
6.4
73
12
5.1
1060
700
120
Max. Units
Conditions
–––
S
VDS = 10V, ID = 21A
17
ID = 21A
–––
nC
VDS = 10V
–––
VGS = 4.5V
17
VGS = 0V, VDS = 10V
–––
VDD = 10V
–––
ID = 21A
ns
–––
RG = 1.8Ω
–––
VGS = 4.5V
–––
VGS = 0V
–––
VDS = 10V
–––
pF
ƒ = 1.0MHz
Avalanche Characteristics
Symbol
EAS
IAR
Parameter
Single Pulse Avalanche Energy
Avalanche Current
Typ.
Max.
Units
–––
–––
110
21
mJ
A
Diode Characteristics
Symbol
IS
ISM
VSD
trr
Qrr
trr
Qrr
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse
Reverse
Reverse
Reverse
Recovery
Recovery
Recovery
Recovery
Time
Charge
Time
Charge
Min. Typ. Max. Units
–––
–––
54
–––
–––
210
–––
–––
–––
–––
–––
–––
0.9
0.8
37
28
38
30
1.3
–––
56
42
57
45
A
V
ns
nC
ns
nC
Conditions
D
MOSFET symbol
showing the
G
integral reverse
S
p-n junction diode.
TJ = 25°C, IS = 21A, VGS = 0V
TJ = 125°C, IS = 21A, VGS = 0V
TJ = 25°C, IF = 21A, VR=20V
di/dt = 100A/µs
TJ = 125°C, IF = 21A, VR=20V
di/dt = 100A/µs
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IRL3715/S/LPbF
1000
1000
VGS
15V
10V
4.5V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
100
10
2.5V
1
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
100
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
TJ = 25 ° C
TJ = 175 ° C
V DS = 15V
20µs PULSE WIDTH
4.0
5.0
6.0
7.0
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
2.5
VGS , Gate-to-Source Voltage (V)
1
VDS , Drain-to-Source Voltage (V)
1000
3.0
20µs PULSE WIDTH
TJ = 175 °C
1
0.1
100
Fig 1. Typical Output Characteristics
100
2.5V
10
VDS , Drain-to-Source Voltage (V)
10
2.0
VGS
15V
10V
4.5V
3.5V
3.3V
3.0V
2.7V
BOTTOM 2.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
8.0
ID = 52A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRL3715/S/LPbF
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
Ciss
1000
Coss
Crss
100
14
VGS , Gate-to-Source Voltage (V)
10000
10
8
6
4
2
0
10
100
FOR TEST CIRCUIT
SEE FIGURE 13
0
5
15
20
25
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
TJ = 175 ° C
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
10
QG , Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
10
100
1
TJ = 25 ° C
0.1
0.2
V GS = 0 V
0.7
1.2
1.7
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 16V
VDS = 10V
12
10
1
ID = 21A
2.2
100µsec
10
1msec
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRL3715/S/LPbF
60
V DS
LIMITED BY PACKAGE
VGS
ID , Drain Current (A)
50
RD
D.U.T.
RG
+
-VDD
40
4.5V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
30
20
Fig 10a. Switching Time Test Circuit
VDS
10
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.02
0.01
0.1
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
0.01
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
VGS
20V
tp
A
0.01Ω
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
EAS , Single Pulse Avalanche Energy (mJ)
IRL3715/S/LPbF
240
TOP
200
BOTTOM
ID
8.5A
15A
21A
160
120
80
40
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
4.5 V
50KΩ
12V
.2µF
.3µF
QGS
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRL3715/S/LPbF
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
+
-
-
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
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7
IRL3715/S/LPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113)
2.62 (.103)
10.54 (.415)
10.29 (.405)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
4- DRAIN
14.09 (.555)
13.47 (.530)
1.40 (.055)
1.15 (.045)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2 - DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- EMITTER
3- SOURCE
4 - DRAIN
HEXFET
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
L OT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y L INE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
8
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
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IRL3715/S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
INT ERNATIONAL
RECTIFIER
LOGO
Note: "P" in assembly line
position indicates "Lead-Free"
PART NUMBER
F530S
ASSEMBLY
LOT CODE
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
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PART NUMBER
F530S
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 0 = 2000
WEEK 02
A = ASSEMBLY SITE CODE
9
IRL3715/S/LPbF
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
ASS EMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
10
PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPT IONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S IT E CODE
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IRL3715/S/LPbF
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
1.65 (.065)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is only applied to TO-220A package
Starting TJ = 25°C, L = 0.51mH
RG = 25Ω, IAS = 21A,VGS=10V
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Calculated continuous current based on maximum allowable junction temperature.
Package limitation current is 30A.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.06/04
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11
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/