Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface SDA 2546-5 Preliminary Data MOS IC Features ● Word-organized reprogrammable nonvolatile memory ● ● ● ● ● ● ● ● in n-channel floating-gate technology (E2PROM) 512 × 8-bit organization Supply voltage 5 V Serial 2-line bus for data input and output (I2C Bus) Reprogramming mode, 10 ms erase/write cycle Reprogramming by means of on-chip control (without external control) The end of the programming cycle can be checked Data retention in excess of 10 years More than 104 reprogramming cycles per address P-DIP-8-1 Type Ordering Code Package SDA 2546-5 Q67100-H5096 P-DIP-8-1 Circuit Description I2C Bus Interface The I2C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits. It consists of a data line SDA and a clock line SCL. The data line requires an external pull-up resistor to VCC (open drain output stages). The possible operational states of the I2C Bus are shown in figure 1. In the quiescent state, both lines SDA and SCL are high, i.e. the output states are disabled. As long as SCL remains "1", information changes on the data bus indicate the start or the end of a data transfer between two components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" a stop condition. During a data transfer the information on the data bus will only change when the clock line SCL is "0". The information on SDA is valid as long as SCL is "1". In conjunction with an I2C Bus system, the device can operate as a receiver, and as a transmitter (slave receiver/listener, or slave transmitter/talker). Between the falling edge of the eighth transmission pulse and a ninth acknowledge clock pulse, the device sets the SDA-line to low as a reception confirmation, if the chip select conditions have been met. During the output of data, the data output of the memory becomes high, during the ninth clock pulse (acknowledge master). The signal timing required for the operation of the I2C Bus is summarized in figure 2. Semiconductor Group 29 07.94 SDA 2546-5 Control Functions of the I2C Bus The device is controlled by the controller (master) via I2C Bus in two operating modes: real cycle, and reprogramming cycle, including erase and write to a memory address. In both operating modes, the controller, as transmitter, has to provide 3 bytes to the bus after the start condition. Each byte has to be followed by an acknowledge bit. During a memory read, at least eight additional clock pulses are required to accept the data from the memory, before the stop condition may follow. In the programming case, the active programming process is only started by the stop condition after data input, see figure 3. The chip select word includes the chip select bit CS. Thus is possible to parallel two memory devices. Chip select is obtained when the control bits logically correspond to the condition selected at the select input CS. The most significant bits A8 and A9 are inputs with the chip select words CS/E. Checking the End of the Programming Cycle and Breaking off the Programming Cycle Addressing the chip by the input of CS/E during active reprogramming terminates the programming cycle. If the chip is addressed by entering CS/A, this will be ignored. Only when the programming cycle has terminated will the chip react on CS/A. With this procedure the end of the programming cycle can be checked, see figure 3. Memory Read After the input of the two control words CS/E and WA, the resetting of the start condition and the input of a third control word CS/A, the memory is set ready to read. During acknowledge clock no. 9, the memory information is transferred in parallel to the internal data register. Subsequent to the falling edge of the acknowledge clock, the data output is low-impedance and the first data bit can be sampled, see figure 4. With each shift clock, an additional bit reaches the output. After reading a byte, the internal address counter is automatically incremented through the master receiver acknowledge, so that any number of memory locations can be read one after the other. At address 512, an overflow to address 0 is not initiated. With the stop condition, the data output returns to high-impedance mode. The internal sequence control of the memory component is reset from the read to the quiescent with the stop condition. Semiconductor Group 30 SDA 2546-5 Memory Reprogramming The reprogramming cycle of a memory word comprises an erase and a subsequent write process. During erase, all eight bits of the selected word are set into "1" state. During the write process, "0" states are generated according to the information in the internal data register, i.e. according to the third input control word. After the 27th and the last clock of the control word input, the active programming process is started by the stop condition. The active reprogramming process is executed under on-chip control and can be terminated by addressing the device via SCL and SDA. The time required for reprogramming depends on component deviation and data patterns. Therefore, with rated supply voltage the erase/write process is max. 20 ms, or typically, 10 ms. For the input of a data word without write request (write request is defined as data bit in the data register set to "0"), the write process is suppressed and the programming time is shortened. During a subsequent programming of an already erased memory address, the erase process is suppressed again, so that the reprogramming time is also shortened. Switch-On and Chip Reset After the supply voltage VCC has been connected, the data output will be in the high impedance mode. As a rule, the first operating mode to be entered should be the read process of a word address. Subsequent to the data output and to the stop condition, the internal control logic is reset. In case of a subsequent active programming operation, however, the stop condition will not reset the control logic. Chip Erase To erase the entire memory the control word CS/E is entered, the address register is loaded with address 0 and the data register with FF (hex), respectively. Immediately prior to generating the stop condition, the input TP2 is connected from 0 to 5 V. The subsequent stop condition initiates the chip erase. As soon as the erase procedure has terminated, TP2 is again connected to 0 V. Semiconductor Group 31 SDA 2546-5 Pin Configuration (top view) Pin Definitions and Functions Pin No. Symbol Function 1 VSS Ground 2 CS Chip select 3 TP1 to VSS 4 TP2 0 V normal function, TP2 = 5 V condition for the erase of the complete memory 5 SDA Data line 6 SCL Clock line 7 TP3 open 8 VCC Supply voltage Semiconductor Group 32 SDA 2546-5 Block Diagram Semiconductor Group 33 SDA 2546-5 Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Supply voltage VCC – 0.3 6 V Input voltage VI – 0.3 6 V Power dissipation PD 130 mW Storage temperature Tstg 125 ˚C Thermal resistance (system-air) R th SA 100 K/W Junction temperature Tj 85 ˚C – 40 Operating Range Supply voltage VCC 4.75 5.25 V Ambient temperature TA 0 70 ˚C Semiconductor Group 34 SDA 2546-5 Characteristics TA = 25 ˚C Parameter Symbol Limit Values Unit min. typ. max. 4.75 5.0 5.25 V Test Condition Supply voltage VCC Supply current ICC 20 mA Input voltages SDA/SCL VIL 1.5 V Input voltages SDA/SCL VIH VCC V Input currents SDA/SCL IIH 10 µA VIH = VCC Output current SDA IQL 3.0 mA VQL = 0.4 V Leakage current SDA IQH 10 µA VQH = VCC max Input voltages CS/TP1/TP2 VIL 0.2 V Input voltages CS/TP1/TP2 VIH VCC V Input currents CS/TP1/TP2 IIH 100 µA Clock frequency fSCL 100 kHz Reprogramming duration tPROG 20 ms Input capacity CI 10 pF Total erase tGL 20 ms VCC = 5.25 V Inputs 3.0 Outputs Inputs Semiconductor Group 4.5 10 35 VCC = 5.25 V erase and write TP2 = 5 V SDA 2546-5 Test Circuit Application Circuit Semiconductor Group 36 SDA 2546-5 Diagrams Figure 1 Operational States of the I2C Bus Figure 2 Timing Conditions for the I2C Bus (high-speed mode) Semiconductor Group 37 SDA 2546-5 Timing Conditions Parameter Symbol Limit Values min. Unit max. Minimum time the bus must be free before a new transmission can start tBUF 4.7 µs Start condition hold time tHD; STA 4.0 µs Clock low period tLOW 4.7 µs Clock high period tHIGH 4.0 µs Start condition set-up time, only valid for repeated start code tSU; STA 4.7 µs Data set-up time tSU; DAT 250 ns Rise time of both the SDA- and SCL-line tR 1 µs Fall time of both the SDA- and SCL-line tF 300 ns Stop condition set-up time tSU; SPO 4.7 µs Note that a transmitter must internally provide at least a hold time to bridge the undefined region (max. 300 ns) of the falling edge of SCL. All values refer to VIH and VIL level. Semiconductor Group 38 SDA 2546-5 Figure 3 Programming Control word input ST CS/E As WA As DE As SP (the reprogramming starts after this stop condition) Check for program end by ST CS/A As 1. when As = 1 programming is not finished 2. when As = 0 programming is finished Program interruption by ST CS/E As Am DA Am SP Am SP Figure 4 Read Control word input read a) complete (with word address input) ST CS/E As WA As ST CS/A As DA n bytes Last byte Automatic incrementation of the word address b) shortened: Bit 0 … 8 the last adapted word address keep unchanged ST CS/A As DA n bytes Autoincrement before stop condition Semiconductor Group 39 Am DA Last byte Am = 0 Am = 1 SDA 2546-5 Control Word Table Clock No. 1 2 3 4 5 6 7 8 9 (Acknowledge) CS/E CS/A WA DE DA 1 1 A7 D7 D7 0 0 A6 D6 D6 1 1 A5 D5 D5 0 0 A4 D4 D4 0 – A3 D3 D3 A8 – A2 D2 D2 CS CS A1 D1 D1 0 1 A0 D0 D0 0 0 0 0 0/1 through memory through memory through memory through memory through master Control Word Input Key CS/E Chip select for data input into memory (with the word-address-bit A8) CS/A Chip select for data output out of memory WA Memory word address DE Data word for memory DA Data word read out of memory D0 to D7 Data bits ST Start condition SP Stop condition As Acknowledge bit from memory Am Acknowledge bit from master CS Chip select bits A0 to A8 Memory word address bits Semiconductor Group 40