INFINEON SDA5648

Decoder for Program Delivery
Control and Video Program System
PDC / VPS Decoder
SDA 5648
SDA 5648X
CMOS IC
Features
● Single-chip receiver for PDC data, broadcast either
●
●
●
●
●
●
●
●
●
●
●
– in Broadcast Data Service Packet (BDSP) 8/30/2
according to CCIR teletext system B, or
– in dedicated line no. 16 of the vertical blanking interval
(VPS)
Reception of Unified Date and Time (UDT) broadcast in
BDSP 8/30/1
Low external components count
On-chip data and sync slicer
I2C-Bus interface for communication with external
microcontroller
Selection of PDC/VPS operating mode software controlled
by I2C-Bus register
Pin and software compatible to VPS Decoder SDA 5642
Supply voltage: 5 V ± 10 %
Video input signal level: 0.7 Vpp to 1.4 Vpp
Technology: CMOS
Package: P-DIP-14-3 and P-DSO-20-1
Operating temperature range: 0 to 70 °C
P-DIP-14-3
P-DSO-20-1
Type
Ordering Code
Package
SDA 5648
Q67000-A5186
P-DIP-14-3
SDA 5648X
Q67006-A5198
P-DSO-20-1 Tape & Reel
Functional Description
The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data
of the PDC system from the data lines broadcast during the vertical blanking interval of a standard
video signal.
The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet
(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data
line no. 16 in the case of VPS.
Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes
no. 15 through 21 of packet 8/30 format 1.
Semiconductor Group
21
12.94
SDA 5648
SDA 5648X
Pin Configuration
(top view)
P-DIP-14-3
P-DSO-20-1
Operating mode (PDC/VPS) is selected by a control register which can be written to via the I2C-Bus
interface.
Semiconductor Group
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SDA 5648
SDA 5648X
Pin Definitions and Functions
Pin No.
Pin No.
Symbol
P-DIP-14-3 P-DSO-20-1
Function
VSS
Ground (0 V)
1
VSSA
Analog ground (0 V)
2
VSSD
Digital ground (0 V)
3
N.C.
Not connected
2
4
SCL
Serial clock input of I2C-Bus.
3
5
SDA
Serial data input of I2C-Bus.
4
6
CS0
Chip select input determining the I2C-Bus addresses:
20H / 21H, when pulled low
22H / 23H, when pulled high.
5
7
VCS
Video Composite Sync output from sync slicer used for
PLL based clock generation.
8
N.C.
Not connected
6
9
DAVN
Data available output active low, when PDC/VPS data
is received.
7
10
EHB
Output signaling the presence of the first field active
high.
8
11
TI
Test input; activates test mode when pulled high.
9
12
PD1
Phase detector/charge pump output of data PLL
(DAPLL).
13
N.C.
Not connected
10
14
PD2/VCO2 Connector of the loop filter for the SYSPLL.
11
15
VCO1
Input to the voltage controlled oscillator #1 of the
DAPLL.
12
16
IREF
Reference current input for the on-chip analog circuit.
13
17
CVBS
Composite video signal input.
18
N.C.
Not connected
VDD
Positive supply voltage (+ 5 V nom.).
19
VDDD
Positive supply voltage for the digital circuits
(+ 5 V nom.).
20
VDDA
Positive supply voltage for the analog circuits
(+ 5 V nom.).
1
14
Semiconductor Group
23
SDA 5648
SDA 5648X
Block Diagram
Semiconductor Group
24
SDA 5648
SDA 5648X
Circuit Description
Referring to the functional block diagram of the PDC / VPS decoder, the composite video signal with
negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for
clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the
slicer, an analog circuitry separating the sync and the data parts of the CVBS signal, thus yielding
the digital composite sync signal VCS and a digital data signal for further processing by comparing
those signals to internally generated slicing levels.
The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other
hand, to the clock generator and the Timing block. The VCS signal represents a key signal that is
used for deriving a system clock signal by means of a PLL.
The data slicer separates the data signal from the CVBS signal by comparing the video voltage to
an internally generated slicing level which is found by averaging the data signal during TV line no.
16 in the VPS mode or by averaging the data signal during the clock run-in period of the teletext
lines during the data entry window (DEW) in PDC mode.
The clock generator delivers the system clock needed for the basic timing as well as for the
regeneration of the data clock. It is based on two phase locked loops (PLL’s) all parts of which are
integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed
of a voltage controlled oscillator (VCO), a phase/frequency detector (PFD), and a charge pump
which converts the digital output signals of the PFD to an analog current. That current is
transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO frequencies are 10 MHz and 13.875 MHz for VPS mode and PDC mode, respectively.
All signals necessary for the control of sync and data slicing as well as for the data acquisition are
generated by the Timing block.
In PDC mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) information are acquired. The relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are
extracted. The 8/30/1-bytes are stored in the acquisition register in a transparent way without any
bit manipulation, whereas the Hamming coded bytes of packet 8/30/2 are Hamming-checked and
bytes with one bit error are corrected. The storage of error free or corrected 8/30/2-data bytes in the
transfer register to the I2C-Bus is signalled by the DAVN output going low. The reception and
storage of 8/30/1- data, however, is not indicated by the DAVN output. The presence of 8/30/1 data
can only be checked by polling the data register via the I2C-Bus.
In VPS mode, the extracted data bits of TV line no. 16 are checked for biphase errors. With no
biphase errors encountered, the acquired bytes are stored in the transfer register to the I2C-Bus.
That transfer is signalled by a H/L transition of the DAVN output, as well.
In both operating modes data are updated when a new data line has been received, provided that
the chip is not accessed via the I2C-Bus at the same time.
A micro controller can read the stored bytes via the I2C-Bus interface at any time. However, one
must be aware that the storage of new data from the acquisition interface is inhibited as long as the
PDC decoder is being accessed via the I2C-Bus. At the end of an I2C-Bus reading the transfer
registers are set to FF (hex) until they are updated by the reception of new data packet contained
in the CVBS signal.
Semiconductor Group
25
SDA 5648
SDA 5648X
I2C-Bus
General Information
The I2C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i.e., both
reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only
by the bus master usually being a micro controller, whereas the SDA line is controlled either by the
master or by the slave. A data transfer can only be initiated by the bus master when the bus is free,
i.e., both SDA and SCL lines are in a high state. As a general rule for the I2C-Bus, the SDA line
changes state only when the SCL line is low. The only exception to that rule are the Start Condition
and the Stop Condition. Further details are given below. The following abbreviations are used:
START :
AS :
AM :
NAM :
STOP :
Start Condition generated by master
Ackknowledge by slave
Ackknowledge by master
No Ackknowledge by master
Stop Condition generated by master
Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the
following table
CS0 Input
Write Mode
Read Mode
Low
20 (hex)
21 (hex)
High
22 (hex)
23 (hex)
Write Mode
For writing to the PDC decoder, the following format has to be used:
START
Chipadress White Mode
AS
Byte Set Control Register
AS
STOP
Data Transfer (Write Mode)
Step1: In order to start a data transfer the master generates a Start Condition on the bus by pulling
the SDA line low while the SCL line is held high.
Step 2: The bus master puts the chip address on the SDA line during the next eight SCL pulses.
Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate
an acknowledge (AS) by pulling the SDA line to a low level.
Step 4: The controller transmits the data byte to set the Control register.
Step 5: The slave acknowledges the reception of the byte.
Step 6: The master concludes the data communication by generating a Stop Condition.
The write mode is used to set the I2C-Bus control register which determines the operating mode:
Semiconductor Group
26
SDA 5648
SDA 5648X
Control Register
Bit Number
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
DIS
PDC/
VPS
FOR1/
FOR2
Default: All bits are set to 0 on power-up.
Bit 0:
Determines, which kind of data is accessed via the I2C-Bus when PDC mode is active.
Value
0
1
BDSP
8/ 30/ 2
data accessible
BDSP 8/ 30/ 1 or
header row
data accessible (refer to description of Bit 2)
Bit 1:
Determines the operating mode.
Value
0
1
VPS mode active
PDC mode active
Bits 2 through 7 are used for test purposes.
DIS: Don‘t care.
Bits 3 through 7 must not be changed for normal operation by user software!
Read Mode
For reading from the PDC decoder, the following format has to be used.
START
Chipaddress Read Mode
Semiconductor Group
AS
1st Byte
27
AM
…
Last
Byte
NAM
STOP
SDA 5648
SDA 5648X
Data Transfer (Read Mode)
Step1: To start a data transfer the master generates a Start Condition on the bus by pulling the
SDA line low while the SCL line is held high. The byte address counter in the decoder is
reset and points to the first byte to be output.
Step 2: The bus master puts the chip address on the SDA line during the next eight SCL pulses.
Step 3: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate
an acknowledge (AS) by pulling the SDA line to a low level. At this moment, the slave
switches to transmitting mode.
Step 4: During the next eight clock pulses the slave puts the addressed data byte onto the SDA
line.
Step 5: The reception of the byte is acknowledged by the master device which, in turn, pulls down
the SDA line during the next SCL clock pulse. By acknowledging a byte, the master
prompts the slave to increment its internal address counter and to provide the output of the
next data byte.
Step 6: Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read.
Step 7: The last byte is output by the slave since it will not be acknowledged by the master.
Step 8: To conclude the read operation, the master doesn’t acknowledge the last byte to be
received. A No Acknowledge by the master (NAM) causes the slave to switch from
transmitting to receiving mode. Note that the master can prematurely cease any reading
operation by not acknowledging a byte.
Step 9: The master gains control over the SDA line and concludes the data transfer by generating
a Stop Condition on the bus, i. e., by producing a low/high transition on the SDA line while
the SCL line is in a high state. With the SDA and the SCL lines being both in a high state,
the I2C-Bus is free and ready for another data transfer to be started.
The contents of up to 7 registers (bytes) can be read starting with byte 1 bit 7 (refer to the following
table).
Semiconductor Group
28
SDA 5648
SDA 5648X
Order of Data Output on the I2C-Bus and Bit Allocation of the 3 Different Operating Modes
I2C-Bus
PDC Packet 8/30
Format 1
t
VPS Mode
Format 2
Byte 1
bit 7
6
5
4
3
2
1
0
byte 15
bit 02) byte 16
1
2
3
4
byte 17
5
6
7
bit 01) byte 11
1
2
3
bit 0
1
2
3
bit 02)
1
2
3
4
5
6
7
Byte 2
bit 7
6
5
4
3
2
1
0
byte 16
bit 0
1
2
3
4
5
6
7
byte 18
bit 0
1
2
3
bit 0
1
2
3
byte 12
bit 0
1
2
3
4
5
6
7
bit 7
6
5
4
3
2
1
0
byte 17
bit 0
1
2
3
4
5
6
7
byte 20
bit 0
1
2
3
bit 0
1
2
3
byte 13
bit 0
1
2
3
4
5
6
7
bit 7
6
5
4
3
2
1
0
byte 18
bit 0
1
2
3
4
5
6
7
byte 22
bit 0
1
2
3
bit 0
1
2
3
byte 14
bit 0
1
2
3
4
5
6
7
Byte 3
Byte 4
byte 19
byte 21
byte 23
1) Message bit numbers according to EBU specification of PDC system.
2) Transmission bit number
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SDA 5648
SDA 5648X
Order of Data Output on the I2C-Bus and Bit Allocation of the 3 Different Operating Modes
(cont’d)
I2C-Bus
PDC Packet 8/30
Format 1
Byte 5
Byte 6
Byte 7
bit 7
6
5
4
3
2
1
0
byte 19
bit 7
6
5
4
3
2
1
0
byte 20
bit 7
6
5
4
3
2
1
0
byte 21
Semiconductor Group
VPS Mode
Format 2
bit 0
1
2
3
4
5
6
7
byte 14
bit 0
1
2
3
4
5
6
7
byte 24
bit 0
1
2
3
4
5
6
7
byte 13
byte 15
byte 25
– set to “1”
– set to “1”
– set to “1”
– set to “1”
30
bit 0
1
2
3
bit 0
1
2
3
byte 5
bit 0
1
2
3
4
5
6
7
bit 0
1
2
3
bit 0
1
2
3
byte 15
bit 0
1
2
3
4
5
6
7
bit 0
1
2
3
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
– set to “1”
SDA 5648
SDA 5648X
Description of DAVN and EHB Outputs
DAVN (Data Valid active low)
EHB (First Field active high)
Signal Output
VPS Mode
PDC Mode
8/30/2
8/30/1
in line 16 when
valid VPS data is
received
in the line
carrying
valid
8/30/2 data
in the line
carrying
valid
8/30/1 data
at the start of
line 16
at the beginning of the next field
i.e.,at the start of the next data entry window
DAVN
H/L-transition
(set low)
L/H-transition
(set high)
always set high
on power-up or
during I2C-Bus accesses when the bus master doesn’t
acknowledge in order to generate the stop condition
EHB
L/H-transition
at the beginning of the first field
H/L-transition
at the beginning of the second field
In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and reproduce the
state of the CS0 input.
Semiconductor Group
31
SDA 5648
SDA 5648X
Electrical Characteristics
Absolute Maximum Ratings
TA = 25 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test
Condition
max.
Ambient temperature
TA
0
70
°C
in operation
Storage temperature
Tstg
– 40
125
°C
by storage
Total power dissipation
Ptot
300
mW
Power dissipation per output
PDQ
10
mW
Input voltage
VIM
– 0.3
6
V
Supply voltage
VDD
– 0.3
6
V
Thermal resistance
Rth SU
80
K/W
5
5.5
V
5
15
mA
70
°C
Operating Range
Supply voltage
VDD
Supply current
IDD
Ambient temperature range
TA
4.5
0
Characteristics
TA = 25 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Input Signals SDA, SCL, CS0
H-input voltage
VIH
0.7 × VDD
VDD
L-input voltage
VIL
0
0.3 × VDD V
Input capacitance
CI
10
pF
Input current
IIM
10
µA
V
V
Input Signal TI
H-input voltage
VIH
0.9 × VDD
VDD
L-input voltage
VIL
0
0.1 × VDD V
Input capacitance
CI
10
pF
Input current
IIM
10
µA
Semiconductor Group
32
Test
Condition
SDA 5648
SDA 5648X
Characteristics (cont’d)
TA = 25 °C
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test
Condition
Input Signals CVBS
(pos. Video, neg. Sync)
Video input signal level
VCVBS
0.7
1.0
2.0
V
Synchron signal amplitude
VSYNC
0.15
0.3
1.0
V
Data amplitude
VDAT
0.25
0.5
1.5 × VSYNC
1.0
V
Coupling capacitor
CC
H-input current
IIH
L-input current
IIL
Source impedance
RS
Leakage resistance at
coupling capacitor
RC
33
– 1000
0.91
– 400
1
VPS mode
PDC mode
nF
10
µA
VI = 5 V
– 100
µA
VI = 0 V
250
Ω
1.2
MΩ
Output Signals DAVN, EHB, VCS
H-output voltage
VQH
L-output voltage
VQL
V
IQ = – 100 µA
0.4
V
IQ = 1.6 mA
0.4
V
IQ = 3.0 mA
5.5
V
VDD – 0.5
Output Signals SDA (Open-Drain-Stage)
L-output voltage
VQL
Permissible output voltage
PLL-Loop Filter Components (see application circuit)
Resistance at PD2/VCO2
R1
6.8
kΩ
Resistance at VCO1
R2
1200
kΩ
Attenuation resistance
R3
6.8
kΩ
Resistance at PD2/VCO2
R5
1200
kΩ
Integration capacitor
C1
2.2
nF
Integration capacitor
C3
33
nF
100
kΩ
VCO – Frequence Range Adjustment
Resistance at IREF (for bias
current adjustment)
Semiconductor Group
R4
33
SDA 5648
SDA 5648X
I2C-Bus Timing
Parameter
Symbol
Limit Values
min.
max.
100
Unit
Clock frequency
fSCL
0
Inactive time prior to new transmission start-up
tBUF
4.7
µs
Hold time during start condition
tHD;STA
4.0
µs
Low-period of clock
tLOW
4.7
µs
High-period of clock
tHIGH
4.0
µs
Set-up time for data
tSU;DAT
250
ns
Rise time for SDA and SCL signal
tTLH
1
µs
Fall time for SDA and SCL signal
tTHL
300
ns
Set-up time for SCL clock during stop condition
tSU;STO
All values referred to VIH and VIL levels.
Semiconductor Group
34
4.7
kHz
µs
SDA 5648
SDA 5648X
PDC/VPS-Receiver
Application Circuit
Semiconductor Group
35
SDA 5648
SDA 5648X
I2C-Bus Signals During Write Operations
Semiconductor Group
36
SDA 5648
SDA 5648X
I2C-Bus Signals During Read Operations
Semiconductor Group
37
SDA 5648
SDA 5648X
Semiconductor Group
38
SDA 5648
SDA 5648X
Position of Teletext and VPS Data Lines within the Vertical Blanking Interval
(shown for first field)
Definition of Voltage Levels for VPS Data Line
Semiconductor Group
39
SDA 5648
SDA 5648X
BDSP 8/30 Format 1 Bit Allocation
Byte No.
Bit No.
0
15
16
Contents
1
2
3
4
Weight
Weight
2–2 2 –1 20
21
MJD Digit
4
Weight 10
5
6
7
Time Offset Code
Sign
22
23
1
1
0
1
1
1
Modified Julian Date (MJD)
1. Byte
17
MJD Digit
Weight 102
MJD Digit
Weight 103
Modified Julian Date
2. Byte
18
MJD Digit
Weight 100
MJD Digit
Weight 101
Modified Julian Date (MJD)
3. Byte
19
UTC Hours
Units
UTC Hours
Tens
Universal Time Coordinated (UTC)
1. Byte
20
UTC Minutes
Units
UTC Minutes
Tens
Universal Time Coordinated
2. Byte
21
UTC Seconds
UTC Seconds
Universal Time Coordinated
Units
Tens
3. Byte
This corresponds to the coding adopted in CCIR teletext system B BDSP 8/30 format 1.
NB: The received bytes are output on the I2C-bus in a transparent way, i.e., on a bit-first-in-first-out
basis. No bit manipulation is performed on the chip in this operating mode. When evaluating the
numbers, note that each 4-bit-digit has been incremented by one prior to transmission, and the least
significant bits are transmitted first.
Semiconductor Group
40
SDA 5648
SDA 5648X
Structure of the Teletext Data Packet 8/30 Format 2
Semiconductor Group
41
SDA 5648
SDA 5648X
BDSP 8/30 Format 2 Bit Allocation
The four message bits of byte 13 are used as follows:
byte 13 bit 0 – LCI b1 )
label channel identifier
1 – LCI b2 )
2 – LUF
label update flag
3 – reserved but as yet undefined
The message bits of bytes 14 – 25 are used in a way similar to the coding of the label in the
dedicated television line as follows:
byte 14 bit 0 PCS b1 )
1 PCS b2 )
status of
analogue sound
2
3
reserved but yet
undefined
)
)
byte 15 bit 0 CNI
1 CNI
2 CNI
3 CNI
b1
b2
b3
b4
byte 16 bit 0 CNI
1 CNI
b9 )
b10 )
2 PIL
3 PIL
byte 17 bit 0 PIL
1 PIL
2 PIL
b1
b2
b3
b4
b5
)
)
)
)
)
3 PIL
byte 18 bit 0 PIL
1 PIL
2 PIL
b6
b7
b8
b9
)
)
)
)
3 PIL
byte 19 bit 0 PIL
1 PIL
2 PIL
3 PIL
b10
b11
b12
b13
b14
)
)
)
)
)
Semiconductor Group
)
)
)
)
country
network (or
program provider)
day
month
hour
42
byte 20 bit 0 PIL
1 PIL
2 PIL
3 PIL
byte 21 bit 0 PIL
1 PIL
b15
b16
b17
b18
b19
b20
)
)
)
)
)
)
2 CNI
3 CNI
byte 22 bit 0 CNI
1 CNI
b5
b6
b7
b8
)
)
)
)
2 CNI
3 CNI
byte 23 bit 0 CNI
1 CNI
2 CNI
3 CNI
b11
b12
b13
b14
b15
b16
)
)
)
)
)
)
byte 24 bit 0 PTY
1 PTY
2 PTY
3 PTY
byte 25 bit 0 PTY
1 PTY
2 PTY
3 PTY
b1
b2
b3
b4
b5
b6
b7
b8
)
)
)
)
)
)
)
)
minute
country
network (or
program
provider)
program
type
Semiconductor Group
......
5
M
L
0 1 2 3 4 5 6 7
1 2 3 4 1 2 3 4
6 to 10
CNI
PIL
.......
......
11
12
13
43
Net.
or
prog.
prov.
bin.
M
Day
binary
L M
Month
binary
L M
Hour
binary
L M
Minute
binary
Abbreviations: CNI =
PCS =
PIL =
PTY =
N N P ...................
PTY not in use
Country and Network Identification
Program Control Status
Program Identification Label
Program Type
M = Most-significant bit
L = Least-significant bit
................
14
PTY
15
......................P
N ....................................... N
N ....................................... N
N ....................................... N
N ....................................... N
N ....................................... N
Program type
binary
L
1 1 1 1 1 1 1 1
A ............................. A
A ............................. A
A ............................. A
A ............................. A
A ............................. A
L M
N ....................................... N
Network or
program
provider
binary
A = Bit value is that of the current PTY code
N = Bit value is that of the current CNI code
P = Bit value is that of the current PIL code
......................
......................P
N N P ...................
Unenhanced VPS 1 1 1 1
......................
N N 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1
Continuation code N ....... N
................
N N 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
L M
Country
binary
L M
N ....... N
N ....... N
Time
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
N N 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
Interruption code
CNI
9 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 5 6 7 8 11 12 13 14 15 16 1 2 3 4 5 6 7 8
Record inhibit/term. N ....... N
Not relevant
to PDC
N N 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bits b1 and
b2: 00 don’t
know
01 mono
10 stereo
11 dual
sound
Bits b3 and
b4 are
reserved
3&4
Not relevant
to PDC
Timer control code N ....... N
Start
code
2
Reserved for
enhancement
of VPS
Reserved code
values for
receiver control
(service codes)
Content → Clock
run-in
Transmission bit No. →
1
......






......
Byte No. →
CNI
.......












































Parameter bits bi, I = →
PCS
......
Parameter →
SDA 5648
SDA 5648X
Data Format of the Program Delivery Data in the Dedicated TV Line