INFINEON TLE7242-2G

Data Sheet, Rev. 1.0, July 2008
TLE7242-2G
4 Channel Fixed Frequency Constant Current
Control IC
Automotive Power
TLE7242-2G
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1
1.1
1.2
1.3
1.3.1
1.3.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On / Off Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Constant Current Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
3.1
3.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
4.1
4.2
4.3
General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
13
5
5.1
5.2
5.3
5.3.1
5.3.2
5.4
5.5
5.6
5.6.1
5.6.2
5.6.2.1
5.6.2.2
5.6.2.3
5.6.2.4
5.6.2.5
5.6.2.6
5.6.2.7
5.6.2.8
5.6.2.9
5.6.2.10
5.6.2.11
5.6.2.12
5.6.2.13
Functional Description and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply and Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-State Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-State Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #0 - IC Version / Manufacturer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #1 - Main Period Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #2 - PWM Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #3 - Current Set Point and Dither Amplitude Set . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #4 - Dither Period Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #5 - Control Variable Set (KP and KI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #6 - Dynamic Threshold Value Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #7 - On/Off Control and Fault Mask Configuration . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #8 - Diagnostic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #9 - Diagnostic Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #10 - Current Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #11 - Autozero Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Message #12 - Duty Cycle Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
15
16
19
20
24
24
25
26
28
28
29
30
31
33
34
36
38
40
42
43
44
46
6
6.1
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Sheet
2
3
3
4
4
4
5
Rev. 1.0, 2008-07-09
4 Channel Fixed Frequency Constant Current Control
IC
1
Overview
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
TLE7242-2G
Low side constant current control pre-driver integrated circuit
Four independent channels
Output current programmable with 11 bit resolution
– Current range = 0 to 1.2A (typ) with a 0.2 Ω sense resistor
– Resolution = 0.78125 mA/bit (typ) with a 0.2 Ω sense resistor
– +/- 2% full scale error over temperature when autozero is used
Programmable PWM frequency via SPI from approximately
50 Hz to 4 KHz (typ)
PG-DSO-28-26
Programmable KP and KI coefficients for the PI controller for each
channel
Programmable Transient Mode of operation to reduce settling time when large changes in the current set point
are commanded.
Programmable superimposed dither.
– Dither programmed by setting a dither step size and the number of PWM periods in each dither period
– Programmed via the SPI interface
– The dither for each channel can be enabled and programmed independently
Programmable synchronization of the PWM control signals.
– Phase delay time set via the SPI interface
– Synchronization initiated via signal at the PHASE_SYNC input pin.
– Channels within one device and between multiple devices can be synchronized.
Each channel can be configured to function as a simple on/off predriver or a constant current predriver via SPI
Interface and Control
– 32 Bit SPI (Serial Peripheral Interface) - Slave only
– ENABLE pin to disable all channels or freeze all channels
– Active low RESET_B pin resets internal registers to their default state and disables all channels.
– Open drain FAULT pin can be programmed to transition low when various faults are detected.
– 5.0V and 3.3V logic compatible I/O
Protection
– Over current shutdown - monitored at POSx pin.
– Programmable over current threshold
– Programmable over current delay time
– Programmable over current retry time
– Battery pin (BAT) overvoltage shutdown.
Diagnostics
– Over current
Type
Package
Marking
TLE7242-2G
PG-DSO-28-26
TLE7242-2G
Data Sheet
3
Rev. 1.0, 2008-07-09
TLE7242-2G
Overview
•
•
•
•
– Open load in on state
– Open load in off state
– Short to ground
– Test complete bit - indicates that fault detection test has completed
Control loop monitor capabilities
– The average current measurement over the last completed PWM cycle of each channel can be accessed
via SPI.
– The PWM duty cycle of each channel can be accessed via SPI
– The auto zero values used to null the offsets of the input amplifiers can be accessed via SPI
Required External Components:
– N-Channel Logic level (5V) MOSFET transistor with typical Ron ≤ 100 mΩ (e.g. BSO604NS2)
– Recirculation diode (ultrafast)
– Sense resistor (0.2Ω for 1.2A average output current range)
Green Product (RoHS compliant)
AEC Qualified
1.2
•
•
Applications
Variable Force Solenoids (e.g. automatic transmission solenoids)
Other constant current solenoids
– Idle Air Control
– Exhaust Gas Recirculation
– Vapor Management Valve
– Suspension Control
1.3
General Description
The TLE7242 2G IC is a four channel low-side constant current control predriver IC. Each channel can be
configured to function either in on/off mode or in constant current mode by setting the appropriate MODE bit in SPI
message #7.
1.3.1
On / Off Mode Operation
For On/Off operation, the POSx and NEGx pins must be connected to the circuit in either of the configurations
shown in Figure 1. If the sense resistor is included, the load current can be monitored by the microcontroller via
a SPI command. The open load in on state fault detection feature is disabled in on/off mode.
Note: An external flyback clamp is required in this configuration otherwise the IC may be damaged.
Data Sheet
4
Rev. 1.0, 2008-07-09
TLE7242-2G
Overview
VBAT
VBAT
Solenoid
Solenoid
POSx
POSx
CESD
CESD
RSENSE
NEGx
NEGx
RG
QDRV
RG
OUTx
QDRV
OUTx
Figure 1
External Circuit Diagram for On/Off Mode Operation
1.3.2
Constant Current Mode Operation
During constant current operation, the POSx and NEGx pins must be connected to the circuit in the configuration
shown in Figure 2.
Note: An external recirculation diode is required in this configuration otherwise the IC may be damaged.
VBAT
Solenoid
DRECIRC
POSx
CESD
RSENSE
NEGx
RG
QDRV
OUTx
Figure 2
External Circuit Diagram for Constant Current Mode Operation
The constant current control circuit can operate in two modes; steady state mode and transient mode.
Steady-State Mode
During steady-state operation, the PWM control signal driven at the OUTx pin is controlled by the control loop
shown in Figure 3. The PWM Frequency is programmed via the SPI message # 1. In this message the main period
divider, N, can be set to any value between 79 and 214 -1. The equation for calculating the PWM frequency is:
FPWM =
Data Sheet
5
FCLK
32 * N
Rev. 1.0, 2008-07-09
TLE7242-2G
Overview
The 11 bit Current Set Point is programmed via the SPI message #3. The equation for calculating the current
setpoint is:
Currentsetpoint [mA] =
setpoint(11bit) 320
∗
RSENSE
211
The Proportional coefficient (KP) and the Integral coefficient (KI) of the control loop are programmed in SPI
message #5. The KP and KI values should be set to values that result in the desired transient response of the
control loop. The duty cycle of the OUTx pin can be calculated from the difference equations:
Rsense
* error (k − 1) + INT ( k )
1 . 28 ∗ N
Rsense
INT ( k ) = KI ∗
* error (k − 1) + INT ( k − 1)
1 . 28 ∗ N
DutyCycle
(k ) =
KP ∗
where error is the difference between the commanded average current and measured average current in units of
Amps.
where k indicates the integral number of PWM periods that have elapsed since current regulation was initiated.
Autozero
Value
“ON”
Autozero
Value
“OFF”
Auto Zero
POSx
CURRENT
READ
Average
+
A/D
Amp
NEGx
CURRENT SET
POINT
DITHER STEP SIZE
DITHER STEPS
-
+
+
KP
+
Dither
Generation
KI
+
+
Σ
PWM
Block
DUTY
CYCLE
OUTx
PWM
CLK
PRELOAD
Underlined = CAN BE PROGRAMMED VIA SPI
Italics = CAN BE MONITORED VIA SPI
Figure 3
Control Loop - Steady-State Mode
Auto Zero
When a channel is configured for constant current operation and the current set point is 000h for 256 consecutive
PWM periods, an autozero sequence is initiated. The autozero sequence will measure the offset of the current
Data Sheet
6
Rev. 1.0, 2008-07-09
TLE7242-2G
Overview
measurement amplifiers. If the autozero function is enabled in SPI message #7, then the measured offset will be
subtracted from the A/D converter output as shown in Figure 3 when the current set point is greater than 0.
Dither
A triangular dither waveform can be superimposed on the current set point by setting the Dither Enable bit in SPI
message #3. The amplitude and frequency of the dither waveform are programmed for each channel via SPI
messages #3 and #4. See the SPI message section for details.
The first programmed value is the step size of the dither waveform which is the number of bits added or subtracted
from the setpoint per PWM period. One LSb of the dither step size is 1/16 the magnitude of the nominal setpoint
current value. The second programmed value is the number of steps in one quarter of the dither waveform.
When dither is enabled, a new average current set point will not be activated until the current dither cycle has
completed. The dither cycle is completed on the positive zero crossing of the dither waveform. A new dither
amplitude setting, a new dither frequency setting, or a dither disable command will also not be activated until the
current dither cycle has completed see Figure 4.
PWM_START
Dither
Dither
Parameter
Change
Figure 4
New Dither Values Programmed and the Resultant Waveform Timing
Note: the actual dither waveform is attenuated and phase shifted according to the frequency response of the
control loop.
If a channel enters transient mode operation while the dither waveform is active, the dither wave-form will pause
until transient mode is exited.
Transient Mode
When a large change in the current set point occurs, the device can be programmed to enter transient mode of
operation. The setpoint change threshold required to initiate transient mode can be programmed in
SPI message #6. The purpose of this mode of operation is to reduce the transition time of the load current after a
large change in setpoint. In this mode of operation the OUTx pin signal is controlled by the state machine shown
in Figure 5. The control method in this mode is similar to hysteretic control, the OUTx signal transitions high or
low based on the immediate value of the measured output current. The PWM frequency is not fixed in this mode
of operation. The device will automatically switch from transient mode of operation to steady state operation at the
start of the first PWM period after the new set point has been reached.
Data Sheet
7
Rev. 1.0, 2008-07-09
TLE7242-2G
Overview
OUTx = High
Set Point change > Threshold
New Set Point > Old Set Point
Reset
SteadyState
Mode
next
ADC value
Start of PWM period
CALC
DC
INT
PRELOAD
OUTx := LOW
Controller := stop
OUTx := LOW
Controller := stop
Measured Current < New
Set Point
LEAVE
HYST MODE
OUTx := LOW
Controller := stop
Set point change > Threshold
New Set Point < Old Set Point
Measured Current > New
Set Point
Start of PWM period
OUTx = Low
Figure 5
OUTx = Low
Measured Current > New Set Point
Measured Current < New Set Point
OUTx = High
Transient Mode State Diagram
A typical current waveform during transient mode operation is shown in Figure 6. Starting from a set point I, the
new set point II is accepted a short time after the rising edge on CS_B. The OUTx pin remains high until the
measured load current has reached the new set point. The OUTx pin is then toggled on and off to maintain the
load current near the new set point until the next PWM period begins. The device will then switch back to steady
state control and the OUTx pin will be controlled by the control loop shown in Figure 3.
During the transition from transient mode operation to steady state operation, the integrator is pre-loaded with a
SPI programmable value. This value should be chosen to give an initial PWM duty cycle approximately equal to
the duty cycle required to regulate the load current at the new set point.
iL
Steady State
Mode Begins
setpoint ΙΙ
Transient Mode
Begins
setpoint Ι
t
PWM
setpoint ΙΙ accepted
SPI CS_B
Figure 6
Data Sheet
Transient Mode Timing Diagram
8
Rev. 1.0, 2008-07-09
TLE7242-2G
Block Diagram
2
Block Diagram
V5D
V5A
Supply
Biasing
Monitoring
GND_D
GND_A
POS0
Current
Control
Block
V_SIGNAL
NEG0
V5D
OUT0
Diagnostics
BAT
POS1
NEG1
Current
Control
Block
SCK
V5D
OUT1
SI
SPI
Interface
SO
CS_B
Diagnostics
V_SIGNAL
V_SIGNAL
POS2
NEG2
Current
Control
Block
RESET_B
V5D
OUT2
ENABLE
Diagnostics
FAULT
PHASE_SYNC
POS3
Current
Control
Block
Logic
NEG3
V5D
OUT3
CLK
Diagnostics
TEST
Figure 7
Data Sheet
Block Diagram
9
Rev. 1.0, 2008-07-09
TLE7242-2G
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment
1
28
FAULT
OUT 2
2
27
RESET_B
POS 3
3
26
ENABLE
NEG 3
4
25
CS_B
NEG 2
5
24
SCK
POS 2
6
23
V5D
GND_A
7
V5A
8
POS 1
9
NEG 1
10
NEG 0
TLE7242 2G
OUT 3
22
CLK
21
GND_D
20
SO
19
V_SIGNAL
11
18
SI
POS 0
12
17
TEST
OUT 1
13
16
PHASE_SYNC
OUT 0
14
15
BAT
Figure 8
Pin Configuration
3.2
Pin Definitions and Functions
Pin
Symbol
I/O
Analog Function
/Digital
1
OUT3
O
A
Gate driver output for channel #3. Connect to the gate of the
external MOSFET.
2
OUT2
O
A
Gate driver output for channel #2. Connect to the gate of the
external MOSFET.
3
POS3
I
A
Channel #3 Positive sense pin. Connect to the "load" side of the
external sense resistor.
4
NEG3
I
A
Channel #3 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
5
NEG2
I
A
Channel #2 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
6
POS2
I
A
Channel #2 Positive sense pin. Connect to the "load" side of the
external sense resistor.
7
GND_A
-
-
Analog Ground
8
V5A
-
-
5V supply pin for analog. An external capacitor is to be connected
between this pin and GND_A near this pin.
9
POS1
I
A
Channel #1 Positive sense pin. Connect to the "load" side of the
external sense resistor.
Data Sheet
10
Rev. 1.0, 2008-07-09
TLE7242-2G
Pin Configuration
Pin
Symbol
I/O
Analog Function
/Digital
10
NEG1
I
A
Channel #1 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
11
NEG0
I
A
Channel #0 Negative sense pin. Connect to the "FET" side of the
external sense resistor.
12
POS0
I
A
Channel #0 Positive sense pin. Connect to the "load" side of the
external sense resistor.
13
OUT1
O
A
Gate driver output for channel #1. Connect to the gate of the
external MOSFET.
14
OUT0
O
A
Gate driver output for channel #0. Connect to the gate of the
external MOSFET.
15
BAT
I
A
Battery sense input for over voltage detection. Connect through a
series resistor (e.g. 1 Kohm) to the solenoid supply voltage. A
large electrolytic capacitor (e.g. 47uF) should be placed between
the BAT supply and ground.
16
PHASE_SYNC
I
D
Used to synchronize the rising edges of the PWM signal on the
OUTx pins for each channel.
17
TEST
I
D
Used for IC Test. Must be connected to GND_D for specified
operation of the IC.
18
SI
I
D
SPI Serial data in
19
V_SIGNAL
I
-
Supply pin for the SPI SO output and the pull-ups of the digital
inputs CS_B and RESET_B. An external capacitor must be connected between this pin and GND_D near this pin.
20
SO
O
D
SPI Serial data out
21
GND_D
-
-
GND pin for digital and driver circuitry.
22
CLK
I
D
Main clock input for the IC. A clock input of 20 MHz to 40 MHz is
required.
23
V5D
-
-
5V supply pin for the digital circuit blocks and the OUT pin driver
circuits. A pair of external capacitors is to be connected between
this pin and GND_D very near this pin. Example values of the
external capacitors are 100nF and 100pF.
24
SCK
I
D
SPI Clock input
25
CS_B
I
D
SPI Chip Select Bar (low active signal)
26
ENABLE
I
D
When this input pin is low all channels are turned off (zero current)
or remain in their last state, depending on how the channel is
programmed to respond
27
RESET_B
I
D
When this input pin is low all channels are turned off and all
internal registers are reset to their default state. The part must be
held in reset by an external source until all supplies are stable and
within tolerance.
28
FAULT
O
D
This open drain output pin is pulled low when a fault condition is
detected. Certain faults can be masked via SPI.
Data Sheet
11
Rev. 1.0, 2008-07-09
TLE7242-2G
General Product Characteristics
4
General Product Characteristics
4.1
Maximum Ratings
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
-13
50
V
–
-0.3
6.0
V
–
-0.3
50
V
–
-0.2
13
V
–
-0.3
min(V5D+
0.3; 6)
V
–
Voltages
VBAT
V5D,V5A,
Vsignal
Vpos, Vneg
Vpos-Vneg
Vout
4.1.1
Battery Input (VBAT)
4.1.2
Supply Voltage (logic)
4.1.3
POSx, NEGx
4.1.4
POSx-NEGx
4.1.5
OUTx
4.1.6
RESET_B, SI, SCK, CS_B, CLK, TEST, Vio
PHASE_SYNC, ENABLE
-0.3
min(V5D+
0.3; 6)
V
–
4.1.7
SO, FAULT
Vio
-0.3
min(Vsignal V
+ 0.3; 6)
–
4.1.8
Maximum difference between V5D and
V5A
-500
500
mV
–
ICLAMP
5
–5
mA
–
Tstg
Tj
-65
150
°C
–
-40
150
°C
–
Currents
4.1.9
Input Clamp Current
Temperatures
4.1.10
Storage Temperature
4.1.11
Junction Temperature
ESD Susceptibility
4.1.12
HBM
–
-2
2
kV
2)
4.1.13
CDM all pins
–
-500
500
V
3)
4.1.14
CDM corner pins
–
-750
750
V
3)
1) Not subject to production test, specified by design.
2) ESD Susceptability HBM according to EIA/JESD 22-A 114B
3) ESD Susceptability CDM according to EIA/JESD22-C101
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
12
Rev. 1.0, 2008-07-09
TLE7242-2G
General Product Characteristics
4.2
Functional Range
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Pos.
Parameter
Symbol
Limit Values
VBAT
4.2.1
Supply Voltage (VBAT)
- Full Parametric Operation on all
functions except FET Pre-drivers
4.2.2
VV5D
Supply Voltage (V5A)
VV5A
V_SIGNAL
VV_SIGNAL
Clock Frequency
fCLK
PWM Frequency
fPWM
Common Mode Voltage on POSx, Vpos ,Vneg
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
Supply Voltage (V5D)
Unit
Conditions
Min.
Max.
5.5
42
V
–
4.75
5.25
V
–
4.75
5.25
V
–
3.0
5.25
V
–
20
40
MHz
50
4000
Hz
–
42
V
–
NEGx pins
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3
Thermal Resistance
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
Pos.
4.3.1
Parameter
Symbol
Junction to Ambient RthJA
Limit Values
Min.
Typ.
Max.
–
50
–
Unit
Conditions
K/W
1)
1) Specified RthJA value according to natural convestion on FR4 2s0p board; The Product (Chip + Package) was simulated
on a 60.0 X 45.0 X1.5 mm board (2 X 70um).
Data Sheet
13
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5
Functional Description and Electrical Characteristics
Note: The listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA = 25 oC and the given supply voltage.
5.1
Supply and Reference
The device includes a power-on reset circuit. This feature will disable the channels and reset the internal registers
to their default values when the voltage on V5A and/or V5D are below their respective reset thresholds.
The V5D pin and GND_D pin are the supply and ground pins for the digital circuit blocks and the OUTx pin driver
circuits. The current through these pins contain high frequency components. Decoupling with ceramic capacitors
and careful PCB layout are required to obtain good EMC performance.
The V5A pin and GND_A pin are the supply and ground pins for the analog circuit blocks.
The V_SIGNAL pin supplies the SPI output pin (SO) and is the source voltage for the pull up currents on the CS_B
and RESET_B pins. V_SIGNAL should be connected to the I/O supply of the microcontroller (3.3V or 5.0V).
The BAT pin is an input pin used to detect over voltage faults. This pin is not a power supply input. A series resistor
should be connected between this pin and the solenoid supply voltage for transient protection.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
5.1.1
Undervoltage reset (internally
triggered)
VV5A
3.5
–
4.5
V
Internal reset
occurs if V5A is
under the
undervoltage limit
5.1.2
Undervoltage reset (internally
triggered)
VV5D
1.0
–
4.5
V
Internal reset
occurs if V5D is
under the
undervoltage limit
5.1.3
V5D supply current
IV5D
–
–
30
50
mA
mA
fCLK=20MHz
fCLK=40MHz
5.1.4
V5A supply current
–
–
25
mA
5.1.5
V_SIGNAL supply current
IV5A
IV_SIGNAL
–
–
1.0
mA
5.1.6
VBAT current
IVBAT
–
–
150
50
5
µA
µA
µA
SO pin in hi-Z state,
digital inputs in
default state
full operating range
V5A=5V, BAT=14V1)
V5A=0V, BAT=14V1)
1) Not subject to production test, specified by design.
Data Sheet
14
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.2
Input / Output
All digital inputs are compatible with 3.3 V and 5 V I/O logic levels. The supply voltage for the SPI output SO is the
V_SIGNAL pin. All digital inputs are pulled to a known state by a weak internal current source or current sink when
not connected. However, unused digital input pins should be connected to ground or to V_SIGNAL (according to
the desired functionality) by an external connection or resistor. All input pin weak internal current sources are
supplied by the V_SIGNAL pin.
The RESET_B pin is an active low input pin. When this pin is low, all channels are off, and all internal registers
are reset to their default states. The device must be held in reset by an external source until all the power supplies
have stabilized. The IC contains an internal power on and undervoltage reset which becomes active when V5D or
V5A fall below the undervoltage reset threshold (VUVA, VUVD).
The ENABLE pin is an active high input pin which must be held high for normal operation of the device. When this
pin is held low all channels are either turned off or will remain in the last state, depending on how the enable
behavior of the channel is programmed via SPI. The default condition is that all channels are turned off when the
ENABLE pin is low.
The CLK pin is the main clock input for the device. The input thresholds are compatible with 3.3 V and 5.0 V logic
levels. No synchronization is required between the clock signal connected to the CLK pin and the SPI clock signal
(SCK). All frequencies of operation (PWM signals, A/D sampling, diagnostics, etc.) are based on this clock input.
Also, this clock is required in order for the device to accept and respond to SPI messages.
1/f clk
t14
CLK
VIH min
VILmax
t15
Figure 9
CLK Timing Diagram
The PHASE_SYNC pin is an input pin that can be used by the microcontroller to synchronize the PWM control
signals of multiple channels. The desired phase delay between the rising edge of the signal applied to the
PHASE_SYNC pin and the rising edge of the PWM signal of each channel can be programmed independently via
SPI message #2. The equation for calculating the offset is:
Toffset =
PhaseSynchOffset
32 * FPWM
Each time the phase sequence occurs, the IC will latch a bit which is reported via the response to SPI message
#11. (See SPI interface section for bit/message location.) This latch is cleared when the message is read.
Note: The PWM periods are restarted when a rising edge is detected on the PHASE_SYNC pin. A periodic pulse
train on this pin will disturb the current regulation.
Data Sheet
15
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
normal
turn off
time
gate turns off
on-time cut
short
OUTx
T1
PWM/32 CLK
T1
Programmed delay =
8/32 PWM periods
PHASE_SYNC
Figure 10
Phase Synchronization Diagram
The TEST pin is an input pin that is used during IC level test. This pin should be connected directly to ground for
normal device operation.
The FAULT pin is an open drain output pin. This pin will be pulled low by the device when an unmasked fault has
been detected. The fault masks are programmed via SPI message #7.
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
5.2.1
Logic input low voltage
5.2.2
Logic input high voltage
5.2.3
Logic output low voltage
5.2.4
Logic output high voltage
Symbol
VILMAX
VIHMIN
VOLMAX
VOHMIN
Limit Values
Unit
Min.
Typ.
Max.
–
–
0.8
V
2.0
–
–
V
–
–
0.2
V
–
V
0.8*V_ –
Conditions
IL=200µA
IL=-200µA
SIGNAL
5.2.5
Pull down digital input (SI, CLK,
SCK, PHASE_SYNC, ENABLE,
TEST)
Ipd
10
–
50
µA
Vin=V_SIGNAL
(current drain to
ground)
5.2.6
Pull up digital input (CS_B,
RESET_B)
Ipu
-10
–
-50
µA
Vin=0V (Current
drain from
V_SIGNAL)
5.2.7
Fault Pin voltage
Vfault
–
–
0.4
V
5.2.8
CLK high time (rise 2.0V to fall
2.0V)
t14
8
–
–
ns
5.2.9
CLK low time (fall 0.8V to rise 0.8V) t15
8
–
–
ns
5.3
Active state;
Ifault=2mA
Diagnostics
The TLE7242 2G includes both on-state and off-state diagnostics. On-state diagnostics are active when the OUTx
pin is driven high and off-state diagnostics are active when the OUTx pin is driven low. A detected fault can be
used to activate the open drain FAULT pin on the IC. This pin can be used to interrupt the microcontroller when a
Data Sheet
16
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
fault is detected. Certain faults can be prevented from activating the FAULT pin by setting the fault mask register
in SPI message #7.
Once a fault is detected it is latched into the FAULT register. The microcontroller can access the FAULT register
by sending SPI message #9.
If the RESET_B line transitions high-to-low, a RL bit is latched into the FAULT register. The register is cleared after
it is read from the SPI. The RL bit in the FAULT register will not be set again until the next high-to-low transition
occurs on the RESET_B pin.
If the ENABLE pin voltage is low, the ENL bit is latched in the FAULT register. The ENL bit is cleared when the
ENABLE pin returns to a high state and the FAULT register is accessed by SPI message #9.
The diagnostic delay timers for the on-state and off-state diagnostic functions are derived from the master clock
signal applied to the pin CLK using a programmable predivider. This predivider is programmable by the DT1 and
DT0 bits in SPI message #7.
Table 1
Timebase for Diagnostics
DT1
DT0
Pre-divider
Tested Timer and Fault Detection Timer
Period.
FCLK=20 MHz
FCLK=40 MHz
0
0
128
64 µsec
32 µsec
0
1
192
96 µsec
48 µsec
1
0
192
96 µsec
48 µsec
1
1
256
128 µsec
64 µsec
t DIAG _ PERIOD =
n fault * predivider
FCLK
9 ≤ n fault ≤ 10
Three fault types in 4 different fault bits are defined:
The fault bit is 1 if the fault is detected.
Table 2
Diagnostic Flags / Bits
Fault Type
Abr.
Gate is ON
Gate is OFF
Short to Ground Fault
SG
OL-ON-F reported (=0 in
ON/OFF mode)
Bit SG-F
Short to Battery Fault
SB
Bit SB-F
Open Load Fault
OL
BIT OL-ON-F
(=0 in ON/OFF mode)
Bit OL-OFF-F
Note: In order to differentiate between a Short to Ground Failure and an Open Load Failure, the channel must be
turned off (setpoint = 0ma).
Tested Diagnostic Bits
The tested bits allow the distinction between a true No Fault and a No Fault due to an untested state (the detection
interval has yet to occur). For instance when the calculated duty cycle is too low to complete the short to battery
test.
Data Sheet
17
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Two fault tested bits are defined:
The tested bit is set to 1 when the fault test has completed successfully.
Table 3
Diagnostics Tested Bits / Flags
Tested Type
OUTx High
OUTx Low
Short to Ground and Open load OFF
tested
Short to Battery tested
Bit OFF-T
Bit SB-T
Each fault type can be described by the two bits: FAULT and TESTED.
Table 4
FAULT
FAULT vs. TESTED Bits Matrix and Interpretation
TESTED
Interpretation by microcontroller
0
0
This fault type has not been tested
0
1
No Fault - The fault type has been tested and no fault is present
1
0
This combination cannot occur
1
1
Fault - This particular fault type has occurred
Divider Select
(SPI register)
read SPI fault
register
Predivider
Tested timer
1..10
(shared)
1:128
1:192
1:256
Masterclock
clear
LOGIC
fault filter timer
(1..10) (shared)
clear
clear
SG-F (Short to Ground Fault)
OFF-T (Short to Ground and Open
Load Off Tested)
SB-F (Short to Battery Fault)
clear
OL-OFF-FD
VPOS
OL-FA
digital filter
SG-FD
open load OFF
(only while OFF)
SB-FD
VOL
SB-T (Short to Battery Tested)
OL-OFF-F (Open Load Off Fault)
OL-ON-F
digital filter
VPOS
SG-FA
OL-ON-F (Open Load On Fault)
short to ground
(only while OFF)
VSG
digital filter
VPOS
SB-FA
short to battery
(only while ON)
VSB
PWM mode enabled
PWM Start
Gate is ON
Figure 11
Data Sheet
Gate On Counter
1..64
Diagnostic Block Diagram
18
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.3.1
On-State Diagnostics
When the OUTx pin transitions high, the fault timers are cleared to 0 and the tested timer starts. If the tested timer
expires, the Bit SB-T (in the SPI register #9) is set to 1. If the OUTx pin transitions low, the tested timer is cleared
and then used for the off-state diagnostics.
If the analog SB fault signal (SB-FA) changes to 1, the fault filter timer starts. If the fault filter timer expires, the
digitally filtered SB fault signal (SB-FD) is set to one. If SB-FA changes to 0, SB-FD changes immediately to 0 and
the filter timer is cleared to 0.
A SB-FD=1 and SB-T=1 switches off the OUTx signal and the SB-F bit in the FAULT register will be set. The OUTx
pin remains in the off state until the fault retry PWM period counter expires.
If the SPI fault register is read, then the SB-F bit and the SB-FT bit in the FAULT register are cleared. Also, the
tested timer is cleared to 0.
The Short to Battery (SB) detection functions in both on/off and constant current mode. The SG-FD and OL-OFFFD signals are held to 0 while the OUTx pin is high.
If the TLE7242 2G IC is in ON/OFF mode, Open Load ON detection is disabled (OL-ON-F = 0).
If the TLE7242 2G IC is not in ON/OFF mode and the OUTx pin is high for 64 PWM periods, then open load fault
ON mode is detected and the OL-ON-F bit in the FAULT register is set. This bit will be cleared when a SPI fault
read occurs. If the OUTx pin remains in a high state, then the open load - on fault condition is detected again after
another 64 PWM cycles.
PWM_Start
OUTx
Fault Retry Time
(Address #8)
Tested
Timer
Tested
Timer
SB-T
short
Load
ok
Vpos
Vsb
SB-F
Fault
Filter
Fault
Filter
Load
Current
SPI READ
ADDR 9
Short to Vbat
Figure 12
Data Sheet
On-State Diagnostic Timing - Short to Vbat
19
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
PWM_Start
OUTx
Vpos
64 * PWM period
OL-ON-F
SPI Message
Diagnostic Read
Figure 13
Open - On
5.3.2
Off-State Diagnostics
The off-state diagnostics function in both constant current mode and in on/off mode.
When the OUTx pin transitions low, the fault timers are cleared to 0 and the tested timer starts to count up. If the
tested timer expires, the Bit OFF-T in the FAULT register is set. If a SPI fault register read occurs, the tested timer
is cleared to 0 and starts again to count up. If the OUTx pin transitions high, the tested-timer is cleared to zero and
then used for on-state diagnostics.
If the analog OL fault signal (OL-FA) changes to 1, the fault filter timer starts to count up. If the fault filter timer
expires, the digitally filtered OL fault signal (OL-ON-FD) is set to one.
If OL-FA changes to 0, OL-FD changes immediately to 0 and the fault filter timer is cleared to 0.
If the analog SG fault signal (SG-FA) changes to 1, the fault filter timer is cleared to 0 and starts to count up. If the
fault filter timer expires, the digitally filtered SG fault signal (SG-FD) is set to one. If SG-FA changes to 0, SG-FD
changes immediately to 0 and the fault filter timer is cleared to 0.
If SG-FD = 1 and the tested timer is expired then the SG-F bit in the FAULT register is set and the OL-OFF-F bit
in the FAULT register remains unchanged (independently from OL-OFF-FD).
If SG-FD = 0 and OL-OFF-FD = 1 then the OL-F Bit in the FAULT register is set.
If a SPI fault read occurs, the OFF-T Bit, the SG-F Bit and the OL-F Bit in the SPI registers are cleared to zero
(and the timers are cleared to 0).
Data Sheet
20
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Solenoid
V SUPPLY
V5A
(Vol+Vsg)/2
(2.5V)
SG/OL-OFF
TESTED
OL-OFFFAULT
SGFAULT
Figure 14
Tested Timer
(OFF)
latch
Ipu(sg)
(100ua)
+
POSx
OA
Ipd(ol)
(100ua)
Cpos
NEGx
OL-OFF-FD
Digital
Filter
OL-FA
SG-FD
Digital
Filter
SG-FA
latch
latch
CMP
+
-
+
CMP
Vol (3V)
Cneg
OUTx
Vsg (2V)
Off-State Diagnostics
OUTx
Tested
Tim er
OFF-T
Tested
Tim er
open
LOAD
V POS
ok
Vol
Vsg
OL-O FF-F
Fault
Filter
Fault
Filter
SPI M essage
Diagnostic Read
Figure 15
Data Sheet
Off-State Diagnostics Timing Diagram - open
21
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
OUTx
OFF-T
Tested
Timer
Tested
Timer
Short to
ground
LOAD
ok
V POS
Vol
Vsg
Fault
Filter
SG-F
Fault
Filter
SPI READ
ADDR 9
Figure 16
Off-State Diagnostics Timing Diagram - short to ground
Over voltage Shutdown and Diagnostics
If the voltage at the BAT pin is above VBATOV, the output drivers set all OUTx pins to low, and a diagnostic bit is
set (SPI Message +11 bit OVL). During over voltage condition the integrator of the steady state current control is
halted (actual value of the duty cycle is not changed during over voltage). All other functions operate normally (e.g.
ADC, Dithering, Auto zero, Filters, …).
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
5.3.1
Over voltage shutdown
VBATOV
42
–
–
5.3.2
Open load detection voltage
V5A-2.5 –
V5A-1.5 V
5.3.3
POS pin OL pull down current
VPOS(OL)
IPD(OL)
60
150
VPOS(SHG) V5A-3.5 –
IPD(SHG) -60
-100
5.3.4
Short to GND detection voltage
5.3.5
POS pin SG pull-up current
5.3.6
NEG bias current - Low common INEG(L)
mode
-40
5.3.7
NEG bias current - High common INEG(H)
mode
0
Data Sheet
100
22
Unit
Conditions
V
Raise VBAT until all
outputs shut down
µA
V5A=5V,
VPOS=VNEG=V5A
V5A-2.5 V
-150
µA
V5A=5V,
VPOS=VNEG=0V
–
10
µA
V5A=5V,
VPOS=VNEG=0V
–
60
µA
V5A=5V,
VPOS=VNEG=V5A
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
5.3.8
POS Fault Threshold Voltage
VFLT
0.6
0.7
0.8
V
POS voltage
required to trigger a
short to battery
fault: config bits =
00
5.3.9
POS Fault Threshold Voltage
VFLT
0.8
0.9
1.0
V
POS voltage
required to trigger a
short to battery
fault: config bits =
01
5.3.10
POS Fault Threshold Voltage
VFLT
1.0
1.1
1.2
V
POS voltage
required to trigger a
short to battery
fault: config bits =
10
5.3.11
POS Fault Threshold Voltage
VFLT
1.2
1.3
1.4
V
POS voltage
required to trigger a
short to battery
fault: config bits =
11
5.3.12
Fault Filter Timer
nfault
9
10
clocks
5.3.13
Fault Filter Time
Tff
n fault ⋅ predivider
f CLK
5.3.14
Tested Timer Time
Ttt
n fault ⋅ predivider
f CLK
Data Sheet
23
Clock Divider (SPI
Message 7)
00 - Predivider 128
01, 10 - Predivider
192
11 - Predivider 256
Clock Divider (SPI
Message 7)
00 - Predivider 128
01, 10 - Predivider
192
11 - Predivider 25
6
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.4
Output Driver
The OUTx pins of the device are connected to the gates of the external MOSFET transistors. The OUTx pin driver
circuits charge and discharge the MOSFET gate capacitance with a constant current source and sink. The supply
for the current source is the V5D pin. Internal resistors to ground are included on the OUTx pins so that the external
MOSFET is held in the off state when power is not applied to the device.
An external resistor is typically placed between the OUTx pin and the gate of the external MOSFET in order to set
the MOSFET turn-on and turn-off times. The value of the resistor must be chosen such that the turn-on and turnoff times of the MOSFET are no longer than 1/(Fpwm*32).
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
5.4.1
Passive Gate Pull Down
Resistance
RPD
50
–
200
kΩ
Internal pull down
resistor present at
each OUTx pin
5.4.2
OUTx source current
-15
–
-30
mA
VOUT = V5D-2V
5.4.3
OUTx sink current
IO_SRC
IO_SNK
15
–
30
mA
VOUT = 2V
5.5
Current Control
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
5.5.1
Offset Error
Output from Average block in
Figure 3.
1 count = 320/Rsense * 2-14 mA
0
–
240
counts Autozero
disabled.VposVneg=0mV
Vpos, Vneg ≤ 30V
5.5.2
Gain Error
-2%
–
2%
%
Data Sheet
24
Autozero
Enabled.VposVneg=300mV
Vpos, Vneg ≤ 30V
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6
Serial Peripheral Interface (SPI)
SPI messages for the TLE7242 2G IC are 32-bit values broken down into the following fields.
Bit 31: Read/Write Bit - 0 = Read 1 = Write
Bits 30-26: Message Identifier
Bits 25-24: Channel Number (00, 01, 10, 11)
Bits 23-0: Message Data
The message from the microcontroller must be sent MSB first. The data from the SO pin is sent MSB first. The
TLE7242 2G will sample data from the SI pin on the rising edge of SCK and will shift data out of the SO pin on the
rising edge of SCK.
All SPI messages must be exactly 32-bits long, otherwise the SPI message is discarded. The response to an
invalid message (returned in the next SPI message) is the message with identifier 00000 (Manufacturer ID).
When the ENABLE pin is low, all SPI writes commands are executed as read commands.
When RESET_B pin is low, the SPI port is disabled. No SPI messages are received and no responses are sent.
The SO pin remains in a high impedance state.
There is a one message delay in the response to each message (i.e. the response for message N will be returned
during message N+1).
Read/Write operation is referenced from the SPI master. The TLE7242 2G IC is the slave device.
Some messages, such as diagnostic information, do not use the channel number field. In these cases the channel
number is not part of the response.
When bit 31 is = 0 to denote a read operation to the IC, the message data in bits 23-0 of the sent message are
ignored, but will contain valid data in the response message.
All response data (either from a read or write operation) is the direct contents of the addressed internal register,
and is not an echo of the data sent in the previous SPI message.
The response to the first SPI message after a reset is message #0 (IC Version / Manufacturer).
Data Sheet
25
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.1
SPI Signal Description
Electrical Characteristics:
V5D = 4.75V to 5.25V, Vbat = 5.5V to 42V, Tj = -40 °C to +150 °C, all voltages with respect to ground, positive
current flowing into pin (unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
5.6.1
TLEAD
t1
140
–
–
ns
CS_B falling (0.8V)
to SCK rising (0.8V)
5.6.2
TLAG
t2
50
–
–
ns
SCK falling (0.8V)
to CS_B rising
(0.8V)
t3
450
–
–
ns
CS_B rise (2.0V) to
CS_B fall (2.0V)
100
–
–
ns
SCK rise to rise
5.6.5
t4
t5
10
–
–
ns
SCK falling (0.8V)
to CS_B fall (2.0V)
5.6.6
t6
40
–
–
ns
SCK high time (rise
2.0V to fall 2.0V)
5.6.7
t7
40
–
–
ns
SCK low time (fall
0.8V to rise 0.8V)
5.6.8
t8
10
–
–
ns
CS_B rise (2.0V) to
SCK rise (0.8V)
5.6.3
5.6.4
1/FSCK Period of SCK
5.6.9
TSU_SI
t9
20
–
–
ns
SI setup time to
SCK rise (0.8V)
5.6.10
THOLD_SI
t10
20
–
–
ns
SI hold time after
SCK rise (2.0V)
5.6.11
TSO_ENABLE
t11
–
–
110
ns
CS_B fall (2.0V) to
SO Bit0 valid
5.6.12
TVALID
t12
–
–
80
ns
SO data valid after
SCK rise (2.0V)
5.6.13
TSO_DISABLE
t13
–
–
110
ns
SO tristate after
CS_B rise (2.0V)
5.6.14
Number of clock pulses while CS_B
low
32
–
32
5.6.15
SO rise time
–
–
50
ns
(20% to 80%)
5.6.16
SO fall time
–
–
50
ns
(80% to 20%)
5.6.17
Input pin capacitance. CS_B, SI,
and SCK
TSO_RISE
TSO_FALL
Cin
–
–
20
pF
5.6.18
SO pin capacitance
Cso
–
–
25
pF
Data Sheet
26
Tristate
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
t1
t2
t3
CS_B
time
t4
t5
SCK
t6
clock
1
don’t care
t9
SI
t7
t 11
SO
Figure 17
Data Sheet
high impedance
clock
2
clock
3
clock
31
clock
32
don’t care
Bit 30
Bit 29
Bit 1
Bit 0
LSB
don’t care
time
t 10
Bit 31
MSB
don’t care
t8
t 12
Bit 31
MSB
Bit 30
time
t13
Bit 29
Bit 1
Bit 0
LSB
don’t care
high impedance
time
SPI Timing Diagram
27
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2
SPI Message Structure
5.6.2.1
SPI Message #0 - IC Version / Manufacturer
Sent Values:
IC Version / Manufacturer
31
30
29
28
R/W
15
Reset Value: 00 C1 00 00H
27
26
25
24
23
22
MSG_ID
14
13
12
21
20
19
18
17
16
3
2
1
0
not used
11
10
9
8
7
6
5
4
not used
Field
Bits
Type
Description
R/W
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 0000 = IC Version / Manufacturer
Response:
IC Version / Manufacturer
31
30
29
28
0
15
Reset Value: 00 C1 00 00H
27
26
MSG_ID
14
13
12
11
10
25
24
0
0
9
8
23
21
20
18
17
16
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Field
Bits
MSG_ID
30:26
Message Identifier
0 0000 = IC Version / Manufacturer
IC Manuf ID
16:23
IC Manufacturer ID Number
1100 0001= Infineon Technologies
Version
Number
8:15
Version Number
0000 0010 = K11
Data Sheet
19
IC Manuf ID
Version Number
Type
22
Description
28
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.2
SPI Message #1 - Main Period Set
Sent Values:
Main Period Set
31
30
29
R/W
15
Reset Value: 00 00 02 71H
28
27
26
MSG_ID
14
13
12
11
10
25
24
CH1
CH0
9
8
not used
23
22
21
20
7
6
5
Bits
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 0001 = Main Period Set
Channel
25:24
Channel Number
N
13:0
PWM Divider N
4
Type
29
0
0
0
28
27
26
2
1
0
13
12
11
10
25
24
23
22
21
20
19
18
17
16
CH1
CH0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
PWM Divider - N
Field
Bits
MSG_ID
30:26
Message Identifier
0 0001 = Main Period Set
Channel
25:24
Channel Number
N
13:0
PWM Divider N
Type
Description
FPWM =
Data Sheet
3
Reset Value: 00 00 02 71H
MSG_ID
14
16
Description
Response:
Main Period Set
15
17
PWM Divider - N
R/W
30
18
unused
Field
31
19
FCLK
32 * N
29
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.3
SPI Message #2 - PWM Offset
Sent Values:
PWM Offset
31
30
Reset Value: 00 00 00 00H
29
R/W
15
28
27
26
MSG_ID
14
13
12
11
10
25
24
CH1
CH0
9
8
23
22
21
20
7
6
Bits
R/W
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 0010 = PWM Offset
Channel
25:24
Channel Number
5
4
3
2
1
0
Phase Synch Offset
Response:
PWM Offset
Reset Value: 00 00 00 00H
29
0
28
27
26
MSG_ID
25
24
23
22
21
20
19
18
17
16
CH1
CH0
0
0
0
0
0
0
0
0
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
Field
Bits
MSG_ID
30:26
Message Identifier
0 0010 = PWM Offset
Channel
25:24
Channel Number
Phase Synch 4:0
Type
Phase Sync Offset
Description
Phase Synch Offset
Toffset =
Data Sheet
16
Description
Phase Synch 4:0
30
17
Phase Sync Offset
Field
31
18
unused
not used
Type
19
PhaseSynchOffset
32 * FPWM
30
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.4
SPI Message #3 - Current Set Point and Dither Amplitude Set
Dither
Sent Values:
Current Set Point and Dither Amplitude Set
31
30
29
R/W
28
27
26
MSG_ID
15
14
13
Dither Step Size
12
11
10
Reset Value: 00 00 00 00H
25
24
23
22
CH1
CH0
EN
ON/
OFF
9
8
7
6
Dither
ON/
OFF
20
19
18
17
16
1
0
Dither Step Size
5
4
3
2
Current Set Point
Field
Bits
R/W
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 0011 = Current Set Point and Dither Amplitude Set
Channel
25:24
Channel Number
EN
23
Sets behavior of channel when the pin ENABLE is low.
0 = channel turned off
1 = channel remains at last current set point.
ON/OFF
22
Used when the channel is configured for on/off operation
0 = off
1 = on
Step Size
21:12
Dither Step Size
(LSB value is 2-4 of the Current Set point LSB)
Dither
ON/OFF
11
Dither Enable
0=Disabled 1=Enabled
Current
Setpoint
10:0
Average Current Set Point
Resolution = 0.78125 mA / bit when 0.2 ohm external resistor is used.
Data Sheet
Type
21
Description
31
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Response:
Current Set Point and Dither Amplitude Set
31
30
29
28
R/W
27
26
MSG_ID
15
14
13
12
Dither Step Size
11
Reset Value: 00 00 00 00H
25
24
23
22
CH1
CH0
EN
ON/
OFF
9
8
7
6
10
Dither
ON/
OFF
Type
21
20
19
18
17
16
1
0
Dither Step Size
5
4
3
2
Current Set Point
Field
Bits
Description
MSG_ID
30:26
Message Identifier
0 0011 = Current Set Point and Dither Amplitude Set
Channel
25:24
Channel Number
EN
23
Sets behavior of channel when the pin ENABLE is low.
0 = channel turned off
1 = channel remains at last current set point.
ON/OFF
22
Used when the channel is configured for on/off operation
0 = off
1 = on
Step Size
21:12
Dither Step Size
(LSB value is 2-4 of the Current Set point LSB)
Dither
ON/OFF
11
Dither Enable
0=Disabled 1=Enabled
Current
Setpoint
10:0
Average Current Set Point
Resolution = 0.78125 mA / bit when 0.2 ohm external resistor is used.
Ditheramplitude [mApp] =
2 * DitherStepSize * DitherSteps 320
∗
RSENSE
215
Dither amplitude is the peak to peak amplitude of the dither waveform. Note: the actual dither waveform is
attenuated and phase shifted according to the frequency response of the control loop.
Dither Steps is the number of PWM periods in ¼ of the dither waveform, set in SPI message #4.
RSENSE is the value of the external sense resistor
Current setpoint [mA] =
Data Sheet
32
Setpoint
320
∗
11
R SENSE
2
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.5
SPI Message #4 - Dither Period Set
Sent Values:
Dither Period Set
31
30
29
R/W
15
Reset Value: 00 00 00 00H
28
27
26
MSG_ID
14
13
12
11
10
25
24
CH1
CH0
9
8
23
22
21
20
18
17
16
2
1
0
unused
7
6
5
4
not used
3
Dither Steps
Field
Bits
R/W
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 0100 = Dither Period Set
Channel
25:24
Channel Number
Dither Steps
5:0
Dither Steps - # of Dither Steps in 1/4 of the dither waveform period.
Response:
Dither Period Set
Reset Value: 00 00 00 00H
31
30
29
0
Type
19
28
27
Description
26
MSG_ID
25
24
23
22
21
20
19
18
17
16
CH1
CH0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
Type
Dither Steps
Field
Bits
Description
MSG_ID
30:26
Message Identifier
0 0100 = Dither Period Set
Channel
25:24
Channel Number
Dither Steps
5:0
Dither Steps - # of Dither Steps in 1/4 of the dither waveform period.
DitherPeriod [sec] =
Data Sheet
33
4 * DitherSteps
FPWM
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.6
SPI Message #5 - Control Variable Set (KP and KI)
Sent Values:
Control Variable Set (KP and KI)
31
30
29
R/W
15
28
27
Reset Value: 00 80 08 00H
26
MSG_ID
14
13
12
11
10
25
24
CH1
CH0
9
8
23
22
21
20
19
18
17
16
3
2
1
0
KP
7
6
KP
5
4
KI
Field
Bits
R/W
31
Type
Read / Write Bit
0 = Read
1 = Write
Description
MSG_ID
30:26
Message Identifier
0 0101 = Control Variable Set (KP and KI)
Channel
25:24
Channel Number
KP
23:12
KP - Proportional Coefficient
KI
11:0
KI - Integral Coefficient
Response:
Control Variable Set (KP and KI)
31
30
29
R/W
15
28
27
Reset Value: 00 80 08 00H
26
MSG_ID
14
13
12
11
10
25
24
CH1
CH0
9
8
23
22
21
20
19
18
17
16
3
2
1
0
KP
7
6
KP
5
4
KI
Field
Bits
MSG_ID
30:26
Message Identifier
0 0101 = Control Variable Set (KP and KI)t
Channel
25:24
Channel Number
KP
23:12
KP - Proportional Coefficient
KI
11:0
KI - Integral Coefficient
Data Sheet
Type
Description
34
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
The duty cycle of the OUTx pin can be calculated from the difference equations:
Rsense
* error (k − 1) + INT ( k )
1 . 28 ∗ N
Rsense
INT ( k ) = KI ∗
* error (k − 1) + INT ( k − 1)
1 . 28 ∗ N
DutyCycle
(k ) =
KP ∗
where error is the difference between the commanded average current and the measured average current in units
of Amps,
where k indicates the integral number of PWM periods that have elapsed since current regulation was initiated.
Data Sheet
35
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.7
SPI Message #6 - Dynamic Threshold Value Set
Sent Values:
Dynamic Threshold Value Set)
31
30
29
R/W
15
28
27
Reset Value: 00 7F F4 00H
26
MSG_ID
14
13
12
11
10
25
24
23
CH1
CH0
unused
9
8
7
Transient Mode Threshold
22
21
20
19
18
17
16
1
0
Transient Mode Threshold
6
5
4
3
2
Integrator Preload Value
Field
Bits
R/W
31
Type
Read / Write Bit
0 = Read
1 = Write
Description
MSG_ID
30:26
Message Identifier
0 0110 = Dynamic Threshold Value Set
Channel
25:24
Channel Number
Transient
22:12
Mode Thresh
Transient Mode Threshold
Setpoint changes grater than this threshold will activate the transient
mode of operation.
Int. Preload
Integrator Preload Value
This value will be loaded into the integrator when the controller
transitions from transient mode to steady state mode.
11:0
Response:
Dynamic Threshold Value Set
31
30
29
R/W
15
28
27
Reset Value: 00 7F F4 00H
26
MSG_ID
14
13
12
11
10
25
24
23
CH1
CH0
0
9
8
7
Transient Mode Threshold
22
21
20
19
17
16
1
0
Transient Mode Threshold
6
5
4
3
2
Integrator Preload Value
Field
Bits
MSG_ID
30:26
Message Identifier
0 0110 = Dynamic Threshold Value Set
Channel
25:24
Channel Number
Data Sheet
18
Type
Description
36
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Field
Bits
Type
Description
Transient
22:12
Mode Thresh
Transient Mode Threshold
Setpoint changes grater than this threshold will activate the transient
mode of operation.
Int. Preload
Integrator Preload Value
This value will be loaded into the integrator when the controller
transitions from transient mode to steady state mode.
11:0
CurrentThreshold [mA] =
TransientModeThreshold 320
∗
RSENSE
211
Preload = IntPreloadValue ∗ Current Set Point ∗ 2 8
The Preload value is limited to a maximum value of N * 217
Data Sheet
37
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.8
SPI Message #7 - On/Off Control and Fault Mask Configuration
Sent Values:
On/Off Control and Fault Mask Configuration
31
30
29
R/W
28
27
26
MSG_ID
15
14
FMR
FME
13
12
DIAG_TMR
25
Reset Value: 00 00 00 00H
24
unused
11
10
9
8
23
22
21
20
19
18
17
16
CM0
CM1
CM2
CM3
FM0
FM1
FM2
FM3
7
6
5
4
3
2
1
0
AZ
unused
Disable
Field
Bits
R/W
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 0111 = On/Off Control and Fault Mask Configuration
CMx
23, 22, 21,
20
Control Mode for Channel #x
0 = Current Control
1 = On/off
FMx
19, 18, 17,
16
Fault Mask for Channel #x
0 = faults don’t trigger FAULT pin
1 = fault triggers FAULT pin
FMR
15
Fault Mask for RESET_B pin
0 = A low state on the ENABLE pin does not activate the FAULT pin.
1 = A low state on the ENABLE pin does activate the FAULT pin.
Note: when a high to low transition is detected on the ENABLE pin,
the ENABLE fault will be latched until the ENABLE pin returns high
AND a diagnostic read message is received.
FME
14
Fault Mast for ENABLE pin
0 = A low state on the RESET_B pin does not activate the FAULT pin.
1 = A low state on the RESET_B pin does activate the FAULT pin.
DIAG_TMR
13:12
Diagnostic Timer
00 = TIME_1 pre-divider = 128
01 = TIME_2 pre-divider = 192
10 = TIME_2 pre-divider = 192
11 = TIME_3 pre-divider = 256
AZ Disable
11
Auto-Zero Disable
0 = Auto-Zero Enabled
1 = Auto-Zero Disabled
Data Sheet
Type
Description
38
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Response:
On/Off Control and Fault Mask Configuration
31
30
29
R/W
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
CM0
CM1
CM2
CM3
FM0
FM1
FM2
FM3
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
MSG_ID
15
14
FMR
FME
13
12
DIAG_TMR
11
AZ
Disable
Field
Bits
MSG_ID
30:26
Message Identifier
0 0111 = On/Off Control and Fault Mask Configuration
CMx
23, 22, 21,
20
Control Mode for Channel #x
0 = Current Control
1 = On/off
FMx
19, 18, 17,
16
Fault Mask for Channel #x
0 = faults don’t trigger FAULT pin
1 = fault triggers FAULT pin
FMR
15
Fault Mask for RESET_B pin
0 = A low state on the ENABLE pin does not activate the FAULT pin.
1 = A low state on the ENABLE pin does activate the FAULT pin.
Note: when a high to low transition is detected on the ENABLE pin,
the ENABLE fault will be latched until the ENABLE pin returns high
AND a diagnostic read message is received.
FME
14
Fault Mask for ENABLE pin
0 = A low state on the RESET_B pin does not activate the FAULT pin.
1 = A low state on the RESET_B pin does activate the FAULT pin.
DIAG_TMR
13:12
Diagnostic Timer
00 = TIME_1 pre-divider = 128
01 = TIME_2 pre-divider = 192
10 = TIME_2 pre-divider = 192
11 = TIME_3 pre-divider = 256
AZ Disable
11
Auto-Zero Disable
0 = Auto-Zero Enabled
1 = Auto-Zero Disabled
Data Sheet
Type
Reset Value: 00 00 00 00H
Description
39
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.9
SPI Message #8 - Diagnostic Configuration
Sent Values:
Diagnostic Configuration
31
30
29
R/W
28
Reset Value: xx FF FF FFH
27
26
MSG_ID
15
14
13
12
25
24
23
unused
11
SB_RETRY1
10
9
SB2
22
21
SB0
8
7
6
5
4
Bits
31
Read / Write Bit
0 = Read
1 = Write
MSG_ID
30:26
Message Identifier
0 1000= Diagnostic Configuration
SBx
23:22
17:16
11:10
5:4
Short To Battery Threshold
00 = 0.7 V
01 = 0.9 V
10 = 1.1 V
11 = 1.3 V
14
13
SB_RETRY1
Field
Bits
MSG_ID
30:26
Data Sheet
3
2
1
0
28
Reset Value: xx FF FF FFH
27
26
MSG_ID
15
SB1
Short to Battery Retry Time
Retry after 4 * SB_RETRY * PWM periods
Response Values:
Diagnostic Configuration
0
16
Description
SB_RETRYx 21:18
15:12
9:6
3:0
29
17
SB_RETRY3
R/W
30
18
SB3
Field
31
19
SB_RETRY0
SB_RETRY2
Type
20
12
11
10
SB2
Type
25
24
0
0
9
8
23
22
21
SB0
7
SB_RETRY2
20
19
18
17
SB_RETRY0
6
5
4
SB3
3
16
SB1
2
1
0
SB_RETRY3
Description
Message Identifier
0 1000= Diagnostic Configuration
40
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Field
Bits
SBx
23:22
17:16
11:10
5:4
SB_RETRYx 21:18
15:12
9:6
3:0
Type
Description
Short To Battery Threshold
00 = 0.7 V
01 = 0.9 V
10 = 1.1 V
11 = 1.3 V
Short to Battery Retry Time
Retry after 4 * SB_RETRY * PWM periods
Retry Period =
4 ∗ SB_Retry x
f PWM
If the SB_RETRY field is programmed to the value 0, the short to battery retry period is identical to the programmed
the PWM period as programmed in SPI message #1.
Data Sheet
41
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.10
SPI Message #9 - Diagnostic Read
Sent Values:
Diagnostic Read
31
30
29
R/W
Reset Value: xx 00 00 03H
28
27
26
25
24
23
22
21
MSG_ID
15
14
13
12
20
19
18
17
16
3
2
1
0
unused
11
10
9
8
7
6
5
4
unused
Field
Bits
R/W
31
Type
Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
Description
MSG_ID
30:26
Message Identifier
0 1001 = Diagnostic Read
Response Values:
Diagnostic Read
31
30
29
0
Reset Value: xx 00 00 03H
28
27
26
MSG_ID
15
14
13
12
11
OLOFF1
OLON1
SG2
OFFTST2
SB2
24
23
SG0
OFFTST0
SB0
9
8
7
6
5
OLON2
SG3
OFFTST3
SB3
SBOLTST2 OFF2
22
21
SBOLTST0 OFF0
20
19
18
17
16
OLON0
SG1
OFFTST1
SB1
SBTST1
4
3
2
1
0
OLON3
ENL
RBL
SBOLTST3 OFF3
Field
Bits
MSG_ID
30:26
Message Identifier
0 1001= Diagnostic Read (channel 0-3)
SGx
25,19,13,7
Short to Ground - Fault
OFF-TSTx
24,18,12,6
Short to Ground & Open Load (Gate Off) - Tested
SBx
23,17,11,5
Short to Battery - Fault
SB-TSTx
22,16,10,4
Short to Battery - Tested
OL-OFFx
21,15,9,3
Open Load (Gate Off) - Fault
OL-ONx
20,14,8,2
Open Load (Gate On) - Fault
ENL
1
Enable Pin Latch
RBL
0
Reset_B Pin Latch
Data Sheet
Type
10
25
Description
42
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.11
SPI Message #10 - Current Read
Sent Values:
Current Read
31
30
Reset Value: xx 00 00 00H
29
R/W
15
28
27
26
MSG_ID
14
13
12
11
10
25
24
23
CH1
CH0
9
8
22
21
20
19
18
17
16
2
1
0
unused
7
6
5
4
3
unused
Field
Bits
R/W
31
Type
Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
Description
MSG_ID
30:26
Message Identifier
0 1010 = Current Read
Channel
25:24
Channel Number
Response Values:
Current Read
31
30
29
0
Reset Value: xx 00 00 00H
28
27
26
MSG_ID
15
14
0
0
13
12
11
10
25
24
23
22
21
20
19
18
17
16
CH1
CH0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Current Read
Field
Bits
MSG_ID
30:26
Message Identifier
0 1010 = Current Read
Channel
25:24
Channel Number
Current Read 13:0
Type
Description
Current Read
CurrentRead [mA] =
Data Sheet
CurrentRead 320
∗
RSENSE
214
43
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.12
SPI Message #11 - Autozero Read
Sent Values:
Autozero Read
31
30
Reset Value: xx 00 00 00H
29
R/W
28
27
26
MSG_ID
15
14
13
12
11
10
25
24
CH1
CH0
9
8
23
22
21
20
19
18
17
16
2
1
0
unused
7
6
5
4
3
unused
Field
Bits
R/W
31
Type
Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
Description
MSG_ID
30:26
Message Identifier
0 1011 = Autozero Read
Channel
25:24
Channel Number
Response Values:
Autozero Read
31
30
29
0
Reset Value: xx 00 00 00H
28
27
26
MSG_ID
15
14
OVL
PSL
13
12
11
AZon AZoff
10
25
24
23
22
21
20
19
18
17
16
CH1
CH0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Autozero (on) value
Field
Bits
MSG_ID
30:26
Message Identifier
01011 = Autozero Read
Channel
25:24
Channel Number
OVL
15
Overvoltage latch
This latch is set when the voltage on the BAT pin exceeds the
overvoltage threshold. The latch is reset when the BAT pin voltage is
below the threshold and the Autozero Read message is received.
Data Sheet
Type
Autozero (off) value
Description
44
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
Field
Bits
Type
Description
PSL
14
Phase sync latch
This latch is set when a rising edge occurs on the PHASE_SYNC pin.
The latch is reset when the Autozero Read message is received.
AZ on
13
Autozero (on) occurred
This latch is set when an autozero sequence has completed with a
low common mode input voltage. The latch is reset when the
Autozero Read message is received
AZ off
12
Autozero (off) occurred
This latch is set when an autozero sequence has completed with a
high common mode input voltage. The latch is reset when the
Autozero Read message is received
AZ (on) value 11:6
Autozero (on) value
The stored Autozero value used when the POS and NEG pin common
mode voltage is low.
AZ (off) value 5:0
Autozero (off) value
The stored Autozero value used when the POS and NEG pin common
mode voltage is high
Data Sheet
45
Rev. 1.0, 2008-07-09
TLE7242-2G
Functional Description and Electrical Characteristics
5.6.2.13
SPI Message #12 - Duty Cycle Read
Sent Values:
Duty Cycle Read
31
30
29
R/W
15
Reset Value: xx 00 00 00H
28
27
26
MSG_ID
14
13
12
11
10
25
24
CH1
CH0
9
8
23
22
21
20
19
18
17
16
2
1
0
unused
7
6
5
4
3
unused
Field
Bits
R/W
31
Type
Read / Write Bit
0 = Read
1 = Write (interpreted as a read)
Description
MSG_ID
30:26
Message Identifier
0 1100 = Duty Cycle Read
Channel
25:24
Channel Number
Response Values:
Autozero Read
31
30
29
0
15
Reset Value: xx 00 00 00H
28
27
26
MSG_ID
14
13
12
11
10
25
24
23
22
21
20
19
CH1
CH0
0
0
0
0
0
9
8
7
6
5
4
3
18
17
16
Duty Cycle
2
1
0
Duty Cycle
Field
Bits
Type
Description
MSG_ID
30:26
Message Identifier
0 1100 = Duty Cycle Read
Channel
25:24
Channel Number
Duty Cycle
18:0
Duty Cycle
Duty cycle of the PWM output of the selected channel.
Duty Cycle =
Data Sheet
DutyCycle
∗ 100 %
32 ∗ N
46
Rev. 1.0, 2008-07-09
TLE7242-2G
Application Information
6
Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBAT
VBAT
330 Ω
BAT
10nF
VB AT
Constant
Current
Solenoid
47uF
+5V Digital
V5D
100pF
POS0
100nF
NEG0
GND_D
0.2 Ω
OUT0
+5V Analog
Power Supply
e.g. TLE6368
10nF
SPD15N06S2L-64
10nF
VBAT
1KΩ
V5A
VB AT
Constant
Current
Solenoid
GND_A
+3.3V or +5V
(µC I/O Voltage Level)
POS1
V_SIGNAL
NEG1
10nF
10K Ω
0.2 Ω
FAULT
ENABLE
PHASE_SYNC
SPD15N06S2L-64
VBAT
TLE7242-2G
VB AT
Constant
Current
Solenoid
POS2
CLK
NEG2
0.2 Ω
SPD15N06S2L-64
10nF
VBAT
1KΩ
SCK
On/Off
Solenoid
SI
SO
CS_B
POS3
36V
NEG3
OUT3
TEST
Figure 18
10nF
1KΩ
RESET_B
OUT2
SPI
PERIPHERAL
µController
TC1766
(AUDO-NG)
CLOCK
OUT
I/O PORTS
OUT1
SPD15N06S2L-64
10nF
1KΩ
Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real application.
6.1
•
•
Further Application Information
Please contact us to get the Pin FMEA
For further information you may contact http://www.infineon.com/
Data Sheet
47
Rev. 1.0, 2008-07-09
TLE7242-2G
Package Outlines
7
Package Outlines
Figure 19
PG-DSO-28-26
Green Product (RoHS-compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pbfree finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.
Data Sheet
48
Dimensions in mm
Rev. 1.0, 2008-07-09
TLE7242-2G
Revision History
8
Revision History
0
Version
Date
Changes
1.0
July 9, 2008
Release of datasheet
Data Sheet
49
Rev. 1.0, 2008-07-09
Edition 2008-07-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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